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URL https://opencores.org/ocsvn/manchesterwireless/manchesterwireless/trunk

Subversion Repositories manchesterwireless

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  • This comparison shows the changes necessary to convert path 
    /manchesterwireless/branches
    from Rev 9 to Rev 12
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Rev 9 → Rev 12

/singledouble/synthTest.ucf
0,0 → 1,31
#PACE: Start of Constraints generated by PACE
 
#PACE: Start of PACE I/O Pin Assignments
NET "anode_ctrl<0>" LOC = "d14" ;
NET "anode_ctrl<1>" LOC = "g14" ;
NET "anode_ctrl<2>" LOC = "f14" ;
NET "anode_ctrl<3>" LOC = "e13" ;
NET "character_o<0>" LOC = "e14" ;
NET "character_o<1>" LOC = "g13" ;
NET "character_o<2>" LOC = "n15" ;
NET "character_o<3>" LOC = "p15" ;
NET "character_o<4>" LOC = "r16" ;
NET "character_o<5>" LOC = "f13" ;
NET "character_o<6>" LOC = "n16" ;
NET "character_o<7>" LOC = "p16" ;
NET "clk_i" LOC = "t9" ;
NET "data_i" LOC = "c10" ;
NET "ready_o" LOC = "b14" ;
NET "recieved_debug<0>" LOC = "a8" ;
NET "recieved_debug<1>" LOC = "b10" ;
NET "recieved_debug<2>" LOC = "b11" ;
NET "recieved_debug<3>" LOC = "a12" ;
NET "rst_i" LOC = "m13" ;
NET "testpin" LOC = "d5" ;
NET "waitforstart_rdy" LOC = "a13" ;
 
#PACE: Start of PACE Area Constraints
 
#PACE: Start of PACE Prohibit Constraints
 
#PACE: End of Constraints generated by PACE
/singledouble/globals.vhd
6,15 → 6,15
constant WORD_LENGTH : integer := 4;
 
-- when each transmitter bit is 3.24 ms and the FPGA clock is 50 MHz
-- then:
 
-- then:
 
-- single is nominally 23200
constant INTERVAL_MIN_SINGLE: integer := 10000;
constant INTERVAL_MIN_SINGLE: integer := 34000;--10000
constant INTERVAL_MAX_SINGLE: integer := 65000;
-- double is nominally 43000-50000
constant INTERVAL_MIN_DOUBLE: integer := 90000;--80000
constant INTERVAL_MIN_DOUBLE: integer := 80000;--90000
constant INTERVAL_MAX_DOUBLE: integer := 120000;
 
 
constant INTERVAL_QUADRUPLE: integer := 650000;--350000
end globals;
/singledouble/simTest.vhd
8,7 → 8,7
 
architecture Behavioral of testSim is
 
component decodeManchester
component manchesterWireless
port (
clk_i : in std_logic;
rst_i : in std_logic;
21,15 → 21,15
end component;
 
signal decode_output : std_logic_vector(WORD_LENGTH-1 downto 0);
-- up/down and left/right buffers
signal parity_o_buff, parity_o_reg : std_logic;
-- up/down and left/right buffers
signal parity_o_buff, parity_o_reg : std_logic;
signal button_o_buff, button_o_reg : std_logic_vector(1 downto 0);
signal ud_buff1, ud_buff2, lr_buff1, lr_buff2 : std_logic_vector(6 downto 0);
signal ud_buff1, ud_buff2, lr_buff1, lr_buff2 : std_logic_vector(6 downto 0);
signal ud_buff1_reg, ud_buff2_reg, lr_buff1_reg, lr_buff2_reg : std_logic_vector(6 downto 0);
signal char_select : integer range 0 to 3;
signal reset_manchester, soft_reset, ready_o_buff : std_logic;
signal reset_manchester, soft_reset, ready_o_buff : std_logic;
signal clk_i : std_logic;
signal rst_i : std_logic := '1';
signal data_i : std_logic;
39,14 → 39,14
signal button_o : std_logic_vector(1 downto 0);
signal parity_o : std_logic;
signal recieved_debug : std_logic_vector(3 downto 0);
signal waitforstart_rdy : std_logic;
signal waitforstart_rdy : std_logic;
signal coded_rdy: std_logic;
signal coded : std_logic_vector(WORD_LENGTH-1 downto 0);
constant half_period : time := 10 ns;
constant period : time := 2*half_period;
constant mid_single : time := (INTERVAL_MIN_SINGLE+INTERVAL_MAX_SINGLE)/2*period;
constant WORD : std_logic_vector(28 downto 0) := "01100101100101010101010101010";
constant WORD : std_logic_vector(28 downto 0) := "01100101100101010101010101010";
 
begin
character_o(7) <= '1'; -- turn off decimal point
54,7 → 54,7
reset_manchester <= rst_i or soft_reset;
ready_o <= ready_o_buff;
 
inst_decodeManchester: decodeManchester
inst_manchesterWireless: manchesterWireless
port map(
clk_i => clk_i,
rst_i => reset_manchester,
128,7 → 128,7
"00" when "00", -- 11
"11" when others;
 
parity_o_buff <= decode_output(9);
parity_o_buff <= decode_output(9);
parity_o <= parity_o_reg;
 
process (clk_i,rst_i)
137,33 → 137,33
if rst_i = '1' then
char_select <= 0;
counter := 0;
div_clk := '0';
div_clk := '0';
soft_reset <= '0';
elsif (clk_i'event and clk_i = '1') then
-- register the output
if (ready_o_buff = '1') then
ud_buff1_reg <= ud_buff1;
ud_buff2_reg <= ud_buff2;
lr_buff1_reg <= lr_buff1;
lr_buff2_reg <= lr_buff2;
button_o_reg <= button_o_buff;
parity_o_reg <= parity_o_buff;
soft_reset <= '1';
else
soft_reset <= '0';
end if;
elsif (clk_i'event and clk_i = '1') then
-- register the output
if (ready_o_buff = '1') then
ud_buff1_reg <= ud_buff1;
ud_buff2_reg <= ud_buff2;
lr_buff1_reg <= lr_buff1;
lr_buff2_reg <= lr_buff2;
button_o_reg <= button_o_buff;
parity_o_reg <= parity_o_buff;
soft_reset <= '1';
else
soft_reset <= '0';
end if;
counter := counter + 1;
if (counter = 1023) then
-- this is for simulation
-- ModelSim does not want to roll over
if char_select < 3 then
char_select <= char_select + 1;
else
char_select <= 0;
end if;
-- this is for simulation
-- ModelSim does not want to roll over
if char_select < 3 then
char_select <= char_select + 1;
else
char_select <= 0;
end if;
counter := 0;
end if;
 
216,7 → 216,7
wait for half_period;
clk_i <= not clk_i;
end loop;
end process;
end process;
end Behavioral;
 

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