URL
https://opencores.org/ocsvn/manchesterwireless/manchesterwireless/trunk
Subversion Repositories manchesterwireless
Compare Revisions
- This comparison shows the changes necessary to convert path
/manchesterwireless
- from Rev 3 to Rev 4
- ↔ Reverse comparison
Rev 3 → Rev 4
/trunk/decode/simTest.vhd
10,9 → 10,9
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architecture Behavioral of sim_test is |
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COMPONENT twoToOne |
COMPONENT decode |
PORT( |
clk_i : in std_logic; |
clk_i : in std_logic; |
rst_i : in std_logic; |
encoded_i : in std_logic_vector(3 downto 0); |
nd_i : in std_logic; |
29,7 → 29,7
-- 0100 = double one |
-- 1000 = double zero |
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signal clk_i : std_logic; |
signal clk_i : std_logic; |
signal rst_i : std_logic; |
signal encoded_i : std_logic_vector(3 downto 0) := "0000"; |
signal nd_i : std_logic := '0'; |
41,8 → 41,8
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begin |
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Inst_twoToOne: twoToOne PORT MAP( |
clk_i => clk_i, |
Inst_decode: decode PORT MAP( |
clk_i => clk_i, |
rst_i => rst_i, |
encoded_i => encoded_i, |
nd_i => nd_i, |
/trunk/singleDouble/simTest.vhd
9,7 → 9,7
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architecture Behavioral of test_sim is |
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COMPONENT md16 |
COMPONENT singleDouble |
PORT( |
clk_i : in std_logic; |
ce_i : in std_logic; |
31,7 → 31,7
signal reset : std_logic := '1'; |
begin |
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Inst_md16: md16 PORT MAP( |
Inst_singleDouble: singleDouble PORT MAP( |
clk_i => clk, |
ce_i => ce_i, |
rst_i => reset, |
42,15 → 42,15
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process |
begin |
loop |
reset <= '1'; |
ce_i <= '0'; |
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wait for 2*md_period; |
loop |
reset <= '1'; |
ce_i <= '0'; |
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wait for 2*md_period; |
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reset <= '0'; |
ce_i <= '1'; |
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wait for 2*md_period; |
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mdi <= not mdi; |