URL
https://opencores.org/ocsvn/mcs-4/mcs-4/trunk
Subversion Repositories mcs-4
Compare Revisions
- This comparison shows the changes necessary to convert path
/mcs-4
- from Rev 3 to Rev 4
- ↔ Reverse comparison
Rev 3 → Rev 4
/trunk/rtl/verilog/alu.v
7,7 → 7,7
// This file is part of the MCS-4 project hosted at OpenCores: |
// http://www.opencores.org/cores/mcs-4/ |
// |
|
|
// |
// These materials are provided under the Creative Commons |
// "Attribution-NonCommercial-ShareAlike" Public License. They |
118,12 → 118,12
// Feedback from Accumulator |
reg n0873, n0872, n0871, n0870; |
always @(posedge sysclk) begin |
if (acc_ada) |
{n0873, n0872, n0871, n0870} <= acc ^ 4'b1010; |
if (acc_adac) |
{n0873, n0872, n0871, n0870} <= acc ^ 4'b0101; |
if (m12) |
{n0873, n0872, n0871, n0870} <= 4'b1010; |
if (acc_ada) |
{n0873, n0872, n0871, n0870} <= acc; |
if (acc_adac) |
{n0873, n0872, n0871, n0870} <= ~acc; |
end |
|
// Carry generator |
145,10 → 145,10
wire n0861 = n0914; |
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// Adder |
wire n0877 = ~((n0893 & n0559 & n0873) | (n0861 & (n0893 | n0873 | n0559))); |
wire n0878 = ~((n0877 & n0550 & n0870) | (n0553 & (n0887 | n0870 | n0550))); |
wire n0878 = ~((n0887 & n0550 & n0870) | (n0553 & (n0887 | n0870 | n0550))); |
wire n0875 = ~((n0889 & n0553 & n0871) | (n0556 & (n0889 | n0871 | n0553))); |
wire n0879 = ~((n0891 & n0556 & n0872) | (n0559 & (n0891 | n0872 | n0556))); |
wire n0877 = ~((n0893 & n0559 & n0873) | (n0861 & (n0893 | n0873 | n0559))); |
wire n0846 = ~n0878; |
wire n0847 = n0875; |
wire n0848 = ~n0879; |
/trunk/rtl/verilog/counter.v
7,7 → 7,7
// This file is part of the MCS-4 project hosted at OpenCores: |
// http://www.opencores.org/cores/mcs-4/ |
// |
|
|
// |
// These materials are provided under the Creative Commons |
// "Attribution-NonCommercial-ShareAlike" Public License. They |
/trunk/rtl/verilog/i4004.v
7,7 → 7,7
// This file is part of the MCS-4 project hosted at OpenCores: |
// http://www.opencores.org/cores/mcs-4/ |
// |
|
|
// |
// These materials are provided under the Creative Commons |
// "Attribution-NonCommercial-ShareAlike" Public License. They |
61,6 → 61,7
wire jms; |
wire sc; |
wire dc; |
wire n0636; |
wire sc_m22_clk2; |
wire fin_fim_src_jin; |
wire inc_isz_add_sub_xch_ld; |
158,6 → 159,7
.jms(jms), |
.sc(sc), |
.dc(dc), |
.n0636(n0636), |
.sc_m22_clk2(sc_m22_clk2), |
.fin_fim_src_jin(fin_fim_src_jin), |
.inc_isz_add_sub_xch_ld(inc_isz_add_sub_xch_ld), |
274,6 → 276,7
.poc(poc), |
.m12_m22_clk1_m11_m12(gate), |
.data(data), |
.n0636(n0636), |
.sc_m22_clk2(sc_m22_clk2), |
.fin_fim_src_jin(fin_fim_src_jin), |
.inc_isz_add_sub_xch_ld(inc_isz_add_sub_xch_ld), |
/trunk/rtl/verilog/instruction_decode.v
7,7 → 7,7
// This file is part of the MCS-4 project hosted at OpenCores: |
// http://www.opencores.org/cores/mcs-4/ |
// |
|
|
// |
// These materials are provided under the Creative Commons |
// "Attribution-NonCommercial-ShareAlike" Public License. They |
50,6 → 50,7
output wire dc, // DC (Double Cycle, ~SC) |
|
// Outputs to the Scratch Pad (SP) board |
output wire n0636, // JIN+FIN |
output wire sc_m22_clk2, // SC&M22&CLK2 |
output wire fin_fim_src_jin, // FIN+FIM+SRC+JIN |
output wire inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD |
124,6 → 125,7
wire ope = (opr == 4'b1111); |
|
assign ope_n = ~ope; |
assign n0636 = jin_fin; |
assign jcn_isz = jcn | isz; |
assign jun_jms = jun | jms; |
wire ldm_bbl = ldm | bbl; |
171,12 → 173,14
// The Condition Flip-Flop |
reg n0397; |
wire n0486 = ~((opa[2] & acc_0) | (opa[1] & cy_1) | (opa[0] & n0432)); |
wire n0419 = ~((add_0 & ~isz) & (~jcn | ((~n0486 | opa[3]) & (n0486 | ~opa[3])))); |
wire n0413 = ~((sc & n0419 & x32) | (~x32 | n0397)); |
wire n0419 = ~((add_0 | ~isz) & (~jcn | ((n0486 | opa[3]) & (~n0486 | ~opa[3])))); |
wire n0413 = ~((sc & n0419 & x32) | (~x32 & n0397)); |
reg n0405; |
always @(posedge sysclk) begin |
if (clk2) |
n0405 <= n0413; |
end |
always @(posedge sysclk) begin |
if (clk1) |
n0397 <= ~n0405; |
end |
183,9 → 187,9
assign cn_n = ~n0397; |
|
// The Single-Cycle Flip-Flop |
reg n0343; |
reg n0343 = 1'b0; |
wire n0368 = ~((sc & (fin_fim | jcn_isz | jun_jms) & x32) | (n0343 & ~x32)); |
reg n0362; |
reg n0362 = 1'b1; |
always @(posedge sysclk) begin |
if (clk2) |
n0362 <= n0368; |
/trunk/rtl/verilog/instruction_pointer.v
7,7 → 7,7
// This file is part of the MCS-4 project hosted at OpenCores: |
// http://www.opencores.org/cores/mcs-4/ |
// |
|
|
// |
// These materials are provided under the Creative Commons |
// "Attribution-NonCommercial-ShareAlike" Public License. They |
/trunk/rtl/verilog/scratchpad.v
7,7 → 7,7
// This file is part of the MCS-4 project hosted at OpenCores: |
// http://www.opencores.org/cores/mcs-4/ |
// |
|
|
// |
// These materials are provided under the Creative Commons |
// "Attribution-NonCommercial-ShareAlike" Public License. They |
40,6 → 40,7
inout wire [3:0] data, |
|
// Inputs from the Instruction Decode board |
input wire n0636, // JIN+FIN |
input wire sc_m22_clk2, // SC&M22&CLK2 |
input wire fin_fim_src_jin, // FIN+FIM+SRC+JIN |
input wire inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD |
123,6 → 124,9
wire wrab1 = clk2 & ((m22 & n0564) | (~opa0_n & n0568)); |
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// Force row 0 if FIN&X12 |
wire fin_x12 = (n0636 & opa0_n) & x12; |
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// Manage the row data buffer |
always @(posedge sysclk) begin |
if (precharge) |
129,12 → 133,12
dram_temp <= 8'b0; |
|
if (row_read) |
dram_temp <= dram_array[row]; |
dram_temp <= dram_array[fin_x12 ? 3'b000 : row]; |
|
if (wrab0) |
dram_temp[ 7:4] <= ~din_n; |
if (wrab1) |
dram_temp[ 3:0] <= ~din_n; |
if (wrab1) |
dram_temp[ 7:4] <= ~din_n; |
end |
|
// Handle row writes |
148,8 → 152,8
always @* begin |
(* PARALLEL_CASE *) |
case (1'b1) |
rrab0: dout = dram_temp[ 3:0]; |
rrab1: dout = dram_temp[ 7:4]; |
rrab0: dout = dram_temp[ 7:4]; |
rrab1: dout = dram_temp[ 3:0]; |
default: dout = 4'bzzzz; |
endcase |
end |
/trunk/rtl/verilog/timing_io.v
7,7 → 7,7
// This file is part of the MCS-4 project hosted at OpenCores: |
// http://www.opencores.org/cores/mcs-4/ |
// |
|
|
// |
// These materials are provided under the Creative Commons |
// "Attribution-NonCommercial-ShareAlike" Public License. They |