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URL https://opencores.org/ocsvn/mdct/mdct/trunk

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Rev 26 → Rev 27

/trunk/source/DCT1D.vhd
37,45 → 37,13
rst : in std_logic;
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
romedatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao : in T_ROM1DATAO;
romodatao : in T_ROM1DATAO;
 
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro : out T_ROM1ADDRO;
romoaddro : out T_ROM1ADDRO;
ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
ramwe : out STD_LOGIC;
90,239 → 58,277
type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0);
signal databuf_reg : INPUT_DATA;
signal latchbuf_reg : INPUT_DATA;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal inpcnt_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal ramdatai_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramwe_s : STD_LOGIC;
signal wmemsel_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal col_2_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
begin
signal databuf_reg : INPUT_DATA;
signal latchbuf_reg : INPUT_DATA;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal inpcnt_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal ramwe_s : STD_LOGIC;
signal wmemsel_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal col_2_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
ramwe_sg:
ramwe <= ramwe_s;
signal even_not_odd : std_logic;
signal even_not_odd_d1 : std_logic;
signal even_not_odd_d2 : std_logic;
signal even_not_odd_d3 : std_logic;
signal ramwe_d1 : STD_LOGIC;
signal ramwe_d2 : STD_LOGIC;
signal ramwe_d3 : STD_LOGIC;
signal ramwe_d4 : STD_LOGIC;
signal ramwaddro_d1 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d2 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d3 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d4 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal wmemsel_d1 : STD_LOGIC;
signal wmemsel_d2 : STD_LOGIC;
signal wmemsel_d3 : STD_LOGIC;
signal wmemsel_d4 : STD_LOGIC;
signal romedatao_d1 : T_ROM1DATAO;
signal romodatao_d1 : T_ROM1DATAO;
signal romedatao_d2 : T_ROM1DATAO;
signal romodatao_d2 : T_ROM1DATAO;
signal romedatao_d3 : T_ROM1DATAO;
signal romodatao_d3 : T_ROM1DATAO;
signal dcto_1 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_2 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_3 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_4 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
ramdatai_sg:
ramdatai <= ramdatai_s;
-- temporary
odv_sg:
odv <= ramwe_s;
dcto_sg:
dcto <= ramdatai_s(RAMDATA_W-1) & ramdatai_s(RAMDATA_W-1) & ramdatai_s;
wmemsel_sg:
wmemsel <= wmemsel_reg;
begin
 
ramwaddro <= ramwaddro_d4;
ramwe <= ramwe_d4;
ramdatai <= dcto_4(DA_W-1 downto 12);
wmemsel <= wmemsel_d4;
process(clk)
process(clk,rst)
begin
if clk = '1' and clk'event then
if rst = '1' then
inpcnt_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
stage2_reg <= '0';
stage2_cnt_reg <= (others => '1');
ramdatai_s <= (others => '0');
ramwe_s <= '0';
ramwaddro <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
wmemsel_reg <= '0';
col_2_reg <= (others => '0');
else
stage2_reg <= '0';
ramwe_s <= '0';
--------------------------------
-- 1st stage
--------------------------------
if idv = '1' then
inpcnt_reg <= inpcnt_reg + 1;
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT;
if inpcnt_reg = N-1 then
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
stage2_reg <= '1';
end if;
if rst = '1' then
inpcnt_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
stage2_reg <= '0';
stage2_cnt_reg <= (others => '1');
ramwe_s <= '0';
ramwaddro_s <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
wmemsel_reg <= '0';
col_2_reg <= (others => '0');
elsif clk = '1' and clk'event then
stage2_reg <= '0';
ramwe_s <= '0';
--------------------------------
-- 1st stage
--------------------------------
if idv = '1' then
inpcnt_reg <= inpcnt_reg + 1;
 
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT;
 
if inpcnt_reg = N-1 then
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
stage2_reg <= '1';
end if;
--------------------------------
end if;
--------------------------------
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
if stage2_cnt_reg(0) = '0' then
ramdatai_s <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao0),DA_W) +
(RESIZE(SIGNED(romedatao1),DA_W-1) & '0') +
(RESIZE(SIGNED(romedatao2),DA_W-2) & "00") +
(RESIZE(SIGNED(romedatao3),DA_W-3) & "000") +
(RESIZE(SIGNED(romedatao4),DA_W-4) & "0000") +
(RESIZE(SIGNED(romedatao5),DA_W-5) & "00000") +
(RESIZE(SIGNED(romedatao6),DA_W-6) & "000000") +
(RESIZE(SIGNED(romedatao7),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romedatao8),DA_W-8) & "00000000"),
DA_W)(DA_W-1 downto 12));
else
ramdatai_s <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao0),DA_W) +
(RESIZE(SIGNED(romodatao1),DA_W-1) & '0') +
(RESIZE(SIGNED(romodatao2),DA_W-2) & "00") +
(RESIZE(SIGNED(romodatao3),DA_W-3) & "000") +
(RESIZE(SIGNED(romodatao4),DA_W-4) & "0000") +
(RESIZE(SIGNED(romodatao5),DA_W-5) & "00000") +
(RESIZE(SIGNED(romodatao6),DA_W-6) & "000000") +
(RESIZE(SIGNED(romodatao7),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romodatao8),DA_W-8) & "00000000"),
DA_W)(DA_W-1 downto 12));
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- write RAM
ramwe_s <= '1';
-- reverse col/row order for transposition purpose
ramwaddro_s <= STD_LOGIC_VECTOR(col_2_reg & row_reg);
-- increment column counter
col_reg <= col_reg + 1;
col_2_reg <= col_2_reg + 1;
-- finished processing one input row
if col_reg = 0 then
row_reg <= row_reg + 1;
-- switch to 2nd memory
if row_reg = N - 1 then
wmemsel_reg <= not wmemsel_reg;
col_reg <= (others => '0');
end if;
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- write RAM
ramwe_s <= '1';
-- reverse col/row order for transposition purpose
ramwaddro <= STD_LOGIC_VECTOR(col_2_reg & row_reg);
-- increment column counter
col_reg <= col_reg + 1;
col_2_reg <= col_2_reg + 1;
-- finished processing one input row
if col_reg = 0 then
row_reg <= row_reg + 1;
-- switch to 2nd memory
if row_reg = N - 1 then
wmemsel_reg <= not wmemsel_reg;
col_reg <= (others => '0');
end if;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
col_2_reg <= (others => '0');
end if;
----------------------------------
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
col_2_reg <= (others => '0');
end if;
----------------------------------
end if;
end process;
-- output data pipeline
p_data_out_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
ramwe_d1 <= '0';
ramwe_d2 <= '0';
ramwe_d3 <= '0';
ramwe_d4 <= '0';
ramwaddro_d1 <= (others => '0');
ramwaddro_d2 <= (others => '0');
ramwaddro_d3 <= (others => '0');
ramwaddro_d4 <= (others => '0');
wmemsel_d1 <= '0';
wmemsel_d2 <= '0';
wmemsel_d3 <= '0';
wmemsel_d4 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
ramwe_d1 <= ramwe_s;
ramwe_d2 <= ramwe_d1;
ramwe_d3 <= ramwe_d2;
ramwe_d4 <= ramwe_d3;
ramwaddro_d1 <= ramwaddro_s;
ramwaddro_d2 <= ramwaddro_d1;
ramwaddro_d3 <= ramwaddro_d2;
ramwaddro_d4 <= ramwaddro_d3;
wmemsel_d1 <= wmemsel_reg;
wmemsel_d2 <= wmemsel_d1;
wmemsel_d3 <= wmemsel_d2;
wmemsel_d4 <= wmemsel_d3;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA_W) +
(RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA_W-2) & "00"),
DA_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA_W) +
(RESIZE(SIGNED(romodatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA_W-2) & "00"),
DA_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA_W-4) & "0000"),
DA_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA_W-4) & "0000"),
DA_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA_W-6) & "000000"),
DA_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA_W-6) & "000000"),
DA_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romedatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romodatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
end if;
end if;
end process;
-- read precomputed MAC results from LUT
romeaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(0) &
databuf_reg(1)(0) &
databuf_reg(2)(0) &
databuf_reg(3)(0);
romeaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(1) &
databuf_reg(1)(1) &
databuf_reg(2)(1) &
databuf_reg(3)(1);
romeaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(2) &
databuf_reg(1)(2) &
databuf_reg(2)(2) &
databuf_reg(3)(2);
romeaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(3) &
databuf_reg(1)(3) &
databuf_reg(2)(3) &
databuf_reg(3)(3);
romeaddro4 <= STD_LOGIC_VECTOR( col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(4) &
databuf_reg(1)(4) &
databuf_reg(2)(4) &
databuf_reg(3)(4);
romeaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(5) &
databuf_reg(1)(5) &
databuf_reg(2)(5) &
databuf_reg(3)(5);
romeaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(6) &
databuf_reg(1)(6) &
databuf_reg(2)(6) &
databuf_reg(3)(6);
romeaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(7) &
databuf_reg(1)(7) &
databuf_reg(2)(7) &
databuf_reg(3)(7);
romeaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(8) &
databuf_reg(1)(8) &
databuf_reg(2)(8) &
databuf_reg(3)(8);
-- odd
romoaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(0) &
databuf_reg(5)(0) &
databuf_reg(6)(0) &
databuf_reg(7)(0);
romoaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(1) &
databuf_reg(5)(1) &
databuf_reg(6)(1) &
databuf_reg(7)(1);
romoaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(2) &
databuf_reg(5)(2) &
databuf_reg(6)(2) &
databuf_reg(7)(2);
romoaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(3) &
databuf_reg(5)(3) &
databuf_reg(6)(3) &
databuf_reg(7)(3);
romoaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(4) &
databuf_reg(5)(4) &
databuf_reg(6)(4) &
databuf_reg(7)(4);
romoaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(5) &
databuf_reg(5)(5) &
databuf_reg(6)(5) &
databuf_reg(7)(5);
romoaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(6) &
databuf_reg(5)(6) &
databuf_reg(6)(6) &
databuf_reg(7)(6);
romoaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(7) &
databuf_reg(5)(7) &
databuf_reg(6)(7) &
databuf_reg(7)(7);
romoaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(8) &
databuf_reg(5)(8) &
databuf_reg(6)(8) &
databuf_reg(7)(8);
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 8 loop
-- even
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
p_romdatao_d1 : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
/trunk/source/DCT2D.VHD
32,55 → 32,15
port(
clk : in STD_LOGIC;
rst : in std_logic;
romedatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao9 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao10 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao9 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao10 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao : in T_ROM2DATAO;
romodatao : in T_ROM2DATAO;
ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dataready : in STD_LOGIC;
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro9 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro10 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro9 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro10 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro : out T_ROM2ADDRO;
romoaddro : out T_ROM2ADDRO;
ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
rmemsel : out STD_LOGIC;
datareadyack : out STD_LOGIC
92,20 → 52,43
type input_data2 is array (N-1 downto 0) of SIGNED(RAMDATA_W downto 0);
signal databuf_reg : input_data2;
signal latchbuf_reg : input_data2;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rmemsel_reg : STD_LOGIC;
signal stage1_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal databuf_reg : input_data2;
signal latchbuf_reg : input_data2;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rmemsel_reg : STD_LOGIC;
signal stage1_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal dataready_2_reg : STD_LOGIC;
signal even_not_odd : std_logic;
signal even_not_odd_d1 : std_logic;
signal even_not_odd_d2 : std_logic;
signal even_not_odd_d3 : std_logic;
signal even_not_odd_d4 : std_logic;
signal odv_d0 : std_logic;
signal odv_d1 : std_logic;
signal odv_d2 : std_logic;
signal odv_d3 : std_logic;
signal odv_d4 : std_logic;
signal odv_d5 : std_logic;
signal dcto_1 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_2 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_3 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_4 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_5 : std_logic_vector(DA2_W-1 downto 0);
signal romedatao_d1 : T_ROM2DATAO;
signal romodatao_d1 : T_ROM2DATAO;
signal romedatao_d2 : T_ROM2DATAO;
signal romodatao_d2 : T_ROM2DATAO;
signal romedatao_d3 : T_ROM2DATAO;
signal romodatao_d3 : T_ROM2DATAO;
signal romedatao_d4 : T_ROM2DATAO;
signal romodatao_d4 : T_ROM2DATAO;
begin
 
ramraddro_sg:
114,257 → 97,260
rmemsel_sg:
rmemsel <= rmemsel_reg;
process(clk)
process(clk,rst)
begin
if clk='1' and clk'event then
if rst = '1' then
stage2_cnt_reg <= (others => '1');
rmemsel_reg <= '0';
stage1_reg <= '0';
stage2_reg <= '0';
colram_reg <= (others => '0');
rowram_reg <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
dcto <= (others => '0');
odv <= '0';
colr_reg <= (others => '0');
rowr_reg <= (others => '0');
dataready_2_reg <= '0';
else
if rst = '1' then
stage2_cnt_reg <= (others => '1');
rmemsel_reg <= '0';
stage1_reg <= '0';
stage2_reg <= '0';
colram_reg <= (others => '0');
rowram_reg <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
odv_d0 <= '0';
colr_reg <= (others => '0');
rowr_reg <= (others => '0');
dataready_2_reg <= '0';
elsif clk='1' and clk'event then
stage2_reg <= '0';
odv_d0 <= '0';
datareadyack <= '0';
dataready_2_reg <= dataready;
stage2_reg <= '0';
odv <= '0';
datareadyack <= '0';
dataready_2_reg <= dataready;
----------------------------------
-- read DCT 1D to barrel shifer
----------------------------------
if stage1_reg = '1' then
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
colram_reg <= colram_reg + 1;
colr_reg <= colr_reg + 1;
if colram_reg = N-2 then
rowr_reg <= rowr_reg + 1;
end if;
if colram_reg = N-1 then
rowram_reg <= rowram_reg + 1;
if rowram_reg = N-1 then
stage1_reg <= '0';
colr_reg <= (others => '0');
-- release memory
rmemsel_reg <= not rmemsel_reg;
end if;
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
-- 8 point input latched
stage2_reg <= '1';
end if;
----------------------------------
-- read DCT 1D to barrel shifer
----------------------------------
if stage1_reg = '1' then
 
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
colram_reg <= colram_reg + 1;
colr_reg <= colr_reg + 1;
if colram_reg = N-2 then
rowr_reg <= rowr_reg + 1;
end if;
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
if stage2_cnt_reg(0) = '0' then
dcto <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao0),DA2_W) +
(RESIZE(SIGNED(romedatao1),DA2_W-1) & '0') +
(RESIZE(SIGNED(romedatao2),DA2_W-2) & "00") +
(RESIZE(SIGNED(romedatao3),DA2_W-3) & "000") +
(RESIZE(SIGNED(romedatao4),DA2_W-4) & "0000") +
(RESIZE(SIGNED(romedatao5),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romedatao6),DA2_W-6) & "000000") +
(RESIZE(SIGNED(romedatao7),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romedatao8),DA2_W-8) & "00000000") +
(RESIZE(SIGNED(romedatao9),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romedatao10),DA2_W-10) & "0000000000"),
DA2_W)(DA2_W-1 downto 12));
else
dcto <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao0),DA2_W) +
(RESIZE(SIGNED(romodatao1),DA2_W-1) & '0') +
(RESIZE(SIGNED(romodatao2),DA2_W-2) & "00") +
(RESIZE(SIGNED(romodatao3),DA2_W-3) & "000") +
(RESIZE(SIGNED(romodatao4),DA2_W-4) & "0000") +
(RESIZE(SIGNED(romodatao5),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romodatao6),DA2_W-6) & "000000") +
(RESIZE(SIGNED(romodatao7),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romodatao8),DA2_W-8) & "00000000") +
(RESIZE(SIGNED(romodatao9),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romodatao10),DA2_W-10) & "0000000000"),
DA2_W)(DA2_W-1 downto 12));
if colram_reg = N-1 then
rowram_reg <= rowram_reg + 1;
if rowram_reg = N-1 then
stage1_reg <= '0';
colr_reg <= (others => '0');
-- release memory
rmemsel_reg <= not rmemsel_reg;
end if;
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
-- write RAM
odv <= '1';
-- increment column counter
col_reg <= col_reg + 1;
-- finished processing one input row
if col_reg = N - 1 then
row_reg <= row_reg + 1;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
end if;
--------------------------------
-- 8 point input latched
stage2_reg <= '1';
end if;
end if;
----------------------------------
-- wait for new data
----------------------------------
-- one of ram buffers has new data, process it
if dataready = '1' and dataready_2_reg = '0' then
stage1_reg <= '1';
-- to account for 1T RAM delay, increment RAM address counter
colram_reg <= (others => '0');
colr_reg <= (0=>'1',others => '0');
datareadyack <= '1';
end if;
----------------------------------
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- output data valid
odv_d0 <= '1';
-- increment column counter
col_reg <= col_reg + 1;
-- finished processing one input row
if col_reg = N - 1 then
row_reg <= row_reg + 1;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
end if;
--------------------------------
----------------------------------
-- wait for new data
----------------------------------
-- one of ram buffers has new data, process it
if dataready = '1' and dataready_2_reg = '0' then
stage1_reg <= '1';
-- to account for 1T RAM delay, increment RAM address counter
colram_reg <= (others => '0');
colr_reg <= (0=>'1',others => '0');
datareadyack <= '1';
end if;
----------------------------------
end if;
end process;
p_data_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
even_not_odd_d4 <= '0';
odv_d1 <= '0';
odv_d2 <= '0';
odv_d3 <= '0';
odv_d4 <= '0';
odv_d5 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
dcto_5 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
even_not_odd_d4 <= even_not_odd_d3;
odv_d1 <= odv_d0;
odv_d2 <= odv_d1;
odv_d3 <= odv_d2;
odv_d4 <= odv_d3;
odv_d5 <= odv_d4;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA2_W) +
(RESIZE(SIGNED(romedatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA2_W-2) & "00"),
DA2_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA2_W) +
(RESIZE(SIGNED(romodatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA2_W-2) & "00"),
DA2_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romedatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romodatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
end if;
if even_not_odd_d4 = '0' then
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romedatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romedatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
else
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romodatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romodatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
end if;
end if;
end process;
dcto <= dcto_5(DA2_W-1 downto 12);
odv <= odv_d5;
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 10 loop
-- read precomputed MAC results from LUT
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
 
-- read precomputed MAC results from LUT
romeaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(0) &
databuf_reg(1)(0) &
databuf_reg(2)(0) &
databuf_reg(3)(0);
romeaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(1) &
databuf_reg(1)(1) &
databuf_reg(2)(1) &
databuf_reg(3)(1);
romeaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(2) &
databuf_reg(1)(2) &
databuf_reg(2)(2) &
databuf_reg(3)(2);
romeaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(3) &
databuf_reg(1)(3) &
databuf_reg(2)(3) &
databuf_reg(3)(3);
romeaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(4) &
databuf_reg(1)(4) &
databuf_reg(2)(4) &
databuf_reg(3)(4);
romeaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(5) &
databuf_reg(1)(5) &
databuf_reg(2)(5) &
databuf_reg(3)(5);
romeaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(6) &
databuf_reg(1)(6) &
databuf_reg(2)(6) &
databuf_reg(3)(6);
romeaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(7) &
databuf_reg(1)(7) &
databuf_reg(2)(7) &
databuf_reg(3)(7);
romeaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(8) &
databuf_reg(1)(8) &
databuf_reg(2)(8) &
databuf_reg(3)(8);
romeaddro9 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(9) &
databuf_reg(1)(9) &
databuf_reg(2)(9) &
databuf_reg(3)(9);
romeaddro10 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(10) &
databuf_reg(1)(10) &
databuf_reg(2)(10) &
databuf_reg(3)(10);
-- odd
romoaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(0) &
databuf_reg(5)(0) &
databuf_reg(6)(0) &
databuf_reg(7)(0);
romoaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(1) &
databuf_reg(5)(1) &
databuf_reg(6)(1) &
databuf_reg(7)(1);
romoaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(2) &
databuf_reg(5)(2) &
databuf_reg(6)(2) &
databuf_reg(7)(2);
romoaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(3) &
databuf_reg(5)(3) &
databuf_reg(6)(3) &
databuf_reg(7)(3);
romoaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(4) &
databuf_reg(5)(4) &
databuf_reg(6)(4) &
databuf_reg(7)(4);
romoaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(5) &
databuf_reg(5)(5) &
databuf_reg(6)(5) &
databuf_reg(7)(5);
romoaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(6) &
databuf_reg(5)(6) &
databuf_reg(6)(6) &
databuf_reg(7)(6);
romoaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(7) &
databuf_reg(5)(7) &
databuf_reg(6)(7) &
databuf_reg(7)(7);
romoaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(8) &
databuf_reg(5)(8) &
databuf_reg(6)(8) &
databuf_reg(7)(8);
romoaddro9 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(9) &
databuf_reg(5)(9) &
databuf_reg(6)(9) &
databuf_reg(7)(9);
romoaddro10 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(10) &
databuf_reg(5)(10) &
databuf_reg(6)(10) &
databuf_reg(7)(10);
p_romdatao_dly : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
romedatao_d4 <= (others => (others => '0'));
romodatao_d4 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
romedatao_d4 <= romedatao_d3;
romodatao_d4 <= romodatao_d3;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
/trunk/source/DBUFCTL.VHD
51,25 → 51,21
memswitchrd_reg <= rmemsel;
 
MEM_SWITCH : process(clk)
MEM_SWITCH : process(clk,rst)
begin
if clk = '1' and clk'event then
if rst = '1' then
memswitchwr_reg <= '0'; -- initially mem 1 is selected
dataready <= '0';
else
memswitchwr_reg <= wmemsel;
if wmemsel /= memswitchwr_reg then
dataready <= '1';
end if;
if datareadyack = '1' then
dataready <= '0';
end if;
end if;
if rst = '1' then
memswitchwr_reg <= '0'; -- initially mem 1 is selected
dataready <= '0';
elsif clk = '1' and clk'event then
memswitchwr_reg <= wmemsel;
if wmemsel /= memswitchwr_reg then
dataready <= '1';
end if;
if datareadyack = '1' then
dataready <= '0';
end if;
end if;
end process;
/trunk/source/MDCT.VHD
1,7 → 1,7
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- COPYRIGHT (C) 2006-2009 --
-- --
--------------------------------------------------------------------------------
--
47,330 → 47,55
 
architecture RTL of MDCT is
 
------------------------------
-- 1D DCT
------------------------------
component DCT1D
port(
clk : in STD_LOGIC;
rst : in std_logic;
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
romedatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal ramdatao_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramraddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramdatai_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramwe_s : STD_LOGIC;
signal romedatao_s : T_ROM1DATAO;
signal romodatao_s : T_ROM1DATAO;
signal romeaddro_s : T_ROM1ADDRO;
signal romoaddro_s : T_ROM1ADDRO;
signal rome2datao_s : T_ROM2DATAO;
signal romo2datao_s : T_ROM2DATAO;
signal rome2addro_s : T_ROM2ADDRO;
signal romo2addro_s : T_ROM2ADDRO;
signal odv2_s : STD_LOGIC;
signal dcto2_s : STD_LOGIC_VECTOR(OP_W-1 downto 0);
signal trigger2_s : STD_LOGIC;
signal trigger1_s : STD_LOGIC;
signal ramdatao1_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramdatao2_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramwe1_s : STD_LOGIC;
signal ramwe2_s : STD_LOGIC;
signal memswitchrd_s : STD_LOGIC;
signal memswitchwr_s : STD_LOGIC;
signal wmemsel_s : STD_LOGIC;
signal rmemsel_s : STD_LOGIC;
signal dataready_s : STD_LOGIC;
signal datareadyack_s : STD_LOGIC;
 
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
ramwe : out STD_LOGIC;
wmemsel : out STD_LOGIC
);
end component;
begin
 
------------------------------
-- 1D DCT (2nd stage)
------------------------------
component DCT2D
port(
clk : in STD_LOGIC;
rst : in std_logic;
romedatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao9 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao10 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao9 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao10 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dataready : in STD_LOGIC;
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro9 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro10 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro9 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro10 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
rmemsel : out STD_LOGIC;
datareadyack : out STD_LOGIC
);
end component;
 
------------------------------
-- RAM
------------------------------
component RAM
port (
d : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
waddr : in STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
raddr : in STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0)
);
end component;
 
------------------------------
-- ROME
------------------------------
component ROME
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end component;
 
------------------------------
-- ROMO
------------------------------
component ROMO
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end component;
 
------------------------------
-- DBUFCTL
------------------------------
component DBUFCTL
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
wmemsel : in STD_LOGIC;
rmemsel : in STD_LOGIC;
datareadyack : in STD_LOGIC;
memswitchwr : out STD_LOGIC;
memswitchrd : out STD_LOGIC;
dataready : out STD_LOGIC
);
end component;
 
signal romedatao0_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romedatao1_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romedatao2_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romedatao3_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romedatao4_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romedatao5_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romedatao6_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romedatao7_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romedatao8_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romodatao0_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romodatao1_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romodatao2_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romodatao3_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romodatao4_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romodatao5_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romodatao6_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romodatao7_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romodatao8_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal ramdatao_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal romeaddro0_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romeaddro1_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romeaddro2_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romeaddro3_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romeaddro4_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romeaddro5_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romeaddro6_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romeaddro7_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romeaddro8_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romoaddro0_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romoaddro1_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romoaddro2_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romoaddro3_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romoaddro4_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romoaddro5_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romoaddro6_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romoaddro7_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romoaddro8_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal ramraddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramdatai_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramwe_s : STD_LOGIC;
signal rome2datao0_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal rome2datao1_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal rome2datao2_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal rome2datao3_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal rome2datao4_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal rome2datao5_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal rome2datao6_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal rome2datao7_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal rome2datao8_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal rome2datao9_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal rome2datao10_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romo2datao0_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romo2datao1_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romo2datao2_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romo2datao3_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romo2datao4_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romo2datao5_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romo2datao6_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romo2datao7_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romo2datao8_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romo2datao9_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romo2datao10_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal rome2addro0_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal rome2addro1_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal rome2addro2_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal rome2addro3_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal rome2addro4_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal rome2addro5_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal rome2addro6_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal rome2addro7_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal rome2addro8_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal rome2addro9_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal rome2addro10_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romo2addro0_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romo2addro1_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romo2addro2_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romo2addro3_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romo2addro4_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romo2addro5_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romo2addro6_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romo2addro7_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romo2addro8_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romo2addro9_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romo2addro10_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal odv2_s : STD_LOGIC;
signal dcto2_s : STD_LOGIC_VECTOR(OP_W-1 downto 0);
signal trigger2_s : STD_LOGIC;
signal trigger1_s : STD_LOGIC;
signal ramdatao1_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramdatao2_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramwe1_s : STD_LOGIC;
signal ramwe2_s : STD_LOGIC;
signal memswitchrd_s : STD_LOGIC;
signal memswitchwr_s : STD_LOGIC;
signal wmemsel_s : STD_LOGIC;
signal rmemsel_s : STD_LOGIC;
signal dataready_s : STD_LOGIC;
signal datareadyack_s : STD_LOGIC;
 
begin
 
------------------------------
-- 1D DCT port map
------------------------------
U_DCT1D : DCT1D
U_DCT1D : entity work.DCT1D
port map(
clk => clk,
rst => rst,
dcti => dcti,
idv => idv,
romedatao0 => romedatao0_s,
romedatao1 => romedatao1_s,
romedatao2 => romedatao2_s,
romedatao3 => romedatao3_s,
romedatao4 => romedatao4_s,
romedatao5 => romedatao5_s,
romedatao6 => romedatao6_s,
romedatao7 => romedatao7_s,
romedatao8 => romedatao8_s,
romodatao0 => romodatao0_s,
romodatao1 => romodatao1_s,
romodatao2 => romodatao2_s,
romodatao3 => romodatao3_s,
romodatao4 => romodatao4_s,
romodatao5 => romodatao5_s,
romodatao6 => romodatao6_s,
romodatao7 => romodatao7_s,
romodatao8 => romodatao8_s,
romedatao => romedatao_s,
romodatao => romodatao_s,
odv => odv1,
dcto => dcto1,
romeaddro0 => romeaddro0_s,
romeaddro1 => romeaddro1_s,
romeaddro2 => romeaddro2_s,
romeaddro3 => romeaddro3_s,
romeaddro4 => romeaddro4_s,
romeaddro5 => romeaddro5_s,
romeaddro6 => romeaddro6_s,
romeaddro7 => romeaddro7_s,
romeaddro8 => romeaddro8_s,
romoaddro0 => romoaddro0_s,
romoaddro1 => romoaddro1_s,
romoaddro2 => romoaddro2_s,
romoaddro3 => romoaddro3_s,
romoaddro4 => romoaddro4_s,
romoaddro5 => romoaddro5_s,
romoaddro6 => romoaddro6_s,
romoaddro7 => romoaddro7_s,
romoaddro8 => romoaddro8_s,
romeaddro => romeaddro_s,
romoaddro => romoaddro_s,
ramwaddro => ramwaddro_s,
ramdatai => ramdatai_s,
ramwe => ramwe_s,
380,59 → 105,19
------------------------------
-- 1D DCT port map
------------------------------
U_DCT2D : DCT2D
U_DCT2D : entity work.DCT2D
port map(
clk => clk,
rst => rst,
romedatao0 => rome2datao0_s,
romedatao1 => rome2datao1_s,
romedatao2 => rome2datao2_s,
romedatao3 => rome2datao3_s,
romedatao4 => rome2datao4_s,
romedatao5 => rome2datao5_s,
romedatao6 => rome2datao6_s,
romedatao7 => rome2datao7_s,
romedatao8 => rome2datao8_s,
romedatao9 => rome2datao9_s,
romedatao10 => rome2datao10_s,
romodatao0 => romo2datao0_s,
romodatao1 => romo2datao1_s,
romodatao2 => romo2datao2_s,
romodatao3 => romo2datao3_s,
romodatao4 => romo2datao4_s,
romodatao5 => romo2datao5_s,
romodatao6 => romo2datao6_s,
romodatao7 => romo2datao7_s,
romodatao8 => romo2datao8_s,
romodatao9 => romo2datao9_s,
romodatao10 => romo2datao10_s,
romedatao => rome2datao_s,
romodatao => romo2datao_s,
ramdatao => ramdatao_s,
dataready => dataready_s,
odv => odv,
dcto => dcto,
romeaddro0 => rome2addro0_s,
romeaddro1 => rome2addro1_s,
romeaddro2 => rome2addro2_s,
romeaddro3 => rome2addro3_s,
romeaddro4 => rome2addro4_s,
romeaddro5 => rome2addro5_s,
romeaddro6 => rome2addro6_s,
romeaddro7 => rome2addro7_s,
romeaddro8 => rome2addro8_s,
romeaddro9 => rome2addro9_s,
romeaddro10 => rome2addro10_s,
romoaddro0 => romo2addro0_s,
romoaddro1 => romo2addro1_s,
romoaddro2 => romo2addro2_s,
romoaddro3 => romo2addro3_s,
romoaddro4 => romo2addro4_s,
romoaddro5 => romo2addro5_s,
romoaddro6 => romo2addro6_s,
romoaddro7 => romo2addro7_s,
romoaddro8 => romo2addro8_s,
romoaddro9 => romo2addro9_s,
romoaddro10 => romo2addro10_s,
romeaddro => rome2addro_s,
romoaddro => romo2addro_s,
ramraddro => ramraddro_s,
rmemsel => rmemsel_s,
datareadyack => datareadyack_s
441,7 → 126,7
------------------------------
-- RAM1 port map
------------------------------
U1_RAM : RAM
U1_RAM : entity work.RAM
port map (
d => ramdatai_s,
waddr => ramwaddro_s,
455,7 → 140,7
------------------------------
-- RAM2 port map
------------------------------
U2_RAM : RAM
U2_RAM : entity work.RAM
port map (
d => ramdatai_s,
waddr => ramwaddro_s,
474,7 → 159,7
------------------------------
-- DBUFCTL
------------------------------
U_DBUFCTL : DBUFCTL
U_DBUFCTL : entity work.DBUFCTL
port map(
clk => clk,
rst => rst,
488,416 → 173,47
);
 
------------------------------
-- ROME port map
-- 1st stage ROMs
------------------------------
U1_ROME0 : ROME
port map(
addr => romeaddro0_s,
clk => clk,
datao => romedatao0_s
);
------------------------------
-- ROME port map
------------------------------
U1_ROME1 : ROME
G_ROM_ST1 : for i in 0 to 8 generate
U1_ROME : entity work.ROME
port map(
addr => romeaddro1_s,
clk => clk,
addr => romeaddro_s(i),
clk => clk,
datao => romedatao1_s
datao => romedatao_s(i)
);
------------------------------
-- ROME port map
------------------------------
U1_ROME2 : ROME
U1_ROMO : entity work.ROMO
port map(
addr => romeaddro2_s,
clk => clk,
datao => romedatao2_s
);
------------------------------
-- ROME port map
------------------------------
U1_ROME3 : ROME
port map(
addr => romeaddro3_s,
clk => clk,
datao => romedatao3_s
);
------------------------------
-- ROME port map
------------------------------
U1_ROME4 : ROME
port map(
addr => romeaddro4_s,
addr => romoaddro_s(i),
clk => clk,
datao => romedatao4_s
);
------------------------------
-- ROME port map
------------------------------
U1_ROME5 : ROME
port map(
addr => romeaddro5_s,
clk => clk,
datao => romedatao5_s
);
------------------------------
-- ROME port map
------------------------------
U1_ROME6 : ROME
port map(
addr => romeaddro6_s,
clk => clk,
datao => romedatao6_s
);
------------------------------
-- ROME port map
------------------------------
U1_ROME7 : ROME
port map(
addr => romeaddro7_s,
clk => clk,
datao => romedatao7_s
);
------------------------------
-- ROME port map
------------------------------
U1_ROME8 : ROME
port map(
addr => romeaddro8_s,
clk => clk,
datao => romedatao8_s
);
datao => romodatao_s(i)
);
end generate G_ROM_ST1;
 
------------------------------
-- ROMO port map
-- 2nd stage ROMs
------------------------------
U1_ROMO0 : ROMO
G_ROM_ST2 : for i in 0 to 10 generate
U2_ROME : entity work.ROME
port map(
addr => romoaddro0_s,
clk => clk,
datao => romodatao0_s
);
------------------------------
-- ROMO port map
------------------------------
U1_ROMO1 : ROMO
port map(
addr => romoaddro1_s,
addr => rome2addro_s(i),
clk => clk,
datao => romodatao1_s
datao => rome2datao_s(i)
);
------------------------------
-- ROMO port map
------------------------------
U1_ROMO2 : ROMO
port map(
addr => romoaddro2_s,
clk => clk,
datao => romodatao2_s
);
------------------------------
-- ROMO port map
------------------------------
U1_ROMO3 : ROMO
port map(
addr => romoaddro3_s,
clk => clk,
datao => romodatao3_s
);
------------------------------
-- ROMO port map
------------------------------
U1_ROMO4 : ROMO
port map(
addr => romoaddro4_s,
clk => clk,
datao => romodatao4_s
);
------------------------------
-- ROMO port map
------------------------------
U1_ROMO5 : ROMO
port map(
addr => romoaddro5_s,
clk => clk,
datao => romodatao5_s
);
------------------------------
-- ROMO port map
------------------------------
U1_ROMO6 : ROMO
port map(
addr => romoaddro6_s,
clk => clk,
datao => romodatao6_s
);
------------------------------
-- ROMO port map
------------------------------
U1_ROMO7 : ROMO
port map(
addr => romoaddro7_s,
clk => clk,
datao => romodatao7_s
);
------------------------------
-- ROMO port map
------------------------------
U1_ROMO8 : ROMO
port map(
addr => romoaddro8_s,
clk => clk,
datao => romodatao8_s
);
------------------------------
-- 2 stage ROMs
------------------------------
------------------------------
-- ROME port map
------------------------------
U2_ROME0 : ROME
U2_ROMO : entity work.ROMO
port map(
addr => rome2addro0_s,
addr => romo2addro_s(i),
clk => clk,
datao => rome2datao0_s
datao => romo2datao_s(i)
);
------------------------------
-- ROME port map
------------------------------
U2_ROME1 : ROME
port map(
addr => rome2addro1_s,
clk => clk,
datao => rome2datao1_s
);
------------------------------
-- ROME port map
------------------------------
U2_ROME2 : ROME
port map(
addr => rome2addro2_s,
clk => clk,
datao => rome2datao2_s
);
------------------------------
-- ROME port map
------------------------------
U2_ROME3 : ROME
port map(
addr => rome2addro3_s,
clk => clk,
datao => rome2datao3_s
);
------------------------------
-- ROME port map
------------------------------
U2_ROME4 : ROME
port map(
addr => rome2addro4_s,
clk => clk,
datao => rome2datao4_s
);
------------------------------
-- ROME port map
------------------------------
U2_ROME5 : ROME
port map(
addr => rome2addro5_s,
clk => clk,
datao => rome2datao5_s
);
------------------------------
-- ROME port map
------------------------------
U2_ROME6 : ROME
port map(
addr => rome2addro6_s,
clk => clk,
datao => rome2datao6_s
);
------------------------------
-- ROME port map
------------------------------
U2_ROME7 : ROME
port map(
addr => rome2addro7_s,
clk => clk,
datao => rome2datao7_s
);
------------------------------
-- ROME port map
------------------------------
U2_ROME8 : ROME
port map(
addr => rome2addro8_s,
clk => clk,
datao => rome2datao8_s
);
------------------------------
-- ROME port map
------------------------------
U2_ROME9 : ROME
port map(
addr => rome2addro9_s,
clk => clk,
datao => rome2datao9_s
);
------------------------------
-- ROME port map
------------------------------
U2_ROME10 : ROME
port map(
addr => rome2addro10_s,
clk => clk,
datao => rome2datao10_s
);
 
------------------------------
-- ROMO port map
------------------------------
U2_ROMO0 : ROMO
port map(
addr => romo2addro0_s,
clk => clk,
datao => romo2datao0_s
);
------------------------------
-- ROMO port map
------------------------------
U2_ROMO1 : ROMO
port map(
addr => romo2addro1_s,
clk => clk,
datao => romo2datao1_s
);
------------------------------
-- ROMO port map
------------------------------
U2_ROMO2 : ROMO
port map(
addr => romo2addro2_s,
clk => clk,
datao => romo2datao2_s
);
------------------------------
-- ROMO port map
------------------------------
U2_ROMO3 : ROMO
port map(
addr => romo2addro3_s,
clk => clk,
datao => romo2datao3_s
);
------------------------------
-- ROMO port map
------------------------------
U2_ROMO4 : ROMO
port map(
addr => romo2addro4_s,
clk => clk,
datao => romo2datao4_s
);
------------------------------
-- ROMO port map
------------------------------
U2_ROMO5 : ROMO
port map(
addr => romo2addro5_s,
clk => clk,
datao => romo2datao5_s
);
------------------------------
-- ROMO port map
------------------------------
U2_ROMO6 : ROMO
port map(
addr => romo2addro6_s,
clk => clk,
datao => romo2datao6_s
);
------------------------------
-- ROMO port map
------------------------------
U2_ROMO7 : ROMO
port map(
addr => romo2addro7_s,
clk => clk,
datao => romo2datao7_s
);
------------------------------
-- ROMO port map
------------------------------
U2_ROMO8 : ROMO
port map(
addr => romo2addro8_s,
clk => clk,
datao => romo2datao8_s
);
------------------------------
-- ROMO port map
------------------------------
U2_ROMO9 : ROMO
port map(
addr => romo2addro9_s,
clk => clk,
datao => romo2datao9_s
);
------------------------------
-- ROMO port map
------------------------------
U2_ROMO10 : ROMO
port map(
addr => romo2addro10_s,
clk => clk,
datao => romo2datao10_s
);
end generate G_ROM_ST2;
end RTL;
/trunk/source/MDCT_PKG.vhd
56,6 → 56,11
constant FM : INTEGER := -1138;
constant GM : INTEGER := -400;
type T_ROM1DATAO is array(0 to 8) of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
type T_ROM1ADDRO is array(0 to 8) of STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
type T_ROM2DATAO is array(0 to 10) of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
type T_ROM2ADDRO is array(0 to 10) of STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
 
 
end MDCT_PKG;

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