URL
https://opencores.org/ocsvn/mips789/mips789/trunk
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/mips789
- from Rev 60 to Rev 61
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Rev 60 → Rev 61
/trunk/rtl/verilog/dvc.v
0,0 → 1,94
/****************************************************************** |
* * |
* Author: Liwei * |
* * |
* This file is part of the "mips789" project. * |
* Downloaded from: * |
* http://www.opencores.org/pdownloads.cgi/list/mips789 * |
* * |
* If you encountered any problem, please contact me via * |
* Email:mcupro@opencores.org or mcupro@163.com * |
* * |
******************************************************************/ |
|
`include "mips789_defs.v" |
|
module tmr0 ( |
input clk, |
input clr, |
input[31:0] din , |
input ld, |
input tmr_en, |
output tmr_req, |
output [31:0] cntr_o |
); |
reg [31:0]s_cntr; |
reg [31:0]cntr; |
assign cntr_o=cntr; |
always @(posedge clk) |
if (ld) |
s_cntr<= din; |
always @(posedge clk) |
if (ld) |
cntr<=din; |
else if (cntr==0) |
cntr<=s_cntr; |
else if (tmr_en) |
cntr<=cntr-1; |
wire w_irq = cntr==0; |
tmr_d itmr_d( |
.clr(clr), |
.clk(clk), |
.d(w_irq), |
.q(tmr_req) |
); |
endmodule |
|
|
module tmr_d(input clr,input clk,input d,output reg q ); |
|
always @(posedge clk) |
|
if (clr) q<=0; |
else q<=d|q; |
|
endmodule |
|
module seg7led_cv( |
input [7:0] data, |
output reg [6:0] seg7led2, |
output reg [6:0] seg7led1 |
); |
|
always @(*) |
begin |
seg7led2= seg(data[3:0]) ; |
seg7led1= seg(data[7:4]) ; |
end |
|
function [7:0] seg; |
input [3:0] addr; |
begin |
case(addr) |
0: seg = 7'b011_1111; |
1: seg = 7'b000_0110; |
2: seg = 7'b101_1011; |
3: seg = 7'b100_1111; |
4: seg = 7'b110_0110; |
5: seg = 7'b110_1101; |
6: seg = 7'b111_1100; |
7: seg = 7'b000_0111; |
8: seg = 7'b111_1111; |
9: seg = 7'b110_0111; |
10: seg = 7'b111_0111; |
11: seg = 7'b111_1100; |
12: seg = 7'b101_1000; |
13: seg = 7'b101_1110; |
14: seg = 7'b111_1001; |
15: seg = 7'b111_0001; |
default seg = 7'bx; |
endcase |
end |
endfunction |
|
endmodule |
/trunk/rtl/verilog/RF_components.v
0,0 → 1,163
/****************************************************************** |
* * |
* Author: Liwei * |
* * |
* This file is part of the "mips789" project. * |
* Downloaded from: * |
* http://www.opencores.org/pdownloads.cgi/list/mips789 * |
* * |
* If you encountered any problem, please contact me via * |
* Email:mcupro@opencores.org or mcupro@163.com * |
* * |
******************************************************************/ |
|
`include "mips789_defs.v" |
module ext( |
input [31:0] ins_i , |
output reg [31:0] res , |
input [2:0]ctl |
); |
|
wire [25:0] instr25_0; |
assign instr25_0 = ins_i[25:0] ; |
|
wire[15:0] sign = {16{instr25_0[15]}}; |
|
always @ (*) |
case (ctl) |
`EXT_SIGN :res ={sign,instr25_0[15:0]};//sign |
`EXT_UNSIGN :res ={16'b0,instr25_0[15:0]};//zeroext |
`EXT_J :res ={4'b0,instr25_0[25:0],2'b0};//jmp |
`EXT_B :res ={sign[13:0],instr25_0[15:0],2'B0};//branch |
`EXT_SA :res ={27'b0,instr25_0[10:6]} ;//sll,srl |
`EXT_S2H :res ={instr25_0[15:0],16'B0};//shift to high |
default: res=32'bx; |
endcase |
endmodule |
|
|
module compare ( |
input [31:0] s, |
input [31:0] t, |
input [2:0]ctl, |
output reg res |
); |
always @ (*) |
case (ctl) |
`CMP_BEQ: res = (s==t); |
`CMP_BNE: res = (s!=t); |
`CMP_BLTZ: res = s[31]; |
`CMP_BGTZ: res = ~s[31] && (|s[30:0]); |
`CMP_BLEZ: res = s[31] |(~|s); |
`CMP_BGEZ: res = ~s[31]; |
default res=1'Bx; |
endcase |
endmodule |
|
|
module pc_gen( |
input [2:0]ctl, |
output reg [31:0]pc_next, |
input [3:0] pc_prectl, |
input check, |
input [31:0]s, |
input [31:0]pc, |
input [31:0]zz_spc, |
input [31:0]imm, |
input [31:0]irq |
); |
|
wire [32:0] br_addr = pc + imm ; |
always @ (*) |
if(pc_prectl == `PC_IGN ) |
begin |
case (ctl) |
`PC_RET : pc_next = zz_spc ; |
`PC_J : pc_next ={pc[31:28],imm[27:0]}; |
`PC_JR : pc_next = s; |
`PC_BC : pc_next = (check)?({br_addr[31:0]}):(pc+4); |
default |
/* `PC_NEXT :*/ pc_next = pc + 4 ; |
endcase |
end |
else |
begin |
case (pc_prectl) |
`PC_KEP : pc_next=pc; |
`PC_IRQ : pc_next=irq; |
default |
/* `PC_RST : pc_next='d0;*/ |
pc_next =0; |
endcase |
end |
|
endmodule |
|
|
|
module reg_array( |
data, |
wraddress, |
rdaddress_a, |
rdaddress_b, |
wren, |
clock, |
qa, |
qb, |
rd_clk_cls, |
// bank_sel |
); |
|
input [31:0] data; |
input [4:0] wraddress; |
input [4:0] rdaddress_a; |
input [4:0] rdaddress_b; |
// input bank_sel; |
input rd_clk_cls; |
input wren; |
|
reg [31:0] r_data; |
reg [4:0] r_wraddress; |
reg [4:0] r_rdaddress_a; |
reg [4:0] r_rdaddress_b; |
|
reg r_wren; |
input clock; |
output [31:0] qa; |
output [31:0] qb; |
reg [31:0]reg_bank[0:31]; |
|
integer i; |
initial |
begin |
for(i=0;i<32;i=i+1) |
reg_bank[i]=0; |
end |
|
always@(posedge clock) |
begin |
r_data <=data; |
r_wraddress<=wraddress; |
r_wren<=wren; |
end |
|
always@(posedge clock) |
if (~rd_clk_cls) |
begin |
r_rdaddress_a <=rdaddress_a; |
r_rdaddress_b <=rdaddress_b; |
end |
|
always@(posedge clock) |
if (r_wren) |
reg_bank[r_wraddress] <= r_data ; |
|
assign qa=(r_rdaddress_a[4:0]==0)?0: |
((r_wraddress==r_rdaddress_a)&&(1==r_wren))?r_data: |
reg_bank[r_rdaddress_a]; |
|
assign qb=(r_rdaddress_b[4:0]==0)?0: |
((r_wraddress==r_rdaddress_b)&&(1==r_wren))?r_data: |
reg_bank[r_rdaddress_b]; |
|
endmodule |
/trunk/rtl/verilog/ulit.v
0,0 → 1,223
/****************************************************************** |
* * |
* Author: Liwei * |
* * |
* This file is part of the "mips789" project. * |
* Downloaded from: * |
* http://www.opencores.org/pdownloads.cgi/list/mips789 * |
* * |
* If you encountered any problem, please contact me via * |
* Email:mcupro@opencores.org or mcupro@163.com * |
* * |
******************************************************************/ |
|
`include "mips789_defs.v" |
|
module cal_cpi ( //just used to calculate CPI(Cycles Per Instruction) for stimulation |
input clk, |
input rst, |
input is_nop, |
output reg [100:0] ins_no, |
output reg [100:0] clk_no); |
|
always @(posedge clk ) |
if (~rst )clk_no=0; |
else |
clk_no = 1+clk_no; |
|
always @(posedge clk ) |
if (~rst )ins_no=0; |
else if (~is_nop) |
ins_no = 1+ins_no; |
endmodule |
|
|
module add32( |
input [31:0]d_i, |
output [31:0]d_o |
); |
assign d_o = d_i + 4; |
endmodule |
|
|
module jack( |
input [31:0] ins_i , |
output [4:0] rs_o, |
output [4:0] rt_o, |
output [4:0] rd_o |
); |
assign rs_o = ins_i[25:21]; |
assign rt_o = ins_i[20:16]; |
assign rd_o = ins_i[15:11]; |
endmodule |
|
|
|
module wb_mux( |
input [31:0]alu_i, |
input [31:0]dmem_i, |
input sel, |
output [31:0]wb_o |
); |
|
assign wb_o = (sel==`WB_MEM)?dmem_i:alu_i; |
|
endmodule |
|
module or32( |
input [31:0]a, |
input [31:0]b, |
output [31:0]c |
); |
|
assign c = a|b ; |
|
endmodule |
|
module rd_sel( |
input [4:0]rd_i, |
input [4:0]rt_i, |
input[1:0] ctl, |
output reg [4:0]rd_o |
); |
|
always @(*) |
case (ctl) |
`RD_RD:rd_o=rd_i; |
`RD_RT:rd_o=rt_i; |
`RD_R31:rd_o='d31; |
default : |
rd_o=0; |
endcase |
endmodule |
/* |
|
module dly3clk( |
input r1_i, |
output reg r1_o, |
input clk, |
input rst |
); |
reg r1_r,r1_rr; |
|
always@(posedge clk) |
if(rst)r1_r<=0; |
else r1_r<=r1_i; |
|
always@(posedge clk) |
if(rst)r1_rr<=0; |
else r1_rr<=r1_r; |
|
always@(posedge clk) |
if(rst)r1_o<=0; |
else r1_o<=r1_rr; |
|
endmodule */ |
|
//these modules below are genated automaticly by a software written in C language... |
//Some of these may not be used |
|
module ext_ctl_reg_clr_cls(input[`EXT_CTL_LEN-1:0] ext_ctl_i,output reg[`EXT_CTL_LEN-1:0] ext_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) ext_ctl_o<=0;else if(cls)ext_ctl_o<=ext_ctl_o;else ext_ctl_o<=ext_ctl_i;endmodule |
module rd_sel_reg_clr_cls(input[`RD_SEL_LEN-1:0] rd_sel_i,output reg[`RD_SEL_LEN-1:0] rd_sel_o,input clk,input clr,input cls);always@(posedge clk)if(clr) rd_sel_o<=0;else if(cls)rd_sel_o<=rd_sel_o;else rd_sel_o<=rd_sel_i;endmodule |
module cmp_ctl_reg_clr_cls(input[`CMP_CTL_LEN-1:0] cmp_ctl_i,output reg[`CMP_CTL_LEN-1:0] cmp_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) cmp_ctl_o<=0;else if(cls)cmp_ctl_o<=cmp_ctl_o;else cmp_ctl_o<=cmp_ctl_i;endmodule |
module pc_gen_ctl_reg_clr_cls(input[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_i,output reg[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) pc_gen_ctl_o<=0;else if(cls)pc_gen_ctl_o<=pc_gen_ctl_o;else pc_gen_ctl_o<=pc_gen_ctl_i;endmodule |
module fsm_ctl_reg_clr_cls(input[`FSM_CTL_LEN-1:0] fsm_ctl_i,output reg[`FSM_CTL_LEN-1:0] fsm_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) fsm_ctl_o<=0;else if(cls)fsm_ctl_o<=fsm_ctl_o;else fsm_ctl_o<=fsm_ctl_i;endmodule |
module muxa_ctl_reg_clr_cls(input[`MUXA_CTL_LEN-1:0] muxa_ctl_i,output reg[`MUXA_CTL_LEN-1:0] muxa_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) muxa_ctl_o<=0;else if(cls)muxa_ctl_o<=muxa_ctl_o;else muxa_ctl_o<=muxa_ctl_i;endmodule |
module muxb_ctl_reg_clr_cls(input[`MUXB_CTL_LEN-1:0] muxb_ctl_i,output reg[`MUXB_CTL_LEN-1:0] muxb_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) muxb_ctl_o<=0;else if(cls)muxb_ctl_o<=muxb_ctl_o;else muxb_ctl_o<=muxb_ctl_i;endmodule |
module alu_func_reg_clr_cls(input[`ALU_FUNC_LEN-1:0] alu_func_i,output reg[`ALU_FUNC_LEN-1:0] alu_func_o,input clk,input clr,input cls);always@(posedge clk)if(clr) alu_func_o<=0;else if(cls)alu_func_o<=alu_func_o;else alu_func_o<=alu_func_i;endmodule |
module alu_we_reg_clr_cls(input[`ALU_WE_LEN-1:0] alu_we_i,output reg[`ALU_WE_LEN-1:0] alu_we_o,input clk,input clr,input cls);always@(posedge clk)if(clr) alu_we_o<=0;else if(cls)alu_we_o<=alu_we_o;else alu_we_o<=alu_we_i;endmodule |
module dmem_ctl_reg_clr_cls(input[`DMEM_CTL_LEN-1:0] dmem_ctl_i,output reg[`DMEM_CTL_LEN-1:0] dmem_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) dmem_ctl_o<=0;else if(cls)dmem_ctl_o<=dmem_ctl_o;else dmem_ctl_o<=dmem_ctl_i;endmodule |
module wb_mux_ctl_reg_clr_cls(input[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_i,output reg[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) wb_mux_ctl_o<=0;else if(cls)wb_mux_ctl_o<=wb_mux_ctl_o;else wb_mux_ctl_o<=wb_mux_ctl_i;endmodule |
module wb_we_reg_clr_cls(input[`WB_WE_LEN-1:0] wb_we_i,output reg[`WB_WE_LEN-1:0] wb_we_o,input clk,input clr,input cls);always@(posedge clk)if(clr) wb_we_o<=0;else if(cls)wb_we_o<=wb_we_o;else wb_we_o<=wb_we_i;endmodule |
module ins_reg_clr_cls(input[`INS_LEN-1:0] ins_i,output reg[`INS_LEN-1:0] ins_o,input clk,input clr,input cls);always@(posedge clk)if(clr) ins_o<=0;else if(cls)ins_o<=ins_o;else ins_o<=ins_i;endmodule |
module pc_reg_clr_cls(input[`PC_LEN-1:0] pc_i,output reg[`PC_LEN-1:0] pc_o,input clk,input clr,input cls);always@(posedge clk)if(clr) pc_o<=0;else if(cls)pc_o<=pc_o;else pc_o<=pc_i;endmodule |
module spc_reg_clr_cls(input[`SPC_LEN-1:0] spc_i,output reg[`SPC_LEN-1:0] spc_o,input clk,input clr,input cls);always@(posedge clk)if(clr) spc_o<=0;else if(cls)spc_o<=spc_o;else spc_o<=spc_i;endmodule |
module r1_reg_clr_cls(input[`R1_LEN-1:0] r1_i,output reg[`R1_LEN-1:0] r1_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r1_o<=0;else if(cls)r1_o<=r1_o;else r1_o<=r1_i;endmodule |
module r2_reg_clr_cls(input[`R2_LEN-1:0] r2_i,output reg[`R2_LEN-1:0] r2_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r2_o<=0;else if(cls)r2_o<=r2_o;else r2_o<=r2_i;endmodule |
module r3_reg_clr_cls(input[`R3_LEN-1:0] r3_i,output reg[`R3_LEN-1:0] r3_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r3_o<=0;else if(cls)r3_o<=r3_o;else r3_o<=r3_i;endmodule |
module r4_reg_clr_cls(input[`R4_LEN-1:0] r4_i,output reg[`R4_LEN-1:0] r4_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r4_o<=0;else if(cls)r4_o<=r4_o;else r4_o<=r4_i;endmodule |
module r5_reg_clr_cls(input[`R5_LEN-1:0] r5_i,output reg[`R5_LEN-1:0] r5_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r5_o<=0;else if(cls)r5_o<=r5_o;else r5_o<=r5_i;endmodule |
module r32_reg_clr_cls(input[`R32_LEN-1:0] r32_i,output reg[`R32_LEN-1:0] r32_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r32_o<=0;else if(cls)r32_o<=r32_o;else r32_o<=r32_i;endmodule |
|
|
module ext_ctl_reg_clr(input[`EXT_CTL_LEN-1:0] ext_ctl_i,output reg[`EXT_CTL_LEN-1:0] ext_ctl_o,input clk,input clr);always@(posedge clk)if(clr)ext_ctl_o<=0;else ext_ctl_o<=ext_ctl_i;endmodule |
module rd_sel_reg_clr(input[`RD_SEL_LEN-1:0] rd_sel_i,output reg[`RD_SEL_LEN-1:0] rd_sel_o,input clk,input clr);always@(posedge clk)if(clr)rd_sel_o<=0;else rd_sel_o<=rd_sel_i;endmodule |
module cmp_ctl_reg_clr(input[`CMP_CTL_LEN-1:0] cmp_ctl_i,output reg[`CMP_CTL_LEN-1:0] cmp_ctl_o,input clk,input clr);always@(posedge clk)if(clr)cmp_ctl_o<=0;else cmp_ctl_o<=cmp_ctl_i;endmodule |
module pc_gen_ctl_reg_clr(input[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_i,output reg[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_o,input clk,input clr);always@(posedge clk)if(clr)pc_gen_ctl_o<=0;else pc_gen_ctl_o<=pc_gen_ctl_i;endmodule |
module fsm_ctl_reg_clr(input[`FSM_CTL_LEN-1:0] fsm_ctl_i,output reg[`FSM_CTL_LEN-1:0] fsm_ctl_o,input clk,input clr);always@(posedge clk)if(clr)fsm_ctl_o<=0;else fsm_ctl_o<=fsm_ctl_i;endmodule |
module muxa_ctl_reg_clr(input[`MUXA_CTL_LEN-1:0] muxa_ctl_i,output reg[`MUXA_CTL_LEN-1:0] muxa_ctl_o,input clk,input clr);always@(posedge clk)if(clr)muxa_ctl_o<=0;else muxa_ctl_o<=muxa_ctl_i;endmodule |
module muxb_ctl_reg_clr(input[`MUXB_CTL_LEN-1:0] muxb_ctl_i,output reg[`MUXB_CTL_LEN-1:0] muxb_ctl_o,input clk,input clr);always@(posedge clk)if(clr)muxb_ctl_o<=0;else muxb_ctl_o<=muxb_ctl_i;endmodule |
module alu_func_reg_clr(input[`ALU_FUNC_LEN-1:0] alu_func_i,output reg[`ALU_FUNC_LEN-1:0] alu_func_o,input clk,input clr);always@(posedge clk)if(clr)alu_func_o<=0;else alu_func_o<=alu_func_i;endmodule |
module alu_we_reg_clr(input[`ALU_WE_LEN-1:0] alu_we_i,output reg[`ALU_WE_LEN-1:0] alu_we_o,input clk,input clr);always@(posedge clk)if(clr)alu_we_o<=0;else alu_we_o<=alu_we_i;endmodule |
module dmem_ctl_reg_clr(input[`DMEM_CTL_LEN-1:0] dmem_ctl_i,output reg[`DMEM_CTL_LEN-1:0] dmem_ctl_o,input clk,input clr);always@(posedge clk)if(clr)dmem_ctl_o<=0;else dmem_ctl_o<=dmem_ctl_i;endmodule |
module wb_mux_ctl_reg_clr(input[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_i,output reg[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_o,input clk,input clr);always@(posedge clk)if(clr)wb_mux_ctl_o<=0;else wb_mux_ctl_o<=wb_mux_ctl_i;endmodule |
module wb_we_reg_clr(input[`WB_WE_LEN-1:0] wb_we_i,output reg[`WB_WE_LEN-1:0] wb_we_o,input clk,input clr);always@(posedge clk)if(clr)wb_we_o<=0;else wb_we_o<=wb_we_i;endmodule |
module ins_reg_clr(input[`INS_LEN-1:0] ins_i,output reg[`INS_LEN-1:0] ins_o,input clk,input clr);always@(posedge clk)if(clr)ins_o<=0;else ins_o<=ins_i;endmodule |
module pc_reg_clr(input[`PC_LEN-1:0] pc_i,output reg[`PC_LEN-1:0] pc_o,input clk,input clr);always@(posedge clk)if(clr)pc_o<=0;else pc_o<=pc_i;endmodule |
module spc_reg_clr(input[`SPC_LEN-1:0] spc_i,output reg[`SPC_LEN-1:0] spc_o,input clk,input clr);always@(posedge clk)if(clr)spc_o<=0;else spc_o<=spc_i;endmodule |
module r1_reg_clr(input[`R1_LEN-1:0] r1_i,output reg[`R1_LEN-1:0] r1_o,input clk,input clr);always@(posedge clk)if(clr)r1_o<=0;else r1_o<=r1_i;endmodule |
module r2_reg_clr(input[`R2_LEN-1:0] r2_i,output reg[`R2_LEN-1:0] r2_o,input clk,input clr);always@(posedge clk)if(clr)r2_o<=0;else r2_o<=r2_i;endmodule |
module r3_reg_clr(input[`R3_LEN-1:0] r3_i,output reg[`R3_LEN-1:0] r3_o,input clk,input clr);always@(posedge clk)if(clr)r3_o<=0;else r3_o<=r3_i;endmodule |
module r4_reg_clr(input[`R4_LEN-1:0] r4_i,output reg[`R4_LEN-1:0] r4_o,input clk,input clr);always@(posedge clk)if(clr)r4_o<=0;else r4_o<=r4_i;endmodule |
module r5_reg_clr(input[`R5_LEN-1:0] r5_i,output reg[`R5_LEN-1:0] r5_o,input clk,input clr);always@(posedge clk)if(clr)r5_o<=0;else r5_o<=r5_i;endmodule |
module r32_reg_clr(input[`R32_LEN-1:0] r32_i,output reg[`R32_LEN-1:0] r32_o,input clk,input clr);always@(posedge clk)if(clr)r32_o<=0;else r32_o<=r32_i;endmodule |
|
|
module ext_ctl_reg(input[`EXT_CTL_LEN-1:0] ext_ctl_i,output reg[`EXT_CTL_LEN-1:0] ext_ctl_o,input clk);always@(posedge clk) ext_ctl_o<=ext_ctl_i;endmodule |
module rd_sel_reg(input[`RD_SEL_LEN-1:0] rd_sel_i,output reg[`RD_SEL_LEN-1:0] rd_sel_o,input clk);always@(posedge clk) rd_sel_o<=rd_sel_i;endmodule |
module cmp_ctl_reg(input[`CMP_CTL_LEN-1:0] cmp_ctl_i,output reg[`CMP_CTL_LEN-1:0] cmp_ctl_o,input clk);always@(posedge clk) cmp_ctl_o<=cmp_ctl_i;endmodule |
module pc_gen_ctl_reg(input[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_i,output reg[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_o,input clk);always@(posedge clk) pc_gen_ctl_o<=pc_gen_ctl_i;endmodule |
module fsm_ctl_reg(input[`FSM_CTL_LEN-1:0] fsm_ctl_i,output reg[`FSM_CTL_LEN-1:0] fsm_ctl_o,input clk);always@(posedge clk) fsm_ctl_o<=fsm_ctl_i;endmodule |
module muxa_ctl_reg(input[`MUXA_CTL_LEN-1:0] muxa_ctl_i,output reg[`MUXA_CTL_LEN-1:0] muxa_ctl_o,input clk);always@(posedge clk) muxa_ctl_o<=muxa_ctl_i;endmodule |
module muxb_ctl_reg(input[`MUXB_CTL_LEN-1:0] muxb_ctl_i,output reg[`MUXB_CTL_LEN-1:0] muxb_ctl_o,input clk);always@(posedge clk) muxb_ctl_o<=muxb_ctl_i;endmodule |
module alu_func_reg(input[`ALU_FUNC_LEN-1:0] alu_func_i,output reg[`ALU_FUNC_LEN-1:0] alu_func_o,input clk);always@(posedge clk) alu_func_o<=alu_func_i;endmodule |
module alu_we_reg(input[`ALU_WE_LEN-1:0] alu_we_i,output reg[`ALU_WE_LEN-1:0] alu_we_o,input clk);always@(posedge clk) alu_we_o<=alu_we_i;endmodule |
module dmem_ctl_reg(input[`DMEM_CTL_LEN-1:0] dmem_ctl_i,output reg[`DMEM_CTL_LEN-1:0] dmem_ctl_o,input clk);always@(posedge clk) dmem_ctl_o<=dmem_ctl_i;endmodule |
module wb_mux_ctl_reg(input[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_i,output reg[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_o,input clk);always@(posedge clk) wb_mux_ctl_o<=wb_mux_ctl_i;endmodule |
module wb_we_reg(input[`WB_WE_LEN-1:0] wb_we_i,output reg[`WB_WE_LEN-1:0] wb_we_o,input clk);always@(posedge clk) wb_we_o<=wb_we_i;endmodule |
module ins_reg(input[`INS_LEN-1:0] ins_i,output reg[`INS_LEN-1:0] ins_o,input clk);always@(posedge clk) ins_o<=ins_i;endmodule |
module pc_reg(input[`PC_LEN-1:0] pc_i,output reg[`PC_LEN-1:0] pc_o,input clk);always@(posedge clk) pc_o<=pc_i;endmodule |
module spc_reg(input[`SPC_LEN-1:0] spc_i,output reg[`SPC_LEN-1:0] spc_o,input clk);always@(posedge clk) spc_o<=spc_i;endmodule |
module r1_reg(input[`R1_LEN-1:0] r1_i,output reg[`R1_LEN-1:0] r1_o,input clk);always@(posedge clk) r1_o<=r1_i;endmodule |
module r2_reg(input[`R2_LEN-1:0] r2_i,output reg[`R2_LEN-1:0] r2_o,input clk);always@(posedge clk) r2_o<=r2_i;endmodule |
module r3_reg(input[`R3_LEN-1:0] r3_i,output reg[`R3_LEN-1:0] r3_o,input clk);always@(posedge clk) r3_o<=r3_i;endmodule |
module r4_reg(input[`R4_LEN-1:0] r4_i,output reg[`R4_LEN-1:0] r4_o,input clk);always@(posedge clk) r4_o<=r4_i;endmodule |
module r5_reg(input[`R5_LEN-1:0] r5_i,output reg[`R5_LEN-1:0] r5_o,input clk);always@(posedge clk) r5_o<=r5_i;endmodule |
module r32_reg(input[`R32_LEN-1:0] r32_i,output reg[`R32_LEN-1:0] r32_o,input clk);always@(posedge clk) r32_o<=r32_i;endmodule |
|
|
module ext_ctl_reg_cls(input[`EXT_CTL_LEN-1:0] ext_ctl_i,output reg[`EXT_CTL_LEN-1:0] ext_ctl_o,input clk,input cls);always@(posedge clk)if(cls) ext_ctl_o<=ext_ctl_o;else ext_ctl_o<=ext_ctl_i;endmodule |
module rd_sel_reg_cls(input[`RD_SEL_LEN-1:0] rd_sel_i,output reg[`RD_SEL_LEN-1:0] rd_sel_o,input clk,input cls);always@(posedge clk)if(cls) rd_sel_o<=rd_sel_o;else rd_sel_o<=rd_sel_i;endmodule |
module cmp_ctl_reg_cls(input[`CMP_CTL_LEN-1:0] cmp_ctl_i,output reg[`CMP_CTL_LEN-1:0] cmp_ctl_o,input clk,input cls);always@(posedge clk)if(cls) cmp_ctl_o<=cmp_ctl_o;else cmp_ctl_o<=cmp_ctl_i;endmodule |
module pc_gen_ctl_reg_cls(input[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_i,output reg[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_o,input clk,input cls);always@(posedge clk)if(cls) pc_gen_ctl_o<=pc_gen_ctl_o;else pc_gen_ctl_o<=pc_gen_ctl_i;endmodule |
module fsm_ctl_reg_cls(input[`FSM_CTL_LEN-1:0] fsm_ctl_i,output reg[`FSM_CTL_LEN-1:0] fsm_ctl_o,input clk,input cls);always@(posedge clk)if(cls) fsm_ctl_o<=fsm_ctl_o;else fsm_ctl_o<=fsm_ctl_i;endmodule |
module muxa_ctl_reg_cls(input[`MUXA_CTL_LEN-1:0] muxa_ctl_i,output reg[`MUXA_CTL_LEN-1:0] muxa_ctl_o,input clk,input cls);always@(posedge clk)if(cls) muxa_ctl_o<=muxa_ctl_o;else muxa_ctl_o<=muxa_ctl_i;endmodule |
module muxb_ctl_reg_cls(input[`MUXB_CTL_LEN-1:0] muxb_ctl_i,output reg[`MUXB_CTL_LEN-1:0] muxb_ctl_o,input clk,input cls);always@(posedge clk)if(cls) muxb_ctl_o<=muxb_ctl_o;else muxb_ctl_o<=muxb_ctl_i;endmodule |
module alu_func_reg_cls(input[`ALU_FUNC_LEN-1:0] alu_func_i,output reg[`ALU_FUNC_LEN-1:0] alu_func_o,input clk,input cls);always@(posedge clk)if(cls) alu_func_o<=alu_func_o;else alu_func_o<=alu_func_i;endmodule |
module alu_we_reg_cls(input[`ALU_WE_LEN-1:0] alu_we_i,output reg[`ALU_WE_LEN-1:0] alu_we_o,input clk,input cls);always@(posedge clk)if(cls) alu_we_o<=alu_we_o;else alu_we_o<=alu_we_i;endmodule |
module dmem_ctl_reg_cls(input[`DMEM_CTL_LEN-1:0] dmem_ctl_i,output reg[`DMEM_CTL_LEN-1:0] dmem_ctl_o,input clk,input cls);always@(posedge clk)if(cls) dmem_ctl_o<=dmem_ctl_o;else dmem_ctl_o<=dmem_ctl_i;endmodule |
module wb_mux_ctl_reg_cls(input[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_i,output reg[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_o,input clk,input cls);always@(posedge clk)if(cls) wb_mux_ctl_o<=wb_mux_ctl_o;else wb_mux_ctl_o<=wb_mux_ctl_i;endmodule |
module wb_we_reg_cls(input[`WB_WE_LEN-1:0] wb_we_i,output reg[`WB_WE_LEN-1:0] wb_we_o,input clk,input cls);always@(posedge clk)if(cls) wb_we_o<=wb_we_o;else wb_we_o<=wb_we_i;endmodule |
module ins_reg_cls(input[`INS_LEN-1:0] ins_i,output reg[`INS_LEN-1:0] ins_o,input clk,input cls);always@(posedge clk)if(cls) ins_o<=ins_o;else ins_o<=ins_i;endmodule |
module pc_reg_cls(input[`PC_LEN-1:0] pc_i,output reg[`PC_LEN-1:0] pc_o,input clk,input cls);always@(posedge clk)if(cls) pc_o<=pc_o;else pc_o<=pc_i;endmodule |
module spc_reg_cls(input[`SPC_LEN-1:0] spc_i,output reg[`SPC_LEN-1:0] spc_o,input clk,input cls);always@(posedge clk)if(cls) spc_o<=spc_o;else spc_o<=spc_i;endmodule |
module r1_reg_cls(input[`R1_LEN-1:0] r1_i,output reg[`R1_LEN-1:0] r1_o,input clk,input cls);always@(posedge clk)if(cls) r1_o<=r1_o;else r1_o<=r1_i;endmodule |
module r2_reg_cls(input[`R2_LEN-1:0] r2_i,output reg[`R2_LEN-1:0] r2_o,input clk,input cls);always@(posedge clk)if(cls) r2_o<=r2_o;else r2_o<=r2_i;endmodule |
module r3_reg_cls(input[`R3_LEN-1:0] r3_i,output reg[`R3_LEN-1:0] r3_o,input clk,input cls);always@(posedge clk)if(cls) r3_o<=r3_o;else r3_o<=r3_i;endmodule |
module r4_reg_cls(input[`R4_LEN-1:0] r4_i,output reg[`R4_LEN-1:0] r4_o,input clk,input cls);always@(posedge clk)if(cls) r4_o<=r4_o;else r4_o<=r4_i;endmodule |
module r5_reg_cls(input[`R5_LEN-1:0] r5_i,output reg[`R5_LEN-1:0] r5_o,input clk,input cls);always@(posedge clk)if(cls) r5_o<=r5_o;else r5_o<=r5_i;endmodule |
module r32_reg_cls(input[`R32_LEN-1:0] r32_i,output reg[`R32_LEN-1:0] r32_o,input clk,input cls);always@(posedge clk)if(cls) r32_o<=r32_o;else r32_o<=r32_i;endmodule |
|
|
|
module portio16( |
inout [15:0] io_port, |
output [15:0] dfport, |
input [15:0] d2port, |
input wr_en |
); |
|
assign dfport = io_port ; |
assign io_port = wr_en ? d2port : 16'bz; |
|
endmodule |
/trunk/rtl/verilog/mips_core.v
0,0 → 1,332
/****************************************************************** |
* * |
* Author: Liwei * |
* * |
* This file is part of the "mips789" project. * |
* Downloaded from: * |
* http://www.opencores.org/pdownloads.cgi/list/mips789 * |
* * |
* If you encountered any problem, please contact me via * |
* Email:mcupro@opencores.org or mcupro@163.com * |
* * |
******************************************************************/ |
|
`include "mips789_defs.v" |
|
module mips_core ( |
clk,irq_i,rst,cop_dout,irq_addr, |
zz_din,zz_ins_i,iack_o,cop_addr_o, |
cop_data_o,cop_mem_ctl_o,zz_addr_o, |
zz_dout,zz_pc_o,zz_wr_en_o |
); |
|
input clk; |
wire clk; |
input irq_i; |
wire irq_i; |
input rst; |
wire rst; |
input [31:0] cop_dout; |
wire [31:0] cop_dout; |
input [31:0] irq_addr; |
wire [31:0] irq_addr; |
input [31:0] zz_din; |
wire [31:0] zz_din; |
input [31:0] zz_ins_i; |
wire [31:0] zz_ins_i; |
output [31:0] zz_addr_o; |
wire [31:0] zz_addr_o; |
output [31:0] zz_dout; |
wire [31:0] zz_dout; |
output [31:0] zz_pc_o; |
wire [31:0] zz_pc_o; |
output [3:0] zz_wr_en_o; |
wire [3:0] zz_wr_en_o; |
output iack_o; |
wire iack_o; |
output [31:0] cop_addr_o; |
wire [31:0] cop_addr_o; |
output [31:0] cop_data_o; |
wire [31:0] cop_data_o; |
output [3:0] cop_mem_ctl_o; |
wire [3:0] cop_mem_ctl_o; |
|
|
wire NET1375; |
wire NET1572; |
wire NET1606; |
wire NET1640; |
wire NET21531; |
wire NET457; |
wire NET767; |
wire [2:0] BUS109; |
wire [2:0] BUS1158; |
wire [2:0] BUS117; |
wire [2:0] BUS1196; |
wire [31:0] BUS15471; |
wire [4:0] BUS1724; |
wire [4:0] BUS1726; |
wire [4:0] BUS18211; |
wire [2:0] BUS197; |
wire [2:0] BUS2140; |
wire [2:0] BUS2156; |
wire [31:0] BUS22401; |
wire [31:0] BUS24839; |
wire [31:0] BUS27031; |
wire [2:0] BUS271; |
wire [31:0] BUS28013; |
wire [1:0] BUS371; |
wire [31:0] BUS422; |
wire [1:0] BUS5832; |
wire [1:0] BUS5840; |
wire [3:0] BUS5985; |
wire [2:0] BUS5993; |
wire [4:0] BUS6275; |
wire [31:0] BUS7101; |
wire [31:0] BUS7117; |
wire [31:0] BUS7160; |
wire [31:0] BUS7219; |
wire [31:0] BUS7231; |
wire [4:0] BUS748; |
wire [4:0] BUS756; |
wire [4:0] BUS775; |
wire [31:0] BUS7772; |
wire [31:0] BUS7780; |
wire [31:0] BUS9589; |
wire [31:0] BUS9884; |
|
|
mem_module MEM_CTL |
( |
.Zz_addr(zz_addr_o), |
.Zz_dout(zz_dout), |
.Zz_wr_en(zz_wr_en_o), |
.clk(clk), |
.din(BUS9884), |
.dmem_addr_i(BUS9589), |
.dmem_ctl(BUS5985), |
.dout(BUS22401), |
.zZ_din(zz_din) |
); |
|
assign NET21531 = NET1572 | iack_o; |
|
rf_stage iRF_stage |
( |
.clk(clk), |
.cmp_ctl_i(BUS109), |
.ext_ctl_i(BUS117), |
.ext_o(BUS7219), |
.fw_alu_i(cop_addr_o), |
.fw_cmp_rs(BUS2140), |
.fw_cmp_rt(BUS2156), |
.fw_mem_i(BUS15471), |
.iack_o(iack_o), |
.id2ra_ctl_clr_o(NET1606), |
.id2ra_ctl_cls_o(NET1572), |
.id_cmd(BUS197), |
.ins_i(zz_ins_i), |
.irq_addr_i(irq_addr), |
.irq_i(irq_i), |
.pc_gen_ctl(BUS271), |
.pc_i(BUS27031), |
.pc_next(zz_pc_o), |
.ra2ex_ctl_clr_o(NET1640), |
.rd_index_o(BUS775), |
.rd_sel_i(BUS371), |
.rs_n_o(BUS748), |
.rs_o(BUS24839), |
.rst_i(rst), |
.rt_n_o(BUS756), |
.rt_o(BUS7160), |
.wb_addr_i(BUS18211), |
.wb_din_i(BUS15471), |
.wb_we_i(NET1375), |
.zz_spc_i(BUS28013) |
); |
|
|
|
exec_stage iexec_stage |
( |
.alu_func(BUS6275), |
.alu_ur_o(BUS9589), |
.clk(clk), |
.dmem_data_ur_o(BUS9884), |
.dmem_fw_ctl(BUS5993), |
.ext_i(BUS7231), |
.fw_alu(cop_addr_o), |
.fw_dmem(BUS15471), |
.muxa_ctl_i(BUS5832), |
.muxa_fw_ctl(BUS1158), |
.muxb_ctl_i(BUS5840), |
.muxb_fw_ctl(BUS1196), |
.pc_i(BUS27031), |
.rs_i(BUS7101), |
.rst(rst), |
.rt_i(BUS7117), |
.spc_cls_i(NET21531), |
.zz_spc_o(BUS28013) |
); |
|
|
|
r32_reg alu_pass0 |
( |
.clk(clk), |
.r32_i(BUS9589), |
.r32_o(cop_addr_o) |
); |
|
|
|
r32_reg alu_pass1 |
( |
.clk(clk), |
.r32_i(cop_addr_o), |
.r32_o(BUS422) |
); |
|
|
|
or32 cop_data_or |
( |
.a(cop_dout), |
.b(BUS7772), |
.c(BUS7780) |
); |
|
|
|
r32_reg cop_data_reg |
( |
.clk(clk), |
.r32_i(BUS9884), |
.r32_o(cop_data_o) |
); |
|
|
|
r32_reg cop_dout_reg |
( |
.clk(clk), |
.r32_i(BUS22401), |
.r32_o(BUS7772) |
); |
|
|
|
decode_pipe decoder_pipe |
( |
.alu_func_o(BUS6275), |
.alu_we_o(NET767), |
.clk(clk), |
.cmp_ctl_o(BUS109), |
.dmem_ctl_o(cop_mem_ctl_o), |
.dmem_ctl_ur_o(BUS5985), |
.ext_ctl_o(BUS117), |
.fsm_dly(BUS197), |
.id2ra_ctl_clr(NET1606), |
.id2ra_ctl_cls(NET1572), |
.ins_i(zz_ins_i), |
.muxa_ctl_o(BUS5832), |
.muxb_ctl_o(BUS5840), |
.pc_gen_ctl_o(BUS271), |
.ra2ex_ctl_clr(NET1640), |
.rd_sel_o(BUS371), |
.wb_mux_ctl_o(NET457), |
.wb_we_o(NET1375) |
); |
|
|
|
r32_reg ext_reg |
( |
.clk(clk), |
.r32_i(BUS7219), |
.r32_o(BUS7231) |
); |
|
|
|
forward iforward |
( |
.alu_rs_fw(BUS1158), |
.alu_rt_fw(BUS1196), |
.alu_we(NET767), |
.clk(clk), |
.cmp_rs_fw(BUS2140), |
.cmp_rt_fw(BUS2156), |
.dmem_fw(BUS5993), |
.fw_alu_rn(BUS1724), |
.fw_mem_rn(BUS18211), |
.mem_We(NET1375), |
.rns_i(BUS748), |
.rnt_i(BUS756) |
); |
|
|
|
r32_reg pc |
( |
.clk(clk), |
.r32_i(zz_pc_o), |
.r32_o(BUS27031) |
); |
|
|
|
r5_reg rnd_pass0 |
( |
.clk(clk), |
.r5_i(BUS775), |
.r5_o(BUS1726) |
); |
|
|
|
r5_reg rnd_pass1 |
( |
.clk(clk), |
.r5_i(BUS1726), |
.r5_o(BUS1724) |
); |
|
|
|
r5_reg rnd_pass2 |
( |
.clk(clk), |
.r5_i(BUS1724), |
.r5_o(BUS18211) |
); |
|
|
|
r32_reg rs_reg |
( |
.clk(clk), |
.r32_i(BUS24839), |
.r32_o(BUS7101) |
); |
|
|
|
r32_reg rt_reg |
( |
.clk(clk), |
.r32_i(BUS7160), |
.r32_o(BUS7117) |
); |
|
|
|
wb_mux wb_mux |
( |
.alu_i(BUS422), |
.dmem_i(BUS7780), |
.sel(NET457), |
.wb_o(BUS15471) |
); |
|
endmodule |
/trunk/rtl/verilog/mips789_defs.v
0,0 → 1,195
/****************************************************************** |
* * |
* Author: Liwei * |
* * |
* This file is part of the "mips789" project. * |
* Downloaded from: * |
* http://www.opencores.org/pdownloads.cgi/list/mips789 * |
* * |
* If you encountered any problem, please contact me via * |
* Email:mcupro@opencores.org or mcupro@163.com * |
* * |
******************************************************************/ |
|
`ifndef INCLUDE_H |
`define INCLUDE_H |
|
`define FRQ 50000000 |
`define SER_RATE 19200 |
|
`define FW_ALU 3'b001 |
`define FW_MEM 3'b010 |
`define FW_NOP 3'b100 |
|
`define ALU_MFHI 6 |
`define ALU_MFLO 7 |
`define ALU_MULTTU 8 |
`define ALU_MULT 9 |
`define ALU_DIVU 10 |
`define ALU_DIV 11 |
|
|
`define DMEM_SB 1 |
`define DMEM_LBS 2 |
`define DMEM_LB 3 |
`define DMEM_LBU 4 |
`define DMEM_SW 5 |
`define DMEM_LW 6 |
`define DMEM_SH 7 |
`define DMEM_LHS 8 |
`define DMEM_LH 9 |
`define DMEM_LHU 10 |
`define DMEM_NOP 0 |
|
`define ALU_SRL 1 |
`define ALU_SLL 2 |
`define ALU_SRA 4 |
|
`define WB_ALU 0 |
`define WB_MEM 1 |
`define WB_NOP 0 |
|
`define RD_RD 1 |
`define RD_RT 2 |
`define RD_R31 3 |
`define RD_NOP 0 |
`define RD_ZR 0 |
|
`define EXT_CTL_LEN 3 |
`define RD_SEL_LEN 2 |
`define CMP_CTL_LEN 3 |
`define PC_GEN_CTL_LEN 3 |
`define FSM_CTL_LEN 3 |
`define MUXA_CTL_LEN 2 |
`define MUXB_CTL_LEN 2 |
`define ALU_FUNC_LEN 5 |
`define ALU_WE_LEN 1 |
`define DMEM_CTL_LEN 4 |
`define WB_MUX_CTL_LEN 1 |
`define WB_WE_LEN 1 |
`define INS_LEN 32 |
`define PC_LEN 32 |
`define SPC_LEN 32 |
`define R32_LEN 32 |
`define R5_LEN 5 |
`define R1_LEN 1 |
`define R2_LEN 2 |
`define R3_LEN 3 |
`define R4_LEN 4 |
|
`define ALU_ADD 12 |
`define ALU_ADDU 13 |
`define ALU_SUB 14 |
`define ALU_SUBU 15 |
`define ALU_SLTU 16 |
`define ALU_SLT 17 |
`define ALU_OR 18 |
`define ALU_AND 19 |
`define ALU_XOR 20 |
`define ALU_NOR 21 |
`define ALU_PA 22 |
`define ALU_PB 23 |
|
`define D2_MUL_DLY 4'b0000 |
`define IDLE 4'b0001 |
`define MUL 4'b0010 |
`define CUR 4'b0011 |
`define RET 4'b0100 |
`define IRQ 4'b0101 |
`define RST 4'b0110 |
`define LD 4'b0111 |
`define NOI 4'b1000 |
|
|
`define ALU_NOP 0 |
`define ALU_MTLO 30 |
`define ALU_MTHI 31 |
`define ALU_MULTU 8 |
|
`define PC_IGN 1 |
`define PC_KEP 2 |
`define PC_IRQ 4 |
`define PC_RST 8 |
|
`define PC_J 1 |
`define PC_JR 2 |
`define PC_BC 4 |
`define PC_NEXT 5 |
`define PC_NOP 0 |
`define PC_RET 6 |
`define PC_SPC 6 |
|
`define RF 13 |
`define EXEC 10 |
`define DMEM 4 |
`define WB 2 |
`define MUXA_PC 1 |
`define MUXA_RS 2 |
`define MUXA_EXT 3 |
`define MUXA_SPC 0 |
`define MUXA_NOP 0 |
`define MUXB_RT 1 |
`define MUXB_EXT 2 |
`define MUXB_NOP 0 |
|
`define CMP_BEQ 1 |
`define CMP_BNE 2 |
`define CMP_BLEZ 3 |
`define CMP_BGEZ 4 |
`define CMP_BGTZ 5 |
`define CMP_BLTZ 6 |
`define CMP_NOP 0 |
|
`define FSM_CUR 1 |
`define FSM_MUL 2 |
`define FSM_RET 4 |
`define FSM_NOP 0 |
`define FSM_LD 5 |
`define FSM_NOI 6 |
|
`define REG_NOP 0 |
`define REG_CLR 1 |
`define REG_KEP 2 |
|
`define EXT_SIGN 1 |
`define EXT_UNSIGN 2 |
`define EXT_J 3 |
`define EXT_B 4 |
`define EXT_SA 5 |
`define EXT_S2H 6 |
`define EXT_NOP 0 |
|
`define EN 1 |
`define DIS 0 |
`define IGN 0 |
/* |
`define UART_DATA_ADDR 'H80_00_00_28 |
`define CMD_ADDR 'H80_00_00_14 |
`define STATUS_ADDR 'H80_00_00_18 |
`define SEG7LED_ADDR 'H80_00_00_1C |
`define SIM_DIS_ADDR 'H80_00_00_20 |
`define LCD_DATA_ADDR 'H80_00_00_24 |
`define IRQ_MASK_ADDR 'H80_00_00_34 |
`define TMR_IRQ_ADDR 'H80_00_00_28 |
`define TMR_DATA_ADDR 'H80_00_00_34 |
`define KEY1_IRQ_ADDR 'H80_00_00_2C |
`define KEY2_IRQ_ADDR 'H80_00_00_30 |
*/ |
`define JTAG_BASE_ADDR 'h8100_0000 |
`define JTAG_RD_FIFO 'h8100_0100 |
`define JTAG_RD_FIFO_FLAG 'h8100_0200 |
`define USB_DATA_ADDR 'h8100_0300 |
`define USB_CTL_ADDR 'h8100_0400 |
|
`define COUNTER_VALUE1 (`FRQ/`SER_RATE/2-1) |
`define COUNTER_VALUE2 (`COUNTER_VALUE1*2+1) |
`define COUNTER_VALUE3 (`COUNTER_VALUE1+3) |
|
`define DEFAULT_IRQ_ADDR 'H00_00_00_5C |
|
`define ALTERA |
|
`else |
|
|
`endif |
/trunk/rtl/verilog/mem_module.v
0,0 → 1,212
/****************************************************************** |
* * |
* Author: Liwei * |
* * |
* This file is part of the "mips789" project. * |
* Downloaded from: * |
* http://www.opencores.org/pdownloads.cgi/list/mips789 * |
* * |
* If you encountered any problem, please contact me via * |
* Email:mcupro@opencores.org or mcupro@163.com * |
* * |
******************************************************************/ |
|
`include "mips789_defs.v" |
|
|
module mem_module ( |
clk,din,dmem_addr_i,dmem_ctl, |
zZ_din,Zz_addr,Zz_dout,Zz_wr_en,dout |
) ; |
|
input clk; |
wire clk; |
input [31:0] din; |
wire [31:0] din; |
input [31:0] dmem_addr_i; |
wire [31:0] dmem_addr_i; |
input [3:0] dmem_ctl; |
wire [3:0] dmem_ctl; |
input [31:0] zZ_din; |
wire [31:0] zZ_din; |
output [31:0] Zz_addr; |
wire [31:0] Zz_addr; |
output [31:0] Zz_dout; |
wire [31:0] Zz_dout; |
output [3:0] Zz_wr_en; |
wire [3:0] Zz_wr_en; |
output [31:0] dout; |
wire [31:0] dout; |
|
wire [3:0] BUS512; |
wire [1:0] BUS629; |
wire [31:0] BUS650; |
|
|
infile_dmem_ctl_reg dmem_ctl_post |
( |
.byte_addr_o(BUS629), |
.clk(clk), |
.ctl_i(dmem_ctl), |
.ctl_o(BUS512), |
.dmem_addr_i(BUS650) |
); |
|
|
|
mem_addr_ctl i_mem_addr_ctl |
( |
.addr_i(BUS650), |
.ctl(dmem_ctl), |
.wr_en(Zz_wr_en) |
); |
|
|
|
mem_din_ctl i_mem_din_ctl |
( |
.ctl(dmem_ctl), |
.din(din), |
.dout(Zz_dout) |
); |
|
|
|
mem_dout_ctl i_mem_dout_ctl |
( |
.byte_addr(BUS629), |
.ctl(BUS512), |
.din(zZ_din), |
.dout(dout) |
); |
|
|
|
assign BUS650[31:0] = dmem_addr_i[31:0]; |
|
assign Zz_addr[31:0] = BUS650[31:0]; |
|
endmodule |
|
|
module infile_dmem_ctl_reg( |
input clk, |
input [3:0]ctl_i, |
input [31:0]dmem_addr_i, |
output reg [1:0]byte_addr_o, |
output reg [3:0]ctl_o |
); |
|
wire [1:0]byte_addr_i; |
assign byte_addr_i = dmem_addr_i[1:0] ; |
|
always @(posedge clk) |
begin |
ctl_o<=(dmem_addr_i[31]==0)?ctl_i:0; |
byte_addr_o<=byte_addr_i; |
end |
|
endmodule |
|
module mem_addr_ctl( |
input [3:0]ctl, |
input [31:0]addr_i, |
output reg[3:0]wr_en |
); |
always@(*) |
case (ctl) |
`DMEM_SB: |
begin |
case(addr_i[1:0]) |
0:wr_en = 4'b1000; |
1:wr_en = 4'b0100; |
2:wr_en = 4'b0010; |
3:wr_en = 4'b0001; |
default :wr_en = 4'b000; |
endcase |
end |
`DMEM_SH : |
begin |
case(addr_i[1:0]) |
'd0:wr_en=4'b1100; |
'd2:wr_en=4'b0011; |
default :wr_en = 4'b0000; |
endcase |
end |
`DMEM_SW : |
begin |
wr_en=4'b1111; |
end |
default wr_en=4'b0000; |
endcase |
|
endmodule |
|
|
module mem_dout_ctl( |
input [1:0]byte_addr, |
input [3:0]ctl, |
input [31:0] din, |
output reg [31:0] dout |
); |
|
always @(*) |
case (ctl) |
|
`DMEM_LBS : |
case (byte_addr) |
|
'd0:dout={{24{din[31]}},din[31:24]}; |
'd1:dout={{24{din[23]}},din[23:16]}; |
'd2:dout={{24{din[15]}},din[15:8]}; |
'd3:dout={{24{din[7]}},din[7:0] }; |
default : |
dout=32'bX; |
endcase |
`DMEM_LBU : |
case (byte_addr) |
'd3:dout={24'b0,din[7:0]}; |
'd2:dout={24'b0,din[15:8]}; |
'd1:dout={24'b0,din[23:16]}; |
'd0:dout={24'b0,din[31:24]}; |
default : |
dout=32'bX; |
endcase |
`DMEM_LHU : |
case (byte_addr) |
'd0:dout={16'b0,din[31:24],din[23:16]}; |
'd2:dout={16'b0,din[15:8],din[7 :0]}; |
default:dout=32'bX; |
endcase |
`DMEM_LHS : |
case (byte_addr) |
'd0 :dout={{16{din[31]}},din[31:24],din[23:16]}; |
'd2 :dout={{16{din[15]}},din[15:8],din[7 :0]}; |
default:dout=32'bX; |
endcase |
`DMEM_LW : |
dout=din; |
default : |
dout=0; |
endcase |
endmodule |
|
module mem_din_ctl( |
input [3:0]ctl, |
input [31:0]din, |
output reg [31:0]dout |
); |
|
always @(*) |
|
case (ctl) |
`DMEM_SB : |
dout={din[7:0],din[7:0],din[7:0],din[7:0]}; |
`DMEM_SH : |
dout = {din[15:0],din[15:0]}; |
`DMEM_SW : |
dout =din; |
default dout=32'bX; |
endcase |
|
endmodule |
/trunk/rtl/verilog/ram_module.v
0,0 → 1,78
/****************************************************************** |
* * |
* Author: Liwei * |
* * |
* This file is part of the "mips789" project. * |
* Downloaded from: * |
* http://www.opencores.org/pdownloads.cgi/list/mips789 * |
* * |
* If you encountered any problem, please contact me via * |
* Email:mcupro@opencores.org or mcupro@163.com * |
* * |
******************************************************************/ |
|
module mem_array |
( |
input clk, |
input [31:0] pc_i, |
output [31:0] ins_o, |
input [3:0] wren, |
input [31:0]din, |
input [31:0]data_addr_i, |
output [31:0]dout |
); |
wire [31:0] data_addr; |
wire [31:0]dout_w; |
assign dout = dout_w; |
assign data_addr=data_addr_i[31:2]; |
wire [29:0]pc= pc_i[31:2]; |
|
ram2048x8_3 ram3( |
.data_a(32'b0), |
.wren_a(1'b0), |
.address_a(pc), |
.data_b(din[31:24]), |
.address_b(data_addr), |
.wren_b(wren[3]), |
.clock(clk), |
.q_a(ins_o[31:24]), |
.q_b(dout_w[31:24]) |
); |
|
ram2048x8_2 ram2( |
.data_a(32'b0), |
.wren_a(1'b0), |
.address_a(pc), |
.data_b(din[23:16]), |
.address_b(data_addr), |
.wren_b(wren[2]), |
.clock(clk), |
.q_a(ins_o[23:16]), |
.q_b(dout_w[23:16]) |
); |
|
ram2048x8_1 ram1( |
.data_a(32'b0), |
.wren_a(1'b0), |
.address_a(pc), |
.data_b(din[15:8]), |
.address_b(data_addr), |
.wren_b(wren[1]), |
.clock(clk), |
.q_a(ins_o[15:8]), |
.q_b(dout_w[15:8]) |
); |
|
ram2048x8_0 ram0( |
.data_a(32'b0), |
.wren_a(1'b0), |
.address_a(pc), |
.data_b(din[7:0]), |
.address_b(data_addr), |
.wren_b(wren[0]), |
.clock(clk), |
.q_a(ins_o[7:0]), |
.q_b(dout_w[7:0]) |
); |
|
endmodule |
/trunk/rtl/verilog/ctl_fsm.v
0,0 → 1,177
/****************************************************************** |
* * |
* Author: Liwei * |
* * |
* This file is part of the "mips789" project. * |
* Downloaded from: * |
* http://www.opencores.org/pdownloads.cgi/list/mips789 * |
* * |
* If you encountered any problem, please contact me via * |
* Email:mcupro@opencores.org or mcupro@163.com * |
* * |
******************************************************************/ |
|
`include "mips789_defs.v" |
module ctl_FSM ( |
input clk, |
input [2:0] id_cmd, |
input irq, |
input rst, |
output reg iack, |
output reg zz_is_nop, |
output reg id2ra_ctl_clr, |
output reg id2ra_ctl_cls, |
output reg id2ra_ins_clr, |
output reg id2ra_ins_cls, |
output reg [3:0] pc_prectl, |
output reg ra2exec_ctl_clr |
); |
parameter |
ID_CUR = `FSM_CUR, ID_LD = `FSM_LD , |
ID_MUL = `FSM_MUL, ID_NOI = `FSM_NOI, |
ID_RET = `FSM_RET, |
|
PC_IGN = `PC_IGN , PC_IRQ = `PC_IRQ, |
PC_KEP = `PC_KEP , PC_RST = `PC_RST; |
|
reg [5:0] delay_counter; |
reg [4:0] CurrState ; |
reg [4:0] NextState ; |
reg riack; |
always @(posedge clk) if (~rst) riack<=0; else riack<=iack; |
|
always @(*) |
begin //deal with iack |
case (CurrState ) |
`IRQ:iack=1'b1; |
`RET:iack=1'b0; |
//onlt this 2 states those will change the iack state |
default iack=riack; |
endcase |
end |
|
always @ (posedge clk ) |
if (~rst)delay_counter <=0; |
else |
case (CurrState) |
//any delay state can be added here |
`MUL: delay_counter <=delay_counter + 1; |
default : delay_counter <=0; |
endcase |
|
///////////////////////////////////////////////////////// |
// Finite State Machine |
// |
/*Finite State Machine part1*/ |
always @ (posedge clk) if (~rst) CurrState <= `RST; else CurrState <= NextState ; |
|
always @ (*)/*Finite State Machine part2*/ |
begin |
case (CurrState) |
`IDLE: |
begin |
if (~rst) NextState = `RST; |
// else if ((irq)&&(~riack)) NextState = `IRQ; |
else if (id_cmd ==ID_NOI) NextState = `NOI; |
else if (id_cmd==ID_CUR) NextState = `CUR; |
else if (id_cmd==ID_MUL) NextState = `MUL; |
else if (id_cmd==ID_LD) NextState = `LD; |
else if (id_cmd==ID_RET) NextState = `RET; |
else NextState = `IDLE; |
end |
`NOI: |
begin |
if (id_cmd ==ID_NOI) NextState = `NOI; |
else if (id_cmd==ID_CUR) NextState = `CUR; |
else if (id_cmd==ID_MUL) NextState = `MUL; |
else if (id_cmd==ID_LD) NextState = `LD; |
else if (id_cmd==ID_RET) NextState = `RET; |
else NextState = `IDLE; |
end |
`CUR: NextState = `NOI; |
`RET: NextState = `IDLE; |
`IRQ: NextState = `IDLE; |
`RST: NextState = `IDLE; |
`LD: NextState = `IDLE; |
`MUL: NextState = (delay_counter==32)?`IDLE:`MUL; |
default NextState =`IDLE; |
endcase |
end |
|
always @ (*)/*Finite State Machine part3*/ |
begin |
case (CurrState ) |
`IDLE: begin id2ra_ins_clr = 1'b0; |
id2ra_ins_cls = 1'b0; |
id2ra_ctl_clr = 1'b0; |
id2ra_ctl_cls = 1'b0; |
ra2exec_ctl_clr = 1'b0; |
pc_prectl=PC_IGN; |
zz_is_nop = 0;end |
`MUL: begin |
id2ra_ins_clr = 1'b1; |
id2ra_ins_cls = 1'b0; |
id2ra_ctl_clr = 1'b1; |
id2ra_ctl_cls = 1'b0; |
ra2exec_ctl_clr = 1'b0; |
pc_prectl =PC_KEP; |
zz_is_nop =0; end |
`CUR: begin |
id2ra_ins_clr = 1'b0; |
id2ra_ins_cls = 1'b1; |
id2ra_ctl_clr = 1'b0; |
id2ra_ctl_cls = 1'b1; |
ra2exec_ctl_clr = 1'b1; |
pc_prectl =PC_KEP; |
zz_is_nop = 1; end |
`RET: begin id2ra_ins_clr = 1'b0; |
id2ra_ins_cls = 1'b0; |
id2ra_ctl_clr = 1'b0; |
id2ra_ctl_cls = 1'b0; |
ra2exec_ctl_clr = 1'b0; |
pc_prectl =PC_IGN; |
zz_is_nop = 1'b0; end |
`IRQ: begin |
id2ra_ins_clr = 1'b1; |
id2ra_ins_cls = 1'b0; |
id2ra_ctl_clr = 1'b1; |
id2ra_ctl_cls = 1'b0; |
ra2exec_ctl_clr = 1'b1; |
pc_prectl =PC_IRQ; |
zz_is_nop = 1'b0;end |
`RST: begin |
id2ra_ins_clr = 1'b1; |
id2ra_ins_cls = 1'b0; |
id2ra_ctl_clr = 1'b1; |
id2ra_ctl_cls = 1'b0; |
ra2exec_ctl_clr = 1'b1; |
pc_prectl=PC_RST; |
zz_is_nop = 1'b1; end |
`LD:begin |
id2ra_ins_clr = 1'b1; |
id2ra_ins_cls = 1'b0; |
id2ra_ctl_clr = 1'b1; |
id2ra_ctl_cls = 1'b0; |
ra2exec_ctl_clr = 1'b0; |
pc_prectl =PC_KEP; |
zz_is_nop = 1'b0;end |
`NOI:begin |
id2ra_ins_clr = 1'b0; |
id2ra_ins_cls = 1'b0; |
id2ra_ctl_clr = 1'b0; |
id2ra_ctl_cls = 1'b0; |
ra2exec_ctl_clr = 1'b0; |
pc_prectl=PC_IGN; |
zz_is_nop = 1'b0;end |
default begin |
id2ra_ins_clr = 1'b1; |
id2ra_ins_cls = 1'b0; |
id2ra_ctl_clr = 1'b1; |
id2ra_ctl_cls = 1'b0; |
ra2exec_ctl_clr = 1'b1; |
pc_prectl=PC_RST; |
zz_is_nop = 1'b1;end |
endcase |
end |
endmodule |
|
/trunk/rtl/verilog/mips_top.v
0,0 → 1,112
/****************************************************************** |
* * |
* Author: Liwei * |
* * |
* This file is part of the "mips789" project. * |
* Downloaded from: * |
* http://www.opencores.org/pdownloads.cgi/list/mips789 * |
* * |
* If you encountered any problem, please contact me via * |
* Email:mcupro@opencores.org or mcupro@163.com * |
* * |
******************************************************************/ |
|
`include "mips789_defs.v" |
// synopsys translate_off |
`define use_rst |
// synopsys translate_on |
|
`define use_rst |
module mips_top ( |
input clk, |
`ifdef use_rst |
input rst, |
`endif |
|
input tdi, |
output tdo, |
output tms, |
output tck, |
input int2,int1, |
inout [15:0] usb_data , |
output addr0, addr1, cs,wr,rd,oe,pkt_end ,led ,oe573 , |
input pa1,pa3, |
output trst,brst,dint |
); |
|
`ifndef use_rst |
wire rst = 1'b1; |
`endif |
assign trst=1'b1; |
assign brst=1'b1; |
assign dint=1'b1; |
|
wire [31:0] data2core; |
wire [31:0] data2mem; |
wire [31:0] ins2core; |
wire [31:0] mem_Addr; |
wire [31:0] pc; |
wire [3:0] wr_en; |
wire CLK; |
reg r_rst,rr_rst; |
always @(posedge CLK) |
r_rst<=rst; |
always @(posedge CLK) |
rr_rst<=r_rst; |
wire sys_rst = rr_rst; |
// assign CLK = clk; |
pll24_80 PLL( |
.inclk0(clk), |
.c0(CLK)); |
// synopsys translate_off |
`define just_sim |
// synopsys translate_on |
|
`ifdef just_sim |
|
sim_mem_array sim_array |
`else |
|
mem_array ram_8k//FPGA RAM |
`endif |
( |
.clk(CLK), |
.pc_i(pc), |
.ins_o(ins2core), |
.wren(wr_en), |
.din(data2mem), |
.data_addr_i(mem_Addr), |
.dout(data2core) |
); |
|
mips_sys isys |
( |
.zz_addr_o(mem_Addr), |
.zz_din(data2core), |
.zz_dout(data2mem), |
.zz_ins_i(ins2core), |
.zz_pc_o(pc), |
.zz_wr_en_o(wr_en), |
|
.clk(CLK), |
.rst(sys_rst), |
.tdi(tdi), |
.tdo(tdo), |
.tms(tms), |
.tck(tck), |
.int2(int2), |
.int1(int1), |
.usb_data(usb_data) , |
.addr0(addr0), |
.addr1(addr1), |
.cs(cs), |
.wr(wr), |
.rd(rd), |
.oe(oe), |
.pkt_end(pkt_end) , |
.led(led) , |
.oe573(oe573) |
); |
endmodule |
|
|
/trunk/rtl/verilog/RF_stage.v
0,0 → 1,242
/****************************************************************** |
* * |
* Author: Liwei * |
* * |
* This file is part of the "mips789" project. * |
* Downloaded from: * |
* http://www.opencores.org/pdownloads.cgi/list/mips789 * |
* * |
* If you encountered any problem, please contact me via * |
* Email:mcupro@opencores.org or mcupro@163.com * |
* * |
******************************************************************/ |
|
`include "mips789_defs.v" |
|
module rf_stage ( |
clk,irq_i,rst_i,wb_we_i,cmp_ctl_i, |
ext_ctl_i,fw_alu_i,fw_cmp_rs,fw_cmp_rt, |
fw_mem_i,id_cmd,ins_i,irq_addr_i,pc_gen_ctl, |
pc_i,rd_sel_i,wb_addr_i,wb_din_i,zz_spc_i,iack_o, |
id2ra_ctl_clr_o,id2ra_ctl_cls_o,ra2ex_ctl_clr_o,ext_o, |
pc_next,rd_index_o,rs_n_o,rs_o,rt_n_o,rt_o |
) ; |
|
input clk; |
wire clk; |
input irq_i; |
wire irq_i; |
input rst_i; |
wire rst_i; |
input wb_we_i; |
wire wb_we_i; |
input [2:0] cmp_ctl_i; |
wire [2:0] cmp_ctl_i; |
input [2:0] ext_ctl_i; |
wire [2:0] ext_ctl_i; |
input [31:0] fw_alu_i; |
wire [31:0] fw_alu_i; |
input [2:0] fw_cmp_rs; |
wire [2:0] fw_cmp_rs; |
input [2:0] fw_cmp_rt; |
wire [2:0] fw_cmp_rt; |
input [31:0] fw_mem_i; |
wire [31:0] fw_mem_i; |
input [2:0] id_cmd; |
wire [2:0] id_cmd; |
input [31:0] ins_i; |
wire [31:0] ins_i; |
input [31:0] irq_addr_i; |
wire [31:0] irq_addr_i; |
input [2:0] pc_gen_ctl; |
wire [2:0] pc_gen_ctl; |
input [31:0] pc_i; |
wire [31:0] pc_i; |
input [1:0] rd_sel_i; |
wire [1:0] rd_sel_i; |
input [4:0] wb_addr_i; |
wire [4:0] wb_addr_i; |
input [31:0] wb_din_i; |
wire [31:0] wb_din_i; |
input [31:0] zz_spc_i; |
wire [31:0] zz_spc_i; |
output iack_o; |
wire iack_o; |
output id2ra_ctl_clr_o; |
wire id2ra_ctl_clr_o; |
output id2ra_ctl_cls_o; |
wire id2ra_ctl_cls_o; |
output ra2ex_ctl_clr_o; |
wire ra2ex_ctl_clr_o; |
output [31:0] ext_o; |
wire [31:0] ext_o; |
output [31:0] pc_next; |
wire [31:0] pc_next; |
output [4:0] rd_index_o; |
wire [4:0] rd_index_o; |
output [4:0] rs_n_o; |
wire [4:0] rs_n_o; |
output [31:0] rs_o; |
wire [31:0] rs_o; |
output [4:0] rt_n_o; |
wire [4:0] rt_n_o; |
output [31:0] rt_o; |
wire [31:0] rt_o; |
|
|
wire NET6609; |
wire NET6658; |
wire NET7774; |
wire NET904; |
|
wire [3:0] BUS1013; |
wire [31:0] BUS2085; |
wire [4:0] BUS3236; |
wire [4:0] BUS3237; |
wire [4:0] BUS5421; |
wire [31:0] BUS6061; |
wire [31:0] BUS6095; |
|
wire [100:0] CLK_NO; |
wire [100:0] INS_NO; |
|
cal_cpi CAL_CPI |
( |
.clk(clk), |
.clk_no(CLK_NO), |
.ins_no(INS_NO), |
.is_nop(NET7774), |
.rst(rst_i) |
); |
|
|
|
ctl_FSM MAIN_FSM |
( |
.clk(clk), |
.iack(iack_o), |
.id2ra_ctl_clr(id2ra_ctl_clr_o), |
.id2ra_ctl_cls(id2ra_ctl_cls_o), |
.id2ra_ins_clr(NET6609), |
.id2ra_ins_cls(NET6658), |
.id_cmd(id_cmd), |
.irq(irq_i), |
.pc_prectl(BUS1013), |
.ra2exec_ctl_clr(ra2ex_ctl_clr_o), |
.rst(rst_i), |
.zz_is_nop(NET7774) |
); |
|
|
|
pc_gen i_pc_gen |
( |
.check(NET904), |
.ctl(pc_gen_ctl), |
.imm(ext_o), |
.irq(irq_addr_i), |
.pc(pc_i), |
.pc_next(pc_next), |
.pc_prectl(BUS1013), |
.s(rs_o), |
.zz_spc(zz_spc_i) |
); |
|
|
|
compare i_cmp |
( |
.ctl(cmp_ctl_i), |
.res(NET904), |
.s(rs_o), |
.t(rt_o) |
); |
|
|
|
ext i_ext |
( |
.ctl(ext_ctl_i), |
.ins_i(BUS2085), |
.res(ext_o) |
); |
|
|
|
r32_reg_clr_cls ins_reg |
( |
.clk(clk), |
.clr(NET6609), |
.cls(NET6658), |
.r32_i(ins_i), |
.r32_o(BUS2085) |
); |
|
|
|
jack jack1 |
( |
.ins_i(BUS2085), |
.rd_o(BUS5421), |
.rs_o(rs_n_o), |
.rt_o(rt_n_o) |
); |
|
|
|
jack jack2 |
( |
.ins_i(ins_i), |
.rs_o(BUS3237), |
.rt_o(BUS3236) |
); |
|
rd_sel rd_sel |
( |
.ctl(rd_sel_i), |
.rd_i(BUS5421), |
.rd_o(rd_index_o), |
.rt_i(rt_n_o) |
);/* |
wire bank_sel; |
dly3clk bank_sel_dly |
( |
.r1_i(iack_o), |
.r1_o(bank_sel), |
.clk(clk), |
.rst(rst_i) |
);*/ |
|
reg_array reg_bank |
( |
.clock(clk), |
.data(wb_din_i), |
.qa(BUS6061), |
.qb(BUS6095), |
.rd_clk_cls(NET6658), |
.rdaddress_a(BUS3237), |
.rdaddress_b(BUS3236), |
.wraddress(wb_addr_i), |
.wren(wb_we_i)/*, |
.bank_sel(1'b0)*/ |
); |
|
fwd_mux rf_fwd_rt |
( |
.din(BUS6095), |
.dout(rt_o), |
.fw_alu(fw_alu_i), |
.fw_ctl(fw_cmp_rt), |
.fw_dmem(fw_mem_i) |
); |
|
fwd_mux rs_fwd_rs |
( |
.din(BUS6061), |
.dout(rs_o), |
.fw_alu(fw_alu_i), |
.fw_ctl(fw_cmp_rs), |
.fw_dmem(fw_mem_i) |
); |
|
endmodule |
/trunk/rtl/verilog/decode_pipe.v
0,0 → 1,1605
/****************************************************************** |
* * |
* Author: Liwei * |
* * |
* This file is part of the "mips789" project. * |
* Downloaded from: * |
* http://www.opencores.org/pdownloads.cgi/list/mips789 * |
* * |
* If you encountered any problem, please contact me via * |
* Email:mcupro@opencores.org or mcupro@163.com * |
* * |
******************************************************************/ |
|
`include "mips789_defs.v" |
module decoder( |
input [31:0]ins_i, |
output reg [`EXT_CTL_LEN-1:0] ext_ctl, |
output reg [`RD_SEL_LEN-1:0] rd_sel, |
output reg [`CMP_CTL_LEN-1:0]cmp_ctl, |
output reg [`PC_GEN_CTL_LEN-1:0]pc_gen_ctl, |
output reg [`FSM_CTL_LEN-1:0]fsm_dly, |
output reg [`MUXA_CTL_LEN-1:0]muxa_ctl, |
output reg [`MUXB_CTL_LEN-1:0]muxb_ctl, |
output reg [`ALU_FUNC_LEN-1:0]alu_func, |
output reg [`DMEM_CTL_LEN-1:0]dmem_ctl, |
output reg [`ALU_WE_LEN-1:0] alu_we, |
output reg [`WB_MUX_CTL_LEN-1:0]wb_mux, |
output reg [`WB_WE_LEN-1:0]wb_we |
); |
|
wire [5:0] inst_op,inst_func; |
wire [4:0] inst_regimm;//,inst_rs,inst_rt,inst_rd,inst_sa; |
wire [4:0] inst_cop0_func;//cop0's function code filed |
wire [25:0] inst_cop0_code;//cop0's code field |
|
assign inst_op = ins_i[31:26]; |
assign inst_func = ins_i[5:0]; |
assign inst_regimm = ins_i[20:16]; |
assign inst_cop0_func = ins_i[25:21]; |
assign inst_cop0_code = ins_i[25:0]; |
|
always @(*) |
begin |
case (inst_op)//synthesis parallel_case |
'd0://special operation |
begin |
case (inst_func) //synthesis parallel_case |
'd0://SLL rd,rt,sa |
begin |
//replaceID = `SLL ; |
ext_ctl = `EXT_SA; |
rd_sel = `RD_RD; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_EXT; |
muxb_ctl = `MUXB_RT; |
alu_func = `ALU_SLL; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_ALU; |
//end of `SLL ; |
end |
'd2://SRL rd,rt,sa |
begin |
//replaceID = `SRL ; |
ext_ctl = `EXT_SA; |
rd_sel = `RD_RD; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_EXT; |
muxb_ctl = `MUXB_RT; |
alu_func = `ALU_SRL; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_ALU; |
//end of `SRL ; |
end |
'd3://SRA rd,rt,sa |
begin |
//replaceID = `SRA ; |
ext_ctl = `EXT_SA; |
rd_sel = `RD_RD; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_EXT; |
muxb_ctl = `MUXB_RT; |
alu_func = `ALU_SRA; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_ALU; |
//end of `SRA ; |
end |
'd4://SLLV rd,rt,rs |
begin |
//replaceID = `SLLV ; |
ext_ctl = `IGN; |
rd_sel = `IGN; |
cmp_ctl = `IGN; |
pc_gen_ctl = `IGN; |
fsm_dly = `IGN; |
muxa_ctl = `IGN; |
muxb_ctl = `IGN; |
alu_func = `IGN; |
alu_we = `IGN; |
dmem_ctl = `IGN; |
wb_we = `IGN; |
wb_mux = 1'bx;//`IGN; |
//end of `SLLV ; |
end |
'd6://SRLV rd,rt,rs |
begin |
//replaceID = `SRLV ; |
ext_ctl = `IGN; |
rd_sel = `IGN; |
cmp_ctl = `IGN; |
pc_gen_ctl = `IGN; |
fsm_dly = `IGN; |
muxa_ctl = `IGN; |
muxb_ctl = `IGN; |
alu_func = `IGN; |
alu_we = `IGN; |
dmem_ctl = `IGN; |
wb_we = `IGN; |
wb_mux = `IGN; |
//end of `SRLV ; |
end |
'd7://SRAV rd,rt,rs |
begin |
//replaceID = `SRAV ; |
ext_ctl = `IGN; |
rd_sel = `IGN; |
cmp_ctl = `IGN; |
pc_gen_ctl = `IGN; |
fsm_dly = `IGN; |
muxa_ctl = `IGN; |
muxb_ctl = `IGN; |
alu_func = `IGN; |
alu_we = `IGN; |
dmem_ctl = `IGN; |
wb_we = `IGN; |
wb_mux = `IGN; |
//end of `SRAV ; |
end |
'd8://JR rs |
begin |
//replaceID = `JR ; |
ext_ctl = `EXT_NOP; |
rd_sel = `RD_NOP; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_JR; |
fsm_dly = `FSM_CUR; |
muxa_ctl = `MUXA_NOP; |
muxb_ctl = `MUXB_NOP; |
alu_func = `ALU_NOP; |
alu_we = `DIS; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_NOP; |
//end of `JR ; |
end |
'd9://JALR jalr rs(rd=31) or jalr rd,rs |
begin |
//replaceID = `JALR ; |
ext_ctl = `IGN; |
rd_sel = `IGN; |
cmp_ctl = `IGN; |
pc_gen_ctl = `IGN; |
fsm_dly = `IGN; |
muxa_ctl = `IGN; |
muxb_ctl = `IGN; |
alu_func = `IGN; |
alu_we = `IGN; |
dmem_ctl = `IGN; |
wb_we = `IGN; |
wb_mux = `IGN; |
//end of `JALR ; |
end |
'd12://SYSCALL |
begin |
//replaceID = `SYSCALL ; |
ext_ctl = `IGN; |
rd_sel = `IGN; |
cmp_ctl = `IGN; |
pc_gen_ctl = `IGN; |
fsm_dly = `IGN; |
muxa_ctl = `IGN; |
muxb_ctl = `IGN; |
alu_func = `IGN; |
alu_we = `IGN; |
dmem_ctl = `IGN; |
wb_we = `IGN; |
wb_mux = `IGN; |
//end of `SYSCALL ; |
end |
'd13://BREAK |
begin |
//replaceID = `BREAK ; |
ext_ctl = `IGN; |
rd_sel = `IGN; |
cmp_ctl = `IGN; |
pc_gen_ctl = `IGN; |
fsm_dly = `IGN; |
muxa_ctl = `IGN; |
muxb_ctl = `IGN; |
alu_func = `IGN; |
alu_we = `IGN; |
dmem_ctl = `IGN; |
wb_we = `IGN; |
wb_mux = `IGN; |
//end of `BREAK ; |
end |
'd16://MFHI rd |
begin |
//replaceID = `MFHI ; |
ext_ctl = `EXT_NOP; |
rd_sel = `RD_RD; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_NOP; |
muxb_ctl = `MUXB_NOP; |
alu_func = `ALU_MFHI; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_ALU; |
//end of `MFHI ; |
end |
'd17://MTHI rs |
begin |
//replaceID = `MTHI ; |
ext_ctl = `EXT_NOP ; |
rd_sel = `RD_NOP; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_NOP; |
alu_func = `ALU_MTHI; |
alu_we = `DIS; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_NOP; |
//end of `MTHI ; |
end |
'd18://MFLO rd |
begin |
//replaceID = `MFLO ; |
ext_ctl = `EXT_NOP ; |
rd_sel = `RD_RD; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_NOP; |
muxb_ctl = `MUXB_NOP; |
alu_func = `ALU_MFLO; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_ALU; |
//end of `MFLO ; |
end |
'd19://MTLO rs |
begin |
//replaceID = `MTLO ; |
ext_ctl = `EXT_NOP ; |
rd_sel = `RD_NOP; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_NOP; |
muxb_ctl = `MUXB_NOP; |
alu_func = `ALU_MFLO; |
alu_we = `DIS; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_NOP; |
|
//end of `MTLO ; |
end |
'd24://MULT rs,rt |
begin |
//replaceID = `MULT ; |
ext_ctl = `EXT_NOP; |
rd_sel = `RD_NOP; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_MUL; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_RT; |
alu_func = `ALU_MULT; |
alu_we = `DIS; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_NOP; |
//end of `MULT ; |
end |
'd25://MULTU rs,rt |
begin |
//replaceID = `MULTU ; |
ext_ctl = `EXT_NOP; |
rd_sel = `RD_NOP; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_MUL; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_RT; |
alu_func = `ALU_MULTU; |
alu_we = `DIS; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_NOP; |
//end of `MULTU ; |
end |
'd26://DIV rs,rt |
begin |
//replaceID = `DIV ; |
ext_ctl = `EXT_NOP; |
rd_sel = `RD_NOP; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_MUL; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_RT; |
alu_func = `ALU_DIV; |
alu_we = `DIS; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_NOP; |
//end of `DIV ; |
end |
'd27://DIVU rs,rt |
begin |
//replaceID = `DIVU ; |
ext_ctl = `EXT_NOP; |
rd_sel = `RD_NOP; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_MUL; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_RT; |
alu_func = `ALU_DIVU; |
alu_we = `DIS; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_NOP; |
//end of `DIVU ; |
end |
'd32://ADD rd,rs,rt |
begin |
//replaceID = `ADD ; |
ext_ctl = `EXT_NOP; |
rd_sel = `RD_RD; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_RT; |
alu_func = `ALU_ADD; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_ALU; |
//end of `ADD ; |
end |
'd33://ADDU rd,rs,rt |
begin |
//replaceID = `ADDU ; |
ext_ctl = `EXT_NOP; |
rd_sel = `RD_RD; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_RT; |
alu_func = `ALU_ADD; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_ALU; |
//end of `ADDU ; |
end |
'd34://SUB rd,rs,rt |
begin |
//replaceID = `SUB ; |
ext_ctl = `EXT_NOP; |
rd_sel = `RD_RD; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_RT; |
alu_func = `ALU_SUB; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_ALU; |
//end of `SUB ; |
end |
'd35://SUBU rd,rs,rt |
begin |
//replaceID = `SUBU ; |
ext_ctl = `EXT_NOP; |
rd_sel = `RD_RD; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_RT; |
alu_func = `ALU_SUBU; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_ALU; |
//end of `SUBU ; |
end |
'd36://AND rd,rs,rt |
begin |
//replaceID = `AND ; |
ext_ctl = `EXT_NOP; |
rd_sel = `RD_RD; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_RT; |
alu_func = `ALU_AND; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_ALU; |
//end of `AND ; |
end |
'd37://OR rd,rs,rt |
begin |
//replaceID = `OR ; |
ext_ctl = `EXT_NOP; |
rd_sel = `RD_RD; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_RT; |
alu_func = `ALU_OR; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_ALU; |
//end of `OR ; |
end |
'd38://XOR rd,rs,rt |
begin |
//replaceID = `XOR ; |
ext_ctl = `EXT_NOP; |
rd_sel = `RD_RD; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_RT; |
alu_func = `ALU_XOR; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_ALU; |
//end of `XOR ; |
end |
'd39://NOR rd,rs,rt |
begin |
//replaceID = `NOR ; |
ext_ctl = `EXT_NOP; |
rd_sel = `RD_RD; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_RT; |
alu_func = `ALU_NOR; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_ALU; |
//end of `NOR ; |
end |
'd42://SLT rd,rs,rt |
begin |
//replaceID = `SLT ; |
ext_ctl = `EXT_SIGN; |
rd_sel = `RD_RD; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_RT; |
alu_func = `ALU_SLT; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_ALU; |
//end of `SLT ; |
end |
'd43://SLTU rd,rs,rt |
begin |
//replaceID = `SLTU ; |
ext_ctl = `EXT_NOP; |
rd_sel = `RD_RD; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_RT; |
alu_func = `ALU_SLTU; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_ALU; |
//end of `SLTU ; |
end |
default: |
begin |
//replaceID = `INVALID ; |
ext_ctl = `IGN; |
rd_sel = `IGN; |
cmp_ctl = `IGN; |
pc_gen_ctl = `IGN; |
fsm_dly = `IGN; |
muxa_ctl = `IGN; |
muxb_ctl = `IGN; |
alu_func = `IGN; |
alu_we = `IGN; |
dmem_ctl = `IGN; |
wb_we = `IGN; |
wb_mux = `IGN; |
//end of `INVALID ; |
end |
endcase |
end |
'd1://regimm opreation |
begin |
case (inst_regimm) //synthesis parallel_case |
'd0://BLTZ rs,offset(signed) |
begin |
//replaceID = `BLTZ ; |
ext_ctl = `EXT_B; |
rd_sel = `RD_NOP; |
cmp_ctl = `CMP_BLTZ; |
pc_gen_ctl = `PC_BC; |
fsm_dly = `FSM_CUR; |
muxa_ctl = `MUXA_NOP; |
muxb_ctl = `MUXB_NOP; |
alu_func = `ALU_NOP; |
alu_we = `DIS; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_NOP; |
//end of `BLTZ ; |
end |
'd1://BGEZ rs,offset(signed) |
begin |
//replaceID = `BGEZ ; |
ext_ctl = `EXT_B; |
rd_sel = `RD_NOP; |
cmp_ctl = `CMP_BGEZ; |
pc_gen_ctl = `PC_BC; |
fsm_dly = `FSM_CUR; |
muxa_ctl = `MUXA_NOP; |
muxb_ctl = `MUXB_NOP; |
alu_func = `ALU_NOP; |
alu_we = `DIS; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_NOP; |
//end of `BGEZ ; |
end |
'd16://BLTZAL rs,offset(signed) |
begin |
//replaceID = `BLTZAL ; |
ext_ctl = `IGN; |
rd_sel = `IGN; |
cmp_ctl = `IGN; |
pc_gen_ctl = `IGN; |
fsm_dly = `IGN; |
muxa_ctl = `IGN; |
muxb_ctl = `IGN; |
alu_func = `IGN; |
alu_we = `IGN; |
dmem_ctl = `IGN; |
wb_we = `IGN; |
wb_mux = `IGN; |
//end of `BLTZAL ; |
end |
'd17://BGEZAL rs,offset(signed) |
begin |
//replaceID = `BGEZAL ; |
//replaceID = `INVALID ; |
ext_ctl = `IGN; |
rd_sel = `IGN; |
cmp_ctl = `IGN; |
pc_gen_ctl = `IGN; |
fsm_dly = `IGN; |
muxa_ctl = `IGN; |
muxb_ctl = `IGN; |
alu_func = `IGN; |
alu_we = `IGN; |
dmem_ctl = `IGN; |
wb_we = `IGN; |
wb_mux = `IGN; |
//end of `INVALID ; |
end |
default: |
begin |
//replaceID = `INVALID ; |
//replaceID = `INVALID ; |
ext_ctl = `IGN; |
rd_sel = `IGN; |
cmp_ctl = `IGN; |
pc_gen_ctl = `IGN; |
fsm_dly = `IGN; |
muxa_ctl = `IGN; |
muxb_ctl = `IGN; |
alu_func = `IGN; |
alu_we = `IGN; |
dmem_ctl = `IGN; |
wb_we = `IGN; |
wb_mux = `IGN; |
//end of `INVALID ; |
end |
endcase |
end |
'd2://J imm26({pc[31:28],imm26,00}) |
begin |
//replaceID = `J ; |
ext_ctl = `EXT_J; |
rd_sel = `RD_NOP; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_J; |
fsm_dly = `FSM_NOI; |
muxa_ctl = `MUXA_NOP; |
muxb_ctl = `MUXB_NOP; |
alu_func = `ALU_NOP; |
alu_we = `DIS; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_NOP; |
//end of `J ; |
end |
'd3://JAL imm26({pc[31:28],imm26,00}) |
begin |
//replaceID = `JAL ; |
|
ext_ctl = `EXT_J; |
rd_sel = `RD_R31; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_J; |
fsm_dly = `FSM_NOI; |
muxa_ctl = `MUXA_PC; |
muxb_ctl = `MUXB_RT; |
alu_func = `ALU_PA; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_ALU; |
//end of `JAL ; |
end |
'd4://BEQ rs,rt,offset(signed) |
begin |
//replaceID = `BEQ ; |
ext_ctl = `EXT_B; |
rd_sel = `RD_NOP; |
cmp_ctl = `CMP_BEQ; |
pc_gen_ctl = `PC_BC; |
fsm_dly = `FSM_CUR; |
muxa_ctl = `MUXA_NOP; |
muxb_ctl = `MUXB_NOP; |
alu_func = `ALU_NOP; |
alu_we = `DIS; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_NOP; |
//end of `BEQ ; |
end |
'd5://BNE rs,rt,offset(signed) |
begin |
//replaceID = `BNE ; |
ext_ctl = `EXT_B; |
rd_sel = `RD_NOP; |
cmp_ctl = `CMP_BNE; |
pc_gen_ctl = `PC_BC; |
fsm_dly = `FSM_CUR; |
muxa_ctl = `MUXA_NOP; |
muxb_ctl = `MUXB_NOP; |
alu_func = `ALU_NOP; |
alu_we = `DIS; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_NOP; |
//end of `BNE ; |
end |
'd6://BLEZ rs,offset(signed) |
begin |
//replaceID = `BLEZ ; |
ext_ctl = `EXT_B; |
rd_sel = `RD_NOP; |
cmp_ctl = `CMP_BLEZ; |
pc_gen_ctl = `PC_BC; |
fsm_dly = `FSM_CUR; |
muxa_ctl = `MUXA_NOP; |
muxb_ctl = `MUXB_NOP; |
alu_func = `ALU_NOP; |
alu_we = `DIS; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_NOP; |
//end of `BLEZ ; |
end |
'd7://BGTZ rs,offset(signed) |
begin |
//replaceID = `BGTZ ; |
ext_ctl = `EXT_B; |
rd_sel = `RD_NOP; |
cmp_ctl = `CMP_BGTZ; |
pc_gen_ctl = `PC_BC; |
fsm_dly = `FSM_CUR; |
muxa_ctl = `MUXA_NOP; |
muxb_ctl = `MUXB_NOP; |
alu_func = `ALU_NOP; |
alu_we = `DIS; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_NOP; |
//end of `BGTZ ; |
end |
'd8://ADDI rt,rs,imm16(singed) |
begin |
//replaceID = `ADDI ; |
ext_ctl = `EXT_SIGN; |
rd_sel = `RD_RT; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_EXT; |
alu_func = `ALU_ADD; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_ALU; |
//end of `ADDI ; |
end |
'd9://ADDIU rt,rs,imm16(singed) |
begin |
//replaceID = `ADDIU ; |
ext_ctl = `EXT_SIGN; |
rd_sel = `RD_RT; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_EXT; |
alu_func = `ALU_ADD; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_ALU; |
//end of `ADDIU ; |
end |
'd10://SLTI rt,rs,imm16(singed) |
begin |
//replaceID = `SLTI ; |
ext_ctl = `EXT_SIGN; |
rd_sel = `RD_RT; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_EXT; |
alu_func = `ALU_SLT; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_ALU; |
//end of `SLTI ; |
end |
'd11://SLTIU rt,rs,imm16(singed) |
begin |
//replaceID = `SLTIU ; |
ext_ctl = `EXT_UNSIGN; |
rd_sel = `RD_RT; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_EXT; |
alu_func = `ALU_SLTU; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_ALU; |
//end of `SLTIU ; |
end |
'd12://ANDI rt,rs,imm16(singed) |
begin |
//replaceID = `ANDI ; |
ext_ctl = `EXT_UNSIGN; |
rd_sel = `RD_RT; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_EXT; |
alu_func = `ALU_AND; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_ALU; |
//end of `ANDI ; |
end |
'd13://ORI rt,rs,imm16(singed) |
begin |
//replaceID = `ORI ; |
ext_ctl = `EXT_UNSIGN; |
rd_sel = `RD_RT; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_EXT; |
alu_func = `ALU_OR; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_NOP; |
//end of `ORI ; |
end |
'd14://XORI rt,rs,imm16(singed) |
begin |
//replaceID = `XORI ; |
ext_ctl = `EXT_UNSIGN; |
rd_sel = `RD_RT; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_EXT; |
alu_func = `ALU_XOR; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `EN; |
wb_mux = `WB_ALU; |
//end of `XORI ; |
end |
'd15://LUI rt,imm16 |
begin |
//replaceID = `LUI ; |
ext_ctl = `EXT_S2H; |
rd_sel = `RD_RT; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_EXT; |
alu_func = `ALU_PB; |
alu_we = `EN; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_ALU; |
//end of `LUI ; |
end |
'd16://COP0 func |
begin |
case(inst_cop0_func) //synthesis parallel_case |
'd0://mfc0 rt,rd // GPR[rd] = CPR[rt] //differ to mips32 definition |
//read saved PC |
begin |
//replaceID = `MFC0; |
ext_ctl = `EXT_NOP; |
rd_sel = `RD_RD; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_SPC; |
muxb_ctl = `MUXB_EXT; |
alu_func = `ALU_PA; |
alu_we = `EN; |
dmem_ctl = `DMEM_LB; |
wb_we = `DIS; |
wb_mux = `WB_ALU; |
end |
|
'd4://mtc0 rt,rd // CPR[rd] = GPR[rt] //follow the mips32 definition |
begin //return from interrupt |
$display("mtco"); |
//replaceID = `MTC0; |
ext_ctl = `EXT_NOP; |
rd_sel = `RD_NOP; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_SPC; |
fsm_dly = `FSM_RET; |
muxa_ctl = `MUXA_NOP; |
muxb_ctl = `MUXB_NOP; |
alu_func = `ALU_NOP; |
alu_we = `DIS; |
dmem_ctl = `DMEM_NOP; |
wb_we = `DIS; |
wb_mux = `WB_NOP; |
end |
default: |
begin |
//replaceID = `INVALID ; |
ext_ctl = `IGN; |
rd_sel = `IGN; |
cmp_ctl = `IGN; |
pc_gen_ctl = `IGN; |
fsm_dly = `IGN; |
muxa_ctl = `IGN; |
muxb_ctl = `IGN; |
alu_func = `IGN; |
alu_we = `IGN; |
dmem_ctl = `IGN; |
wb_we = `IGN; |
wb_mux = `IGN; |
//end of `INVALID ; |
end |
endcase |
end |
'd32://LB rt,offset(base) (offset:signed;base:rs) |
begin |
//replaceID = `LB ; |
ext_ctl = `EXT_SIGN; |
rd_sel = `RD_RT; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_EXT; |
alu_func = `ALU_ADD; |
alu_we = `DIS; |
dmem_ctl = `DMEM_LBS; |
wb_we = `EN; |
wb_mux = `WB_MEM; |
//end of `LB ; |
end |
'd33://LH rt,offset(base) (offset:signed;base:rs) |
begin |
//replaceID = `LH ; |
ext_ctl = `EXT_SIGN; |
rd_sel = `RD_RT; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_EXT; |
alu_func = `ALU_ADD; |
alu_we = `DIS; |
dmem_ctl = `DMEM_LHS; |
wb_we = `EN; |
wb_mux = `WB_MEM; |
//end of `LH ; |
end |
'd34://LWL rt,offset(base) (offset:signed;base:rs) |
begin |
//replaceID = `LWL ; |
ext_ctl = `IGN; |
rd_sel = `IGN; |
cmp_ctl = `IGN; |
pc_gen_ctl = `IGN; |
fsm_dly = `IGN; |
muxa_ctl = `IGN; |
muxb_ctl = `IGN; |
alu_func = `IGN; |
alu_we = `IGN; |
dmem_ctl = `IGN; |
wb_we = `IGN; |
wb_mux = `IGN; |
//end of `LWL ; |
end |
'd35://LW rt,offset(base) (offset:signed;base:rs) |
begin |
//replaceID = `LW ; |
ext_ctl = `EXT_SIGN; |
rd_sel = `RD_RT; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_EXT; |
alu_func = `ALU_ADD; |
alu_we = `DIS; |
dmem_ctl = `DMEM_LW; |
wb_we = `EN; |
wb_mux = `WB_MEM; |
//end of `LW ; |
end |
'd36://LBU rt,offset(base) (offset:signed;base:rs) |
begin |
//replaceID = `LBU ; |
ext_ctl = `EXT_SIGN; |
rd_sel = `RD_RT; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_EXT; |
alu_func = `ALU_ADD; |
alu_we = `DIS; |
dmem_ctl = `DMEM_LBU; |
wb_we = `EN; |
wb_mux = `WB_MEM; |
//end of `LBU ; |
end |
'd37://LHU rt,offset(base) (offset:signed;base:rs) |
begin |
//replaceID = `LHU ; |
ext_ctl = `EXT_SIGN; |
rd_sel = `RD_RT; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_EXT; |
alu_func = `ALU_ADD; |
alu_we = `DIS; |
dmem_ctl = `DMEM_LHU; |
wb_we = `EN; |
wb_mux = `WB_MEM; |
//end of `LHU ; |
end |
'd38://LWR rt,offset(base) (offset:signed;base:rs) |
begin |
//replaceID = `LWR ; |
ext_ctl = `IGN; |
rd_sel = `IGN; |
cmp_ctl = `IGN; |
pc_gen_ctl = `IGN; |
fsm_dly = `IGN; |
muxa_ctl = `IGN; |
muxb_ctl = `IGN; |
alu_func = `IGN; |
alu_we = `IGN; |
dmem_ctl = `IGN; |
wb_we = `IGN; |
wb_mux = `IGN; |
//end of `LWR ; |
end |
'd40://SB rt,offset(base) (offset:signed;base:rs) |
begin |
//replaceID = `SB ; |
ext_ctl = `EXT_SIGN; |
rd_sel = `RD_NOP; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_EXT; |
alu_func = `ALU_ADD; |
alu_we = `DIS; |
dmem_ctl = `DMEM_SB; |
wb_we = `DIS; |
wb_mux = `WB_NOP; |
//end of `SB ; |
end |
'd41://SH rt,offset(base) (offset:signed;base:rs) |
begin |
//replaceID = `SH ; |
ext_ctl = `EXT_SIGN; |
rd_sel = `RD_RT; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_EXT; |
alu_func = `ALU_ADD; |
alu_we = `DIS; |
dmem_ctl = `DMEM_SH; |
wb_we = `DIS; |
wb_mux = `WB_NOP; |
//end of `SH ; |
end |
'd42://SWL rt,offset(base) (offset:signed;base:rs) |
begin |
//replaceID = `SWL ; |
ext_ctl = `IGN; |
rd_sel = `IGN; |
cmp_ctl = `IGN; |
pc_gen_ctl = `IGN; |
fsm_dly = `IGN; |
muxa_ctl = `IGN; |
muxb_ctl = `IGN; |
alu_func = `IGN; |
alu_we = `IGN; |
dmem_ctl = `IGN; |
wb_we = `IGN; |
wb_mux = `IGN; |
//end of `SWL ; |
end |
'd43://SW rt,offset(base) (offset:signed;base:rs) |
begin |
//replaceID = `SW ; |
ext_ctl = `EXT_SIGN; |
rd_sel = `RD_NOP; |
cmp_ctl = `CMP_NOP; |
pc_gen_ctl = `PC_NEXT; |
fsm_dly = `FSM_NOP; |
muxa_ctl = `MUXA_RS; |
muxb_ctl = `MUXB_EXT; |
alu_func = `ALU_ADD; |
alu_we = `DIS; |
dmem_ctl = `DMEM_SW; |
wb_we = `DIS; |
wb_mux = `WB_NOP; |
//end of `SW ; |
end |
'd46://SWR rt,offset(base) (offset:signed;base:rs) |
begin |
//replaceID = `SWR ; |
ext_ctl = `IGN; |
rd_sel = `IGN; |
cmp_ctl = `IGN; |
pc_gen_ctl = `IGN; |
fsm_dly = `IGN; |
muxa_ctl = `IGN; |
muxb_ctl = `IGN; |
alu_func = `IGN; |
alu_we = `IGN; |
dmem_ctl = `IGN; |
wb_we = `IGN; |
wb_mux = `IGN; |
//end of `SWR ; |
end |
default: |
begin |
//replaceID = `INVALID ; |
ext_ctl = `IGN; |
rd_sel = `IGN; |
cmp_ctl = `IGN; |
pc_gen_ctl = `IGN; |
fsm_dly = `IGN; |
muxa_ctl = `IGN; |
muxb_ctl = `IGN; |
alu_func = `IGN; |
alu_we = `IGN; |
dmem_ctl = `IGN; |
wb_we = `IGN; |
wb_mux = `IGN; |
//end of `INVALID ; //replaceID = `INVALID ; |
end |
endcase |
end |
endmodule |
|
|
|
module pipelinedregs ( |
clk,id2ra_ctl_clr,id2ra_ctl_cls,ra2ex_ctl_clr, |
alu_func_i,alu_we_i,cmp_ctl_i,dmem_ctl_i,ext_ctl_i, |
muxa_ctl_i,muxb_ctl_i,pc_gen_ctl_i,rd_sel_i,wb_mux_ctl_i, |
wb_we_i,alu_func_o,alu_we_o,cmp_ctl_o,dmem_ctl_o,dmem_ctl_ur_o, |
ext_ctl,muxa_ctl_o,muxb_ctl_o,pc_gen_ctl_o,rd_sel_o,wb_mux_ctl_o,wb_we_o |
) ; |
|
input clk; |
wire clk; |
input id2ra_ctl_clr; |
wire id2ra_ctl_clr; |
input id2ra_ctl_cls; |
wire id2ra_ctl_cls; |
input ra2ex_ctl_clr; |
wire ra2ex_ctl_clr; |
input [4:0] alu_func_i; |
wire [4:0] alu_func_i; |
input [0:0] alu_we_i; |
wire [0:0] alu_we_i; |
input [2:0] cmp_ctl_i; |
wire [2:0] cmp_ctl_i; |
input [3:0] dmem_ctl_i; |
wire [3:0] dmem_ctl_i; |
input [2:0] ext_ctl_i; |
wire [2:0] ext_ctl_i; |
input [1:0] muxa_ctl_i; |
wire [1:0] muxa_ctl_i; |
input [1:0] muxb_ctl_i; |
wire [1:0] muxb_ctl_i; |
input [2:0] pc_gen_ctl_i; |
wire [2:0] pc_gen_ctl_i; |
input [1:0] rd_sel_i; |
wire [1:0] rd_sel_i; |
input [0:0] wb_mux_ctl_i; |
wire [0:0] wb_mux_ctl_i; |
input [0:0] wb_we_i; |
wire [0:0] wb_we_i; |
output [4:0] alu_func_o; |
wire [4:0] alu_func_o; |
output [0:0] alu_we_o; |
wire [0:0] alu_we_o; |
output [2:0] cmp_ctl_o; |
wire [2:0] cmp_ctl_o; |
output [3:0] dmem_ctl_o; |
wire [3:0] dmem_ctl_o; |
output [3:0] dmem_ctl_ur_o; |
wire [3:0] dmem_ctl_ur_o; |
output [2:0] ext_ctl; |
wire [2:0] ext_ctl; |
output [1:0] muxa_ctl_o; |
wire [1:0] muxa_ctl_o; |
output [1:0] muxb_ctl_o; |
wire [1:0] muxb_ctl_o; |
output [2:0] pc_gen_ctl_o; |
wire [2:0] pc_gen_ctl_o; |
output [1:0] rd_sel_o; |
wire [1:0] rd_sel_o; |
output [0:0] wb_mux_ctl_o; |
wire [0:0] wb_mux_ctl_o; |
output [0:0] wb_we_o; |
wire [0:0] wb_we_o; |
|
|
wire NET7643; |
wire [0:0] BUS4987; |
wire [1:0] BUS5008; |
wire [1:0] BUS5483; |
wire [0:0] BUS5639; |
wire [0:0] BUS5651; |
wire [3:0] BUS5666; |
wire [4:0] BUS5674; |
wire [0:0] BUS5682; |
wire [0:0] BUS5690; |
wire [0:0] BUS5790; |
wire [0:0] BUS7299; |
wire [0:0] BUS7822; |
|
|
muxb_ctl_reg_clr_cls U1 |
( |
.clk(clk), |
.clr(id2ra_ctl_clr), |
.cls(id2ra_ctl_cls), |
.muxb_ctl_i(muxb_ctl_i), |
.muxb_ctl_o(BUS5483) |
); |
|
|
|
wb_mux_ctl_reg_clr_cls U10 |
( |
.clk(clk), |
.clr(id2ra_ctl_clr), |
.cls(id2ra_ctl_cls), |
.wb_mux_ctl_i(wb_mux_ctl_i), |
.wb_mux_ctl_o(BUS5651) |
); |
|
|
|
wb_we_reg_clr_cls U11 |
( |
.clk(clk), |
.clr(id2ra_ctl_clr), |
.cls(id2ra_ctl_cls), |
.wb_we_i(wb_we_i), |
.wb_we_o(BUS5639) |
); |
|
|
|
wb_we_reg U12 |
( |
.clk(clk), |
.wb_we_i(NET7643), |
.wb_we_o(wb_we_o) |
); |
|
|
|
wb_mux_ctl_reg_clr U13 |
( |
.clk(clk), |
.clr(ra2ex_ctl_clr), |
.wb_mux_ctl_i(BUS5651), |
.wb_mux_ctl_o(BUS5690) |
); |
|
|
|
muxb_ctl_reg_clr U14 |
( |
.clk(clk), |
.clr(ra2ex_ctl_clr), |
.muxb_ctl_i(BUS5483), |
.muxb_ctl_o(muxb_ctl_o) |
); |
|
|
|
dmem_ctl_reg_clr U15 |
( |
.clk(clk), |
.clr(ra2ex_ctl_clr), |
.dmem_ctl_i(BUS5666), |
.dmem_ctl_o(dmem_ctl_ur_o) |
); |
|
|
|
alu_func_reg_clr U16 |
( |
.alu_func_i(BUS5674), |
.alu_func_o(alu_func_o), |
.clk(clk), |
.clr(ra2ex_ctl_clr) |
); |
|
|
|
muxa_ctl_reg_clr U17 |
( |
.clk(clk), |
.clr(ra2ex_ctl_clr), |
.muxa_ctl_i(BUS5008), |
.muxa_ctl_o(muxa_ctl_o) |
); |
|
|
|
wb_mux_ctl_reg U18 |
( |
.clk(clk), |
.wb_mux_ctl_i(BUS5790), |
.wb_mux_ctl_o(wb_mux_ctl_o) |
); |
|
|
|
wb_we_reg_clr U19 |
( |
.clk(clk), |
.clr(ra2ex_ctl_clr), |
.wb_we_i(BUS5639), |
.wb_we_o(BUS5682) |
); |
|
|
|
cmp_ctl_reg_clr_cls U2 |
( |
.clk(clk), |
.clr(id2ra_ctl_clr), |
.cls(id2ra_ctl_cls), |
.cmp_ctl_i(cmp_ctl_i), |
.cmp_ctl_o(cmp_ctl_o) |
); |
|
|
|
wb_we_reg U20 |
( |
.clk(clk), |
.wb_we_i(BUS5682), |
.wb_we_o(BUS7822) |
); |
|
|
|
wb_mux_ctl_reg U21 |
( |
.clk(clk), |
.wb_mux_ctl_i(BUS5690), |
.wb_mux_ctl_o(BUS5790) |
); |
|
|
|
wb_we_reg U22 |
( |
.clk(clk), |
.wb_we_i(BUS7299), |
.wb_we_o(alu_we_o) |
); |
|
|
|
assign NET7643 = alu_we_o[0] | BUS7822[0]; |
|
|
alu_we_reg_clr U24 |
( |
.alu_we_i(BUS4987), |
.alu_we_o(BUS7299), |
.clk(clk), |
.clr(ra2ex_ctl_clr) |
); |
|
|
|
alu_func_reg_clr_cls U26 |
( |
.alu_func_i(alu_func_i), |
.alu_func_o(BUS5674), |
.clk(clk), |
.clr(id2ra_ctl_clr), |
.cls(id2ra_ctl_cls) |
); |
|
|
|
dmem_ctl_reg_clr_cls U3 |
( |
.clk(clk), |
.clr(id2ra_ctl_clr), |
.cls(id2ra_ctl_cls), |
.dmem_ctl_i(dmem_ctl_i), |
.dmem_ctl_o(BUS5666) |
); |
|
|
|
ext_ctl_reg_clr_cls U4 |
( |
.clk(clk), |
.clr(id2ra_ctl_clr), |
.cls(id2ra_ctl_cls), |
.ext_ctl_i(ext_ctl_i), |
.ext_ctl_o(ext_ctl) |
); |
|
|
|
rd_sel_reg_clr_cls U5 |
( |
.clk(clk), |
.clr(id2ra_ctl_clr), |
.cls(id2ra_ctl_cls), |
.rd_sel_i(rd_sel_i), |
.rd_sel_o(rd_sel_o) |
); |
|
|
|
alu_we_reg_clr_cls U6 |
( |
.alu_we_i(alu_we_i), |
.alu_we_o(BUS4987), |
.clk(clk), |
.clr(id2ra_ctl_clr), |
.cls(id2ra_ctl_cls) |
); |
|
|
|
muxa_ctl_reg_clr_cls U7 |
( |
.clk(clk), |
.clr(id2ra_ctl_clr), |
.cls(id2ra_ctl_cls), |
.muxa_ctl_i(muxa_ctl_i), |
.muxa_ctl_o(BUS5008) |
); |
|
|
|
pc_gen_ctl_reg_clr_cls U8 |
( |
.clk(clk), |
.clr(id2ra_ctl_clr), |
.cls(id2ra_ctl_cls), |
.pc_gen_ctl_i(pc_gen_ctl_i), |
.pc_gen_ctl_o(pc_gen_ctl_o) |
); |
|
|
|
dmem_ctl_reg U9 |
( |
.clk(clk), |
.dmem_ctl_i(dmem_ctl_ur_o), |
.dmem_ctl_o(dmem_ctl_o) |
); |
|
|
|
endmodule |
|
module decode_pipe |
( |
clk,id2ra_ctl_clr,id2ra_ctl_cls, |
ra2ex_ctl_clr,ins_i,alu_func_o,alu_we_o, |
cmp_ctl_o,dmem_ctl_o,dmem_ctl_ur_o,ext_ctl_o, |
fsm_dly,muxa_ctl_o,muxb_ctl_o,pc_gen_ctl_o,rd_sel_o, |
wb_mux_ctl_o,wb_we_o |
) ; |
|
input clk; |
wire clk; |
input id2ra_ctl_clr; |
wire id2ra_ctl_clr; |
input id2ra_ctl_cls; |
wire id2ra_ctl_cls; |
input ra2ex_ctl_clr; |
wire ra2ex_ctl_clr; |
input [31:0] ins_i; |
wire [31:0] ins_i; |
output [4:0] alu_func_o; |
wire [4:0] alu_func_o; |
output [0:0] alu_we_o; |
wire [0:0] alu_we_o; |
output [2:0] cmp_ctl_o; |
wire [2:0] cmp_ctl_o; |
output [3:0] dmem_ctl_o; |
wire [3:0] dmem_ctl_o; |
output [3:0] dmem_ctl_ur_o; |
wire [3:0] dmem_ctl_ur_o; |
output [2:0] ext_ctl_o; |
wire [2:0] ext_ctl_o; |
output [2:0] fsm_dly; |
wire [2:0] fsm_dly; |
output [1:0] muxa_ctl_o; |
wire [1:0] muxa_ctl_o; |
output [1:0] muxb_ctl_o; |
wire [1:0] muxb_ctl_o; |
output [2:0] pc_gen_ctl_o; |
wire [2:0] pc_gen_ctl_o; |
output [1:0] rd_sel_o; |
wire [1:0] rd_sel_o; |
output [0:0] wb_mux_ctl_o; |
wire [0:0] wb_mux_ctl_o; |
output [0:0] wb_we_o; |
wire [0:0] wb_we_o; |
|
|
wire [4:0] BUS2040; |
wire [0:0] BUS2048; |
wire [2:0] BUS2056; |
wire [3:0] BUS2064; |
wire [2:0] BUS2072; |
wire [1:0] BUS2086; |
wire [1:0] BUS2094; |
wire [2:0] BUS2102; |
wire [1:0] BUS2110; |
wire [0:0] BUS2118; |
wire [0:0] BUS2126; |
|
|
decoder idecoder |
( |
.alu_func(BUS2040), |
.alu_we(BUS2048), |
.cmp_ctl(BUS2056), |
.dmem_ctl(BUS2064), |
.ext_ctl(BUS2072), |
.fsm_dly(fsm_dly), |
.ins_i(ins_i), |
.muxa_ctl(BUS2086), |
.muxb_ctl(BUS2094), |
.pc_gen_ctl(BUS2102), |
.rd_sel(BUS2110), |
.wb_mux(BUS2118), |
.wb_we(BUS2126) |
); |
|
|
|
pipelinedregs pipereg |
( |
.alu_func_i(BUS2040), |
.alu_func_o(alu_func_o), |
.alu_we_i(BUS2048), |
.alu_we_o(alu_we_o), |
.clk(clk), |
.cmp_ctl_i(BUS2056), |
.cmp_ctl_o(cmp_ctl_o), |
.dmem_ctl_i(BUS2064), |
.dmem_ctl_o(dmem_ctl_o), |
.dmem_ctl_ur_o(dmem_ctl_ur_o), |
.ext_ctl(ext_ctl_o), |
.ext_ctl_i(BUS2072), |
.id2ra_ctl_clr(id2ra_ctl_clr), |
.id2ra_ctl_cls(id2ra_ctl_cls), |
.muxa_ctl_i(BUS2086), |
.muxa_ctl_o(muxa_ctl_o), |
.muxb_ctl_i(BUS2094), |
.muxb_ctl_o(muxb_ctl_o), |
.pc_gen_ctl_i(BUS2102), |
.pc_gen_ctl_o(pc_gen_ctl_o), |
.ra2ex_ctl_clr(ra2ex_ctl_clr), |
.rd_sel_i(BUS2110), |
.rd_sel_o(rd_sel_o), |
.wb_mux_ctl_i(BUS2118), |
.wb_mux_ctl_o(wb_mux_ctl_o), |
.wb_we_i(BUS2126), |
.wb_we_o(wb_we_o) |
); |
|
|
|
endmodule |
|
|
|
|
|
/trunk/rtl/verilog/mips_uart.v
0,0 → 1,336
/****************************************************************** |
* * |
* Author: Liwei * |
* * |
* This file is part of the "mips789" project. * |
* Downloaded from: * |
* http://www.opencores.org/pdownloads.cgi/list/mips789 * |
* * |
* If you encountered any problem, please contact me via * |
* Email:mcupro@opencores.org or mcupro@163.com * |
* * |
******************************************************************/ |
|
`include "mips789_defs.v" |
|
module rxd_d(input clr,input clk,input d,output reg q ); |
|
always @(posedge clk) |
|
if (clr) q<=0; |
else q<=d|q; |
|
endmodule |
|
module uart0 ( |
clk,rst,rxd_ft,ser_rxd,txd_ld, |
din,rxd_rdy,ser_txd,txd_busy,dout) ; |
input clk; |
wire clk; |
input rst; |
wire rst; |
input rxd_ft; |
wire rxd_ft; |
input ser_rxd; |
wire ser_rxd; |
input txd_ld; |
wire txd_ld; |
input [7:0] din; |
wire [7:0] din; |
output rxd_rdy; |
wire rxd_rdy; |
output ser_txd; |
wire ser_txd; |
output txd_busy; |
wire txd_busy; |
output [7:0] dout; |
wire [7:0] dout; |
|
wire clk_uart=clk; |
wire w_rxd_rdy; |
integer uart_send; |
initial begin |
|
|
|
uart_send = $fopen("uart_send.txt"); |
|
|
end |
|
always @ (txd_ld) |
begin |
if (txd_ld) $fwrite( uart_send,"%c",din[7:0]); |
end |
|
uart_read uart_rd_tak( |
.sync_reset(rst), |
.clk(clk), |
.rxd(ser_rxd), |
.buffer_reg(dout), |
.int_req(w_rxd_rdy) |
); |
|
rxd_d rxd_rdy_hold_lw |
( |
.clk(clk_uart), |
.clr(rxd_ft), |
.d(w_rxd_rdy), |
.q(rxd_rdy) |
); |
|
uart_write uart_txd |
( |
.sync_reset(rst), |
.clk(clk), |
.txd(ser_txd), |
.data_in(din) , |
.write_request(txd_ld), |
//.write_done(), |
.write_busy(txd_busy) |
); |
|
endmodule |
|
//These modules below are modified slight by Liwei based on YACC,an CPU core in opencores. |
//Thank you TAK |
|
module uart_write( sync_reset, clk, txd, data_in , write_request,write_done,write_busy); |
input sync_reset,clk; |
input [7:0] data_in; |
input write_request; |
output txd,write_done; |
output write_busy; |
|
|
|
wire queue_full; |
wire queing, read_request; |
wire [7:0] queue_data; |
reg read_request_ff; |
|
|
//________|--|___write_request (upper module : its period should be 1clock time.) |
//__________________________|-|______write_done (Responds by this module posedge interrupt) |
//With 512Bytes FIFO. |
//No error handling is supported. |
|
reg [15:0] clk_ctr;//liwei |
reg [2:0] bit_ctr; |
reg [2:0] ua_state; |
reg [7:0] tx_sr; |
reg txd; |
|
wire clk_ctr_equ15, clk_ctr_equ31, bit_ctr_equ7, |
clk_ctr_enable_state, bit_ctr_enable_state ; |
wire tx_state; |
wire empty; |
assign write_busy=queue_full;//Apr.2.2005 |
|
always @ (posedge clk) begin |
if (~sync_reset) read_request_ff<=1'b0; |
else read_request_ff<=read_request; |
end |
|
assign queing= !empty; |
assign read_request = queing && ua_state==3'b000;//Jul.14.2004 |
|
assign write_done=ua_state==3'b101; |
|
`ifdef ALTERA |
fifo512_cyclone alt_fifo( |
.data(data_in), |
.wrreq(write_request), |
.rdreq(read_request), |
.clock(clk), |
.q(queue_data), |
.full(queue_full), |
.empty(empty)); |
`else//debug model in simulations |
|
sim_fifo512_cyclone sim_fifo( |
.data(data_in), |
.wrreq(write_request), |
.rdreq(read_request), |
.clock(clk), |
.q(queue_data), |
.full(queue_full), |
.empty(empty), |
.rst(sync_reset)); |
`endif |
|
|
|
// 7bit counter |
// I set the regerster lenth as 16 .Sufficent but not waste.Liwei |
always @(posedge clk ) begin |
if (~sync_reset) |
clk_ctr <= 0; |
else if (clk_ctr_enable_state && clk_ctr_equ31) clk_ctr<=0; |
else if (clk_ctr_enable_state) clk_ctr <= clk_ctr + 1; |
else clk_ctr <= 0; |
end |
|
|
assign clk_ctr_equ15 = clk_ctr==`COUNTER_VALUE1; |
assign clk_ctr_equ31 = clk_ctr==`COUNTER_VALUE2; |
|
// 3bit counter |
always @(posedge clk) begin |
if (~sync_reset) |
bit_ctr <= 0; |
else if (bit_ctr_enable_state) begin |
if (clk_ctr_equ15) |
bit_ctr <= bit_ctr + 1; |
end |
else |
bit_ctr <= 0; |
end |
|
assign bit_ctr_equ7 = (bit_ctr==7); |
|
assign clk_ctr_enable_state = bit_ctr_enable_state ||ua_state==3'b110 || ua_state==3'b001 || ua_state==3'b100||ua_state==3'b101; |
assign bit_ctr_enable_state = ua_state==3'b010 || ua_state==3'b011; |
|
|
always @(posedge clk ) begin |
if (~sync_reset) ua_state <= 3'b000; |
else begin |
case (ua_state) |
3'b000: if (queing) ua_state <= 3'b001; //wait write_request |
3'b001: if ( clk_ctr_equ15) ua_state <= 3'b010; // write start bit |
3'b010: if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'b011; // start bit, bit0-7 data send |
3'b011: if (clk_ctr_equ15) ua_state <= 3'b100; // bit7 data send |
3'b100: if (clk_ctr_equ15) ua_state <= 3'b101; // stop bit // stop bit send |
3'b101: if (clk_ctr_equ15) ua_state <= 3'b110; //LIWEI // stop bit send |
3'b110: if (clk_ctr_equ15) ua_state <= 3'b111; //LIWEI |
3'b111: ua_state <= 3'h0; // TAK // byte read cycle end |
default: ua_state <= 3'h0; |
endcase |
end |
end |
|
|
|
|
// tx shift reg. |
always @(posedge clk ) begin |
if (~sync_reset) tx_sr<=0; |
else if (read_request_ff) tx_sr <= queue_data[7:0]; //data_in[7:0]; // load |
else if (tx_state ) tx_sr <= {1'b0, tx_sr[7:1]}; |
end |
|
assign tx_state=( ua_state==3'h2 || ua_state==3'h3) && clk_ctr_equ15; |
|
|
// tx |
always @(posedge clk ) begin |
if (~sync_reset) txd <=1'b1; |
else if (~sync_reset) txd<=1'b1; |
else if (ua_state==3'h0) txd<=1'b1; |
else if (ua_state==3'h1 && clk_ctr_equ15) txd<=1'b0; // start bit |
else if (ua_state==3'h2 && clk_ctr_equ15) txd<=tx_sr[0]; |
else if (ua_state==3'h3 && clk_ctr_equ15) txd<=1'b1; // stop bit |
end |
endmodule |
|
|
module uart_read( sync_reset, clk, rxd,buffer_reg, int_req); |
input sync_reset; |
input clk, rxd; |
output [7:0] buffer_reg; |
output int_req; |
|
|
//________|-|______int_req (This module,, posedge interrupt) |
// |
//Spec. Upper module must service within 115.2Kbpsx8bit time. Maybe enough time... |
// |
//No error handling (overrun ) is supported. |
|
reg rxq1; |
reg [15:0] clk_ctr; |
reg [2:0] bit_ctr; |
reg [2:0] ua_state; |
reg [7:0] rx_sr; //.,tx_sr; |
reg int_req; |
reg [7:0] buffer_reg; |
|
wire clk_ctr_equ15, clk_ctr_equ31, bit_ctr_equ7, |
clk_ctr_enable_state, bit_ctr_enable_state ; |
wire clk_ctr_equ0; |
|
//sync_reset |
|
//synchronization |
always @(posedge clk ) begin |
rxq1 <=rxd ; |
end |
|
// 7bit counter |
always @(posedge clk ) begin |
if (~sync_reset) |
clk_ctr <= 0; |
else if (clk_ctr_enable_state && clk_ctr_equ31) clk_ctr<=0; |
else if (clk_ctr_enable_state) clk_ctr <= clk_ctr + 1; |
else clk_ctr <= 0; |
end |
assign clk_ctr_equ15 = (clk_ctr==`COUNTER_VALUE1) ;// |
assign clk_ctr_equ31 = (clk_ctr==`COUNTER_VALUE2) ;// |
assign clk_ctr_equ0= (clk_ctr==`COUNTER_VALUE3); // |
|
|
// 3bit counter |
always @(posedge clk) begin |
if (~sync_reset) |
bit_ctr <= 0; |
else if (bit_ctr_enable_state) begin |
if (clk_ctr_equ15) |
bit_ctr <= bit_ctr + 1; |
end |
else |
bit_ctr <= 0; |
end |
|
assign bit_ctr_equ7 = (bit_ctr==7); |
|
|
assign clk_ctr_enable_state = ua_state !=3'b000 && ua_state<=3'b011; |
assign bit_ctr_enable_state = ua_state==3'h2; |
|
always @(posedge clk ) begin |
if (~sync_reset) ua_state <= 3'h0; |
else begin |
case (ua_state) |
3'h0: if (rxq1==0) ua_state <= 3'h1; // if rxd==0 then goto next state and enable clock // start bit search |
3'h1: if (clk_ctr_equ15) ua_state <= 3'h2; // start bit receive |
3'h2: if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'h3; |
3'h3: if (clk_ctr_equ15) ua_state <=3'h4; // stop bit receive |
3'h4: ua_state <= 3'b000; |
default: ua_state <= 3'b000; |
endcase |
end |
end |
|
|
//reg_we |
always @(posedge clk ) begin |
if (~sync_reset) buffer_reg<=8'h00; |
else if (ua_state==3'h3 && clk_ctr_equ0) buffer_reg<=rx_sr; |
end |
|
//int_req |
always @(posedge clk ) begin |
if (~sync_reset) int_req<=1'b0; |
else if (ua_state==3'h4 ) int_req<=1'b1; |
else int_req<=1'b0; |
end |
|
|
// rx shift reg. |
always @(posedge clk ) begin |
if (~sync_reset) rx_sr <= 0; |
else if (clk_ctr_equ15) rx_sr <= {rxq1, rx_sr[7:1]}; |
end |
|
endmodule |
/trunk/rtl/verilog/mips_dvc.v
0,0 → 1,168
|
/****************************************************************** |
* * |
* Author: Liwei * |
* * |
* This file is part of the "mips789" project. * |
* Downloaded from: * |
* http://www.opencores.org/pdownloads.cgi/list/mips789 * |
* * |
* If you encountered any problem, please contact me via * |
* Email:mcupro@opencores.org or mcupro@163.com * |
* * |
******************************************************************/ |
`include "mips789_defs.v" |
|
/* |
`define JTAG_BASE_ADDR 'h8100_0000 |
`define JTAG_RD_FIFO 'h8100_0100 |
`define JTAG_RD_FIFO_FLAG 'h8100_0200 |
`define USB_DATA_ADDR 'h8100_0300 |
`define USB_CTL_ADDR 'h8100_0400 |
*/ |
module mips_dvc ( |
input [31:0]din, |
input clk, |
input rst, |
input [31:0]addr , |
input [3:0]mem_ctl, |
|
output reg [31:0]dout , |
input tdi, |
output tdo, |
output tms, |
output tck, |
//68013 interface |
input int2,int1, |
inout [15:0] usb_data , |
output reg addr0, addr1, cs,wr,rd,oe,pkt_end ,led ,oe573 |
|
); |
|
reg int1_reg; |
reg int2_reg; |
always @ (posedge clk)int1_reg <= int1; |
always @ (posedge clk)int2_reg <= int2; |
|
wire sv_byte = (mem_ctl==`DMEM_SB); |
wire ld_byte =((mem_ctl==`DMEM_LBS)||(mem_ctl==`DMEM_LBU)); |
wire sv_wd = (mem_ctl==`DMEM_SW); |
wire ld_wd = (mem_ctl==`DMEM_LW); |
|
wire sv_hw = (mem_ctl==`DMEM_SH); |
wire ld_hw = (mem_ctl==`DMEM_LHU ); |
|
wire load = ld_byte|ld_wd|ld_hw; |
|
wire [34:0] fifo_din = {addr[6:4],din[31:0]}; |
wire sel_jtagc = ((addr[31:24]=='h81)&&(addr[23:7]==0));//((addr[31:0] & 'hff00_0000)==`JTAG_BASE_ADDR) ; |
wire wr_jtagc = sv_wd & sel_jtagc ; |
wire rd_fifo_data = (addr== `JTAG_RD_FIFO ) & ld_wd; |
wire rd_fifo_flag = (addr== `JTAG_RD_FIFO_FLAG ) & ld_wd; |
wire [32:0]fifo_dout; |
wire fifo_full; |
wire fifo_empty ; |
wire jtagc_idle; |
reg jtagc_idle_r; |
always @ (posedge clk) jtagc_idle_r<=jtagc_idle; |
JTAGC jtag_controller( |
.clk(clk) , |
.rst(rst) , |
.tdi(tdi) , |
.tdo(tdo) , |
.tms(tms) , |
.tck(tck) , |
.fifo_din(fifo_din), |
.fifo_wr(wr_jtagc), |
.fifo_full(fifo_full), |
.fifo_dout(fifo_dout), |
.fifo_rd(rd_fifo_data), |
.fifo_empty(fifo_empty) , |
.SET_TMS(SET_TMS), |
.jtagc_idle(jtagc_idle) |
); |
reg rd_fifo_data_r ; |
reg dr0_ir1; |
reg fifo_full_r,fifo_empty_r; |
always @ (posedge clk)fifo_full_r <=fifo_full ; |
always @ (posedge clk)fifo_empty_r<=fifo_empty ; |
always @ (posedge clk)rd_fifo_data_r<=rd_fifo_data; |
always @ (posedge clk)if (rd_fifo_data_r)dr0_ir1 <= fifo_dout[32]; |
reg [31:0] jtag_flags;// |
always @ (posedge clk) |
begin |
jtag_flags[0] <= dr0_ir1 ; jtag_flags[1] <= fifo_empty_r ; jtag_flags[2] <= fifo_full_r ; |
jtag_flags[3] <= int2_reg; jtag_flags[4] <= int1_reg; jtag_flags[5] <= jtagc_idle_r ; |
jtag_flags[31:6]<=0; |
end |
//= {26'b0,jtagc_idle_r,int1_reg ,int2_reg, fifo_full_r,fifo_empty_r,dr0_ir1}; |
// 5 4 3 2 1 0 |
/////////////////////////////////////////////////////// |
|
reg usb_wr ; |
reg SET_TMS ; |
|
always @ (posedge clk) |
if ((addr==`USB_CTL_ADDR )& sv_wd ) begin |
usb_wr <= din[0]; |
addr0<= din[1]; |
addr1<= din[2]; |
cs<= din[3]; |
wr<= din[4]; |
rd<= din[5]; |
oe<= din[6]; |
pkt_end<= din[7]; |
SET_TMS <=din[10]; |
led<=din[11]; |
oe573<=din[12]; |
end |
|
|
|
reg [15:0] data_fpga2usb; |
wire [15:0] data_usb2fpga ; |
always @ (posedge clk) |
if ((addr ==`USB_DATA_ADDR)&&sv_hw ) |
begin |
data_fpga2usb<=din[15:0]; |
end |
|
iopin usb16data_pin( |
.en(usb_wr), |
.q(data_usb2fpga), |
.d(data_fpga2usb), |
.pin(usb_data) |
); |
|
reg [15:0] data_usb2fpga_r ; |
always @ (posedge clk)data_usb2fpga_r<=data_usb2fpga; |
reg [31:0]dout_w; |
always@(posedge clk )if (load) |
case(addr) |
`USB_DATA_ADDR:begin dout_w[31:16]<=0;dout_w[15:0]<= data_usb2fpga_r;end |
`JTAG_RD_FIFO_FLAG :dout_w<=jtag_flags; |
`JTAG_RD_FIFO :begin dout_w[31:16]<=0;dout_w[15:0]<= data_usb2fpga_r; end |
`USB_CTL_ADDR :begin |
dout_w[31:13]<=0; // |
dout_w[0]<=usb_wr;// <= din[0]; |
dout_w[1]<=addr0;//<= din[1]; |
dout_w[2]<=addr1;//<= din[2]; |
dout_w[3]<=cs;//<= din[3]; |
dout_w[4]<=wr;//<= din[4]; |
dout_w[5]<=rd;//<= din[5]; |
dout_w[6]<=oe;//<= din[6]; |
dout_w[7]<=pkt_end;//<= din[7]; |
dout_w[10]<=SET_TMS ; |
dout_w[11]<=led; |
dout_w[12]<=oe573; |
end |
default dout_w<=0; |
endcase |
else |
dout_w <=0; |
|
always @ (*) |
if (rd_fifo_data_r) |
dout=fifo_dout[31:0] ; |
else dout=dout_w; |
endmodule |
/trunk/rtl/verilog/forward.v
0,0 → 1,160
/****************************************************************** |
* * |
* Author: Liwei * |
* * |
* This file is part of the "mips789" project. * |
* Downloaded from: * |
* http://www.opencores.org/pdownloads.cgi/list/mips789 * |
* * |
* If you encountered any problem, please contact me via * |
* Email:mcupro@opencores.org or mcupro@163.com * |
* * |
******************************************************************/ |
|
`include "mips789_defs.v" |
|
|
module fw_latch5(input clk,input[4:0]d,output reg [4:0]q); |
always @ (posedge clk) q<=d; |
endmodule |
|
module fw_latch1(input clk,input d,output reg q); |
always @ (posedge clk) q<=d; |
endmodule |
|
module forward_node ( |
input [4:0]rn, |
input [4:0]alu_wr_rn, |
input alu_we, |
input [4:0]mem_wr_rn, |
input mem_we, |
output wire[2:0]mux_fw |
); |
assign mux_fw = ((alu_we)&&(alu_wr_rn==rn)&&(alu_wr_rn!=0))?`FW_ALU: |
((mem_we)&&(mem_wr_rn==rn)&&(mem_wr_rn!=0))?`FW_MEM: |
`FW_NOP; |
endmodule |
|
module fwd_mux( |
input [31:0]din, |
output reg [31:0]dout, |
input [31:0]fw_alu , |
input [2:0]fw_ctl, |
input [31:0]fw_dmem |
); |
always@(*) |
case (fw_ctl) |
`FW_ALU :dout=fw_alu; |
`FW_MEM :dout=fw_dmem; |
default |
/*`FW_NOP :dout=din;*/ |
dout=din; |
endcase |
endmodule |
|
module forward ( |
alu_we,clk,mem_We,fw_alu_rn, |
fw_mem_rn,rns_i,rnt_i,alu_rs_fw, |
alu_rt_fw,cmp_rs_fw,cmp_rt_fw,dmem_fw |
) ; |
|
input alu_we; |
wire alu_we; |
input clk; |
wire clk; |
input mem_We; |
wire mem_We; |
input [4:0] fw_alu_rn; |
wire [4:0] fw_alu_rn; |
input [4:0] fw_mem_rn; |
wire [4:0] fw_mem_rn; |
input [4:0] rns_i; |
wire [4:0] rns_i; |
input [4:0] rnt_i; |
wire [4:0] rnt_i; |
output [2:0] alu_rs_fw; |
wire [2:0] alu_rs_fw; |
output [2:0] alu_rt_fw; |
wire [2:0] alu_rt_fw; |
output [2:0] cmp_rs_fw; |
wire [2:0] cmp_rs_fw; |
output [2:0] cmp_rt_fw; |
wire [2:0] cmp_rt_fw; |
output [2:0] dmem_fw; |
wire [2:0] dmem_fw; |
|
wire [2:0] BUS1345; |
wire [4:0] BUS82; |
wire [4:0] BUS937; |
|
forward_node fw_alu_rs |
( |
.alu_we(alu_we), |
.alu_wr_rn(fw_alu_rn), |
.mem_we(mem_We), |
.mem_wr_rn(fw_mem_rn), |
.mux_fw(alu_rs_fw), |
.rn(BUS82) |
); |
|
|
|
forward_node fw_alu_rt |
( |
.alu_we(alu_we), |
.alu_wr_rn(fw_alu_rn), |
.mem_we(mem_We), |
.mem_wr_rn(fw_mem_rn), |
.mux_fw(BUS1345), |
.rn(BUS937) |
); |
|
|
|
forward_node fw_cmp_rs |
( |
.alu_we(alu_we), |
.alu_wr_rn(fw_alu_rn), |
.mem_we(mem_We), |
.mem_wr_rn(fw_mem_rn), |
.mux_fw(cmp_rs_fw), |
.rn(rns_i) |
); |
|
|
|
forward_node fw_cmp_rt |
( |
.alu_we(alu_we), |
.alu_wr_rn(fw_alu_rn), |
.mem_we(mem_We), |
.mem_wr_rn(fw_mem_rn), |
.mux_fw(cmp_rt_fw), |
.rn(rnt_i) |
); |
|
|
|
fw_latch5 fw_reg_rns |
( |
.clk(clk), |
.d(rns_i), |
.q(BUS82) |
); |
|
|
|
fw_latch5 fw_reg_rnt |
( |
.clk(clk), |
.d(rnt_i), |
.q(BUS937) |
); |
|
|
assign alu_rt_fw[2:0] = BUS1345[2:0]; |
assign dmem_fw[2:0] = BUS1345[2:0]; |
|
endmodule |
|
|
/trunk/rtl/verilog/mips_sys.v
0,0 → 1,91
/****************************************************************** |
* * |
* Author: Liwei * |
* * |
* This file is part of the "mips789" project. * |
* Downloaded from: * |
* http://www.opencores.org/pdownloads.cgi/list/mips789 * |
* * |
* If you encountered any problem, please contact me via * |
* Email:mcupro@opencores.org or mcupro@163.com * |
* * |
******************************************************************/ |
|
|
`include "mips789_defs.v" |
|
|
module mips_sys ( |
input clk, |
input rst, |
input [31:0] zz_din, |
input [31:0] zz_ins_i, |
output [31:0] zz_addr_o, |
output [31:0] zz_dout, |
output [31:0] zz_pc_o, |
output [3:0] zz_wr_en_o, |
input tdi, |
output tdo, |
output tms, |
output tck, |
// |
input int2,int1, |
inout [15:0] usb_data , |
output addr0, addr1, cs,wr,rd,oe,pkt_end ,led ,oe573 |
) ; |
|
|
wire [31:0] cop_addr; |
wire [3:0] cop_mem_ctl; |
wire [31:0] data2cop; |
wire [31:0]cop_data; |
wire clk_sys=clk; |
wire [31:0]irq_addr; |
wire w_irq; |
|
mips_core i_mips_core |
( |
.clk(clk_sys), |
.cop_addr_o(cop_addr), |
.cop_data_o(data2cop), |
.cop_dout(cop_data), |
.cop_mem_ctl_o(cop_mem_ctl), |
.irq_addr(irq_addr), |
.irq_i(1'b0), |
.rst(rst), |
.zz_addr_o(zz_addr_o), |
.zz_din(zz_din), |
.zz_dout(zz_dout), |
.zz_ins_i(zz_ins_i), |
.zz_pc_o(zz_pc_o), |
.zz_wr_en_o(zz_wr_en_o) |
); |
|
mips_dvc imips_dvc( |
.din(data2cop), |
.clk(clk_sys), |
.rst(rst), |
.addr(cop_addr) , |
.mem_ctl(cop_mem_ctl), |
.dout(cop_data), |
.tdi(tdi), |
.tdo(tdo), |
.tms(tms), |
.tck(tck), |
.int2(int2), |
.int1(int1), |
.usb_data(usb_data) , |
.addr0(addr0), |
.addr1(addr1), |
.cs(cs), |
.wr(wr), |
.rd(rd), |
.oe(oe), |
.pkt_end(pkt_end) , |
.led(led) , |
.oe573(oe573) |
); |
|
endmodule |
|
|
/trunk/rtl/verilog/EXEC_stage.v
0,0 → 1,747
/****************************************************************** |
* * |
* Author: Liwei * |
* * |
* This file is part of the "mips789" project. * |
* Downloaded from: * |
* http://www.opencores.org/pdownloads.cgi/list/mips789 * |
* * |
* If you encountered any problem, please contact me via * |
* Email:mcupro@opencores.org or mcupro@163.com * |
* * |
******************************************************************/ |
|
`include "mips789_defs.v" |
|
module exec_stage |
( |
clk,rst,spc_cls_i,alu_func, |
dmem_fw_ctl,ext_i,fw_alu,fw_dmem, |
muxa_ctl_i,muxa_fw_ctl,muxb_ctl_i, |
muxb_fw_ctl,pc_i,rs_i,rt_i,alu_ur_o, |
dmem_data_ur_o,zz_spc_o |
); |
|
input clk; |
wire clk; |
input rst; |
wire rst; |
input spc_cls_i; |
wire spc_cls_i; |
input [4:0] alu_func; |
wire [4:0] alu_func; |
input [2:0] dmem_fw_ctl; |
wire [2:0] dmem_fw_ctl; |
input [31:0] ext_i; |
wire [31:0] ext_i; |
input [31:0] fw_alu; |
wire [31:0] fw_alu; |
input [31:0] fw_dmem; |
wire [31:0] fw_dmem; |
input [1:0] muxa_ctl_i; |
wire [1:0] muxa_ctl_i; |
input [2:0] muxa_fw_ctl; |
wire [2:0] muxa_fw_ctl; |
input [1:0] muxb_ctl_i; |
wire [1:0] muxb_ctl_i; |
input [2:0] muxb_fw_ctl; |
wire [2:0] muxb_fw_ctl; |
input [31:0] pc_i; |
wire [31:0] pc_i; |
input [31:0] rs_i; |
wire [31:0] rs_i; |
input [31:0] rt_i; |
wire [31:0] rt_i; |
output [31:0] alu_ur_o; |
wire [31:0] alu_ur_o; |
output [31:0] dmem_data_ur_o; |
wire [31:0] dmem_data_ur_o; |
output [31:0] zz_spc_o; |
wire [31:0] zz_spc_o; |
|
wire [31:0] BUS2332; |
wire [31:0] BUS2446; |
wire [31:0] BUS468; |
wire [31:0] BUS476; |
|
|
mips_alu MIPS_alu |
( |
.a(BUS476), |
.b(BUS468), |
.c(alu_ur_o), |
.clk(clk), |
.ctl(alu_func), |
.rst(rst) |
); |
|
add32 add4 |
( |
.d_i(pc_i), |
.d_o(BUS2446) |
); |
|
|
fwd_mux dmem_fw_mux |
( |
.dout(dmem_data_ur_o), |
.fw_alu(fw_alu), |
.fw_ctl(dmem_fw_ctl), |
.fw_dmem(fw_dmem), |
.din(rt_i) |
); |
|
|
|
alu_muxa i_alu_muxa |
( |
.a_o(BUS476), |
.ctl(muxa_ctl_i), |
.ext(ext_i), |
.fw_alu(fw_alu), |
.fw_ctl(muxa_fw_ctl), |
.fw_mem(fw_dmem), |
.pc(BUS2332), |
.rs(rs_i), |
.spc(zz_spc_o) |
); |
|
|
|
alu_muxb i_alu_muxb |
( |
.b_o(BUS468), |
.ctl(muxb_ctl_i), |
.ext(ext_i), |
.fw_alu(fw_alu), |
.fw_ctl(muxb_fw_ctl), |
.fw_mem(fw_dmem), |
.rt(rt_i) |
); |
|
|
|
r32_reg pc_nxt |
( |
.clk(clk), |
.r32_i(BUS2446), |
.r32_o(BUS2332) |
); |
|
|
|
r32_reg_cls spc |
( |
.clk(clk), |
.cls(spc_cls_i), |
.r32_i(pc_i), |
.r32_o(zz_spc_o) |
); |
|
endmodule |
|
module mips_alu(clk,rst,a,b,c,ctl); |
input clk,rst ; |
input [31:0] a,b ; |
output [31:0] c ; |
input [4:0]ctl ; |
|
wire [31:0] mul_div_c; |
wire [31:0] alu_c; |
wire [31:0] shift_c; |
|
// assign c = mul_div_c | alu_c | shift_c ; |
assign c = 0 | alu_c | shift_c ; |
|
/* |
muldiv_ff muldiv_ff( |
.clk_i(clk), |
.rst_i(rst),//sys signal |
.op_type(ctl), |
.op1(a), |
.op2(b), |
// .busy_o(busy), |
.res(mul_div_c) |
); |
*/ |
/* |
muldiv mips_muldiv( |
.ready(busy), |
.rst(rst), |
.op1(a), |
.op2(b), |
.clk(clk), |
.dout(mul_div_c), |
.func(ctl) |
); |
*/ |
shifter_tak mips_shifter( |
.a(b), |
.shift_out(shift_c), |
.shift_func(ctl), |
.shift_amount(a) |
); |
|
|
alu mips_alu( |
.a(a), |
.b(b), |
.alu_out(alu_c), |
.alu_func(ctl) |
); |
|
endmodule |
|
module alu_muxa( |
input [31:0]spc, |
input [31:0]pc, |
input [31:0]fw_mem, |
input [31:0]rs, |
input [31:0]fw_alu, |
input [31:0]ext, |
input [1:0] ctl, |
input [2:0] fw_ctl, |
output reg [31:0]a_o |
); |
|
always @(*) |
begin |
case (ctl) |
`MUXA_RS: a_o = (fw_ctl ==`FW_ALU )?fw_alu:(fw_ctl==`FW_MEM)?fw_mem:rs; |
`MUXA_PC: a_o = pc; |
`MUXA_EXT: a_o = ext; |
`MUXA_SPC: a_o = spc; |
default : a_o = rs; |
endcase |
end |
endmodule |
|
module alu_muxb( |
input [31:0] rt, |
input [31:0]fw_alu, |
input [31:0]fw_mem, |
input [31:0]ext , |
input [1:0]ctl , |
input [2:0]fw_ctl , |
output reg [31:0] b_o |
); |
always@(*) |
case (ctl) |
`MUXB_RT :b_o = (fw_ctl ==`FW_ALU )?fw_alu:(fw_ctl==`FW_MEM)?fw_mem:rt; |
`MUXB_EXT : b_o=ext; |
default b_o=rt; |
endcase |
endmodule |
|
|
|
//This file is based on YACC ->alu.v and UCORE ->alu.v |
|
module alu ( |
input [31:0] a, |
input [31:0]b, |
output reg [31:0] alu_out, |
input [4:0] alu_func |
); |
|
reg [32:0] sum; |
|
always @(*) |
begin |
case (alu_func) |
|
`ALU_PA : alu_out=a; |
`ALU_PB : alu_out=b; |
`ALU_ADD : alu_out=a+b; |
`ALU_SUB , |
`ALU_SUBU : alu_out=a + (~b)+1; |
`ALU_OR : alu_out=a | b; |
`ALU_AND : alu_out=a & b; |
`ALU_XOR : alu_out=a ^ b; |
`ALU_NOR : alu_out=~(a | b); |
`ALU_SLTU : alu_out=(a < b)?1:0; |
`ALU_SLT : |
begin |
sum={a[31],a}+~{b[31],b}+33'h0_0000_0001; |
alu_out={31'h0000_0000,sum[32]}; |
end |
|
/* |
`ALU_SLL: alu_out = a<<b[4:0]; |
`ALU_SRL: alu_out = a>>b[4:0]; |
`ALU_SRA: alu_out=~(~a>>b[4:0]); |
//the three operations is done in shifter_tak or shift_ff |
*/ |
|
default : alu_out=32'h0; |
endcase |
end |
endmodule |
|
|
module shifter_ff( |
input [31:0] a, |
output reg [31:0] shift_out, |
input [4:0] shift_func,//connect to alu_func_ctl |
input [31:0] shift_amount//connect to b |
); |
|
always @ (*) |
begin |
case( shift_func ) |
`ALU_SLL: shift_out = a<<shift_amount; |
`ALU_SRL: shift_out = a>>shift_amount; |
`ALU_SRA: shift_out=~(~a>> shift_amount); |
default shift_out='d0; |
endcase |
end |
endmodule |
|
|
module shifter_tak( |
input [31:0] a, |
output reg [31:0] shift_out, |
input [4:0] shift_func,//connect to alu_func_ctl |
input [31:0] shift_amount//connect to b |
); |
|
always @ (*) |
case( shift_func ) |
`ALU_SLL: |
begin |
case ( shift_amount[4:0] ) |
5'b00000: shift_out=a; |
5'b00001: shift_out={a[30:0],1'b0}; |
5'b00010: shift_out={a[29:0],2'b0}; |
5'b00011: shift_out={a[28:0],3'b0}; |
5'b00100: shift_out={a[27:0],4'b0}; |
5'b00101: shift_out={a[26:0],5'b0}; |
5'b00110: shift_out={a[25:0],6'b0}; |
5'b00111: shift_out={a[24:0],7'b0}; |
5'b01000: shift_out={a[23:0],8'b0}; |
5'b01001: shift_out={a[22:0],9'b0}; |
5'b01010: shift_out={a[21:0],10'b0}; |
5'b01011: shift_out={a[20:0],11'b0}; |
5'b01100: shift_out={a[19:0],12'b0}; |
5'b01101: shift_out={a[18:0],13'b0}; |
5'b01110: shift_out={a[17:0],14'b0}; |
5'b01111: shift_out={a[16:0],15'b0}; |
5'b10000: shift_out={a[15:0],16'b0}; |
5'b10001: shift_out={a[14:0],17'b0}; |
5'b10010: shift_out={a[13:0],18'b0}; |
5'b10011: shift_out={a[12:0],19'b0}; |
5'b10100: shift_out={a[11:0],20'b0}; |
5'b10101: shift_out={a[10:0],21'b0}; |
5'b10110: shift_out={a[9:0],22'b0}; |
5'b10111: shift_out={a[8:0],23'b0}; |
5'b11000: shift_out={a[7:0],24'b0}; |
5'b11001: shift_out={a[6:0],25'b0}; |
5'b11010: shift_out={a[5:0],26'b0}; |
5'b11011: shift_out={a[4:0],27'b0}; |
5'b11100: shift_out={a[3:0],28'b0}; |
5'b11101: shift_out={a[2:0],29'b0}; |
5'b11110: shift_out={a[1:0],30'b0}; |
5'b11111: shift_out={a[0],31'b0}; |
default shift_out =32'bx;//never in this case |
endcase |
end |
`ALU_SRL : |
begin |
case (shift_amount[4:0]) |
5'b00000: shift_out=a; |
5'b00001: shift_out={1'b0,a[31:1]}; |
5'b00010: shift_out={2'b0,a[31:2]}; |
5'b00011: shift_out={3'b0,a[31:3]}; |
5'b00100: shift_out={4'b0,a[31:4]}; |
5'b00101: shift_out={5'b0,a[31:5]}; |
5'b00110: shift_out={6'b0,a[31:6]}; |
5'b00111: shift_out={7'b0,a[31:7]}; |
5'b01000: shift_out={8'b0,a[31:8]}; |
5'b01001: shift_out={9'b0,a[31:9]}; |
5'b01010: shift_out={10'b0,a[31:10]}; |
5'b01011: shift_out={11'b0,a[31:11]}; |
5'b01100: shift_out={12'b0,a[31:12]}; |
5'b01101: shift_out={13'b0,a[31:13]}; |
5'b01110: shift_out={14'b0,a[31:14]}; |
5'b01111: shift_out={15'b0,a[31:15]}; |
5'b10000: shift_out={16'b0,a[31:16]}; |
5'b10001: shift_out={17'b0,a[31:17]}; |
5'b10010: shift_out={18'b0,a[31:18]}; |
5'b10011: shift_out={19'b0,a[31:19]}; |
5'b10100: shift_out={20'b0,a[31:20]}; |
5'b10101: shift_out={21'b0,a[31:21]}; |
5'b10110: shift_out={22'b0,a[31:22]}; |
5'b10111: shift_out={23'b0,a[31:23]}; |
5'b11000: shift_out={24'b0,a[31:24]}; |
5'b11001: shift_out={25'b0,a[31:25]}; |
5'b11010: shift_out={26'b0,a[31:26]}; |
5'b11011: shift_out={27'b0,a[31:27]}; |
5'b11100: shift_out={28'b0,a[31:28]}; |
5'b11101: shift_out={29'b0,a[31:29]}; |
5'b11110: shift_out={30'b0,a[31:30]}; |
5'b11111: shift_out={31'b0,a[31:31]}; |
default : shift_out = 32'bx;//never in this case |
endcase |
end |
`ALU_SRA: |
begin// SHIFT_RIGHT_SIGNED |
case ( shift_amount[4:0]) |
5'b00000: shift_out=a; |
5'b00001: shift_out={a[31],a[31:1]}; |
5'b00010: shift_out={{2{a[31]}},a[31:2]}; |
5'b00011: shift_out={{3{a[31]}},a[31:3]}; |
5'b00100: shift_out={{4{a[31]}},a[31:4]}; |
5'b00101: shift_out={{5{a[31]}},a[31:5]}; |
5'b00110: shift_out={{6{a[31]}},a[31:6]}; |
5'b00111: shift_out={{7{a[31]}},a[31:7]}; |
5'b01000: shift_out={{8{a[31]}},a[31:8]}; |
5'b01001: shift_out={{9{a[31]}},a[31:9]}; |
5'b01010: shift_out={{10{a[31]}},a[31:10]}; |
5'b01011: shift_out={{11{a[31]}},a[31:11]}; |
5'b01100: shift_out={{12{a[31]}},a[31:12]}; |
5'b01101: shift_out={{13{a[31]}},a[31:13]}; |
5'b01110: shift_out={{14{a[31]}},a[31:14]}; |
5'b01111: shift_out={{15{a[31]}},a[31:15]}; |
5'b10000: shift_out={{16{a[31]}},a[31:16]}; |
5'b10001: shift_out={{17{a[31]}},a[31:17]}; |
5'b10010: shift_out={{18{a[31]}},a[31:18]}; |
5'b10011: shift_out={{19{a[31]}},a[31:19]}; |
5'b10100: shift_out={{20{a[31]}},a[31:20]}; |
5'b10101: shift_out={{21{a[31]}},a[31:21]}; |
5'b10110: shift_out={{22{a[31]}},a[31:22]}; |
5'b10111: shift_out={{23{a[31]}},a[31:23]}; |
5'b11000: shift_out={{24{a[31]}},a[31:24]}; |
5'b11001: shift_out={{25{a[31]}},a[31:25]}; |
5'b11010: shift_out={{26{a[31]}},a[31:26]}; |
5'b11011: shift_out={{27{a[31]}},a[31:27]}; |
5'b11100: shift_out={{28{a[31]}},a[31:28]}; |
5'b11101: shift_out={{29{a[31]}},a[31:29]}; |
5'b11110: shift_out={{30{a[31]}},a[31:30]}; |
5'b11111: shift_out={{31{a[31]}},a[31:31]}; |
default shift_out=32'bx;//never in this case |
endcase |
end |
default shift_out='d0; |
endcase |
endmodule |
|
module muldiv(ready,rst,op1,op2,clk,dout,func); |
input clk,rst; |
wire sign; |
input [4:0] func ; |
input [31:0] op2, op1; |
output [31:0] dout; |
output ready; |
reg [31:0] quotient, quotient_temp; |
reg [63:0] dividend_copy, divider_copy, diff; |
reg negative_output; |
|
reg [63:0] product, product_temp; |
|
reg [31:0] multiplier_copy; |
reg [63:0] multiplicand_copy; |
|
reg [6:0] mul_bit,div_bit; |
wire ready = ((mul_bit==0)&&(div_bit==0)); |
|
wire [31:0] dividend, divider; |
|
wire [31:0] remainder; |
wire [31:0] multiplier,multiplicand; |
|
reg [31:0] hi,lo; |
|
assign dout = (func==`ALU_MFHI)?hi:(func==`ALU_MFLO)?lo:0; |
|
assign remainder = (!negative_output) ? |
dividend_copy[31:0] : |
~dividend_copy[31:0] + 1'b1; |
|
assign multiplier=op2; |
assign multiplicand=op1; |
assign dividend=op1; |
assign divider = op2; |
assign sign = ((func==`ALU_MULT)||(func==`ALU_DIV)); |
|
initial |
begin |
hi=0; |
lo=0; |
end |
always @( posedge clk /*or negedge rst */) |
if (~rst) |
begin |
mul_bit=0; |
div_bit=0; |
/* |
hi=0; |
lo=0; |
*/ |
negative_output = 0; |
end |
else |
begin |
if((ready)&&((func==`ALU_MULT)||(func==`ALU_MULTTU))) |
begin |
mul_bit = 33; |
product = 0; |
product_temp = 0; |
multiplicand_copy = (!sign || !multiplicand[31]) ? |
{ 32'd0, multiplicand } : |
{ 32'd0, ~multiplicand + 1'b1}; |
multiplier_copy = (!sign || !multiplier[31]) ?multiplier :~multiplier + 1'b1; |
|
negative_output = sign && |
((multiplier[31] && !multiplicand[31]) |
||(!multiplier[31] && multiplicand[31])); |
end |
if ( mul_bit > 1 ) |
begin |
|
if( multiplier_copy[0] == 1'b1 ) |
product_temp = product_temp +multiplicand_copy; |
|
|
product = (!negative_output) ? |
product_temp : |
~product_temp + 1'b1; |
|
multiplier_copy = multiplier_copy >> 1; |
multiplicand_copy = multiplicand_copy << 1; |
mul_bit = mul_bit - 1'b1; |
end |
else if (mul_bit == 1) |
begin |
hi = product[63:32]; |
lo = product[31:0]; |
mul_bit=0; |
end |
|
if((ready)&&((func==`ALU_DIV)||(func==`ALU_DIVU))) |
begin |
div_bit = 33; |
quotient = 0; |
quotient_temp = 0; |
dividend_copy = (!sign || !dividend[31]) ? |
{32'd0,dividend} : |
{32'd0,~dividend + 1'b1}; |
|
divider_copy = (!sign || !divider[31]) ? |
{1'b0,divider,31'd0} : |
{1'b0,~divider + 1'b1,31'd0}; |
|
negative_output = sign && |
((divider[31] && !dividend[31]) |
||(!divider[31] && dividend[31])); |
end |
else if (div_bit > 1) |
begin |
diff = dividend_copy - divider_copy; |
quotient_temp = quotient_temp << 1; |
if( !diff[63] ) |
begin |
dividend_copy = diff; |
quotient_temp[0] = 1'd1; |
end |
quotient = (!negative_output) ?quotient_temp :~quotient_temp + 1'b1; |
divider_copy = divider_copy >> 1; |
div_bit = div_bit - 1'b1; |
end |
else if (div_bit == 1) |
begin |
lo = quotient; |
hi = remainder; |
div_bit=0; |
end |
end |
|
endmodule |
|
//creatied by Zhangfeifei |
//modified by Liwei |
module muldiv_ff |
( clk_i,rst_i, |
op_type,op1,op2, |
rdy,res |
|
); |
|
parameter OP_MULT = `ALU_MULT; |
parameter OP_MULTU = `ALU_MULTU; |
parameter OP_DIV = `ALU_DIV; |
parameter OP_DIVU = `ALU_DIVU; |
parameter OP_MFHI = `ALU_MFHI; |
parameter OP_MFLO = `ALU_MFLO; |
parameter OP_MTHI = `ALU_MTHI; |
parameter OP_MTLO = `ALU_MTLO; |
parameter OP_NONE = `ALU_NOP; |
|
input clk_i; |
input rst_i; |
input [4:0] op_type; |
input [31:0] op1; |
input [31:0] op2; |
output [31:0] res; |
output rdy; |
|
reg rdy; |
reg [64:0] hilo; |
reg [32:0] op2_reged; |
reg [5:0] count; |
reg op1_sign_reged; |
reg op2_sign_reged; |
reg sub_or_yn; |
|
wire [32:0] nop2_reged; |
assign nop2_reged = ~op2_reged +1; |
|
reg sign; |
reg mul; |
reg start; |
|
assign res = (op_type == OP_MFLO )?hilo[31:0]:((op_type == OP_MFHI))?hilo[63:32]:0;//op_type == OP_MFHI or other |
|
reg overflow; |
reg finish; |
reg add1; //if the quotient will add 1 at the end of the divide operation |
reg addop2; //if the remainder will add op2 at the end of the divide operation |
reg addnop2;//if the remainder will add ~op2+1 at the end of the divide operation |
|
|
always @( posedge clk_i /*or negedge rst_i*/) |
begin |
if(~rst_i) |
begin |
count = 6'bx; |
hilo = 65'b0; |
op2_reged = 33'bx; |
op1_sign_reged = 1'bx; |
op2_sign_reged = 1'bx; |
sub_or_yn = 1'bx; |
rdy = 1'b1; |
start = 1'bx; |
sign = 1'bx; |
mul = 1'bx; |
finish = 1'bx; |
add1 = 1'bx; |
addop2 = 1'bx; |
addnop2 = 1'bx; |
end |
else begin |
|
if(op_type == OP_MTHI || op_type == OP_MTLO) |
begin |
if(op_type == OP_MTHI) hilo[64:32] = {1'b0,op1}; |
if(op_type == OP_MTLO) hilo[31:0] = op1; |
rdy = 1; |
end |
else if(rdy) |
begin |
start = (op_type == OP_MULT) || (op_type == OP_MULTU) || (op_type == OP_DIV) || (op_type == OP_DIVU); |
mul = (op_type == OP_MULT) || (op_type == OP_MULTU); |
sign = (op_type == OP_MULT) || (op_type == OP_DIV); |
|
if(start) |
begin:START_SECTION |
reg [32:0] over; |
|
op2_reged = {sign ?op2[31] :1'b0 ,op2}; |
hilo = {~mul && sign?{33{op1[31]}}:33'b0,op1}; |
count = 6'b000000; |
rdy = 0; |
op1_sign_reged = sign?op1[31]:0; |
op2_sign_reged = sign?op2[31]:0; |
sub_or_yn = 0; |
|
over = ~op2_reged + {op1[31],op1}; |
overflow = sign && ~mul ? op1_sign_reged && op2_sign_reged && ~over[32] : 0; |
|
finish = 0; |
end |
end |
else if(start) |
begin |
if(overflow) |
begin |
hilo[63:0] = {hilo[31:0],32'b0}; |
rdy = 1; |
end |
else if(!count[5]) |
begin |
if(mul) |
begin |
if(sign) |
begin |
case({hilo[0],sub_or_yn}) |
2'b10:hilo[64:32] = hilo[64:32] + nop2_reged; |
2'b01:hilo[64:32] = hilo[64:32] + op2_reged; |
default:; |
endcase |
{hilo[63:0],sub_or_yn} = hilo[64:0]; |
end |
else begin |
if(hilo[0]) hilo[64:32] = hilo[64:32] + op2_reged; |
hilo = {1'b0,hilo[64:1]}; |
end |
end |
else begin |
sub_or_yn = hilo[64]== op2_sign_reged; |
hilo[64:1] = hilo[63:0]; |
|
hilo[64:32] = sub_or_yn ? hilo[64:32] + nop2_reged : hilo[64:32] + op2_reged; |
|
hilo[0] = hilo[64]== op2_sign_reged; |
end |
|
count = count + 1'b1; |
end |
else begin |
if(finish) |
begin |
if(add1) hilo[31:0] = hilo[31:0] + 1; |
case({addop2,addnop2}) |
2'b10: hilo[64:32] = hilo[64:32] + op2_reged; |
2'b01: hilo[64:32] = hilo[64:32] + nop2_reged; |
default: ; |
endcase |
rdy = 1; |
end |
else begin |
{add1,addop2,addnop2} = 3'b000; |
finish = 1; |
|
if(~mul) |
begin:LAST_CYCLE_DEAL_SECTION |
reg eqz,eqop2,eqnop2; |
eqz = hilo[64:32] == 0; |
eqop2 = hilo[64:32] == op2_reged; |
eqnop2 = hilo[64:32] == nop2_reged; |
casex({op1_sign_reged,op2_sign_reged,eqz,eqop2,eqnop2}) |
5'b101xx : {add1,addop2,addnop2} = 3'b000; |
5'b100x1 : {add1,addop2,addnop2} = 3'b010; |
5'b111xx : {add1,addop2,addnop2} = 3'b100; |
5'b1101x : {add1,addop2,addnop2} = 3'b101; |
default : |
begin:LAST_CYCLE_DEAL_SECTION_DEFAULT |
|
reg op1s_eq_op2s,op1s_eq_h64; |
op1s_eq_op2s = op1_sign_reged == op2_sign_reged; |
op1s_eq_h64 = op1_sign_reged == hilo[64]; |
|
add1 = ~op1s_eq_op2s; |
case({op1s_eq_op2s,op1s_eq_h64})//synthesis parallel_case |
2'b00: {addop2,addnop2} = 2'b01; |
2'b10: {addop2,addnop2} = 2'b10; |
default: {addop2,addnop2} = 2'b00; |
endcase |
end |
endcase |
end |
end |
end |
end |
end |
end |
endmodule |
|
|