URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
Compare Revisions
- This comparison shows the changes necessary to convert path
/mod_sim_exp
- from Rev 98 to Rev 99
- ↔ Reverse comparison
Rev 98 → Rev 99
/tags/Release_1.0/trunk/rtl/vhdl/core/adder_n.vhd
File deleted
\ No newline at end of file
/tags/Release_1.0/trunk/rtl/vhdl/core/register_n.vhd
File deleted
/tags/Release_1.0/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd
File deleted
\ No newline at end of file
/tags/Release_1.0/trunk/rtl/vhdl/core/cell_1b.vhd
File deleted
/tags/Release_1.0/trunk/rtl/vhdl/core/mont_ctrl.vhd
File deleted
/tags/Release_1.0/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
File deleted
\ No newline at end of file
/tags/Release_1.0/trunk/rtl/vhdl/core/stepping_logic.vhd
File deleted
\ No newline at end of file
/tags/Release_1.0/trunk/rtl/vhdl/core/operand_dp.vhd
File deleted
/tags/Release_1.0/trunk/rtl/vhdl/core/last_stage.vhd
File deleted
\ No newline at end of file
/tags/Release_1.0/trunk/sim/Makefile
File deleted
/tags/Release_1.0/trunk/sim/mod_sim_exp.do
File deleted
\ No newline at end of file
tags/Release_1.0/trunk/sim/out
Property changes :
Deleted: svn:ignore
## -1 +0,0 ##
-sim_output.txt
Index: tags/Release_1.0/trunk/sim/src/sim_input.txt
===================================================================
--- tags/Release_1.0/trunk/sim/src/sim_input.txt (revision 98)
+++ tags/Release_1.0/trunk/sim/src/sim_input.txt (nonexistent)
@@ -1,44 +0,0 @@
--- input generator program
--- generates test values per bit input pair
--- base_width, exp_width, g0, g1, e0, e1, m, R^2, result
-512
-32
-de0bbade38204e63359a46e672a8d0a2fd5300692ab48f9ef732f5c3fa212b90c98229bbb79bece734a622154c904dce9a0f53d4a88b3e558ef7612f6694ce75
-2e5d3fea7d9d0d33ac553eecd5c3f27a310115d283e49377820195c8e67781b6f112a625b14b747fa4cc13d06eba0917246c775f5c732865701ae9349ea8729c
-64150a6d
-8593f0d7
-18f204fe6846aeb6f58174d57a3372363c0d9fcfaa3dc18b1eff7e89bf7678636580d17dd84a873b14b9c0e1680bbdc87647f3c382902d2f58d2754b39bca875
-098eb081ecfa53f3f90e7dbf1e10b6e29ee45d6b02bff85403b335c0c6d5e1ab6eec5d670afb95713ed15f9723e5faedd6a42d95effafa771cb0c72d3a73c905
-068bce0fed3d2cda68f16fa939fd89e1a777c1e359967090ca050e9e855f4c1e08f7d1158d16b7b130be7731ef8a962b61307a5ce65e3c2687c76b0fbea16b6e
-14026cdda1794a94d7fa3cc76c69f6e43b5da0597c4040c6eb5cf65f677cac9bd85b08af0c998241ed365decd2d1cf2a62ccb6138a409224f7f03184d2cd77b5
-047d6c7653eca32d15971be88eba38526fea6bbb9f991ad6c8d9ede11bb11dc888444923c5732d57d31a4aeea397179007927ba14cfdd1078664dcbbfcc3aaf4
-00a84956047b71ed15148f0fc4be161c3fe4fe03650dff8e239982c0ebbbdbfbea2087f0c2f725a023e1e568e56e980e36524cbc29190b698bcb62534aa47c3b
-0ae33423c12184905fb44e34ae955ac5a502c9983910135ae22ae1f477c7e4532cf1134dde48ccc4126124f91085d64d6106c503b6e71b0ce5333d679b0f016f
--- base_width, exp_width, g0, g1, e0, e1, m, R^2, result
-1024
-16
-895f783fab56a353b58a8c4316eacf3012c77e6fbfdb4be7ed3cd27fc1c72a98f7733050ae2a4bd8c2b356f3f81de6f56258f69355b9321117b905723db3fe533ff94c12502b145c53e61608834634eae18e60c5b991b9f8d71b2d971cbe5ac9e09f4814addab421efdcc2870d2c92c87003fcff55ccba1d4f22f5ab90950fb0
-2a46626cf17c40bc08e57582f9852ad12cf0ee16f2440678d35a31147278a27658a66182b41c8327a559d058a9e9df5a55fe9eeccd16fd651c2d7f13a9942e7418052b4ae1b98f8ca3f3e828532a453289bd47b363738f866debf04222abeecac1e11f980b6f115f097f4540aa7735b993f17f55083caeb6a80f80d092c59d2f
-7c1f
-5eb8
-20f8be80ba9b4c7ca011f74c2d41581f0036d233b5e8e58b6dd5ca6db0625d764b927a43fe78844090c6843f29a331b76f8ece93e7e313eccb9bcb6ed2330923899aae43a0fd2430cb6772793755e74862e61e2ac376cfab9d61827e646421b28e9e0e2aca4625731aebbb69ea37e0fa859e499b8a186c8ee6196954170eb807
-06412c26297124ba58188bc306fa67d5e2349d33c677cb3701084ab808780e2d89f5d0b912e4866f37f4fec043a08c1991c2ef1a4d9f81b6bd6e8449cf2dfa510a0417db84ec15bea71c17b483852b918137926002c232d2adfd304c7a1beef79b83544bc405d714a10e1b2ed02e33cfbf25b0dffdda16e76d92e84d778dcc27
-1932ca7ae5c0e8979f823ceac3369726fe80409606a1b92fff2777002d4f71c3eefea8240ab4623c0a926245dc89a3fbf31859f4a8ca74866ebd6ff8409ac0073cc53c26991402aa702bdeaf7ca6ad054bb52cd4a7c0524eb2556e8b4143141e19ad9cd47814f9da438de01a9878d92658abfcbf39550817b54e1eb35e98f7cf
-1563cce47758b785cfd5bf169f156b4e4328b02221faa51d65cc5e819abd176948d3262a5f54a3dd960d1aeaba079bb8ad3d9926d0b5f3ff3dada08f6219e932ff858e754ef7ccc3f3b63cb0be8d2b346ef8054ed96a1bfcb6ab110f52d2c601f4cca7149a7a3ae60aae54611266844562f93a152656d6c857bb8e41209e2904
-19d524c74c54446433fd52e430bc5ab765afcdff9f13cfe2b81958baf4c1804e6f0ded2b6e39a37d59a9d6f9f833c6225920c7700a06f308074df8027b47ee5b4e0e3a96bcf2f44f74e5ff4b9eda59538c88e9e86f321f28584be5a4738eb56925cd464b980cbca2f78c2d456fc9c46bb58d34425dfa4b12ad486a7b79982e7f
-1544b14914333391b50ddc809fdd3b372f607292a3677ac566448683b734ba6feecb8ae791e6ba01dfdf37441676459f27343e727c5ce647e4e5f3fd5cea23e891525229306db57a0df7abf72d167a09cf3daf35e24628a39cd85b824dd548c516a36586e77a844677f3889a58ff57e80734c70d37e403eb0bc122825c36585c
-1324646bfb0bad60a82843ae9b47e64d4fb298550061b01755aed16ba0448afc9cac7557640de2e8eda59e5c9e29483ed5181d997d9f73e8edcfd671a724cc1f2ec976ed97b392148d8f1156f0cb4cab35a2b378c7a63b539daa0588260aa6fb2ab3f8ad497c96305a0fa081ee6ab4bb7067d3ea85c6455bf6f9af37deb38eb3
--- base_width, exp_width, g0, g1, e0, e1, m, R^2, result
-1536
-16
-b2c5bdfaf2ba8f23d35f13f9f77a1b8efd364518248b0ab2010d3260a3445f5a0a8aa4198b0c3207d3458a2e1539a16f8d4ae39b8913a951884085dcf22f2fb08291d7363204e5335e697f7398a9eceb1cafbcd348517674f15bbcbea90537ca2c8e6364d67421f29b9ae1c2e5f17872c08b122dd36a9965916287d08d8e2ece0500d4f1e37b45e29cb056efcd1449220d602e7cf13ec97b6c4f17a7e57af9c8ec65cb9864b7a4c83290855c8ffc55bc1da64e43b9ec4e9f266dce489d14aa8c
-c7a679c71dcaa96a8401dd62d7e71f68532c71819b8fe7ab721fb04b4dced1df8486000094ae3410622cd598ed3e74ab64952eee06659e1a891ccbd3702155bcbd3931224694faa89b4055c056e0aa844139fbbfe3d9b568b58387f1a955ee2e0043e5adbea47beace8589dd09bd98826db084ec7172c76b92d315d164f26c049784ed73ae654e5ca1c1d1faf227ce981b624ea7f57aab0a06b88d2b3105b957b1a19d1899b8e544f05c6de4756b8b095d2e346da3ecdb386b33fbe48f5254b1
-ed01
-611e
-da67cd50b638d8454a6854741126c4a07cc716330a37576e5021ca2fd2f24b31e027c0b9bc2929f2a2a38c9d003ae5b45d153957d2d0fe1cd05a87f375d050f6341d1e83f0583276902503259190aa7b0353e99a8b404da6feabe3a3b4a54263523a3619aedffe301db8be0aa07b04b8d8c1210cbb3034856d6f46dec94cf866558439083e26bd03dc4c11a81239654b516b2f891d20d0f7fc98547fac560ab315de74e6eb71dccef15a3ac85d3daa6072603a608a1d9201d5f09ad67ed8ce95
-27d738be5b0ccb62aec64623adfec2fb3fbdc26be7040817f764250d3f8f324ac468575a3953cfa8ea853097d17b71e3ed7a81255688a155c1f84c81f8288019a364e4a267a828ab90919f1d034743f88b81aecef510ef66dc7c45971ec384c4433bd9377cf72c97af9af5b36ea8522dea929d219819bd178b910c8c54365d5071ad39c2527b64d878d3df051b0fc82c71155571f9ea89f9a16b1ec77a05d39fd6840328958da9bb19c637d3952d0b704ff176b4ce18d782030310527785f8b6
-259832af49c727bab597ab8beed93b5f8338e9ccf5c8a891afde35d02d0db4ce1fd83f4643d6d60d5d5c7362ffc51a4ba2eac6a82d2f01e32fa5780c8a2faf09cbe2e17c0fa7cd896fdafcda6e6f5584fcac166574bfb25901541c5c4b5abd9cadc5c9e6512001cfe24741f55f84fb47273edef344cfcb7a9290b92136b30799aa7bc6f7c1d942fc23b3ee57edc69ab4ae94d076e2df2f080367ab8053a9f54cea218b19148e23310ea5c537a2c2559f8d9fc59f75e26dfe2a0f65298127316b
-bf4e8a2aff25f970db92a08206b2662fade7e2dee533fc585f0ebf85280f8760a45a7af38aec082a8bf07b380a3814e52b38147b7e92cde28cb7d0500bacba0e79a7d9752bc3f6b4a8ce7e9091d8f614fe8b970135d27e63f81faa587f35871abd5b3a8d4bd84e6ab717d1e49c5f92470547d4bf977a07eefcbdebe1754278afc06505e4058c099da4632614db98d9e3d7447e2a48403bd9cda0efb7fbc4e43a9e962cc9abe24f6312893a165927614519ccf6897d3f17f3d9ff5ca3abb00117
-4505cc0eb73a76e09af6c512b4b3611d7c3b3108a68ad4d08aca6ca13756e553efe6ade8c7a0ae6b5bbad04ba0a281824de0a13763c3aca96930c4f9aec2e9ed52e9f329db58ec6acc4d1a86df706f3e74b2e088f9064caef6a0074d63e726243779721517848124ea65c1ccd3e8a1471afa3f25811a577757aa2807577a7c6a77c3634813f92cdaade697cb17fa0555918d53a75e05c263e807f107437a5c4032c68f18b8ca54a61caff215debc1a0988933e6e442501a8fbc497403631d543
-51fe92e79cf87e206a6a1d6192cc670090a20ad3fcc36f13ce25fc7ca15f7c0cf5fc1f466beb949c01af87520731b63699900f0d4bbc21d2fc13b30a66fd767d76b6d391fb1418edc2e07057d9fa124c99dfe154e46f98a718a09ccfd01862ebbff0221cdfe9039851872526aee09be7efe4f1fe3d2fdf747e0ab0fce0f5062e7379e19fbe8f25647a081a90e5a8c9c28fa7a2d600c9072b139c901236ec3e04ab2e67c684348d07c0857b7d85dabe1e232eeb63675c63d6732f2bfea20dcd6b
-5ed841eda3b8c955fe433d971816c55f290735fd5c60aa5c0021f441172383463e18835ff4962fcc76c9b59894a8a11c5748183a3453c9e9d3caace2834a285f326d49742b2e56ff7d1dccb91bb2f3059f6a3c509c7fb62d929b8002619bb70676b5ec0617b3d36fd2fabb2701ff9c0b94b3942673de0fe22e4d13969398f8da5563959c05328ef7767b6e4e11e4e31a3196f35919b29464e45e5a8a461bd9533a11a3bdf9c1f57ec911b496b05072f45427293234f8189d0649f8a05b91ffb5
Index: tags/Release_1.0/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
===================================================================
--- tags/Release_1.0/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd (revision 98)
+++ tags/Release_1.0/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd (nonexistent)
@@ -1,684 +0,0 @@
-----------------------------------------------------------------------
----- mod_sim_exp_core_tb ----
----- ----
----- This file is part of the ----
----- Modular Simultaneous Exponentiation Core project ----
----- http://www.opencores.org/cores/mod_sim_exp/ ----
----- ----
----- Description ----
----- testbench for the modular simultaneous exponentiation ----
----- core. Performs some exponentiations to verify the design ----
----- Takes input parameters from sim_input.txt en writes ----
----- result and output to sim_output.txt ----
----- ----
----- Dependencies: ----
----- - multiplier_core ----
----- ----
----- Authors: ----
----- - Geoffrey Ottoy, DraMCo research group ----
----- - Jonas De Craene, JonasDC@opencores.org ----
----- ----
-----------------------------------------------------------------------
----- ----
----- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
----- ----
----- This source file may be used and distributed without ----
----- restriction provided that this copyright statement is not ----
----- removed from the file and that any derivative work contains ----
----- the original copyright notice and the associated disclaimer. ----
----- ----
----- This source file is free software; you can redistribute it ----
----- and/or modify it under the terms of the GNU Lesser General ----
----- Public License as published by the Free Software Foundation; ----
----- either version 2.1 of the License, or (at your option) any ----
----- later version. ----
----- ----
----- This source is distributed in the hope that it will be ----
----- useful, but WITHOUT ANY WARRANTY; without even the implied ----
----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
----- PURPOSE. See the GNU Lesser General Public License for more ----
----- details. ----
----- ----
----- You should have received a copy of the GNU Lesser General ----
----- Public License along with this source; if not, download it ----
----- from http://www.opencores.org/lgpl.shtml ----
----- ----
-----------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-
-library std;
-use std.textio.all;
-
-library ieee;
-use ieee.std_logic_textio.all;
-
-library mod_sim_exp;
-use mod_sim_exp.mod_sim_exp_pkg.all;
-
-entity mod_sim_exp_core_tb is
-end mod_sim_exp_core_tb;
-
-architecture test of mod_sim_exp_core_tb is
- constant nr_stages : integer := 96;
- constant clk_period : time := 10 ns;
- signal clk : std_logic := '0';
- signal reset : std_logic := '1';
- file input : text open read_mode is "src/sim_input.txt";
- file output : text open write_mode is "out/sim_output.txt";
-
- ------------------------------------------------------------------
- -- Signals for multiplier core memory space
- ------------------------------------------------------------------
- signal core_rw_address : std_logic_vector (8 downto 0);
- signal core_data_in : std_logic_vector(31 downto 0);
- signal core_fifo_din : std_logic_vector(31 downto 0);
- signal core_data_out : std_logic_vector(31 downto 0);
- signal core_write_enable : std_logic;
- signal core_fifo_push : std_logic;
- ------------------------------------------------------------------
- -- Signals for multiplier core control
- ------------------------------------------------------------------
- signal core_start : std_logic;
- signal core_run_auto : std_logic;
- signal core_p_sel : std_logic_vector(1 downto 0);
- signal core_dest_op_single : std_logic_vector(1 downto 0);
- signal core_x_sel_single : std_logic_vector(1 downto 0);
- signal core_y_sel_single : std_logic_vector(1 downto 0);
- signal calc_time : std_logic;
- ------------------------------------------------------------------
- -- Signals for multiplier core interrupt
- ------------------------------------------------------------------
- signal core_fifo_full : std_logic;
- signal core_fifo_nopush : std_logic;
- signal core_ready : std_logic;
- signal core_mem_collision : std_logic;
-
-begin
-
-------------------------------------------
--- Generate clk
-------------------------------------------
-clk_process : process
-begin
- while (true) loop
- clk <= '0';
- wait for clk_period/2;
- clk <= '1';
- wait for clk_period/2;
- end loop;
-end process;
-
-------------------------------------------
--- Stimulus Process
-------------------------------------------
-stim_proc : process
- procedure waitclk(n : natural := 1) is
- begin
- for i in 1 to n loop
- wait until rising_edge(clk);
- end loop;
- end waitclk;
-
- procedure loadOp(constant op_sel : std_logic_vector(2 downto 0);
- variable op_data : std_logic_vector(2047 downto 0)) is
- begin
- wait until rising_edge(clk);
- core_rw_address <= op_sel & "000000";
- wait until rising_edge(clk);
- core_write_enable <= '1';
- for i in 0 to (1536/32)-1 loop
- assert (core_mem_collision='0')
- report "collision detected while writing operand!!" severity failure;
- case (core_p_sel) is
- when "11" =>
- core_data_in <= op_data(((i+1)*32)-1 downto (i*32));
- when "01" =>
- if (i < 16) then core_data_in <= op_data(((i+1)*32)-1 downto (i*32));
- else core_data_in <= x"00000000"; end if;
- when "10" =>
- if (i >= 16) then core_data_in <= op_data(((i-15)*32)-1 downto ((i-16)*32));
- else core_data_in <= x"00000000"; end if;
- when others =>
- core_data_in <= x"00000000";
- end case;
-
- wait until rising_edge(clk);
- core_rw_address <= core_rw_address+"000000001";
- end loop;
- core_write_enable <= '0';
- wait until rising_edge(clk);
- end loadOp;
-
- procedure readOp(constant op_sel : std_logic_vector(2 downto 0);
- variable op_data : out std_logic_vector(2047 downto 0);
- variable op_width : integer) is
- begin
- wait until rising_edge(clk);
- core_dest_op_single <= op_sel(1 downto 0);
- if (core_p_sel = "10") then
- core_rw_address <= op_sel & "010000";
- else
- core_rw_address <= op_sel & "000000";
- end if;
- waitclk(2);
-
- for i in 0 to (op_width/32)-2 loop
- op_data(((i+1)*32)-1 downto (i*32)) := core_data_out;
- core_rw_address <= core_rw_address+"000000001";
- waitclk(2);
- end loop;
- op_data(op_width-1 downto op_width-32) := core_data_out;
- wait until rising_edge(clk);
- end readOp;
-
- function ToString(constant Timeval : time) return string is
- variable StrPtr : line;
- begin
- write(StrPtr,Timeval);
- return StrPtr.all;
- end ToString;
-
- -- variables to read file
- variable L : line;
- variable Lw : line;
- variable base_width : integer;
- variable exponent_width : integer;
- variable g0 : std_logic_vector(2047 downto 0) := (others=>'0');
- variable g1 : std_logic_vector(2047 downto 0) := (others=>'0');
- variable e0 : std_logic_vector(2047 downto 0) := (others=>'0');
- variable e1 : std_logic_vector(2047 downto 0) := (others=>'0');
- variable m : std_logic_vector(2047 downto 0) := (others=>'0');
- variable R2 : std_logic_vector(2047 downto 0) := (others=>'0');
- variable R : std_logic_vector(2047 downto 0) := (others=>'0');
- variable gt0 : std_logic_vector(2047 downto 0) := (others=>'0');
- variable gt1 : std_logic_vector(2047 downto 0) := (others=>'0');
- variable gt01 : std_logic_vector(2047 downto 0) := (others=>'0');
- variable one : std_logic_vector(2047 downto 0) := std_logic_vector(conv_unsigned(1, 2048));
- variable result : std_logic_vector(2047 downto 0) := (others=>'0');
- variable data_read : std_logic_vector(2047 downto 0) := (others=>'0');
- variable good_value : boolean;
- variable param_count : integer := 0;
-
- -- constants for operand selection
- constant op_modulus : std_logic_vector(2 downto 0) := "100";
- constant op_0 : std_logic_vector(2 downto 0) := "000";
- constant op_1 : std_logic_vector(2 downto 0) := "001";
- constant op_2 : std_logic_vector(2 downto 0) := "010";
- constant op_3 : std_logic_vector(2 downto 0) := "011";
-
- variable timer : time;
-begin
- -- initialisation
- -- memory
- core_write_enable <= '0';
- core_data_in <= x"00000000";
- core_rw_address <= "000000000";
- -- fifo
- core_fifo_din <= x"00000000";
- core_fifo_push <= '0';
- -- control
- core_start <= '0';
- core_run_auto <= '0';
- core_x_sel_single <= "00";
- core_y_sel_single <= "01";
- core_dest_op_single <= "01";
- core_p_sel <= "11";
-
- -- Generate active high reset signal
- reset <= '1';
- waitclk(100);
- reset <= '0';
- waitclk(100);
-
- while not endfile(input) loop
- readline(input, L); -- read next line
- next when L(1)='-'; -- skip comment lines
- -- read input values
- case param_count is
- when 0 => -- base width
- read(L, base_width, good_value);
- assert good_value report "Can not read base width" severity failure;
- assert false report "Simulating exponentiation" severity note;
- write(Lw, string'("----------------------------------------------"));
- writeline(output, Lw);
- write(Lw, string'("-- EXPONENTIATION --"));
- writeline(output, Lw);
- write(Lw, string'("----------------------------------------------"));
- writeline(output, Lw);
- write(Lw, string'("----- Variables used:"));
- writeline(output, Lw);
- write(Lw, string'("base width: "));
- write(Lw, base_width);
- writeline(output, Lw);
- case (base_width) is
- when 1536 => when 1024 => when 512 =>
- when others =>
- write(Lw, string'("=> incompatible base width!!!")); writeline(output, Lw);
- assert false report "incompatible base width!!!" severity failure;
- end case;
-
- when 1 => -- exponent width
- read(L, exponent_width, good_value);
- assert good_value report "Can not read exponent width" severity failure;
- write(Lw, string'("exponent width: "));
- write(Lw, exponent_width);
- writeline(output, Lw);
-
- when 2 => -- g0
- hread(L, g0(base_width-1 downto 0), good_value);
- assert good_value report "Can not read g0! (wrong lenght?)" severity failure;
- write(Lw, string'("g0: "));
- hwrite(Lw, g0(base_width-1 downto 0));
- writeline(output, Lw);
-
- when 3 => -- g1
- hread(L, g1(base_width-1 downto 0), good_value);
- assert good_value report "Can not read g1! (wrong lenght?)" severity failure;
- write(Lw, string'("g1: "));
- hwrite(Lw, g1(base_width-1 downto 0));
- writeline(output, Lw);
-
- when 4 => -- e0
- hread(L, e0(exponent_width-1 downto 0), good_value);
- assert good_value report "Can not read e0! (wrong lenght?)" severity failure;
- write(Lw, string'("e0: "));
- hwrite(Lw, e0(exponent_width-1 downto 0));
- writeline(output, Lw);
-
- when 5 => -- e1
- hread(L, e1(exponent_width-1 downto 0), good_value);
- assert good_value report "Can not read e1! (wrong lenght?)" severity failure;
- write(Lw, string'("e1: "));
- hwrite(Lw, e1(exponent_width-1 downto 0));
- writeline(output, Lw);
-
- when 6 => -- m
- hread(L, m(base_width-1 downto 0), good_value);
- assert good_value report "Can not read m! (wrong lenght?)" severity failure;
- write(Lw, string'("m: "));
- hwrite(Lw, m(base_width-1 downto 0));
- writeline(output, Lw);
-
- when 7 => -- R^2
- hread(L, R2(base_width-1 downto 0), good_value);
- assert good_value report "Can not read R2! (wrong lenght?)" severity failure;
- write(Lw, string'("R2: "));
- hwrite(Lw, R2(base_width-1 downto 0));
- writeline(output, Lw);
-
- when 8 => -- R
- hread(L, R(base_width-1 downto 0), good_value);
- assert good_value report "Can not read R! (wrong lenght?)" severity failure;
-
- when 9 => -- gt0
- hread(L, gt0(base_width-1 downto 0), good_value);
- assert good_value report "Can not read gt0! (wrong lenght?)" severity failure;
-
- when 10 => -- gt1
- hread(L, gt1(base_width-1 downto 0), good_value);
- assert good_value report "Can not read gt1! (wrong lenght?)" severity failure;
-
- when 11 => -- gt01
- hread(L, gt01(base_width-1 downto 0), good_value);
- assert good_value report "Can not read gt01! (wrong lenght?)" severity failure;
-
- -- select pipeline for all computations
- ----------------------------------------
- writeline(output, Lw);
- write(Lw, string'("----- Selecting pipeline: "));
- writeline(output, Lw);
- case (base_width) is
- when 1536 => core_p_sel <= "11"; write(Lw, string'(" Full pipeline selected"));
- when 1024 => core_p_sel <= "10"; write(Lw, string'(" Upper pipeline selected"));
- when 512 => core_p_sel <= "01"; write(Lw, string'(" Lower pipeline selected"));
- when others =>
- write(Lw, string'(" Invallid bitwidth for design"));
- assert false report "impossible basewidth!" severity failure;
- end case;
- writeline(output, Lw);
-
- writeline(output, Lw);
- write(Lw, string'("----- Writing operands:"));
- writeline(output, Lw);
-
- -- load the modulus
- --------------------
- loadOp(op_modulus, m); -- visual check needed
- write(Lw, string'(" m written"));
- writeline(output, Lw);
-
- -- load g0
- -----------
- loadOp(op_0, g0);
- -- verify
- readOp(op_0, data_read, base_width);
- if (g0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
- write(Lw, string'(" g0 written in operand_0")); writeline(output, Lw);
- else
- write(Lw, string'(" failed to write g0 to operand_0!")); writeline(output, Lw);
- assert false report "Load g0 to op0 data verify failed!!" severity failure;
- end if;
-
- -- load g1
- -----------
- loadOp(op_1, g1);
- -- verify
- readOp(op_1, data_read, base_width);
- if (g1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
- write(Lw, string'(" g1 written in operand_1")); writeline(output, Lw);
- else
- write(Lw, string'(" failed to write g1 to operand_1!")); writeline(output, Lw);
- assert false report "Load g1 to op1 data verify failed!!" severity failure;
- end if;
-
- -- load R2
- -----------
- loadOp(op_2, R2);
- -- verify
- readOp(op_2, data_read, base_width);
- if (R2(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
- write(Lw, string'(" R^2 written in operand_2")); writeline(output, Lw);
- else
- write(Lw, string'(" failed to write R^2 to operand_2!")); writeline(output, Lw);
- assert false report "Load R2 to op2 data verify failed!!" severity failure;
- end if;
-
- -- load a=1
- ------------
- loadOp(op_3, one);
- -- verify
- readOp(op_3, data_read, base_width);
- if (one(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
- write(Lw, string'(" 1 written in operand_3")); writeline(output, Lw);
- else
- write(Lw, string'(" failed to write 1 to operand_3!")); writeline(output, Lw);
- assert false report "Load 1 to op3 data verify failed!!" severity failure;
- end if;
-
- writeline(output, Lw);
- write(Lw, string'("----- Pre-computations: "));
- writeline(output, Lw);
-
- -- compute gt0
- ---------------
- core_x_sel_single <= "00"; -- g0
- core_y_sel_single <= "10"; -- R^2
- core_dest_op_single <= "00"; -- op_0 = (g0 * R) mod m
- wait until rising_edge(clk);
- timer := NOW;
- core_start <= '1';
- wait until rising_edge(clk);
- core_start <= '0';
- wait until core_ready = '1';
- timer := NOW-timer;
- waitclk(10);
- readOp(op_0, data_read, base_width);
- write(Lw, string'(" Computed gt0: "));
- hwrite(Lw, data_read(base_width-1 downto 0));
- writeline(output, Lw);
- write(Lw, string'(" Read gt0: "));
- hwrite(Lw, gt0(base_width-1 downto 0));
- writeline(output, Lw);
- write(Lw, string'(" => calc time is "));
- write(Lw, string'(ToString(timer)));
- writeline(output, Lw);
- write(Lw, string'(" => expected time is "));
- write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
- writeline(output, Lw);
- if (gt0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
- write(Lw, string'(" => gt0 is correct!")); writeline(output, Lw);
- else
- write(Lw, string'(" => Error: gt0 is incorrect!!!")); writeline(output, Lw);
- assert false report "gt0 is incorrect!!!" severity failure;
- end if;
-
- -- compute gt1
- ---------------
- core_x_sel_single <= "01"; -- g1
- core_y_sel_single <= "10"; -- R^2
- core_dest_op_single <= "01"; -- op_1 = (g1 * R) mod m
- wait until rising_edge(clk);
- timer := NOW;
- core_start <= '1';
- wait until rising_edge(clk);
- core_start <= '0';
- wait until core_ready = '1';
- timer := NOW-timer;
- waitclk(10);
- readOp(op_1, data_read, base_width);
- write(Lw, string'(" Computed gt1: "));
- hwrite(Lw, data_read(base_width-1 downto 0));
- writeline(output, Lw);
- write(Lw, string'(" Read gt1: "));
- hwrite(Lw, gt1(base_width-1 downto 0));
- writeline(output, Lw);
- write(Lw, string'(" => calc time is "));
- write(Lw, string'(ToString(timer)));
- writeline(output, Lw);
- write(Lw, string'(" => expected time is "));
- write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
- writeline(output, Lw);
- if (gt1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
- write(Lw, string'(" => gt1 is correct!")); writeline(output, Lw);
- else
- write(Lw, string'(" => Error: gt1 is incorrect!!!")); writeline(output, Lw);
- assert false report "gt1 is incorrect!!!" severity failure;
- end if;
-
- -- compute a
- -------------
- core_x_sel_single <= "10"; -- R^2
- core_y_sel_single <= "11"; -- 1
- core_dest_op_single <= "11"; -- op_3 = (R) mod m
- wait until rising_edge(clk);
- core_start <= '1';
- timer := NOW;
- wait until rising_edge(clk);
- core_start <= '0';
- wait until core_ready = '1';
- timer := NOW-timer;
- waitclk(10);
- readOp(op_3, data_read, base_width);
- write(Lw, string'(" Computed a=(R)mod m: "));
- hwrite(Lw, data_read(base_width-1 downto 0));
- writeline(output, Lw);
- write(Lw, string'(" Read (R)mod m: "));
- hwrite(Lw, R(base_width-1 downto 0));
- writeline(output, Lw);
- write(Lw, string'(" => calc time is "));
- write(Lw, string'(ToString(timer)));
- writeline(output, Lw);
- write(Lw, string'(" => expected time is "));
- write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
- writeline(output, Lw);
- if (R(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
- write(Lw, string'(" => (R)mod m is correct!")); writeline(output, Lw);
- else
- write(Lw, string'(" => Error: (R)mod m is incorrect!!!")); writeline(output, Lw);
- assert false report "(R)mod m is incorrect!!!" severity failure;
- end if;
-
- -- compute gt01
- ---------------
- core_x_sel_single <= "00"; -- gt0
- core_y_sel_single <= "01"; -- gt1
- core_dest_op_single <= "10"; -- op_2 = (gt0 * gt1) mod m
- wait until rising_edge(clk);
- core_start <= '1';
- timer := NOW;
- wait until rising_edge(clk);
- core_start <= '0';
- wait until core_ready = '1';
- timer := NOW-timer;
- waitclk(10);
- readOp(op_2, data_read, base_width);
- write(Lw, string'(" Computed gt01: "));
- hwrite(Lw, data_read(base_width-1 downto 0));
- writeline(output, Lw);
- write(Lw, string'(" Read gt01: "));
- hwrite(Lw, gt01(base_width-1 downto 0));
- writeline(output, Lw);
- write(Lw, string'(" => calc time is "));
- write(Lw, string'(ToString(timer)));
- writeline(output, Lw);
- write(Lw, string'(" => expected time is "));
- write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
- writeline(output, Lw);
- if (gt01(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
- write(Lw, string'(" => gt01 is correct!")); writeline(output, Lw);
- else
- write(Lw, string'(" => Error: gt01 is incorrect!!!")); writeline(output, Lw);
- assert false report "gt01 is incorrect!!!" severity failure;
- end if;
-
- -- load exponent fifo
- ----------------------
- writeline(output, Lw);
- write(Lw, string'("----- Loading exponent fifo: "));
- writeline(output, Lw);
- for i in (exponent_width/16)-1 downto 0 loop
- core_fifo_din <= e1((i*16)+15 downto (i*16)) & e0((i*16)+15 downto (i*16));
- wait until rising_edge(clk);
- core_fifo_push <= '1';
- wait until rising_edge(clk);
- assert (core_fifo_full='0' and core_fifo_nopush='0')
- report "Fifo error, full or nopush" severity failure;
- core_fifo_push <= '0';
- wait until rising_edge(clk);
- end loop;
- waitclk(10);
- write(Lw, string'(" => Done"));
- writeline(output, Lw);
-
- -- start exponentiation
- ------------------------
- writeline(output, Lw);
- write(Lw, string'("----- Starting exponentiation: "));
- writeline(output, Lw);
- core_run_auto <= '1';
- wait until rising_edge(clk);
- timer := NOW;
- core_start <= '1';
- wait until rising_edge(clk);
- core_start <= '0';
- wait until core_ready='1';
- timer := NOW-timer;
- waitclk(10);
- write(Lw, string'(" => calc time is "));
- write(Lw, string'(ToString(timer)));
- writeline(output, Lw);
- write(Lw, string'(" => expected time is "));
- write(Lw, ((nr_stages+(2*(base_width-1)))*clk_period*7*exponent_width)/4);
- writeline(output, Lw);
- write(Lw, string'(" => Done"));
- core_run_auto <= '0';
- writeline(output, Lw);
-
- -- post-computations
- ---------------------
- writeline(output, Lw);
- write(Lw, string'("----- Post-computations: "));
- writeline(output, Lw);
- -- load in 1 to operand 2
- loadOp(op_2, one);
- -- verify
- readOp(op_2, data_read, base_width);
- if (one(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
- write(Lw, string'(" 1 written in operand_2")); writeline(output, Lw);
- else
- write(Lw, string'(" failed to write 1 to operand_2!")); writeline(output, Lw);
- assert false report "Load 1 to op2 data verify failed!!" severity failure;
- end if;
- -- compute result
- core_x_sel_single <= "11"; -- a
- core_y_sel_single <= "10"; -- 1
- core_dest_op_single <= "11"; -- op_3 = (a) mod m
- wait until rising_edge(clk);
- timer := NOW;
- core_start <= '1';
- wait until rising_edge(clk);
- core_start <= '0';
- wait until core_ready = '1';
- timer := NOW-timer;
- waitclk(10);
- readOp(op_3, data_read, base_width);
- write(Lw, string'(" Computed result: "));
- hwrite(Lw, data_read(base_width-1 downto 0));
- writeline(output, Lw);
- write(Lw, string'(" => calc time is "));
- write(Lw, string'(ToString(timer)));
- writeline(output, Lw);
- write(Lw, string'(" => expected time is "));
- write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
- writeline(output, Lw);
-
- when 12 => -- check with result
- hread(L, result(base_width-1 downto 0), good_value);
- assert good_value report "Can not read result! (wrong lenght?)" severity failure;
- writeline(output, Lw);
- write(Lw, string'("----- verifying result: "));
- writeline(output, Lw);
- write(Lw, string'(" Read result: "));
- hwrite(Lw, result(base_width-1 downto 0));
- writeline(output, Lw);
- write(Lw, string'(" Computed result: "));
- hwrite(Lw, data_read(base_width-1 downto 0));
- writeline(output, Lw);
- if (result(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
- write(Lw, string'(" => Result is correct!")); writeline(output, Lw);
- else
- write(Lw, string'(" Error: result is incorrect!!!")); writeline(output, Lw);
- assert false report "result is incorrect!!!" severity failure;
- end if;
- writeline(output, Lw);
-
- when others =>
- assert false report "undefined state!" severity failure;
- end case;
-
- if (param_count = 12) then
- param_count := 0;
- else
- param_count := param_count+1;
- end if;
- end loop;
-
- wait for 1 us;
- assert false report "End of simulation" severity failure;
-
-end process;
-
-------------------------------------------
--- Multiplier core instance
-------------------------------------------
-the_multiplier : mod_sim_exp.mod_sim_exp_pkg.mod_sim_exp_core
-port map(
- clk => clk,
- reset => reset,
--- operand memory interface (plb shared memory)
- write_enable => core_write_enable,
- data_in => core_data_in,
- rw_address => core_rw_address,
- data_out => core_data_out,
- collision => core_mem_collision,
--- op_sel fifo interface
- fifo_din => core_fifo_din,
- fifo_push => core_fifo_push,
- fifo_full => core_fifo_full,
- fifo_nopush => core_fifo_nopush,
--- ctrl signals
- start => core_start,
- run_auto => core_run_auto,
- ready => core_ready,
- x_sel_single => core_x_sel_single,
- y_sel_single => core_y_sel_single,
- dest_op_single => core_dest_op_single,
- p_sel => core_p_sel,
- calc_time => calc_time
-);
-
-end test;
Index: tags/Release_1.0/trunk
===================================================================
--- tags/Release_1.0/trunk (revision 98)
+++ tags/Release_1.0/trunk (nonexistent)
tags/Release_1.0/trunk
Property changes :
Deleted: svn:ignore
## -1 +0,0 ##
-.project