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URL https://opencores.org/ocsvn/modular_oscilloscope/modular_oscilloscope/trunk

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    /modular_oscilloscope/trunk
    from Rev 56 to Rev 57
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Rev 56 → Rev 57

/hdl/modular_oscilloscope.vhd
24,6 → 24,8
 
-- NOTES:
 
 
 
 
--==================================================================================================
-- TO DO
103,12 → 105,18
signal ctrl_we_o_memr: std_logic;
signal clk_daq, clk_port: std_logic;
signal inverted_reset: std_logic;
 
begin
inverted_reset <= not(reset_I);
U_DAQ: daq
generic map(
DEFALT_CONFIG => "0000101000000000"
DEFALT_CONFIG => "0000001000000000"
-- 5432109876543210
--: std_logic_vector := "0000100000000000"
-- bits 8 a 0 clk_pre_scaler
129,7 → 137,7
adc_sleep_O => adc_sleep_O,
adc_chip_sel_O => adc_chip_sel_O,
-- Interno
RST_I => reset_I,
RST_I => inverted_reset,
CLK_I => clk_daq,
DAT_I => ctrl_dat_o_daq,
ADR_I => ctrl_adr_o_daq,
160,7 → 168,7
nFault => nFault_O,
nSelectIn => nSelectIn_I,
-- Interno
RST_I => reset_I,
RST_I => inverted_reset,
CLK_I => clk_port,
DAT_I => ctrl_dat_o_port,
DAT_O => ctrl_dat_i_port,
182,7 → 190,7
ACK_O_port => ctrl_ack_o_port,
WE_I_port => ctrl_we_i_port,
CLK_I_port => clk_port,
RST_I_port => reset_I,
RST_I_port => inverted_reset,
DAT_I_daq => ctrl_dat_i_daq,
DAT_O_daq => ctrl_dat_o_daq,
192,7 → 200,7
ACK_I_daq => ctrl_ack_i_daq,
WE_O_daq => ctrl_we_o_daq,
CLK_I_daq => clk_daq,
RST_I_daq => reset_I,
RST_I_daq => inverted_reset,
DAT_O_memw => ctrl_dat_o_memw,
ADR_O_memw => ctrl_adr_o_memw,
212,7 → 220,7
U_DPORTMEM: dual_port_memory_wb
port map(
-- Puerto A (Higer prioriry)
RST_I_a => reset_I,
RST_I_a => inverted_reset,
CLK_I_a => clk_daq,
DAT_I_a => ctrl_dat_o_memw,
DAT_O_a => open,
222,7 → 230,7
ACK_O_a => ctrl_ack_i_memw,
WE_I_a => ctrl_we_o_memw,
-- Puerto B (Lower prioriry)
RST_I_b => reset_I,
RST_I_b => inverted_reset,
CLK_I_b => clk_port,
DAT_I_b => X"0000",
DAT_O_b => ctrl_dat_i_memr,
/hdl/tbench/modullar_oscilloscope_tbench_text.vhd
91,7 → 91,7
data2 <= data2 + 2;
end if;
if sleep_I = '1' or chip_sel_I = '0' then
if sleep_I = '1' or chip_sel_I = '1' then
data_O <= (others => '0');
else
case sel_I is
233,6 → 233,8
--wait for 30 ns;
nSelectIn_I <= '1';
wait until Busy_O = '0';
Data_IO <= (others => '0');
wait for 30 ns;
Data_IO <= in_data(7 downto 0); -- Data1
nAutoFd_I <= '0'; -- datStb
239,6 → 241,8
wait until Busy_O = '1';
nAutoFd_I <= '1';
wait until Busy_O = '0';
Data_IO <= (others => '0');
wait for 30 ns;
Data_IO <= in_data(15 downto 8); -- Data0
nAutoFd_I <= '0'; -- datStb
264,28 → 268,74
Data_IO <= in_address; -- Address
nSelectIn_I <= '0'; -- addStb
wait until Busy_O = '1';
--wait for 30 ns;
nSelectIn_I <= '1';
wait for 30 ns; -- default
-- wait for 150 ns;
nSelectIn_I <= '1';
wait until Busy_O = '0';
wait for 30 ns;
nStrobe_I <= '1'; -- '1' -> is read
Data_IO <= (others => 'Z'); -- Data1
nAutoFd_I <= '0'; -- datStb
-- wait for 150 ns;
wait until (Busy_O = '1');
wait for 30 ns;
wait for 150 ns;
nAutoFd_I <= '1';
-- wait for 40 ns;
wait until (Busy_O = '0');
wait for 30 ns;
Data_IO <= (others => 'Z'); -- Data0
nAutoFd_I <= '0'; -- datStb
-- wait for 150 ns;
wait until (Busy_O = '1');
wait for 30 ns;
wait for 150 ns;
out_runflag <= Data_IO(6);
nAutoFd_I <= '1';
wait until (Busy_O = '0');
wait for 30 ns;
end procedure ReadData;
------------------------------------------------------------------------------------------------
-- Procedure for read from epp port
procedure ReadData2(
signal out_runflag: out std_logic;
--constant in_address: in std_logic_vector(7 downto 0);
signal Data_IO: inout std_logic_vector(7 downto 0);
signal nStrobe_I: out std_logic;
signal nSelectIn_I: out std_logic;
signal nAutoFd_I: out std_logic;
signal Busy_O: in std_logic
) is
begin
nStrobe_I <= '1'; -- '1' -> is read
Data_IO <= (others => 'Z'); -- Data1
nAutoFd_I <= '0'; -- datStb
-- wait for 150 ns;
wait until (Busy_O = '1');
-- wait for 150 ns;
nAutoFd_I <= '1';
--wait for 40 ns;
wait until (Busy_O = '0');
-- wait for 40 ns;
Data_IO <= (others => 'Z'); -- Data0
nAutoFd_I <= '0'; -- datStb
-- wait for 150 ns;
wait until (Busy_O = '1');
-- wait for 150 ns;
out_runflag <= Data_IO(6);
nAutoFd_I <= '1';
--wait for 40 ns;
wait until (Busy_O = '0');
-- wait for 40 ns;
end procedure ReadData2;
begin
------------------------------------------------------------------------------------------------
-- Init
298,10 → 348,10
Data_IO <= (others => '0');
nAutoFd_I <= '1';
nInit_I <= '1';
reset_I <= '1';
reset_I <= '0';
wait for 700 ns; -- PLL delay
reset_I <= '0';
reset_I <= '1';
-- EPP Mode Negotiation
-- Standar timing and handshake
451,22 → 501,26
-- Test 6 - Trigger
-- daq freq = ctrl freq/2 (default), trigger channel 1, level 70 %, continuous, skipper = 3,
-- channels 1, buffer size = 150h, falling edge, full negative trigger offset
test_number <= 6;
-- test_number <= 6;
WriteData(X"01", X"0002", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- Channels_R
WriteData(X"02", X"0150", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- BuffSize_R
WriteData(X"03", X"02CD", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigLvl_R
WriteData(X"04", X"FF6A", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigOff_R -150
WriteData(X"00", B"00000_00011_1_1_1_1_1_1", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- RunConf_R
-- WriteData(X"01", X"0002", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- Channels_R
-- WriteData(X"02", X"0150", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- BuffSize_R
-- WriteData(X"03", X"02CD", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigLvl_R
-- WriteData(X"04", X"FF6A", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigOff_R -150
-- WriteData(X"00", B"00000_00011_1_1_1_1_1_1", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- RunConf_R
ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
i := 0;
while (i <= 200) loop
ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
i := i + 1;
end loop;
-- ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- i := 0;
-- while (i <= 200) loop
-- ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- i := i + 1;
-- end loop;
-- WriteData(X"01", X"0002", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
------------------------------------------------------------------------------------------------
-- Test 7 - One channel
-- daq freq = ctrl freq/2 (default), trigger channel 0, level 30 %, continuous, skipper = 5,
492,12 → 546,128
-- Test 8 - Test write while working
-- daq freq = ctrl freq/2 (default), trigger channel 1, level 30 %, continuous, skipper = 5,
-- channels 1, buffer size = 50
--
-- test_number <= 8;
--
-- WriteData(X"01", X"0002", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- Channels_R
-- WriteData(X"02", X"0150", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- BuffSize_R
-- WriteData(X"03", X"02CD", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigLvl_R
-- WriteData(X"04", X"FF6A", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigOff_R -150
-- WriteData(X"00", B"00000_00011_1_1_1_1_1_1", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- RunConf_R
--
-- wait for 800 ns;
-- WriteData(X"01", X"0002", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
--
-- ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- i := 0;
-- while (i <= 200) loop
-- ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- i := i + 1;
-- end loop;
-- ------------------------------------------------------------------------------------------------
-- Test 9 - Test read with full buffer
-- daq freq = ctrl freq/2 (default), w/o trigger, w/o skipper, channels 1 and 2,
-- buffer size = 50h, continuous
-- test_number <= 9;
--
-- WriteData(X"01", X"0003", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- Channels_R
-- WriteData(X"02", X"0050", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- BuffSize_R
-- WriteData(X"03", X"0000", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigLvl_R
-- WriteData(X"04", X"0000", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigOff_R
-- WriteData(X"00", X"0001", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- RunConf_R
--
-- wait for 5000 ns;
-- i := 0;
-- ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- while (i <= 25) loop
-- ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- i := i + 1;
-- end loop;
--
-- -- big buffer
-- WriteData(X"01", X"0003", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- Channels_R
-- WriteData(X"02", X"03E8", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- BuffSize_R
-- WriteData(X"03", X"0000", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigLvl_R
-- WriteData(X"04", X"0000", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigOff_R
-- WriteData(X"00", X"0001", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- RunConf_R
--
--
-- ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- while (runflag = '1') loop
-- ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- end loop;
--
 
 
------------------------------------------------------------------------------------------------
-- Test 10 - Test simple continuous
-- daq freq = ctrl freq/2 (default), trigger channel 1, level 70 %, continuous, skipper = 3,
-- channels 1, buffer size = 150h, falling edge, full negative trigger offset
test_number <= 10;
WriteData(X"01", X"0002", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- Channels_R
WriteData(X"02", X"0050", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- BuffSize_R
WriteData(X"03", X"02CD", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigLvl_R
WriteData(X"04", X"FF6A", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigOff_R -150
WriteData(X"00", X"FFC1", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- RunConf_R
--1111111111000011
--wait for 5000 ns;
wait for 100 ns;
test_number <= 11;
ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
while (runflag = '1') loop
ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
end loop;
-- ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- i := 0;
-- while (i <= 50) loop
-- ReadData2(runflag, Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- i := i + 1;
-- end loop;
--
--
--
-- test_number <= 12;
-- WriteData(X"01", X"0002", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- Channels_R
-- WriteData(X"02", X"0050", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- BuffSize_R
-- WriteData(X"03", X"01FF", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigLvl_R
-- WriteData(X"04", X"0000", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigOff_R -150
-- WriteData(X"00", X"FFC3", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- RunConf_R
-- --1111 1111 1100 0011
-- ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- i := 0;
-- while (i <= 150) loop
-- ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- i := i + 1;
-- end loop;
WriteData(X"01", X"0002", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
 
wait for 1000 ns;
--
-- -- reading an address
--
WriteData(X"09", X"0002", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
nStrobe_I <= '1'; -- '1' -> is read
Data_IO <= (others => 'Z'); -- Data0 -- Address
nSelectIn_I <= '0'; -- addStb
wait until Busy_O = '1';
wait for 30 ns; -- default
-- wait for 150 ns;
nSelectIn_I <= '1';
wait until Busy_O = '0';
wait for 30 ns;
wait for 100 ns;
tb_InitFlag <= false;
wait;
/hdl/ctrl/ctrl.vhd
24,7 → 24,7
 
--==================================================================================================
-- TO DO
 
 
--==================================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
173,7 → 173,7
--------------------------------------------------------------------------------------------------
-- Instances
U_OUTMGR0: ctrl_output_manager
U_CTRL_OUTMGR0: ctrl_output_manager
generic map(
MEM_ADD_WIDTH => 14 --: integer := 14
)
344,7 → 344,7
------------------------------------------------------------------------------------------------
-- Machine
P_sm_comb: process (present_state, reg_trigger_en, trigger_out_adr, memwr_out_adr,
memwr_in_ack_mem, outmgr_finish, continuous, ack_i_daq)
memwr_in_ack_mem, outmgr_finish, continuous, ack_i_daq,next_status1,trigger_act)
begin
-- signals from output manager are described in next process
case present_state is
361,13 → 361,20
trigger_en <= '-';
status(0) <= '1';
next_status1 <= not(next_status1); -- will be changed every buffer full read
-- next_status1: above
strobe_adc <= '0';
-- -- -- --
next_state <= ST_RUNNING;
-- if there is an error manager, influde an if for errors in parameters
if outmgr_finish = '0' then
next_state <= ST_RUNNING;
next_status1 <= not(status(1)); -- will be changed every buffer full read
else
next_state <= ST_INIT;
next_status1 <= status(1);
end if;
-- if there is an error manager, include "if" for errors in parameters
when ST_RUNNING =>
471,7 → 478,7
 
P_sm_clkd: process (RST_I_daq, stop, start, CLK_I_daq, next_state, write_in_adc)
P_sm_clkd: process (RST_I_daq, stop, start, CLK_I_daq, next_state, write_in_adc,next_status1)
begin
if RST_I_daq = '1' then
479,10 → 486,13
status(1) <= '0';
elsif stop = '1' then
present_state <= ST_IDLE;
status(1) <= '0';
elsif write_in_adc = '1' then
present_state <= ST_ADCWRITE_INIT;
status(1) <= next_status1;
elsif start = '1' and present_state /= ST_ADCWRITE and present_state /= ST_ADCWRITE_INIT then
present_state <= ST_INIT;
status(1) <= next_status1;
elsif CLK_I_daq'event and CLK_I_daq = '1' then
present_state <= next_state;
status(1) <= next_status1;
/hdl/ctrl/address_allocation.vhd
3,29 → 3,34
--| UNSL - Argentine
--|
--| File: ctrl_address_allocation.vhd
--| Version: 0.1
--| Version: 0.21
--| Tested in: Actel A3PE1500
--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
--|-------------------------------------------------------------------------------------------------
--| Description:
--| CONTROL - Address allocations
--| Registers and intercomunications.
--|
--|
--|-------------------------------------------------------------------------------------------------
--| File history:
--| 0.1 | jul-2009 | First testing
--| 0.2 | aug-2009 | New status flag
--| 0.21 | sep-2009 | Smarter stop signal
----------------------------------------------------------------------------------------------------
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
 
--| Wishbone Rev. B.3 compatible
----------------------------------------------------------------------------------------------------
 
 
 
--==================================================================================================
-- TO DO
 
-- [OK] Finish ADC conf write
 
--==================================================================================================
 
 
205,7 → 210,17
--------------------------------------------------------------------------------------------------
-- Stop signal
stop_O <= CYC_I_port and STB_I_port and WE_I_port;
-- It asserts when there is a write in the confing registers
P_stop: process (CLK_I, STB_I_port, WE_I_port, status_I, ADR_I_port)
begin
if CLK_I'event and CLK_I = '1' then
if status_I(0) = '0' then
stop_O <= '0';
elsif CYC_I_port = '1' and STB_I_port = '1' and WE_I_port = '1' and ADR_I_port(3) = '0' then
stop_O <= '1';
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------
-- DAT_I
/hdl/epp/eppwbn_16bit_test.vhd
128,6 → 128,7
 
 
s_to_mem_ADR_I_a <= (13 downto 8 => '0') & ADR_O_master;
SL_MEM2: dual_port_memory_wb port map(
-- Puerto A
RST_I_a => s_not_rst,
177,11 → 178,11
CYC_O => CYC_O_master,
STB_O => STB_O_master,
ACK_I => ACK_I_master,
WE_O => WE_O_master,
WE_O => WE_O_master
-- MONITORES
-- TEMPORAL
epp_mode_monitor => s_not_epp_mode
--epp_mode_monitor => s_not_epp_mode
);
 
/hdl/epp/eppwbn_16bit.vhd
111,8 → 111,8
U_EPPWBN_8TO16: eppwbn_width_extension
generic map(
TIME_OUT_VALUE => 255,
TIME_OUT_WIDTH => 8
TIME_OUT_VALUE => 1023,
TIME_OUT_WIDTH => 10
)
port map(
-- Master EPP to slave width exteneder
/hdl/epp/eppwbn_wbn_side.vhd
3,19 → 3,22
--| UNSL - Argentine
--|
--| File: eppwbn_wbn_side.vhd
--| Version: 0.2
--| Version: 0.5
--| Tested in: Actel APA300
--| Tested in: Actel A3PE1500
--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
--|-------------------------------------------------------------------------------------------------
--| Description:
--| EPP - Wishbone bridge.
--| This module is in the wishbone side (IEEE Std. 1284-2000).
--| EPP - Wishbone bridge.
--| This module is in the wishbone side (IEEE Std. 1284-2000).
--|-------------------------------------------------------------------------------------------------
--| File history:
--| 0.01 | nov-2008 | First release
--| 0.01 | nov-2008 | First release
--| 0.1 | jan-2009 | Sinc reset
--| 0.2 | feb-2009 | Some improvements
--| 0.5 | sep-2009 | New design, full sincronous
----------------------------------------------------------------------------------------------------
 
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
25,123 → 28,213
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
 
 
entity eppwbn_wbn_side is
port(
-- generic(
-- WAIT_DELAY : integer := 4 -- min value: 3
-- );
port(
inStrobe: in std_logic; -- HostClk/nWrite
iData: inout std_logic_vector (7 downto 0); -- AD8..1/AD8..1 (Data1..Data8)
iBusy: out std_logic; -- PtrBusy/PeriphAck/nWait
inAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
inSelectIn: in std_logic; -- 1284 Active/nAStrb
RST_I: in std_logic;
CLK_I: in std_logic;
DAT_I: in std_logic_vector (7 downto 0);
DAT_O: out std_logic_vector (7 downto 0);
ADR_O: out std_logic_vector (7 downto 0);
CYC_O: out std_logic;
STB_O: out std_logic;
ACK_I: in std_logic ;
WE_O: out std_logic;
 
-- al puerto epp
-- Nomenclatura IEEE Std. 1284-2000
-- Negotiation/ECP/EPP (Compatibiliy)
inStrobe: in std_logic; -- HostClk/nWrite
iData: inout std_logic_vector (7 downto 0); -- AD8..1/AD8..1 (Data1..Data8)
-- inAck: out std_logic; -- PtrClk/PeriphClk/Intr
iBusy: out std_logic; -- PtrBusy/PeriphAck/nWait
-- iPError: out std_logic; -- AckData/nAckReverse
-- iSel: out std_logic; -- XFlag (Select)
inAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
-- iPeriphLogicH: out std_logic; -- (Periph Logic High)
-- inInit: in std_logic; -- nReverseRequest
-- inFault: out std_logic; -- nDataAvail/nPeriphRequest
inSelectIn: in std_logic; -- 1284 Active/nAStrb
-- iHostLogicH: in std_logic; -- (Host Logic High)
-- i indica interna en el core y controlada por el bloque de control
-- a la interface wishbone
RST_I: in std_logic;
CLK_I: in std_logic;
DAT_I: in std_logic_vector (7 downto 0);
DAT_O: out std_logic_vector (7 downto 0);
ADR_O: out std_logic_vector (7 downto 0);
CYC_O: out std_logic;
STB_O: out std_logic;
ACK_I: in std_logic ;
WE_O: out std_logic;
rst_pp: in std_logic -- reset desde la interfaz del puerto paralelo
);
rst_pp: in std_logic -- reset from pp
);
end eppwbn_wbn_side;
 
architecture con_registro of eppwbn_wbn_side is
architecture bridge2 of eppwbn_wbn_side is
 
signal adr_ack,data_ack: std_logic;
signal adr_reg,data_reg: std_logic_vector (7 downto 0); -- registros internos temporales
signal pre_STB_O: std_logic; -- registro que maneja a STB_O
type StateType is (
ST_IDLE,
ST_ADDR,
ST_WRITING_D1,
ST_WRITING_D2,
ST_READING_D1,
ST_READING_D2
);
signal next_state, present_state: StateType;
 
signal nWrite: std_logic;
signal nWait: std_logic;
signal nDStrb: std_logic;
signal nAStrb: std_logic;
signal strb_hist: std_logic_vector(4 downto 0);
signal strb_ris: std_logic;
signal strb_fall: std_logic;
signal strb_wb: std_logic;
signal ack_pp: std_logic;
 
signal adr_reg, data_reg: std_logic_vector (7 downto 0); -- registros internos temporales
--signal waiting: std_logic_vector(WAIT_DELAY-1 downto 0);
begin
 
 
STB_O <= pre_STB_O ;
CYC_O <= pre_STB_O;
DAT_O <= data_reg; -- se utiliza el mismo registro para salida de datos
-- a wishbone, lectura y escritura de datos desde epp
-- Data R/W
data_strobing: process (inAutoFd, ACK_I, CLK_I, pre_STB_O, RST_I, rst_pp, data_ack,inStrobe,iData)
begin
 
data_reg <= (others => '0');
pre_STB_O <= '0';
data_ack <= '0';
elsif inAutoFd = '0' and data_ack = '0' and pre_STB_O = '0' then -- Data strobe
if (inStrobe = '0') then -- Escritura EPP
data_reg <= iData;
-- Equal
nWrite <= inStrobe;
nAStrb <= inSelectIn;
nDStrb <= inAutoFd;
iBusy <= nWait;
STB_O <= strb_wb;
CYC_O <= strb_wb;
ADR_O <= adr_reg;
DAT_O <= data_reg;
-- Thanks fpga4fun
P_strobes: process(nAStrb, nDStrb, CLK_I, strb_hist, RST_I, rst_pp)
begin
if CLK_I 'event and CLK_I = '1' then
if RST_I = '1' or rst_pp = '1' then
strb_hist <= (others => '1' );
else
strb_hist <= strb_hist(3 downto 0) & (nAStrb and nDStrb); -- only one is zero at a time
end if;
pre_STB_O <= '1';
 
data_ack <= '0';
 
 
elsif (CLK_I'event and CLK_I = '1') then
if RST_I = '1' then
end if;
end process;
strb_ris <= '1' when strb_hist(4 downto 1) = "0111" else '0';
strb_fall <= '1' when strb_hist(4 downto 1) = "0000" else '0';
P_next_st: process(strb_ris, strb_fall, ACK_I, nAStrb, nDStrb, nWrite, present_state)
begin
case present_state is
when ST_ADDR =>
strb_wb <= '0';
ack_pp <= '1';
WE_O <= '0';
-- >>> --
if strb_ris = '1' then
next_state <= ST_IDLE;
else
next_state <= present_state;
end if;
when ST_WRITING_D1 =>
strb_wb <= '0';
ack_pp <= '1';
WE_O <= '0';
-- >>> --
if strb_ris = '1' then
next_state <= ST_WRITING_D2;
else
next_state <= present_state;
end if;
when ST_WRITING_D2 =>
strb_wb <= '1';
ack_pp <= '0';
WE_O <= '1';
-- >>> --
if ACK_I = '1' then
next_state <= ST_IDLE;
else
next_state <= present_state;
end if;
when ST_READING_D1 =>
strb_wb <= '1';
ack_pp <= '0';
WE_O <= '0';
-- >>> --
if strb_ris = '1' then
next_state <= ST_IDLE;
elsif ACK_I = '1' then
next_state <= ST_READING_D2;
else
next_state <= present_state;
end if;
when ST_READING_D2 =>
strb_wb <= '0';
ack_pp <= '1';
WE_O <= '0';
-- >>> --
if strb_ris = '1' then
next_state <= ST_IDLE;
else
next_state <= present_state;
end if;
 
when others => -- ST_IDLE
strb_wb <= '0';
ack_pp <= '0';
WE_O <= '0';
-- >>> --
if strb_fall = '1' then
if nWrite = '0' and nDStrb = '0' then
next_state <= ST_WRITING_D1;
elsif nWrite = '1' and nDStrb = '0' then
next_state <= ST_READING_D1;
elsif nAStrb = '0' then
next_state <= ST_ADDR;
else
next_state <= present_state;
end if;
else
next_state <= present_state;
end if;
end case;
end process;
P_act_st: process(CLK_I, RST_I, rst_pp, next_state, iData, DAT_I, present_state, nWrite)
begin
if (CLK_I'event and CLK_I='1') then
if RST_I = '1' or rst_pp = '1' then
present_state <= ST_IDLE;
data_reg <= (others => '0');
pre_STB_O <= '0';
data_ack <= '0';
adr_reg <= (others => '0');
else
 
pre_STB_O <= '0';
data_ack <= '1';
if (inStrobe = '1') then -- Lectura EPP
data_reg <= DAT_I;
end if;
end if;
present_state <= next_state;
case present_state is
when ST_ADDR =>
--if next_state = ST_IDLE and nWrite = '0' then
if strb_hist(0) = '0' and nWrite = '0' then
adr_reg <= iData;
end if;
when ST_WRITING_D1 =>
--if next_state = ST_WRITING_D2 then
if strb_hist(0) = '0' then
data_reg <= iData;
end if;
when ST_READING_D1 =>
if next_state = ST_READING_D2 then
data_reg <= DAT_I;
end if;
when others =>
end case;
end if;
end if;
 
end process;
 
 
-- Adr R/W
 
adr_strobing: process (inSelectIn, RST_I, rst_pp,inStrobe,iData)
begin
if (RST_I = '1' or rst_pp = '1') then
adr_reg <= (others => '0');
elsif (inSelectIn'event and inSelectIn = '1') then -- Adr strobe
if inStrobe = '0' then
adr_reg <= iData;
end if;
end if;
end process;
ADR_O <= adr_reg;
-- Puerto bidireccional
iData <= data_reg when (inStrobe = '1' and data_ack = '1') else
adr_reg when (inStrobe = '1' and adr_ack = '1') else
(others => 'Z');
end con_registro;
end if;
end process;
nWait <= ack_pp;
iData <= data_reg when (nWrite = '1' and nDStrb = '0' ) else
adr_reg when (nWrite = '1' and nAStrb = '0' ) else
(others => 'Z');
-- P_delay: process(ack_pp, CLK_I, rst_pp, RST_I, waiting)
-- begin
-- if CLK_I'event and CLK_I = '1' then
-- if rst_pp = '1' or RST_I = '1' then
-- waiting <= (others => '0');
-- else
-- waiting <= waiting(WAIT_DELAY-2 downto 0) & ack_pp;
-- end if;
-- end if;
-- end process;
end architecture bridge2;
/hdl/epp/eppwbn_ctrl.vhd
87,10 → 87,12
begin
if (RST_I = '1' or (nInit = '0' and nSelectIn = '0')) then
ext_req_val <= (others => '0');
elsif (nStrobe = '0') and present_state = st_negotiation2 then
ext_req_val <= Data;
else
ext_req_val <= ext_req_val;
elsif nStrobe = '1' then
if present_state = st_negotiation2 then
ext_req_val <= Data;
end if;
-- else
-- ext_req_val <= ext_req_val;
end if;
end process P_data_store;
/hdl/epp/eppwbn_width_extension.vhd
1,9 → 1,11
----------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------100
--| Modular Oscilloscope
--| UNSL - Argentine
--|
--| Version: 0.01
--| Tested in: Actel APA300
--| Tested in: Actel A3PE1500
--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
--|-------------------------------------------------------------------------------------------------
--| Description:
--| EPP - Wishbone bridge.
12,7 → 14,7
--| File history:
--| 0.01 | mar-2009 | First release
----------------------------------------------------------------------------------------------------
 
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
21,6 → 23,8
----------------------------------------------------------------------------------------------------
 
 
 
 
-- COMO USAR:
-- Puente entre un bus de datos de 8 bit (esclavo) y otro de 16 bit (maestro). cada dos acciones del
-- lado de 8 bit realiza una en en lado de 16. Posee un timer configurable con el que vuelve al
38,8 → 42,8
 
entity eppwbn_width_extension is
generic (
TIME_OUT_VALUE: integer := 255;
TIME_OUT_WIDTH: integer := 8
TIME_OUT_VALUE: integer := 512;
TIME_OUT_WIDTH: integer := 9
);
port(
-- Slave signals
135,8 → 139,8
ACK_O_sl <= '0';
end if;
 
if ((CYC_I_sl = '1' and STB_I_sl = '1') and (WE_I_sl /= '1' or ACK_I_ma = '1'))
or ((CYC_I_sl = '1' and STB_I_sl = '1') and (ADR_I_sl /= adr_reg))
if ( (CYC_I_sl = '1' and STB_I_sl = '1' ) and (WE_I_sl /= '1' or ACK_I_ma = '1' ) )
or ( (CYC_I_sl = '1' and STB_I_sl = '1' ) and (ADR_I_sl /= adr_reg) )
or (timer >= time_out_ref) then
next_state <= st_low;
else
/hdl/epp/eppwbn_pkg.vhd
286,34 → 286,6
port(POWERDOWN, CLKA : in std_logic; LOCK, GLA : out
std_logic) ;
end component A3PE_pll;
 
-- component dual_port_memory_wb is
-- port(
-- -- Puerto A (Higer prioriry)
-- RST_I_a: in std_logic;
-- CLK_I_a: in std_logic;
-- DAT_I_a: in std_logic_vector (15 downto 0);
-- DAT_O_a: out std_logic_vector (15 downto 0);
-- ADR_I_a: in std_logic_vector (13 downto 0);
-- CYC_I_a: in std_logic;
-- STB_I_a: in std_logic;
-- ACK_O_a: out std_logic ;
-- WE_I_a: in std_logic;
-- -- Puerto B (Lower prioriry)
-- RST_I_b: in std_logic;
-- CLK_I_b: in std_logic;
-- DAT_I_b: in std_logic_vector (15 downto 0);
-- DAT_O_b: out std_logic_vector (15 downto 0);
-- ADR_I_b: in std_logic_vector (13 downto 0);
-- CYC_I_b: in std_logic;
-- STB_I_b: in std_logic;
-- ACK_O_b: out std_logic ;
-- WE_I_b: in std_logic
-- );
-- end component dual_port_memory_wb;
end package eppwbn_pkg;
/hdl/daq/daq.vhd
50,7 → 50,8
 
entity daq is
generic (
DEFALT_CONFIG : std_logic_vector := "0000100000000000"
DEFALT_CONFIG : std_logic_vector := "0000001000000000"
-- 5432109876543210
-- bits 8 a 0 clk_pre_scaler
-- bits 9 clk_pre_scaler_ena
-- bit 10 adc sleep
67,7 → 68,7
adc_sel_O: out std_logic;
adc_clk_O: out std_logic;
adc_sleep_O: out std_logic;
adc_chip_sel_O: out std_logic;
adc_chip_sel_O: out std_logic; -- '1' disable, '0' select
 
-- Interno
/hdl/memory/A3PE1500/dual_port_memory.vhd
20,12 → 20,12
-- Copyright 1989-2009 Actel Corporation
 
 
 
-- · Parámetros
---- Generales
-- Reset: Not inverted
-- Double clock
-- High Speed
---- Para ambos puertos
---- Both ports
-- Depth: 15360
-- Width: 16
-- BLKx: Not Inverted
34,12 → 34,8
-- DOUT type: DINA0
 
 
-- Version: 8.5 8.5.0.34
 
 
 
 
 
 
library ieee;
use ieee.std_logic_1164.all;
library proasic3e;
63,7 → 59,7
 
RESET: in std_logic -- '1' Reset
) ;
end dual_port_memory;
 
 

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