OpenCores
URL https://opencores.org/ocsvn/modular_oscilloscope/modular_oscilloscope/trunk

Subversion Repositories modular_oscilloscope

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /modular_oscilloscope/trunk
    from Rev 60 to Rev 61
    ↔ Reverse comparison
  •

Rev 60 → Rev 61

/design/RVI/modular_oscilloscope/test_modular_oscilloscope.prj
0,0 → 1,600
KEY LIBERO "8.5"
KEY CAPTURE "8.5.0.34"
KEY DEFAULT_IMPORT_LOC "<project>\..\..\..\hdl\memory\A3PE1500"
KEY DEFAULT_OPEN_LOC ""
KEY HDLTechnology "VHDL"
KEY VendorTechnology_Family "ProASIC3E"
KEY VendorTechnology_Die "IT10X10M3"
KEY VendorTechnology_Package "fg484"
KEY ProjectLocation "D:\Facu\TFuni2\test_modular_oscilloscope"
KEY SimulationType "VHDL"
KEY Vendor "Actel"
KEY ActiveRoot "modular_oscilloscope::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
VALUE="Impl2",NUM=2
VALUE="Impl3",NUM=3
CURREV=3
ENDLIST
LIST FileManager
VALUE "<project>\..\..\..\hdl\ctrl\address_allocation.vhd,hdl"
STATE="utd"
TIME="1256306294"
SIZE="12072"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\..\..\..\hdl\ctrl\channel_selector.vhd,hdl"
STATE="utd"
TIME="1254348574"
SIZE="6229"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\..\..\..\hdl\ctrl\ctrl.vhd,hdl"
STATE="utd"
TIME="1256305960"
SIZE="18618"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\..\..\..\hdl\ctrl\ctrl_pkg.vhd,hdl"
STATE="utd"
TIME="1254348574"
SIZE="12752"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\..\..\..\hdl\ctrl\data_skipper.vhd,hdl"
STATE="utd"
TIME="1254348574"
SIZE="3845"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\..\..\..\hdl\ctrl\generic_counter.vhd,hdl"
STATE="utd"
TIME="1254348574"
SIZE="18970"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\..\..\..\hdl\ctrl\generic_decoder.vhd,hdl"
STATE="utd"
TIME="1254348576"
SIZE="11217"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\..\..\..\hdl\ctrl\memory_writer.vhd,hdl"
STATE="utd"
TIME="1254348576"
SIZE="7600"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\..\..\..\hdl\ctrl\output_manager.vhd,hdl"
STATE="utd"
TIME="1254348514"
SIZE="7275"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\..\..\..\hdl\ctrl\trigger_manager.vhd,hdl"
STATE="utd"
TIME="1256305812"
SIZE="8010"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\..\..\..\hdl\daq\daq.vhd,hdl"
STATE="utd"
TIME="1255647766"
SIZE="9754"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\..\..\..\hdl\daq\daq_pkg.vhd,hdl"
STATE="utd"
TIME="1250627614"
SIZE="2618"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\..\..\..\hdl\epp\eppwbn.vhd,hdl"
STATE="utd"
TIME="1254348458"
SIZE="4506"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\..\..\..\hdl\epp\eppwbn_16bit.vhd,hdl"
STATE="utd"
TIME="1256302788"
SIZE="4070"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\..\..\..\hdl\epp\eppwbn_ctrl.vhd,hdl"
STATE="utd"
TIME="1252974110"
SIZE="7688"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\..\..\..\hdl\epp\eppwbn_epp_side.vhd,hdl"
STATE="utd"
TIME="1244331728"
SIZE="4294"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\..\..\..\hdl\epp\eppwbn_pkg.vhd,hdl"
STATE="utd"
TIME="1254348436"
SIZE="10399"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\..\..\..\hdl\epp\eppwbn_wbn_side.vhd,hdl"
STATE="utd"
TIME="1256308820"
SIZE="8125"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\..\..\..\hdl\epp\eppwbn_width_extension.vhd,hdl"
STATE="utd"
TIME="1256258670"
SIZE="5941"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\..\..\..\hdl\memory\A3PE1500\dual_port_memory.vhd,hdl"
STATE="utd"
TIME="1251749986"
SIZE="199398"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\..\..\..\hdl\memory\dual_port_memory_wb.vhd,hdl"
STATE="utd"
TIME="1254348492"
SIZE="5285"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\..\..\..\hdl\memory\memory_pkg.vhd,hdl"
STATE="utd"
TIME="1254348468"
SIZE="2212"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\..\..\..\hdl\modular_oscilloscope.vhd,hdl"
STATE="utd"
TIME="1256306516"
SIZE="10072"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\..\..\..\hdl\tbench\modullar_oscilloscope_tbench_text.vhd,tb_hdl"
STATE="utd"
TIME="1256243688"
SIZE="30811"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\constraint\modular_oscilloscope_test.pdc,pdc"
STATE="utd"
TIME="1254958644"
SIZE="3987"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope-05.pdb,pdb"
STATE="utd"
TIME="1254953876"
SIZE="289280"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope.adb,adb"
STATE="utd"
TIME="1256259156"
SIZE="3326464"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope.pdb,pdb"
STATE="ood"
TIME="1253061552"
SIZE="287232"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_06.pdb,pdb"
STATE="utd"
TIME="1255124478"
SIZE="294400"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_08.pdb,pdb"
STATE="utd"
TIME="1256246254"
SIZE="290304"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_09.pdb,pdb"
STATE="utd"
TIME="1256254802"
SIZE="294400"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_10.pdb,pdb"
STATE="utd"
TIME="1256258516"
SIZE="287232"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_11.pdb,pdb"
STATE="utd"
TIME="1256304832"
SIZE="16384"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_12.pdb,pdb"
STATE="utd"
TIME="1256308072"
SIZE="16384"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_13.pdb,pdb"
STATE="utd"
TIME="1256310384"
SIZE="16384"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1254173240"
SIZE="1730"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp_10\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1254955580"
SIZE="1734"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp_11\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1255126674"
SIZE="1734"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp_12\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1255729298"
SIZE="1734"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp_13\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1255988894"
SIZE="1734"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp_14\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1255990810"
SIZE="1540"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp_15\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1256164540"
SIZE="1734"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp_16\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1256228322"
SIZE="1734"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp_17\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1256248220"
SIZE="1734"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp_18\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1256254626"
SIZE="1734"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp_19\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1256257352"
SIZE="1734"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp_1\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1254173240"
SIZE="1744"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp_20\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1256258972"
SIZE="1734"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp_21\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1256305190"
SIZE="1540"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp_22\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1256308520"
SIZE="1540"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp_23\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1256310490"
SIZE="1540"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp_2\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1254173240"
SIZE="1328"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp_3\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1254174984"
SIZE="1738"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp_4\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1254182278"
SIZE="1754"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp_5\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1254353302"
SIZE="1754"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp_6\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1254436920"
SIZE="1738"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp_7\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1254438552"
SIZE="1538"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp_8\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1254438624"
SIZE="1538"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_1_fp_9\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1254438812"
SIZE="1738"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_4fifo_01.pdb,pdb"
STATE="utd"
TIME="1253201184"
SIZE="294400"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_ba.sdf,ba_sdf"
STATE="ood"
TIME="1252707118"
SIZE="1401674"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_ba.vhd,ba_hdl"
STATE="ood"
TIME="1252707118"
SIZE="705896"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_fp\modular_oscilloscope.pro,pro"
STATE="utd"
TIME="1254173240"
SIZE="1726"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_new01.pdb,pdb"
STATE="utd"
TIME="1253654446"
SIZE="296448"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_new02_monitor.pdb,pdb"
STATE="utd"
TIME="1254176518"
SIZE="284160"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_new03_CtrlMon.pdb,pdb"
STATE="utd"
TIME="1254351276"
SIZE="290816"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_new04.pdb,pdb"
STATE="utd"
TIME="1254438482"
SIZE="286208"
ENDFILE
VALUE "<project>\designer\impl3\modular_oscilloscope_new07.pdb,pdb"
STATE="utd"
TIME="1255725328"
SIZE="290304"
ENDFILE
VALUE "<project>\simulation\run.do,do"
STATE="utd"
TIME="1256243546"
SIZE="3026"
ENDFILE
VALUE "<project>\smartgen\A3PE_pll_2clk\A3PE_pll_2clk.cxf,actgen_cxf"
STATE="utd"
TIME="1253050176"
SIZE="1637"
ENDFILE
VALUE "<project>\smartgen\A3PE_pll_2clk\A3PE_pll_2clk.gen,gen"
STATE="utd"
TIME="1253050172"
SIZE="628"
PARENT="<project>\smartgen\A3PE_pll_2clk\A3PE_pll_2clk.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\A3PE_pll_2clk\A3PE_pll_2clk.log,log"
STATE="utd"
TIME="1253050176"
SIZE="2875"
PARENT="<project>\smartgen\A3PE_pll_2clk\A3PE_pll_2clk.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\A3PE_pll_2clk\A3PE_pll_2clk.vhd,hdl"
STATE="utd"
TIME="1253050176"
SIZE="4056"
PARENT="<project>\smartgen\A3PE_pll_2clk\A3PE_pll_2clk.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\synthesis\modular_oscilloscope.edn,syn_edn"
STATE="utd"
TIME="1256259070"
SIZE="1463337"
ENDFILE
VALUE "<project>\synthesis\modular_oscilloscope.vhd,syn_hdl"
STATE="ood"
TIME="1252720064"
SIZE="721989"
ENDFILE
VALUE "<project>\synthesis\modular_oscilloscope_sdc.sdc,syn_sdc"
STATE="utd"
TIME="1256259070"
SIZE="310"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "modular_oscilloscope::work"
FILE "<project>\..\..\..\hdl\modular_oscilloscope.vhd,hdl"
LIST AssociatedStimulus
VALUE "<project>\..\..\..\hdl\tbench\modullar_oscilloscope_tbench_text.vhd,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
LiberoState=Post_Synthesis
ideSTIMULUS=StateSuccess
ideSYNTHESIS(<project>\synthesis\modular_oscilloscope.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
LiberoState=Post_Synthesis
ideSTIMULUS=StateSuccess
ideSYNTHESIS(<project>\synthesis\modular_oscilloscope.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl3
LiberoState=Post_Layout
ideSTIMULUS=StateSuccess
ideSYNTHESIS(<project>\synthesis\modular_oscilloscope.edn,syn_edn)=StateSuccess
ideDESIGNER(<project>\designer\impl3\modular_oscilloscope.adb,adb)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
LIST modular_oscilloscope
VALUE "<project>\..\..\..\hdl\tbench\modullar_oscilloscope_tbench_text.vhd,tb_hdl"
ENDLIST
ENDLIST
LIST Other_Association
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=-all
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DumpVCD=false
VCDFileName=power.vcd
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=C:/Actel/LIBERO~1.5/Designer/lib/modelsim/precompiled/vhdl/proasic3e
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
AutoCheckConstraints=TRUE
UpdateViewDrawIni=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
GenerateHDLFromSchematic=TRUE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
NAME="Synplify Pro AE"
FUNCTION="Synthesis"
TOOL="Synplify"
LOCATION="C:\Actel\Libero_v8.5\Synplify\synplify_96A\bin\synplify_pro.exe"
PARAM=""
BATCH=0
EndProfile
NAME="ModelSim AE"
FUNCTION="Simulation"
TOOL="ModelSim"
LOCATION="C:\Actel\Libero_v8.5\Model\win32acoem\modelsim.exe"
PARAM=""
BATCH=0
EndProfile
NAME="WFL"
FUNCTION="Stimulus"
TOOL="WFL"
LOCATION="C:\Actel\Libero_v8.5\WFL\bin\syncad.exe"
PARAM="-pwflite"
BATCH=0
EndProfile
NAME="FlashPro"
FUNCTION="Program"
TOOL="FlashPro"
LOCATION="C:\Actel\Libero_v8.5\FlashPro\bin\FlashPro.exe"
PARAM=""
BATCH=0
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "modular_oscilloscope::work"
LIST Impl1
LiberoState=Post_Synthesis
ideSTIMULUS=StateSuccess
ideSYNTHESIS(<project>\synthesis\modular_oscilloscope.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
LiberoState=Post_Synthesis
ideSTIMULUS=StateSuccess
ideSYNTHESIS(<project>\synthesis\modular_oscilloscope.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl3
LiberoState=Post_Layout
ideSTIMULUS=StateSuccess
ideSYNTHESIS(<project>\synthesis\modular_oscilloscope.edn,syn_edn)=StateSuccess
ideDESIGNER(<project>\designer\impl3\modular_oscilloscope.adb,adb)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
DESIGNFLOW:
ACTIVE_VIEW:0
ENDLIST
design/RVI/modular_oscilloscope/test_modular_oscilloscope.prj Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.