OpenCores

/design/RVI/modular_oscilloscope/modular_oscilloscope.prj File deleted

/design/RVI/modular_oscilloscope/smartgen/A3PE_pll_2clk_work.ixf

0,0 → 1,?rev2len?

design/RVI/modular_oscilloscope/smartgen/A3PE_pll_2clk_work.ixf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: design/RVI/modular_oscilloscope/smartgen/smartgen.aws =================================================================== --- design/RVI/modular_oscilloscope/smartgen/smartgen.aws (nonexistent) +++ design/RVI/modular_oscilloscope/smartgen/smartgen.aws (revision 62) @@ -0,0 +1 @@ +smartgenVHDLVHDL \ No newline at end of file

design/RVI/modular_oscilloscope/smartgen/smartgen.aws Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: design/RVI/modular_oscilloscope/constraint/modular_oscilloscope_test~.pdc =================================================================== --- design/RVI/modular_oscilloscope/constraint/modular_oscilloscope_test~.pdc (nonexistent) +++ design/RVI/modular_oscilloscope/constraint/modular_oscilloscope_test~.pdc (revision 62) @@ -0,0 +1,99 @@ +########################################## +# # +# Constrain for MODULAR OCSILLOSCOPE # +# FPGA PROASIC3E 1500 # +# # +########################################## + +# Setted for modular_oscilloscope.vhd + +########################################## +# PARALLEL PORT signals in RVI board # +########################################## + +set_io Data_IO\[0\] -pinname V13 -fixed yes +set_io Data_IO\[1\] -pinname T13 -fixed yes +set_io Data_IO\[2\] -pinname W14 -fixed yes +set_io Data_IO\[3\] -pinname U14 -fixed yes +set_io Data_IO\[4\] -pinname T14 -fixed yes +set_io Data_IO\[5\] -pinname AB15 -fixed yes +set_io Data_IO\[6\] -pinname W15 -fixed yes +set_io Data_IO\[7\] -pinname AB16 -fixed yes +set_io PError_O -pinname AB17 -fixed yes +# set_io PeriphLogicH_O -pinname AB12 -fixed yes +set_io Sel_O -pinname AA17 -fixed yes +set_io busy_O -pinname W16 -fixed yes +set_io nAck_O -pinname AA16 -fixed yes +set_io nAutoFd_I -pinname AB14 -fixed yes +# Previous: set_io nAutoFd -pinname W13 -fixed yes +set_io nFault_O -pinname U13 -fixed yes +set_io nInit_I -pinname W13 -fixed yes +# Previous: set_io nInit -pinname AB14 -fixed yes +set_io nSelectIn_I -pinname AA13 -fixed yes +# Previous: set_io nSelectIn -pinname V14 -fixed yes +set_io nStrobe_I -pinname V14 -fixed yes +# Previous: set_io nStrobe -pinname AA13 -fixed yes + + + +########################################## +# BUTTONS # +########################################## +# Label on board: PB3 +set_io reset_I -pinname N19 -fixed yes + +########################################## +# CLK # +########################################## +set_io pll_clk_I -pinname T9 -fixed yes + + +########################################## +# LEDS # +########################################## +# Label on board: U15 (Digit 0) +# a +#set_io data_monitor\[0\] -pinname AB4 -fixed yes +# b +#set_io data_monitor\[1\] -pinname AA4 -fixed yes +# g +#set_io data_monitor\[2\] -pinname AA6 -fixed yes +# f +#set_io data_monitor\[3\] -pinname AB6 -fixed yes + +# d +#set_io nSelectIn_monitor -pinname AB5 -fixed yes +# c +#set_io nAutoFd_monitor -pinname Y4 -fixed yes +# e +#set_io nStrobe_monitor -pinname AA5 -fixed yes +# cat +#set_io display_cat -pinname AB7 -fixed yes +# Label on board: D10 +#set_io epp_mode_monitor\[0\] -pinname L20 -fixed yes +# Label on board: D11 +#set_io epp_mode_monitor\[1\] -pinname L16 -fixed yes +# Label on board: PB5 +#set_io select_nibble -pinname M15 -fixed yes + +########################################## +# ADC # +########################################## +set_io adc_data_I\[0\] -pinname N7 -fixed yes +set_io adc_data_I\[1\] -pinname N4 -fixed yes +set_io adc_data_I\[2\] -pinname P3 -fixed yes +set_io adc_data_I\[3\] -pinname P2 -fixed yes +set_io adc_data_I\[4\] -pinname N2 -fixed yes +set_io adc_data_I\[5\] -pinname P6 -fixed yes +set_io adc_data_I\[6\] -pinname P7 -fixed yes +set_io adc_data_I\[7\] -pinname R6 -fixed yes +set_io adc_data_I\[8\] -pinname R5 -fixed yes +set_io adc_data_I\[9\] -pinname R2 -fixed yes +set_io adc_sel_O -pinname T2 -fixed yes +set_io adc_clk_O -pinname T4 -fixed yes +set_io adc_sleep_O -pinname T5 -fixed yes +set_io adc_chip_sel_O -pinname N6 -fixed yes + + + +

design/RVI/modular_oscilloscope/constraint/modular_oscilloscope_test~.pdc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: design/RVI/modular_oscilloscope/constraint/modular_oscilloscope_test.pdc =================================================================== --- design/RVI/modular_oscilloscope/constraint/modular_oscilloscope_test.pdc (nonexistent) +++ design/RVI/modular_oscilloscope/constraint/modular_oscilloscope_test.pdc (revision 62) @@ -0,0 +1,106 @@ +########################################## +# # +# Constrain for MODULAR OCSILLOSCOPE # +# FPGA PROASIC3E 1500 # +# # +########################################## + +# Setted for modular_oscilloscope.vhd + +########################################## +# PARALLEL PORT signals in RVI board # +########################################## + +set_io Data_IO\[0\] -pinname V13 -fixed yes +set_io Data_IO\[1\] -pinname T13 -fixed yes +set_io Data_IO\[2\] -pinname W14 -fixed yes +set_io Data_IO\[3\] -pinname U14 -fixed yes +set_io Data_IO\[4\] -pinname T14 -fixed yes +set_io Data_IO\[5\] -pinname AB15 -fixed yes +set_io Data_IO\[6\] -pinname W15 -fixed yes +set_io Data_IO\[7\] -pinname AB16 -fixed yes +set_io PError_O -pinname AB17 -fixed yes +# set_io PeriphLogicH_O -pinname AB12 -fixed yes +set_io Sel_O -pinname AA17 -fixed yes +set_io busy_O -pinname W16 -fixed yes +set_io nAck_O -pinname AA16 -fixed yes +set_io nAutoFd_I -pinname AB14 -fixed yes +# Previous: set_io nAutoFd -pinname W13 -fixed yes +set_io nFault_O -pinname U13 -fixed yes +set_io nInit_I -pinname W13 -fixed yes +# Previous: set_io nInit -pinname AB14 -fixed yes +set_io nSelectIn_I -pinname AA13 -fixed yes +# Previous: set_io nSelectIn -pinname V14 -fixed yes +set_io nStrobe_I -pinname V14 -fixed yes +# Previous: set_io nStrobe -pinname AA13 -fixed yes + + + +########################################## +# BUTTONS # +########################################## +# Label on board: PB3 +set_io reset_I -pinname N19 -fixed yes + +########################################## +# CLK # +########################################## +set_io pll_clk_I -pinname T9 -fixed yes + + +########################################## +# LEDS # +########################################## +# Label on board: U15 (Digit 0) +# a +#set_io data_monitor\[0\] -pinname AB4 -fixed yes +# b +#set_io data_monitor\[1\] -pinname AA4 -fixed yes +# g +#set_io data_monitor\[2\] -pinname AA6 -fixed yes +# f +#set_io data_monitor\[3\] -pinname AB6 -fixed yes + +# d +#set_io nSelectIn_monitor -pinname AB5 -fixed yes +# c +#set_io nAutoFd_monitor -pinname Y4 -fixed yes +# e +#set_io nStrobe_monitor -pinname AA5 -fixed yes +# cat +#set_io display_cat -pinname AB7 -fixed yes + +# Label on board: D10 +#set_io epp_mode_monitor\[0\] -pinname L20 -fixed yes +set_io status_monitor_O\[3\] -pinname L20 -fixed yes +# Label on board: D11 +#set_io epp_mode_monitor\[1\] -pinname L16 -fixed yes +set_io status_monitor_O\[2\] -pinname L16 -fixed yes +# Label on board: D12 +set_io status_monitor_O\[1\] -pinname K19 -fixed yes +# Label on board: D13 +set_io status_monitor_O\[0\] -pinname J16 -fixed yes + +# Label on board: PB5 +set_io button_PB5_I -pinname M15 -fixed yes + +########################################## +# ADC # +########################################## +set_io adc_data_I\[0\] -pinname N7 -fixed yes +set_io adc_data_I\[1\] -pinname N4 -fixed yes +set_io adc_data_I\[2\] -pinname P3 -fixed yes +set_io adc_data_I\[3\] -pinname P2 -fixed yes +set_io adc_data_I\[4\] -pinname N2 -fixed yes +set_io adc_data_I\[5\] -pinname P6 -fixed yes +set_io adc_data_I\[6\] -pinname P7 -fixed yes +set_io adc_data_I\[7\] -pinname R6 -fixed yes +set_io adc_data_I\[8\] -pinname R5 -fixed yes +set_io adc_data_I\[9\] -pinname R2 -fixed yes +set_io adc_sel_O -pinname T2 -fixed yes +set_io adc_clk_O -pinname T4 -fixed yes +set_io adc_sleep_O -pinname T5 -fixed yes +set_io adc_chip_sel_O -pinname N6 -fixed yes + + +

design/RVI/modular_oscilloscope/constraint/modular_oscilloscope_test.pdc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: design/RVI/modular_oscilloscope/simulation/modelsim.ini.sav =================================================================== --- design/RVI/modular_oscilloscope/simulation/modelsim.ini.sav (nonexistent) +++ design/RVI/modular_oscilloscope/simulation/modelsim.ini.sav (revision 62) @@ -0,0 +1,82 @@ +[Library] +others = $MODEL_TECH/../modelsim.ini +proasic3e = C:/Actel/Libero_v8.5/Designer/lib/modelsim/precompiled/vhdl/proasic3e + + + + + +postsynth = postsynth +presynth = presynth + + + + + + + + + + + + + + + + +postlayout = ../designer/impl3/simulation/postlayout + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +syncad_vhdl_lib = C:\Actel\Libero_v8.5\Designer/lib/actel/syncad_vhdl_lib + +[vcom] +VHDL93 = 1 + +[vsim] +IterationLimit = 5000

design/RVI/modular_oscilloscope/simulation/modelsim.ini.sav Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: design/RVI/modular_oscilloscope/simulation/run.do =================================================================== --- design/RVI/modular_oscilloscope/simulation/run.do (nonexistent) +++ design/RVI/modular_oscilloscope/simulation/run.do (revision 62) @@ -0,0 +1,40 @@ +quietly set ACTELLIBNAME proasic3e +quietly set PROJECT_DIR "D:/Facu/TFuni2/test_modular_oscilloscope" + +if {[file exists presynth/_info]} { + echo "INFO: Simulation library presynth already exists" +} else { + vlib presynth +} +vmap presynth presynth +vmap proasic3e "C:/Actel/Libero_v8.5/Designer/lib/modelsim/precompiled/vhdl/proasic3e" + +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/daq/daq.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/memory/A3PE1500/dual_port_memory.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/memory/dual_port_memory_wb.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/smartgen/A3PE_pll_2clk/A3PE_pll_2clk.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/epp/eppwbn_ctrl.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/epp/eppwbn_epp_side.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/epp/eppwbn_wbn_side.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/epp/eppwbn_pkg.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/epp/eppwbn.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/epp/eppwbn_width_extension.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/epp/eppwbn_16bit.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/ctrl/output_manager.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/ctrl/generic_counter.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/ctrl/ctrl_pkg.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/ctrl/memory_writer.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/ctrl/generic_decoder.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/ctrl/data_skipper.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/ctrl/channel_selector.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/ctrl/trigger_manager.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/ctrl/address_allocation.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/ctrl/ctrl.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/daq/daq_pkg.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/memory/memory_pkg.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/modular_oscilloscope.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../modular_oscilloscope/hdl/tbench/modullar_oscilloscope_tbench_text.vhd" + +vsim -L proasic3e -L presynth -t 1ps presynth.testbench +add wave /testbench/* +run -all

design/RVI/modular_oscilloscope/simulation/run.do Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: design/RVI/modular_oscilloscope/simulation/modelsim.ini =================================================================== --- design/RVI/modular_oscilloscope/simulation/modelsim.ini (nonexistent) +++ design/RVI/modular_oscilloscope/simulation/modelsim.ini (revision 62) @@ -0,0 +1,83 @@ +[Library] +others = $MODEL_TECH/../modelsim.ini +proasic3e = C:/Actel/Libero_v8.5/Designer/lib/modelsim/precompiled/vhdl/proasic3e + + + + + +postsynth = postsynth +presynth = presynth + + + + + + + + + + + + + + + + +postlayout = ../designer/impl3/simulation/postlayout + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +syncad_vhdl_lib = C:\Actel\Libero_v8.5\Designer/lib/actel/syncad_vhdl_lib + +[vcom] +VHDL93 = 1 + +[vsim] +IterationLimit = 5000

design/RVI/modular_oscilloscope/simulation/modelsim.ini Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: design/RVI/modular_oscilloscope/simulation/modelsim.log =================================================================== --- design/RVI/modular_oscilloscope/simulation/modelsim.log (nonexistent) +++ design/RVI/modular_oscilloscope/simulation/modelsim.log (revision 62) @@ -0,0 +1,899 @@ +# Reading C:/Actel/Libero_v8.5/Model/tcl/vsim/pref.tcl +# do run.do +# INFO: Simulation library presynth already exists +# Modifying modelsim.ini +# Modifying modelsim.ini +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package std_logic_arith +# -- Loading package std_logic_unsigned +# -- Loading package numeric_std +# -- Compiling entity daq +# -- Compiling architecture archdaq2 of daq +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Compiling entity dual_port_memory +# -- Compiling architecture def_arch of dual_port_memory +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Compiling entity dual_port_memory_wb +# -- Compiling architecture arch01 of dual_port_memory_wb +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Compiling entity a3pe_pll_2clk +# -- Compiling architecture def_arch of a3pe_pll_2clk +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Compiling entity eppwbn_ctrl +# -- Compiling architecture state_machines of eppwbn_ctrl +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Compiling entity eppwbn_epp_side +# -- Compiling architecture multiplexor of eppwbn_epp_side +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package numeric_std +# -- Loading package std_logic_arith +# -- Loading package std_logic_unsigned +# -- Compiling entity eppwbn_wbn_side +# -- Compiling architecture bridge2 of eppwbn_wbn_side +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Compiling package eppwbn_pkg +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package eppwbn_pkg +# -- Compiling entity eppwbn +# -- Compiling architecture structural of eppwbn +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package std_logic_arith +# -- Loading package std_logic_unsigned +# -- Loading package numeric_std +# -- Loading package eppwbn_pkg +# -- Compiling entity eppwbn_width_extension +# -- Compiling architecture arch_0 of eppwbn_width_extension +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package eppwbn_pkg +# -- Compiling entity eppwbn_16bit +# -- Compiling architecture structural of eppwbn_16bit +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package std_logic_arith +# -- Loading package std_logic_unsigned +# -- Loading package numeric_std +# -- Compiling entity ctrl_output_manager +# -- Compiling architecture arch22 of ctrl_output_manager +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package std_logic_arith +# -- Loading package std_logic_unsigned +# -- Loading package numeric_std +# -- Compiling entity generic_counter +# -- Compiling architecture arch01 of generic_counter +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package math_real +# -- Compiling package ctrl_pkg +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package std_logic_arith +# -- Loading package std_logic_unsigned +# -- Loading package numeric_std +# -- Loading package math_real +# -- Loading package ctrl_pkg +# -- Compiling entity ctrl_memory_writer +# -- Compiling architecture arch12 of ctrl_memory_writer +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package numeric_std +# -- Loading package math_real +# -- Compiling entity generic_decoder +# -- Compiling architecture beh of generic_decoder +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package numeric_std +# -- Loading package math_real +# -- Loading package ctrl_pkg +# -- Compiling entity ctrl_data_skipper +# -- Compiling architecture arch10 of ctrl_data_skipper +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package numeric_std +# -- Loading package math_real +# -- Compiling entity ctrl_channel_selector +# -- Compiling architecture arch01 of ctrl_channel_selector +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package numeric_std +# -- Compiling entity ctrl_trigger_manager +# -- Compiling architecture arch01_trigger of ctrl_trigger_manager +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package std_logic_arith +# -- Loading package std_logic_unsigned +# -- Compiling entity ctrl_address_allocation +# -- Compiling architecture arch01 of ctrl_address_allocation +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package std_logic_arith +# -- Loading package std_logic_unsigned +# -- Loading package math_real +# -- Loading package ctrl_pkg +# -- Compiling entity ctrl +# -- Compiling architecture wsm of ctrl +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Compiling package daq_pkg +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package math_real +# -- Compiling package memory_pkg +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package std_logic_arith +# -- Loading package std_logic_unsigned +# -- Loading package math_real +# -- Loading package ctrl_pkg +# -- Loading package daq_pkg +# -- Loading package memory_pkg +# -- Loading package eppwbn_pkg +# -- Compiling entity modular_oscilloscope +# -- Compiling architecture struc1 of modular_oscilloscope +# -- Loading entity a3pe_pll_2clk +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package math_real +# -- Compiling entity tb_simple_clock +# -- Compiling architecture beh of tb_simple_clock +# -- Loading package std_logic_arith +# -- Loading package std_logic_unsigned +# -- Compiling entity virtual_adc +# -- Compiling architecture beh of virtual_adc +# -- Loading package ctrl_pkg +# -- Loading package daq_pkg +# -- Loading package memory_pkg +# -- Loading package eppwbn_pkg +# -- Compiling entity stimulus +# -- Compiling architecture stimulator of stimulus +# -- Loading entity tb_simple_clock +# -- Loading entity virtual_adc +# -- Compiling entity testbench +# -- Compiling architecture tbgeneratedcode of testbench +# -- Loading entity stimulus +# -- Loading entity modular_oscilloscope +# vsim -L proasic3e -L presynth -t 1ps presynth.testbench +# // ModelSim ACTEL 6.4a Aug 29 2008 +# // +# // Copyright 1991-2008 Mentor Graphics Corporation +# // All Rights Reserved. +# // +# // THIS WORK CONTAINS TRADE SECRET AND +# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY +# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS +# // AND IS SUBJECT TO LICENSE TERMS. +# // +# Loading std.standard +# Loading ieee.std_logic_1164(body) +# Loading ieee.std_logic_arith(body) +# Loading ieee.std_logic_unsigned(body) +# Loading ieee.math_real(body) +# Loading presynth.ctrl_pkg +# Loading presynth.daq_pkg +# Loading presynth.memory_pkg +# Loading presynth.eppwbn_pkg +# Loading presynth.testbench(tbgeneratedcode) +# Loading presynth.stimulus(stimulator) +# Loading presynth.tb_simple_clock(beh) +# Loading presynth.virtual_adc(beh) +# Loading presynth.modular_oscilloscope(struc1) +# Loading ieee.numeric_std(body) +# Loading presynth.daq(archdaq2) +# Loading presynth.eppwbn_16bit(structural) +# Loading presynth.eppwbn(structural) +# Loading presynth.eppwbn_ctrl(state_machines) +# Loading presynth.eppwbn_epp_side(multiplexor) +# Loading presynth.eppwbn_wbn_side(bridge2) +# Loading presynth.eppwbn_width_extension(arch_0) +# Loading presynth.ctrl(wsm) +# Loading presynth.ctrl_output_manager(arch22) +# Loading presynth.ctrl_memory_writer(arch12) +# Loading presynth.generic_counter(arch01) +# Loading presynth.ctrl_data_skipper(arch10) +# Loading presynth.generic_decoder(beh) +# Loading presynth.ctrl_channel_selector(arch01) +# Loading presynth.ctrl_trigger_manager(arch01_trigger) +# Loading presynth.ctrl_address_allocation(arch01) +# Loading presynth.dual_port_memory_wb(arch01) +# Loading presynth.dual_port_memory(def_arch) +# Loading std.textio(body) +# Loading ieee.vital_timing(body) +# Loading ieee.vital_primitives(body) +# Loading proasic3e.vtables +# Loading proasic3e.vcc(vital_act) +# Loading proasic3e.gnd(vital_act) +# Loading proasic3e.buff(vital_act) +# Loading ieee.std_logic_textio(body) +# Loading proasic3e.ram4k9(vital_act) +# Loading proasic3e.or2(vital_act) +# Loading proasic3e.mx2(vital_act) +# Loading proasic3e.nand2(vital_act) +# Loading proasic3e.dfn1(vital_act) +# Loading proasic3e.inv(vital_act) +# Loading proasic3e.and2a(vital_act) +# Loading proasic3e.nor2(vital_act) +# Loading proasic3e.and2(vital_act) +# Loading presynth.a3pe_pll_2clk(def_arch) +# Loading proasic3e.components +# Loading proasic3e.pll(vital_act) +# Loading proasic3e.pllprim(vital_act) +# Loading proasic3e.pllint(vital_act) +# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf +# File in use by: Administrador Hostname: VIRTUAL-BUDI ProcessID: 1212 +# Attempting to use alternate WLF file "./wlftz2kb2e". +# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf +# Using alternate file: ./wlftz2kb2e +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_chsel0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_memwr0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_memwr0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_outmgr0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_outmgr0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_epp16/u_eppwbn8/u_eppwbn +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_epp16/u_eppwbn8/u_eppwbn +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 1 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_outmgr0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 1 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 1 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 2 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 2 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 4 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 4 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 5 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 5 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 400 ps Iteration: 3 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 400 ps Iteration: 3 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 500 ps Iteration: 3 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 500 ps Iteration: 3 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 600 ps Iteration: 3 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 600 ps Iteration: 3 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 2900 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 2900 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 2900 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 2900 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 621695 ps Iteration: 1 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 621695 ps Iteration: 1 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 621695 ps Iteration: 1 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 621695 ps Iteration: 1 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 621695 ps Iteration: 1 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 621695 ps Iteration: 2 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 621695 ps Iteration: 2 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 621695 ps Iteration: 2 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 621695 ps Iteration: 2 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 621695 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 621695 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 621695 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 621695 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 621695 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 621695 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 621695 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 621695 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +do run.do +# INFO: Simulation library presynth already exists +# Modifying modelsim.ini +# Modifying modelsim.ini +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package std_logic_arith +# -- Loading package std_logic_unsigned +# -- Loading package numeric_std +# -- Compiling entity daq +# -- Compiling architecture archdaq2 of daq +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Compiling entity dual_port_memory +# -- Compiling architecture def_arch of dual_port_memory +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Compiling entity dual_port_memory_wb +# -- Compiling architecture arch01 of dual_port_memory_wb +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Compiling entity a3pe_pll_2clk +# -- Compiling architecture def_arch of a3pe_pll_2clk +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Compiling entity eppwbn_ctrl +# -- Compiling architecture state_machines of eppwbn_ctrl +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Compiling entity eppwbn_epp_side +# -- Compiling architecture multiplexor of eppwbn_epp_side +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package numeric_std +# -- Loading package std_logic_arith +# -- Loading package std_logic_unsigned +# -- Compiling entity eppwbn_wbn_side +# -- Compiling architecture bridge2 of eppwbn_wbn_side +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Compiling package eppwbn_pkg +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package eppwbn_pkg +# -- Compiling entity eppwbn +# -- Compiling architecture structural of eppwbn +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package std_logic_arith +# -- Loading package std_logic_unsigned +# -- Loading package numeric_std +# -- Loading package eppwbn_pkg +# -- Compiling entity eppwbn_width_extension +# -- Compiling architecture arch_0 of eppwbn_width_extension +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package eppwbn_pkg +# -- Compiling entity eppwbn_16bit +# -- Compiling architecture structural of eppwbn_16bit +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package std_logic_arith +# -- Loading package std_logic_unsigned +# -- Loading package numeric_std +# -- Compiling entity ctrl_output_manager +# -- Compiling architecture arch22 of ctrl_output_manager +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package std_logic_arith +# -- Loading package std_logic_unsigned +# -- Loading package numeric_std +# -- Compiling entity generic_counter +# -- Compiling architecture arch01 of generic_counter +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package math_real +# -- Compiling package ctrl_pkg +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package std_logic_arith +# -- Loading package std_logic_unsigned +# -- Loading package numeric_std +# -- Loading package math_real +# -- Loading package ctrl_pkg +# -- Compiling entity ctrl_memory_writer +# -- Compiling architecture arch12 of ctrl_memory_writer +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package numeric_std +# -- Loading package math_real +# -- Compiling entity generic_decoder +# -- Compiling architecture beh of generic_decoder +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package numeric_std +# -- Loading package math_real +# -- Loading package ctrl_pkg +# -- Compiling entity ctrl_data_skipper +# -- Compiling architecture arch10 of ctrl_data_skipper +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package numeric_std +# -- Loading package math_real +# -- Compiling entity ctrl_channel_selector +# -- Compiling architecture arch01 of ctrl_channel_selector +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package numeric_std +# -- Compiling entity ctrl_trigger_manager +# -- Compiling architecture arch01_trigger of ctrl_trigger_manager +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package std_logic_arith +# -- Loading package std_logic_unsigned +# -- Compiling entity ctrl_address_allocation +# -- Compiling architecture arch01 of ctrl_address_allocation +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package std_logic_arith +# -- Loading package std_logic_unsigned +# -- Loading package math_real +# -- Loading package ctrl_pkg +# -- Compiling entity ctrl +# -- Compiling architecture wsm of ctrl +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Compiling package daq_pkg +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package math_real +# -- Compiling package memory_pkg +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package std_logic_arith +# -- Loading package std_logic_unsigned +# -- Loading package math_real +# -- Loading package ctrl_pkg +# -- Loading package daq_pkg +# -- Loading package memory_pkg +# -- Loading package eppwbn_pkg +# -- Compiling entity modular_oscilloscope +# -- Compiling architecture struc1 of modular_oscilloscope +# -- Loading entity a3pe_pll_2clk +# Model Technology ModelSim ACTEL vcom 6.4a Compiler 2008.08 Aug 29 2008 +# -- Loading package standard +# -- Loading package std_logic_1164 +# -- Loading package math_real +# -- Compiling entity tb_simple_clock +# -- Compiling architecture beh of tb_simple_clock +# -- Loading package std_logic_arith +# -- Loading package std_logic_unsigned +# -- Compiling entity virtual_adc +# -- Compiling architecture beh of virtual_adc +# -- Loading package ctrl_pkg +# -- Loading package daq_pkg +# -- Loading package memory_pkg +# -- Loading package eppwbn_pkg +# -- Compiling entity stimulus +# -- Compiling architecture stimulator of stimulus +# -- Loading entity tb_simple_clock +# -- Loading entity virtual_adc +# -- Compiling entity testbench +# -- Compiling architecture tbgeneratedcode of testbench +# -- Loading entity stimulus +# -- Loading entity modular_oscilloscope +# vsim -L proasic3e -L presynth -t 1ps presynth.testbench +# Loading std.standard +# Loading ieee.std_logic_1164(body) +# Loading ieee.std_logic_arith(body) +# Loading ieee.std_logic_unsigned(body) +# Loading ieee.math_real(body) +# Loading presynth.ctrl_pkg +# Loading presynth.daq_pkg +# Loading presynth.memory_pkg +# Loading presynth.eppwbn_pkg +# Loading presynth.testbench(tbgeneratedcode) +# Loading presynth.stimulus(stimulator) +# Loading presynth.tb_simple_clock(beh) +# Loading presynth.virtual_adc(beh) +# Loading presynth.modular_oscilloscope(struc1) +# Loading ieee.numeric_std(body) +# Loading presynth.daq(archdaq2) +# Loading presynth.eppwbn_16bit(structural) +# Loading presynth.eppwbn(structural) +# Loading presynth.eppwbn_ctrl(state_machines) +# Loading presynth.eppwbn_epp_side(multiplexor) +# Loading presynth.eppwbn_wbn_side(bridge2) +# Loading presynth.eppwbn_width_extension(arch_0) +# Loading presynth.ctrl(wsm) +# Loading presynth.ctrl_output_manager(arch22) +# Loading presynth.ctrl_memory_writer(arch12) +# Loading presynth.generic_counter(arch01) +# Loading presynth.ctrl_data_skipper(arch10) +# Loading presynth.generic_decoder(beh) +# Loading presynth.ctrl_channel_selector(arch01) +# Loading presynth.ctrl_trigger_manager(arch01_trigger) +# Loading presynth.ctrl_address_allocation(arch01) +# Loading presynth.dual_port_memory_wb(arch01) +# Loading presynth.dual_port_memory(def_arch) +# Loading std.textio(body) +# Loading ieee.vital_timing(body) +# Loading ieee.vital_primitives(body) +# Loading proasic3e.vtables +# Loading proasic3e.vcc(vital_act) +# Loading proasic3e.gnd(vital_act) +# Loading proasic3e.buff(vital_act) +# Loading ieee.std_logic_textio(body) +# Loading proasic3e.ram4k9(vital_act) +# Loading proasic3e.or2(vital_act) +# Loading proasic3e.mx2(vital_act) +# Loading proasic3e.nand2(vital_act) +# Loading proasic3e.dfn1(vital_act) +# Loading proasic3e.inv(vital_act) +# Loading proasic3e.and2a(vital_act) +# Loading proasic3e.nor2(vital_act) +# Loading proasic3e.and2(vital_act) +# Loading presynth.a3pe_pll_2clk(def_arch) +# Loading proasic3e.components +# Loading proasic3e.pll(vital_act) +# Loading proasic3e.pllprim(vital_act) +# Loading proasic3e.pllint(vital_act) +# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf +# File in use by: Administrador Hostname: VIRTUAL-BUDI ProcessID: 1212 +# Attempting to use alternate WLF file "./wlftg67x3y". +# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf +# Using alternate file: ./wlftg67x3y +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_chsel0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_dskip0/u_deco0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_memwr0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_memwr0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_outmgr0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_outmgr0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_epp16/u_eppwbn8/u_eppwbn +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_epp16/u_eppwbn8/u_eppwbn +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 0 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 1 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_outmgr0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 1 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 1 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 2 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 2 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 4 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 4 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 0 ps Iteration: 5 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 0 ps Iteration: 5 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 400 ps Iteration: 3 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 400 ps Iteration: 3 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 500 ps Iteration: 3 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 500 ps Iteration: 3 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 600 ps Iteration: 3 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 600 ps Iteration: 3 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 2900 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 2900 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 2900 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 2900 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 621695 ps Iteration: 1 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 621695 ps Iteration: 1 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 621695 ps Iteration: 1 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 621695 ps Iteration: 1 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 621695 ps Iteration: 1 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 621695 ps Iteration: 2 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 621695 ps Iteration: 2 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 621695 ps Iteration: 2 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 621695 ps Iteration: 2 Instance: /testbench/u_osc0/u_ctrl/u_ctrl_addalloc0 +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 621695 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 621695 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 621695 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 621695 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 621695 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 621695 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# Time: 621695 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq +# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. +# Time: 621695 ps Iteration: 3 Instance: /testbench/u_osc0/u_daq

design/RVI/modular_oscilloscope/simulation/modelsim.log Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: design/RVI/modular_oscilloscope/viewdraw/viewdraw.ini =================================================================== --- design/RVI/modular_oscilloscope/viewdraw/viewdraw.ini (nonexistent) +++ design/RVI/modular_oscilloscope/viewdraw/viewdraw.ini (revision 62) @@ -0,0 +1,63 @@ +NET 12 1 0 +COMPONENT 15 0 0 +ATTRIBUTE 14 0 0 +LABEL 15 0 0 +PIN 3 0 0 +BOX 2 0 0 +LINE 2 0 0 +CIRCLE 2 0 0 +ARC 2 0 0 +TEXT 10 0 0 +SELECTION_LAYER 15 0 0 +BORDER_LAYER 15 0 0 +VALUE_LAYER 7 0 0 +ANNO_LAYER 7 0 0 +GRID 10 +DOTSIZE 5 +BUS_DOTSIZE 12 +BOXSIZE 5 +TEXTSIZE 10 +TEXTORIGIN 3 +BUSWIDTH 4 +BUBBLESIZE 5 +AUTOLOG 10 +SDISTANCE 10 +ADISTANCE 20 +SHEETSIZE 1 +ROUTE 2 +SCOPE 0 +TEXT_THRESHOLD 3 +NEW_ATTR_VIS 1 +BLOCKTYPE 0 +UNDO 16 +GRIDON 1 +BORDERON 1 +HEADERON 1 +COMPTEXTON 1 +TEXTON 1 +ATTRON 1 +LABELON 1 +DETAIL 1 +SNAPTOPIN 1 +UNIQUE_LABEL 0 +VALUESON 1 +CONTEXT_WINDOW 0 +NAMESON 0 +SORTON 1 +PNUMSON 1 +RNUMSON 1 +DEFSHEET 0 +XTRAERRS 1 +DBOXON 0 +PRESERVE_CASE 0 +ALLOW_VALUE_MIXED VERILOG +NETNAME VDD +NETNAME GND +ATTR_RESET SS#1 +ATTR_RESET SS#2 +ATTR_RESET ALL_ID +ATTR_RESET GEN_ID +ATTR_RESET REFDES SYMBOL_VALUE +DIR [pw] D:\Facu\TFuni2\test_modular_oscilloscope\viewdraw +DIR [rm] C:\Actel\Libero_v8.5\Designer\lib\libvd\proasic3e\cells (actelcells) +DIR [rm] C:\Actel\Libero_v8.5\Designer\lib\libvd\asicbin (builtin)

design/RVI/modular_oscilloscope/viewdraw/viewdraw.ini Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: design/RVI/modular_oscilloscope/synthesis/.recordref =================================================================== Index: design/RVI/modular_oscilloscope/synthesis/.recordref =================================================================== --- design/RVI/modular_oscilloscope/synthesis/.recordref (nonexistent) +++ design/RVI/modular_oscilloscope/synthesis/.recordref (revision 62)

design/RVI/modular_oscilloscope/synthesis/.recordref Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: design/RVI/modular_oscilloscope/package/ctrl_pkg.vhd =================================================================== --- design/RVI/modular_oscilloscope/package/ctrl_pkg.vhd (nonexistent) +++ design/RVI/modular_oscilloscope/package/ctrl_pkg.vhd (revision 62) @@ -0,0 +1,309 @@ +-------------------------------------------------------------------------------------------------100 +--| Modular Oscilloscope +--| UNSL - Argentine +--| +--| File: ctrl_pkg.vhd +--| Version: 0.1 +--| Tested in: Actel A3PE1500 +--|------------------------------------------------------------------------------------------------- +--| Description: +--| CONTROL - Package +--| Package for instantiate Control modules. +--| +--|------------------------------------------------------------------------------------------------- +--| File history: +--| 0.11 | aug-2009 | First release +---------------------------------------------------------------------------------------------------- +--| Copyright (R) 2009, Facundo Aguilera. +--| +--| This VHDL design file is an open design; you can redistribute it and/or +--| modify it and/or implement it after contacting the author. +---------------------------------------------------------------------------------------------------- + + + +-- Bloque completo +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.math_real.all; + +package ctrl_pkg is + -------------------------------------------------------------------------------------------------- + -- Componentes + + component generic_decoder is + generic( + INPUT_WIDTH: integer := 5 -- Input with for decoder (decodes INPUT_WIDTH to 2^INPUT_WIDTH) + ); + Port( + enable_I: in std_logic; + data_I: in std_logic_vector(INPUT_WIDTH-1 downto 0); + decoded_O: out std_logic_vector( integer(2**real(INPUT_WIDTH))-1 downto 0) + ); + end component generic_decoder; + + + component generic_counter is + generic( + OUTPUT_WIDTH: integer := 32 -- Output width for counter. + ); + port( + clk_I: in std_logic; + count_O: out std_logic_vector( OUTPUT_WIDTH downto 0); + reset_I: in std_logic; + enable_I: in std_logic + ); + end component generic_counter; + + component ctrl_output_manager is + generic( + MEM_ADD_WIDTH: integer := 14 + ); + port( + ------------------------------------------------------------------------------------------------ + -- MASTER (to memory) + DAT_I_mem: in std_logic_vector (15 downto 0); + --DAT_O_mem: out std_logic_vector (15 downto 0); + ADR_O_mem: out std_logic_vector (MEM_ADD_WIDTH - 1 downto 0); + CYC_O_mem: out std_logic; + STB_O_mem: out std_logic; + ACK_I_mem: in std_logic ; + WE_O_mem: out std_logic; + ------------------------------------------------------------------------------------------------ + -- SLAVE (to I/O ports) + --DAT_I_port: in std_logic_vector (15 downto 0); + DAT_O_port: out std_logic_vector (15 downto 0); + --ADR_I_port: in std_logic_vector (7 downto 0); + CYC_I_port: in std_logic; + STB_I_port: in std_logic; + ACK_O_port: out std_logic ; + WE_I_port: in std_logic; + ------------------------------------------------------------------------------------------------ + -- Common signals + RST_I: in std_logic; + CLK_I: in std_logic; + ------------------------------------------------------------------------------------------------ + -- Internal + load_I: in std_logic; + -- load initial address + enable_I: in std_logic; + -- continue reading from the actual address ('0' means pause, '1' means continue) + initial_address_I: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0); + -- buffer starts and ends here + biggest_address_I: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0); + -- when the buffer arrives here, address is changed to 0 (buffer size) + pause_address_I: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0); + -- address wich is being writed by control + finish_O: out std_logic + -- this is set when communication ends and remains until next restart or actual address change + ); + end component ctrl_output_manager; + + component ctrl_memory_writer is + generic( + MEM_ADD_WIDTH: integer := 14 + ); + port( + ---------------------------------------------------------------------------------------------- + -- to memory + DAT_O_mem: out std_logic_vector (15 downto 0); + ADR_O_mem: out std_logic_vector (MEM_ADD_WIDTH - 1 downto 0); + CYC_O_mem: out std_logic; + STB_O_mem: out std_logic; + ACK_I_mem: in std_logic ; + WE_O_mem: out std_logic; + ---------------------------------------------------------------------------------------------- + -- to acquistion module + DAT_I_adc: in std_logic_vector (15 downto 0); + -- Using an address generator, commented + -- ADR_O_adc: out std_logic_vector (ADC_ADD_WIDTH - 1 downto 0); + CYC_O_adc: out std_logic; + STB_O_adc: out std_logic; + ACK_I_adc: in std_logic ; + --WE_O_adc: out std_logic; + ---------------------------------------------------------------------------------------------- + -- Common signals + RST_I: in std_logic; + CLK_I: in std_logic; + ---------------------------------------------------------------------------------------------- + -- Internal + -- reset memory address to 0 + reset_I: in std_logic; + -- read in clk edge from the actual address ('0' means pause, '1' means continue) + enable_I: in std_logic; + final_address_I: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0); + -- it is set when communication ends and remains until next restart or actual address change + finished_O: out std_logic; + -- when counter finishes, restart + continuous_I: in std_logic + ); + end component ctrl_memory_writer; + + + component ctrl_data_skipper is + generic( + -- max losses = 2**(2**SELECTOR_WIDTH). (i.e., if SELECTOR_WIDTH = 5: 4.2950e+09) + SELECTOR_WIDTH: integer := 5 + ); + port( + -- enable output signal + ack_O: out std_logic; + -- sinal from wishbone interface + ack_I, stb_I: in std_logic; + -- selector from register, equation: losses = 2**(selector_I + 1) * enable_skipper_I + selector_I: in std_logic_vector(SELECTOR_WIDTH-1 downto 0); + -- enable from register + enable_skipper_I: in std_logic; + -- common signals + reset_I, clk_I: in std_logic; + -- set when returns to the first channel + first_channel_I: in std_logic + ); + end component ctrl_data_skipper; + + + component ctrl_channel_selector is + generic( + CHANNEL_WIDTH: integer := 4 -- number of channels 2**CHANNEL_WIDTH, max. 4 + ); + port( + channels_I: in std_logic_vector(integer(2**real(CHANNEL_WIDTH))-1 downto 0); + channel_number_O: out std_logic_vector(CHANNEL_WIDTH - 1 downto 0); + first_channel_O: out std_logic; + clk_I: in std_logic; + enable_I: in std_logic; + reset_I: in std_logic + ); + end component ctrl_channel_selector; + + + component ctrl_trigger_manager is + generic ( + MEM_ADD_WIDTH: integer := 14; + DATA_WIDTH: integer := 10; + CHANNELS_WIDTH: integer := 4 + ); + port ( + data_I: in std_logic_vector (DATA_WIDTH - 1 downto 0); + channel_I: in std_logic_vector (CHANNELS_WIDTH -1 downto 0); + trig_channel_I: in std_logic_vector (CHANNELS_WIDTH -1 downto 0); + address_I: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0); + final_address_I: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0); + -- offset from trigger address (signed). MUST BE: + -- -final_address_I < offset_I < final_address_I + offset_I: in std_logic_vector (MEM_ADD_WIDTH downto 0); + -- trigger level (from max to min, not signed) + level_I: in std_logic_vector (DATA_WIDTH - 1 downto 0); + -- use falling edge when falling_I = '1', else rising edge + falling_I: in std_logic; + clk_I: in std_logic; + reset_I: in std_logic; + enable_I: in std_logic; + -- it is set when trigger condition occurs + trigger_O: out std_logic; + -- address when trigger plus offset + address_O: out std_logic_vector (MEM_ADD_WIDTH - 1 downto 0) + ); + end component ctrl_trigger_manager; + + + component ctrl_address_allocation is + port( + ---------------------------------------------------------------------------------------------- + -- From port + DAT_I_port: in std_logic_vector (15 downto 0); + DAT_O_port: out std_logic_vector (15 downto 0); + ADR_I_port: in std_logic_vector (3 downto 0); + CYC_I_port: in std_logic; + STB_I_port: in std_logic; + ACK_O_port: out std_logic ; + WE_I_port: in std_logic; + RST_I: in std_logic; + CLK_I: in std_logic; + ---------------------------------------------------------------------------------------------- + -- To internal + CYC_O_int: out std_logic; + STB_O_int: out std_logic; + ACK_I_int: in std_logic ; + DAT_I_int: in std_logic_vector(15 downto 0); + ---------------------------------------------------------------------------------------------- + -- Internal + start_O: out std_logic; + continuous_O: out std_logic; + trigger_en_O: out std_logic; + trigger_edge_O: out std_logic; + trigger_channel_O:out std_logic_vector(0 downto 0); + time_scale_O: out std_logic_vector(4 downto 0); + time_scale_en_O: out std_logic; + channels_sel_O: out std_logic_vector(1 downto 0); + buffer_size_O: out std_logic_vector(13 downto 0); + trigger_level_O: out std_logic_vector(9 downto 0); + trigger_offset_O: out std_logic_vector(14 downto 0); + + adc_conf_O: out std_logic_vector(15 downto 0); + + error_number_I: in std_logic_vector (2 downto 0); + status_I: in std_logic_vector(1 downto 0); + + write_in_adc_O: out std_logic; + stop_O: out std_logic + ); + end component ctrl_address_allocation; + + + component ctrl is + port( + ------------------------------------------------------------------------------------------------ + -- (TEMPORAL) to monitors + ctrl_status_monitor: out std_logic_vector(3 downto 0); + + ------------------------------------------------------------------------------------------------ + -- From port + DAT_I_port: in std_logic_vector (15 downto 0); + DAT_O_port: out std_logic_vector (15 downto 0); + ADR_I_port: in std_logic_vector (3 downto 0); + CYC_I_port: in std_logic; + STB_I_port: in std_logic; + ACK_O_port: out std_logic ; + WE_I_port: in std_logic; + CLK_I_port: in std_logic; + RST_I_port: in std_logic; + + ------------------------------------------------------------------------------------------------ + -- To ADC + DAT_I_daq: in std_logic_vector (15 downto 0); + DAT_O_daq: out std_logic_vector (15 downto 0); + ADR_O_daq: out std_logic_vector (1 downto 0); + CYC_O_daq: out std_logic; + STB_O_daq: out std_logic; + ACK_I_daq: in std_logic ; + WE_O_daq: out std_logic; + + CLK_I_daq: in std_logic; + RST_I_daq: in std_logic; + + ------------------------------------------------------------------------------------------------ + -- To memory, A (writing) interface (Higer prioriry) + --DAT_I_memw: in std_logic_vector (15 downto 0); + DAT_O_memw: out std_logic_vector (15 downto 0); + ADR_O_memw: out std_logic_vector (13 downto 0); + CYC_O_memw: out std_logic; + STB_O_memw: out std_logic; + ACK_I_memw: in std_logic ; + WE_O_memw: out std_logic; + + ------------------------------------------------------------------------------------------------ + -- To memory, B (reading) interface + DAT_I_memr: in std_logic_vector (15 downto 0); + --DAT_O_memr: out std_logic_vector (15 downto 0); + ADR_O_memr: out std_logic_vector (13 downto 0); + CYC_O_memr: out std_logic; + STB_O_memr: out std_logic; + ACK_I_memr: in std_logic ; + WE_O_memr: out std_logic + + ); + end component ctrl; + +end package ctrl_pkg; + \ No newline at end of file

design/RVI/modular_oscilloscope/package/ctrl_pkg.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: design/RVI/modular_oscilloscope/package/daq_pkg.vhd =================================================================== --- design/RVI/modular_oscilloscope/package/daq_pkg.vhd (nonexistent) +++ design/RVI/modular_oscilloscope/package/daq_pkg.vhd (revision 62) @@ -0,0 +1,69 @@ +---------------------------------------------------------------------------------------------------- +--| Modular Oscilloscope +--| UNSL - Argentine +--| +--| File: daq_pkg.vhd +--| Version: 0.01 +--| Tested in: Actel A3PE1500 +--|------------------------------------------------------------------------------------------------- +--| Description: +--| Adquisition control module. +--| Package for instantiate all adq modules. +--|------------------------------------------------------------------------------------------------- +--| File history: +--| 0.01 | apr-2009 | First release +---------------------------------------------------------------------------------------------------- +--| Copyright � 2009, Facundo Aguilera. +--| +--| This VHDL design file is an open design; you can redistribute it and/or +--| modify it and/or implement it after contacting the author. +---------------------------------------------------------------------------------------------------- + + +-- Bloque completo +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +package daq_pkg is + -------------------------------------------------------------------------------------------------- + -- Componentes + + component daq is + generic ( + DEFALT_CONFIG : std_logic_vector := "0000100000000000" + -- bits 8 a 0 clk_pre_scaler + -- bits 9 clk_pre_scaler_ena + -- bit 10 adc sleep + -- bit 11 adc_chip_sel + -- bits 12 a 15 sin usar + + -- si clk_pre_scaler_ena = 1 + -- frecuencia_adc = frecuencia_wbn / ((clk_pre_scaler+1)*2) + -- sino frecuencia_adc = frecuencia_wbn + ); + port( + -- Externo + adc_data_I: in std_logic_vector (9 downto 0); + adc_sel_O: out std_logic; + adc_clk_O: out std_logic; + adc_sleep_O: out std_logic; + adc_chip_sel_O: out std_logic; + + + -- Interno + RST_I: in std_logic; + CLK_I: in std_logic; + DAT_I: in std_logic_vector (15 downto 0); + ADR_I: in std_logic_vector (1 downto 0); + CYC_I: in std_logic; + STB_I: in std_logic; + WE_I: in std_logic; + DAT_O: out std_logic_vector (15 downto 0); + ACK_O: out std_logic; + + adc_clk_I: std_logic + ); + end component daq; + +end package daq_pkg; + \ No newline at end of file

design/RVI/modular_oscilloscope/package/daq_pkg.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: design/RVI/modular_oscilloscope/package/memory_pkg.vhd =================================================================== --- design/RVI/modular_oscilloscope/package/memory_pkg.vhd (nonexistent) +++ design/RVI/modular_oscilloscope/package/memory_pkg.vhd (revision 62) @@ -0,0 +1,63 @@ +-------------------------------------------------------------------------------------------------100 +--| Modular Oscilloscope +--| UNSL - Argentine +--| +--| File: memory_pkg.vhd +--| Version: 0.1 +--| Tested in: Actel A3PE1500 +--| Board: RVI Prototype Board + LP Data Conversion Daughter Board +--|------------------------------------------------------------------------------------------------- +--| Description: +--| Memories - Package +--| Package for instantiate Control modules. +--| +--|------------------------------------------------------------------------------------------------- +--| File history: +--| 0.1 | aug-2009 | First release +---------------------------------------------------------------------------------------------------- +--| Copyright (R) 2009, Facundo Aguilera (budinero at gmail.com). +--| +--| This VHDL design file is an open design; you can redistribute it and/or +--| modify it and/or implement it after contacting the author. +---------------------------------------------------------------------------------------------------- + + + +-- Bloque completo +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.math_real.all; + +package memory_pkg is + -------------------------------------------------------------------------------------------------- + -- Componentes + + component dual_port_memory_wb is + port( + -- Puerto A (Higer prioriry) + RST_I_a: in std_logic; + CLK_I_a: in std_logic; + DAT_I_a: in std_logic_vector (15 downto 0); + DAT_O_a: out std_logic_vector (15 downto 0); + ADR_I_a: in std_logic_vector (13 downto 0); + CYC_I_a: in std_logic; + STB_I_a: in std_logic; + ACK_O_a: out std_logic ; + WE_I_a: in std_logic; + + + -- Puerto B (Lower prioriry) + RST_I_b: in std_logic; + CLK_I_b: in std_logic; + DAT_I_b: in std_logic_vector (15 downto 0); + DAT_O_b: out std_logic_vector (15 downto 0); + ADR_I_b: in std_logic_vector (13 downto 0); + CYC_I_b: in std_logic; + STB_I_b: in std_logic; + ACK_O_b: out std_logic ; + WE_I_b: in std_logic + ); + end component dual_port_memory_wb; + +end package memory_pkg; + \ No newline at end of file

design/RVI/modular_oscilloscope/package/memory_pkg.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: design/RVI/modular_oscilloscope/package/eppwbn_pkg.vhd =================================================================== --- design/RVI/modular_oscilloscope/package/eppwbn_pkg.vhd (nonexistent) +++ design/RVI/modular_oscilloscope/package/eppwbn_pkg.vhd (revision 62) @@ -0,0 +1,291 @@ +---------------------------------------------------------------------------------------------------- +--| UNSL - Modular Oscilloscope +--| +--| File: eppwbn_wbn_side.vhd +--| Version: 0.2 +--| Tested in: Actel APA300 +--| Tested in: Actel A3PE1500 +--| Board: RVI Prototype Board + LP Data Conversion Daughter Board +--|------------------------------------------------------------------------------------------------- +--| Description: +--| EPP - Wishbone bridge. +--| Package for instantiate EPP-WBN modules. +--|------------------------------------------------------------------------------------------------- +--| File history: +--| 0.01 | dic-2008 | First release +--| 0.10 | jan-2009 | Added testing memory +--| 0.20 | mar-2009 | Added extension module +---------------------------------------------------------------------------------------------------- +--| Copyright (R) 2008, Facundo Aguilera. +--| +--| This VHDL design file is an open design; you can redistribute it and/or +--| modify it and/or implement it after contacting the author. +---------------------------------------------------------------------------------------------------- + + +-- Bloque completo +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + + +package eppwbn_pkg is + -------------------------------------------------------------------------------------------------- + -- Componentes + + -- Bridge control + component eppwbn_ctrl is + port( + nStrobe: in std_logic; + + Data: in std_logic_vector (7 downto 0); + nAck: out std_logic; + PError: out std_logic; + Sel: out std_logic; + nAutoFd: in std_logic; + PeriphLogicH: out std_logic; + nInit: in std_logic; + nFault: out std_logic; + nSelectIn: in std_logic; + + RST_I: in std_logic; + CLK_I: in std_logic; + + rst_pp: out std_logic; + epp_mode: out std_logic_vector (1 downto 0) + ); + end component eppwbn_ctrl; + + -- Comunication with EPP interface + component eppwbn_epp_side is + port( + epp_mode: in std_logic_vector (1 downto 0); + + ctr_nAck, ctr_PError, ctr_Sel, ctr_nFault: in std_logic; + + ctr_nAutoFd, ctr_nSelectIn, ctr_nStrobe: out std_logic; + + wb_Busy: in std_logic; + wb_nAutoFd: out std_logic; + wb_nSelectIn: out std_logic; + wb_nStrobe: out std_logic; + + nAck, PError, Sel, nFault: out std_logic; + + Busy: out std_logic; + nAutoFd: in std_logic; + nSelectIn: in std_logic; + nStrobe: in std_logic + ); + end component eppwbn_epp_side; + + -- Comunication with WB interface + component eppwbn_wbn_side is + port( + inStrobe: in std_logic; + iData: inout std_logic_vector (7 downto 0); + iBusy: out std_logic; + inAutoFd: in std_logic; + inSelectIn: in std_logic; + + RST_I, CLK_I: in std_logic; + DAT_I: in std_logic_vector (7 downto 0); + DAT_O: out std_logic_vector (7 downto 0); + ADR_O: out std_logic_vector (7 downto 0); + CYC_O, STB_O: out std_logic; + ACK_I: in std_logic ; + WE_O: out std_logic; + + rst_pp: in std_logic + ); + end component eppwbn_wbn_side; + + -- Testing memory + component test_memory is + generic ( --USE_RESET : boolean := false; -- use system reset + + --USE_CS : boolean := false; -- use chip select signal + + DEFAULT_OUT : std_logic; -- Default output + --OPTION : integer := 1; -- 1: Registered read Address(suitable + -- for Altera's FPGAs + -- 0: non registered read address + ADD_WIDTH : integer; + WIDTH : integer); + + port ( + cs: in std_logic; -- chip select + clk: in std_logic; -- write clock + reset: in std_logic; -- System Reset + add: in std_logic_vector(add_width -1 downto 0); -- Address + Data_In: in std_logic_vector(WIDTH -1 downto 0); -- input data + Data_Out: out std_logic_vector(WIDTH -1 downto 0); -- Output Data + WR: in std_logic); -- Read Write Enable + end component test_memory; + + -- Epp-wishbone bridge + component eppwbn is + port( + -- TEMPORAL + --epp_mode_monitor: out std_logic_vector (1 downto 0); + + -- Externo + nStrobe: in std_logic; -- HostClk/nWrite + Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8) + nAck: out std_logic; -- PtrClk/PeriphClk/Intr + busy: out std_logic; -- PtrBusy/PeriphAck/nWait + PError: out std_logic; -- AckData/nAckReverse + Sel: out std_logic; -- XFlag (Select) + nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb + PeriphLogicH: out std_logic; -- (Periph Logic High) + nInit: in std_logic; -- nReverseRequest + nFault: out std_logic; -- nDataAvail/nPeriphRequest + nSelectIn: in std_logic; -- 1284 Active/nAStrb + + -- Interno + RST_I: in std_logic; + CLK_I: in std_logic; + DAT_I: in std_logic_vector (7 downto 0); + DAT_O: out std_logic_vector (7 downto 0); + ADR_O: out std_logic_vector (7 downto 0); + CYC_O: out std_logic; + STB_O: out std_logic; + ACK_I: in std_logic ; + WE_O: out std_logic + ); + end component eppwbn; + + -- Testing component + component eppwbn_test_wb_side is + port( + RST_I: in std_logic; + CLK_I: in std_logic; + DAT_I: in std_logic_vector (7 downto 0); + DAT_O: out std_logic_vector (7 downto 0); + ADR_I: in std_logic_vector (7 downto 0); + CYC_I: in std_logic; + STB_I: in std_logic; + ACK_O: out std_logic ; + WE_I: in std_logic + ); + end component eppwbn_test_wb_side; + + + -- Width extension + component eppwbn_width_extension is + generic ( + TIME_OUT_VALUE: integer; + TIME_OUT_WIDTH: integer + ); + port( + -- Slave signals + DAT_I_sl: in std_logic_vector (7 downto 0); + DAT_O_sl: out std_logic_vector (7 downto 0); + ADR_I_sl: in std_logic_vector (7 downto 0); + CYC_I_sl: in std_logic; + STB_I_sl: in std_logic; + ACK_O_sl: out std_logic ; + WE_I_sl: in std_logic; + + + -- Master signals + DAT_I_ma: in std_logic_vector (15 downto 0); + DAT_O_ma: out std_logic_vector (15 downto 0); + ADR_O_ma: out std_logic_vector (7 downto 0); + CYC_O_ma: out std_logic; + STB_O_ma: out std_logic; + ACK_I_ma: in std_logic ; + WE_O_ma: out std_logic; + + -- Common signals + RST_I: in std_logic; + CLK_I: in std_logic + ); + end component eppwbn_width_extension; + + component eppwbn_16bit is + port( + -- TEMPORAL + --epp_mode_monitor: out std_logic_vector (1 downto 0); + + -- Externo + nStrobe: in std_logic; -- HostClk/nWrite + Data: inout std_logic_vector (7 downto 0);-- AD8..1 (Data1..Data8) + nAck: out std_logic; -- PtrClk/PeriphClk/Intr + busy: out std_logic; -- PtrBusy/PeriphAck/nWait + PError: out std_logic; -- AckData/nAckReverse + Sel: out std_logic; -- XFlag (Select) + nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb + PeriphLogicH: out std_logic; -- (Periph Logic High) + nInit: in std_logic; -- nReverseRequest + nFault: out std_logic; -- nDataAvail/nPeriphRequest + nSelectIn: in std_logic; -- 1284 Active/nAStrb + + + -- Interno + RST_I: in std_logic; + CLK_I: in std_logic; + DAT_I: in std_logic_vector (15 downto 0); + DAT_O: out std_logic_vector (15 downto 0); + ADR_O: out std_logic_vector (7 downto 0); + CYC_O: out std_logic; + STB_O: out std_logic; + ACK_I: in std_logic ; + WE_O: out std_logic + ); + end component eppwbn_16bit; + + component eppwbn_16bit_test is + port( + -- al puerto EPP + nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284 + -- HostClk/nWrite + Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8) + nAck: out std_logic; -- PtrClk/PeriphClk/Intr + busy: out std_logic; -- PtrBusy/PeriphAck/nWait + PError: out std_logic; -- AckData/nAckReverse + Sel: out std_logic; -- XFlag (Select) + nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb + PeriphLogicH: out std_logic; -- (Periph Logic High) + nInit: in std_logic; -- nReverseRequest + nFault: out std_logic; -- nDataAvail/nPeriphRequest + nSelectIn: in std_logic; -- 1284 Active/nAStrb + + -- a los switches + rst: in std_logic; + + -- al clock + clk: in std_logic; + + -- monitores + data_monitor: out std_logic_vector (7 downto 0); + epp_mode_monitor: out std_logic_vector (1 downto 0) + + ); + end component eppwbn_16bit_test; + + component eppwbn_16bit_test_wb_side is + generic ( + ADD_WIDTH : integer ; + WIDTH : integer + ); + port( + RST_I: in std_logic; + CLK_I: in std_logic; + DAT_I: in std_logic_vector (WIDTH-1 downto 0); + DAT_O: out std_logic_vector (WIDTH-1 downto 0); + ADR_I: in std_logic_vector (7 downto 0); + CYC_I: in std_logic; + STB_I: in std_logic; + ACK_O: out std_logic ; + WE_I: in std_logic + ); + end component eppwbn_16bit_test_wb_side; + + -- Clock (Actel specific) + component A3PE_pll is + port(POWERDOWN, CLKA : in std_logic; LOCK, GLA : out + std_logic) ; + end component A3PE_pll; + +end package eppwbn_pkg; + \ No newline at end of file

design/RVI/modular_oscilloscope/package/eppwbn_pkg.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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