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URL https://opencores.org/ocsvn/modular_oscilloscope/modular_oscilloscope/trunk

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    /modular_oscilloscope
    from Rev 53 to Rev 54
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Rev 53 → Rev 54

/trunk/hdl/modular_oscilloscope.vhd
85,7 → 85,7
signal ctrl_adr_o_daq: std_logic_vector (1 downto 0);
signal ctrl_cyc_o_daq: std_logic;
signal ctrl_stb_o_daq: std_logic;
signal ctrl_ack_i_daq: std_logic ;
signal ctrl_ack_i_daq: std_logic;
signal ctrl_we_o_daq: std_logic;
 
signal ctrl_dat_o_memw: std_logic_vector (15 downto 0);
/trunk/hdl/tbench/modullar_oscilloscope_tbench_text.vhd
14,7 → 14,7
--| File history:
--| 0.1 | aug-2009 | First release
----------------------------------------------------------------------------------------------------
 
 
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
25,9 → 25,12
 
--==================================================================================================
 
-- NOTES
 
 
 
 
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
-->> Virtual clock
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
34,7 → 37,7
 
 
entity ctrl_tb_simple_clock is
entity tb_simple_clock is
port (
CLK_PERIOD: in time;-- := 20 ns;
CLK_DUTY: in real; -- := 0.5;
41,9 → 44,9
active: in boolean;
clk_o: out std_logic
);
end entity ctrl_tb_simple_clock ;
end entity tb_simple_clock ;
architecture beh of ctrl_tb_simple_clock is
architecture beh of tb_simple_clock is
begin
P_main: process
begin
59,13 → 62,56
end process;
end architecture beh;
 
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
-->> Virtual ADC
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity virtual_adc is
port (
clk_I: in std_logic;
sel_I: in std_logic;
chip_sel_I: in std_logic;
sleep_I: in std_logic;
data_O: out std_logic_vector(9 downto 0)
);
end entity virtual_adc ;
architecture beh of virtual_adc is
signal data1: std_logic_vector(9 downto 0) := "0000000001"; -- odd
signal data2: std_logic_vector(9 downto 0) := (others => '0'); -- pair
begin
 
P_virtual_adc: process (clk_I, sel_I, chip_sel_I, sleep_I)
 
begin
if clk_I'event and clk_I = '1' then
data1 <= data1 + 2;
data2 <= data2 + 2;
end if;
if sleep_I = '1' or chip_sel_I = '0' then
data_O <= (others => '0');
else
case sel_I is
when '0' =>
data_O <= data1;
when others =>
data_O <= data2;
end case;
end if;
end process;
 
end architecture beh;
 
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
-->> Stimulus
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
--use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
 
 
78,7 → 124,7
entity stimulus is
port(
-- ADC
adc_data_I: inout std_logic_vector (9 downto 0) := 0;
adc_data_I: inout std_logic_vector (9 downto 0) := (others => '0');
adc_sel_O: in std_logic;
adc_clk_O: in std_logic;
adc_sleep_O: in std_logic;
88,7 → 134,7
nStrobe_I: inout std_logic; -- HostClk/nWrite
Data_IO: inout std_logic_vector (7 downto 0);-- AD8..1 (Data1..Data8)
nAck_O: in std_logic; -- PtrClk/PeriphClk/Intr
busy_O: in std_logic; -- PtrBusy/PeriphAck/nWait
Busy_O: in std_logic; -- PtrBusy/PeriphAck/nWait
PError_O: in std_logic; -- AckData/nAckReverse
Sel_O: in std_logic; -- XFlag (Select)
nAutoFd_I: inout std_logic; -- HostBusy/HostAck/nDStrb
99,17 → 145,23
-- Peripherals
reset_I: inout std_logic;
pll_clk_I: inout std_logic -- clock signal go to pll, and is divided in two clocks
pll_clk_I: inout std_logic; -- clock signal go to pll, and is divided in two clocks
test_number: out integer range 0 to 20
);
 
end stimulus;
 
architecture STIMULATOR of stimulus is
 
-- PLL clocks
constant CLK_DAQ_PERIOD: time := 25 ns;
constant CLK_EPP_PERIOD: time := 100 ns;
-- Control Signal Declarations
signal tb_InitFlag : boolean := false;
signal tb_ParameterInitFlag : boolean := false;
signal i: std_logic;
signal runflag: std_logic;
-- Parm Declarations
signal clk_Duty : real := 0.0;
123,7 → 175,7
variable clk_Period_real : real;
begin
-- Basic parameters
clk_Period_real := 20.0; --<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--
clk_Period_real := 40.0; --<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--
clk_Period <= clk_Period_real * 1 ns;
clk_Duty_real := 50.0;
clk_Duty <= clk_Duty_real;
135,9 → 187,9
--------------------------------------------------------------------------------------------------
-- Clocks
-- Instantiation
-- Clock Instantiation
tb_clk: entity work.tb_simple_clock
U_TB_CLK: entity work.tb_simple_clock
port map (
clk_Period => clk_Period,
clk_Duty => clk_Duty,
145,108 → 197,241
clk_o => pll_clk_I
);
-- ADC Instantiation
U_TB_ADC: entity work.virtual_adc
port map(
clk_I => adc_clk_O,
sel_I => adc_sel_O,
chip_sel_I => adc_chip_sel_O,
sleep_I => adc_sleep_O,
data_O => adc_data_I
);
--------------------------------------------------------------------------------------------------
-- Clocked Sequences
P_virtual_adc: process (adc_clk_O)
variable data1: std_logic_vector(9 downto 0) := 1; -- odd
variable data2: std_logic_vector(9 downto 0) := 0; -- pair
begin
if adc_clk_O'event and adc_clk_O = '1' then
data1 <= data1 + 2;
data2 <= data2 + 2;
end if;
case adc_sel_O is
when '0' =>
adc_data_I <= data1;
when others =>
adc_data_I <= data2;
end case;
end process;
-- Main process
P_Unclocked : process
------------------------------------------------------------------------------------------------
-- Procedure for write in epp port
procedure WriteData(
constant in_address: in std_logic_vector(7 downto 0);
constant in_data: in std_logic_vector(15 downto 0);
signal Data_IO: out std_logic_vector(7 downto 0);
signal nStrobe_I: out std_logic;
signal nSelectIn_I: out std_logic;
signal nAutoFd_I: out std_logic;
signal Busy_O: in std_logic
) is
begin
nStrobe_I <= '0'; -- '0' -> is write
 
--------------------------------------------------------------------------------------------------
-- Sequence: Unclocked
P_Unclocked : process
Data_IO <= in_address; -- Address
nSelectIn_I <= '0'; -- addStb
wait until Busy_O = '1';
--wait for 30 ns;
nSelectIn_I <= '1';
wait until Busy_O = '0';
Data_IO <= in_data(7 downto 0); -- Data1
nAutoFd_I <= '0'; -- datStb
wait until Busy_O = '1';
nAutoFd_I <= '1';
wait until Busy_O = '0';
Data_IO <= in_data(15 downto 8); -- Data0
nAutoFd_I <= '0'; -- datStb
wait until Busy_O = '1';
nAutoFd_I <= '1';
wait until Busy_O = '0';
end procedure WriteData;
------------------------------------------------------------------------------------------------
-- Procedure for read from epp port
procedure ReadData(
signal out_runflag: out std_logic;
constant in_address: in std_logic_vector(7 downto 0);
signal Data_IO: inout std_logic_vector(7 downto 0);
signal nStrobe_I: out std_logic;
signal nSelectIn_I: out std_logic;
signal nAutoFd_I: out std_logic;
signal Busy_O: in std_logic
) is
begin
nStrobe_I <= '0'; -- '0' -> is write
Data_IO <= in_address; -- Address
nSelectIn_I <= '0'; -- addStb
wait until Busy_O = '1';
--wait for 30 ns;
nSelectIn_I <= '1';
wait until Busy_O = '0';
nStrobe_I <= '1'; -- '1' -> is read
Data_IO <= (others => 'Z'); -- Data1
nAutoFd_I <= '0'; -- datStb
wait until (Busy_O = '1');
wait for 30 ns;
nAutoFd_I <= '1';
wait until (Busy_O = '0');
Data_IO <= (others => 'Z'); -- Data0
nAutoFd_I <= '0'; -- datStb
wait until (Busy_O = '1');
wait for 30 ns;
out_runflag <= Data_IO(6);
nAutoFd_I <= '1';
wait until (Busy_O = '0');
end procedure ReadData;
begin
------------------------------------------------------------------------------------------------
-- Init
test_number <= 0;
wait until tb_ParameterInitFlag;
tb_InitFlag <= true;
load_I <= '0';
RST_I <= '1';
STB_I_port <= '1';
CYC_I_port <= '1';
WE_I_port <= '0';
initial_address_I <= B"01_0000_0000_0000";
biggest_address_I <= B"11_1100_0000_0000";
pause_address_I <= B"00_0000_1000_0000";
enable_I <= '1';
wait for 1.5 * clk_Period;
nSelectIn_I <= '0';
nStrobe_I <= '0';
Data_IO <= (others => '0');
nAutoFd_I <= '1';
nInit_I <= '1';
reset_I <= '1';
wait for 700 ns; -- PLL delay
RST_I <= '0';
wait for 1.0 * clk_Period;
reset_I <= '0';
load_I <= '1';
wait for 1.0 * clk_Period;
-- EPP Mode Negotiation
-- Standar timing and handshake
nStrobe_I <= '1';
wait for 500 ns;
Data_IO <= X"40";
wait for 500 ns;
load_I <= '0';
wait until ADR_O_mem = B"00_0000_1000_0000";
wait for 8.0 * clk_Period;
nSelectIn_I <= '1';
nAutoFd_I <= '0';
wait until (PError_O = '1' and nAck_O = '0' and nFault_O = '1' and Sel_O = '1');
pause_address_I <= B"01_0000_0000_0000";
wait for 20.0 * clk_Period;
enable_I <= '0';
wait for 8.0 * clk_Period;
nStrobe_I <= '0';
wait for 500 ns;
enable_I <= '1';
wait until finish_O = '1';
wait for 2.0 * clk_Period;
nAutoFd_I <= '1';
nStrobe_I <= '1';
wait until (nAck_O = '1' and Sel_O = '1');
tb_InitFlag <= false;
wait;
------------------------------------------------------------------------------------------------
-- Test 1
-- Writing in all control register
-- 00 RunConf_R RW [ | | | | |TScal04|TScal03|TScal02|
-- TScal01|TScal00|TScalEn| TrCh| TrEdg| TrOn| Cont| Start]
--
-- 01 Channels_R RW [ | | | | | | | |
-- | | | | | | RCh01| RCh00]
--
-- 02 BuffSize_R RW [ | |BuffS13|BuffS12|BuffS11|BuffS10|BuffS09|BuffS08|
-- BuffS07|BuffS06|BuffS05|BuffS04|BuffS03|BuffS02|BuffS01|BuffS00]
--
-- 03 TrigLvl_R RW [ | | | | | |TrLvl09|TrLvl08|
-- TrLvl07|TrLvl06|TrLvl05|TrLvl04|TrLvl03|TrLvl02|TrLvl01|TrLvl00]
--
-- 04 TrigOff_R RW [ |TrOff14|TrOff13|TrOff12|TrOff11|TrOff10|TrOff09|TrOff08|
-- TrOff07|TrOff06|TrOff00|TrOff00|TrOff00|TrOff00|TrOff00|TrOff00]
--
-- 05 ADCConf RW [ | | | | ADCS|ADSleep| ADPSEn| ADPS08|
-- ADPS07| ADPS06| ADPS05| ADPS04| ADPS03| ADPS02| ADPS01| ADPS00]
--
-- 08 Data_O R [ErrFlag|RunFlag| | | | DCh00| Dat09| Dat08|
-- Dat07| Dat06| Dat05| Dat04| Dat03| Dat02| Dat01| Dat00]
--
-- 09 Error_O R [ | | | | | | | |
-- | | | | | ErrN02| ErrN01| ErrN00]
test_number <= 1;
end process;
--------------------------------------------------------------------------------------------------
-- Conditional signals
P_mem: process(STB_O_mem, DAT_I_mem, CYC_O_mem, CLK_I, RST_I,i)
WriteData(X"00", X"FFFE", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
WriteData(X"01", X"FFFF", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
WriteData(X"02", X"FFFF", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
WriteData(X"03", X"FFFF", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
WriteData(X"04", X"FFFF", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
begin
if STB_O_mem = '1' and CYC_O_mem = '1' and i = '1' then
ACK_I_mem <= '1';
else
ACK_I_mem <= '0';
end if;
ReadData(runflag, X"00", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
ReadData(runflag,X"01", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
ReadData(runflag, X"02", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
ReadData(runflag, X"03", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
ReadData(runflag, X"04", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
if CLK_I'event and CLK_I = '1' then
if RST_I = '1' then
DAT_I_mem <= (others => '0');
elsif STB_O_mem = '1' and CYC_O_mem = '1' and i = '1' then
DAT_I_mem <= DAT_I_mem + 1;
end if;
end if;
wait for 50 ns;
------------------------------------------------------------------------------------------------
-- Test 2 - DAQ Config
-- Writing in daq config register
test_number <= 2;
if CLK_I'event and CLK_I = '1' then
if RST_I = '1' then
i <= '0';
elsif STB_O_mem = '1' and CYC_O_mem = '1' then
i <= not(i);
end if;
end if;
WriteData(X"05", X"07FF", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
ReadData(runflag, X"05", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
WriteData(X"05", X"0A00", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
ReadData(runflag, X"05", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
wait for 50 ns;
------------------------------------------------------------------------------------------------
-- Test 3 - Test basic
-- daq freq = ctrl freq/2 (default), w/o trigger, w/o skipper, channels 1 and 2,
-- buffer size = 50h, continuous
test_number <= 3;
WriteData(X"01", X"0003", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- Channels_R
WriteData(X"02", X"0050", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- BuffSize_R
WriteData(X"03", X"0000", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigLvl_R
WriteData(X"04", X"0000", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigOff_R
WriteData(X"00", X"0001", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- RunConf_R
ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
while (runflag = '1') loop
ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
end loop;
wait for 50 ns;
------------------------------------------------------------------------------------------------
-- Test 4 - Skipper
-- daq freq = ctrl freq/2 (default), w/o trigger, skipper = 3, channels 1 and 2,
-- buffer size = 80, no continuous
------------------------------------------------------------------------------------------------
-- Test 5 - Trigger - one shot
-- daq freq = ctrl freq/2 (default), trigger channel 1, level 30 %, not continuous, skipper = 5,
-- channels 1 and 2, buffer size = 100
------------------------------------------------------------------------------------------------
-- Test 6 - Trigger
-- daq freq = ctrl freq/2 (default), trigger channel 1, level 30 %, continuous, skipper = 5,
-- channels 1, buffer size = 50
------------------------------------------------------------------------------------------------
-- Test 7 - One channel
-- daq freq = ctrl freq/2 (default), trigger channel 1, level 30 %, continuous, skipper = 5,
-- channels 1, buffer size = 50
------------------------------------------------------------------------------------------------
-- Test 8 - Test write while working
-- daq freq = ctrl freq/2 (default), trigger channel 1, level 30 %, continuous, skipper = 5,
-- channels 1, buffer size = 50
wait for 100 ns;
tb_InitFlag <= false;
wait;
end process;
266,14 → 451,9
use ieee.std_logic_1164.all;
 
-- Additional libraries used by Model Under Test.
-- ...
 
entity testbench is
generic (
MEM_ADD_WIDTH: integer := 14
);
end testbench;
 
architecture tbGeneratedCode of testbench is
298,13 → 478,13
-- Peripherals
signal reset_I: std_logic;
signal pll_clk_I: std_logic;
signal test_number: integer range 0 to 20;
begin
--------------------------------------------------------------------------------------------------
-- Instantiation of Stimulus.
U_stimulus_0 : entity work.stimulus
generic map (
MEM_ADD_WIDTH=> MEM_ADD_WIDTH
)
port map (
-- ADC
adc_data_I => adc_data_I,
326,15 → 506,14
nSelectIn_I => nSelectIn_I,
-- Peripherals
reset_I => reset_I,
pll_clk_I => pll_clk_I
pll_clk_I => pll_clk_I,
test_number => test_number
);
 
--------------------------------------------------------------------------------------------------
-- Instantiation of Model Under Test.
U_outman_0 : entity work.modular_oscilloscope --<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--
generic map (
MEM_ADD_WIDTH=> MEM_ADD_WIDTH
)
U_OSC0 : entity work.modular_oscilloscope --<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--
port map (
-- ADC
adc_data_I => adc_data_I,
/trunk/hdl/ctrl/ctrl.vhd
340,7 → 340,7
------------------------------------------------------------------------------------------------
-- Machine
P_sm_comb: process (present_state, reg_trigger_en, trigger_out_adr, memwr_out_adr, reg_trigger_en,
P_sm_comb: process (present_state, reg_trigger_en, trigger_out_adr, memwr_out_adr,
memwr_in_ack_mem, outmgr_finish, continuous, ack_i_daq)
begin
-- signals from output manager are described in next process
407,7 → 407,7
trigger_reset <= '1';
trigger_en <= '-';
running <= '1';
running <= '1'; -- aviod an ack if there is a read/write from port
strobe_adc <= '0';
426,7 → 426,7
trigger_reset <= '1';
trigger_en <= '-';
running <= '1';
running <= '1'; -- aviod an ack if there is a read/write from port
strobe_adc <= '1';
449,7 → 449,7
trigger_reset <= '1';
trigger_en <= '-';
running <= '1';
running <= '0';
strobe_adc <= '0';
482,10 → 482,11
------------------------------------------------------------------------------------------------
-- Output
P_OUTMGR: process (RST_I_port, stop, CLK_I_port, CLK_I_port, present_state, trigger_act,
P_OUTMGR: process (RST_I_port, stop, CLK_I_port, present_state, trigger_act,
reg_trigger_en, memwr_out_adr, outmgr_en)
begin
if RST_I_port = '1' or present_state = ST_IDLE or present_state = ST_INIT then
-- load must be '1' only for one cycle, enable must be set until the end
if RST_I_port = '1' or present_state /= ST_RUNNING then
outmgr_load <= '0';
outmgr_en <= '0';
elsif CLK_I_port'event and CLK_I_port = '1' then
492,13 → 493,13
if stop = '1' then
outmgr_load <= '0';
outmgr_en <= '0';
elsif outmgr_en = '1' then
outmgr_load <= '0';
elsif present_state = ST_RUNNING and ( trigger_act = '1' or (reg_trigger_en = '0' and
memwr_out_adr /= 0 ) ) then
outmgr_load <= '1';
outmgr_en <= '1';
-- load must be set only one cycle
elsif outmgr_en = '1' then
outmgr_load <= '0';
end if;
end if;
end process;
/trunk/hdl/ctrl/ctrl_pkg.vhd
169,7 → 169,7
);
port(
channels_I: in std_logic_vector(integer(2**real(CHANNEL_WIDTH))-1 downto 0);
channel_number_O: out std_logic_vector(3 downto 0);
channel_number_O: out std_logic_vector(CHANNEL_WIDTH - 1 downto 0);
first_channel_O: out std_logic;
clk_I: in std_logic;
enable_I: in std_logic;
/trunk/hdl/ctrl/channel_selector.vhd
43,7 → 43,7
----------------------------------------------------------------------------------------------------
entity ctrl_channel_selector is
generic(
CHANNEL_WIDTH: integer := 4 -- number of channels 2**CHANNEL_WIDTH, max. 4
CHANNEL_WIDTH: integer := 4 -- number of channels 2**CHANNEL_WIDTH, max. 4
);
port(
channels_I: in std_logic_vector(integer(2**real(CHANNEL_WIDTH))-1 downto 0);
/trunk/hdl/ctrl/address_allocation.vhd
190,7 → 190,8
--------------------------------------------------------------------------------------------------
-- Read asignments
-- if reading registers, do ack, else use internal ack
ACK_O_port <= CYC_I_port and STB_I_port and (not(ADR_I_port(3)) or ACK_I_int or not(running_I));
ACK_O_port <= (CYC_I_port and STB_I_port) and
((not(ADR_I_port(3)) or ACK_I_int or not(running_I)));
--------------------------------------------------------------------------------------------------
225,7 → 226,12
buffer_size_R <= (others => '0');
trigger_level_R <= (others => '0');
trigger_offset_R <= (others => '0');
trigger_channel_R <= (others => '0');
write_in_adc_R <= '0';
adc_conf_R <= (others => '0');
-- Assignments
elsif CYC_I_port = '1' and STB_I_port = '1' and WE_I_port = '1' and ADR_I_port(3) = '0' then
/trunk/hdl/ctrl/output_manager.vhd
3,7 → 3,7
--| UNSL - Argentine
--|
--| File: ctrl_output_manager.vhd
--| Version: 0.5
--| Version: 0.54
--| Tested in: Actel A3PE1500
--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
--|-------------------------------------------------------------------------------------------------
18,6 → 18,7
--| 0.3 | jul-2009 | One level internal buffer and only one clock
--| 0.31 | jul-2009 | Internal WE signals
--| 0.5 | jul-2009 | Architecture completely renovated (reduced)
--| 0.54 | aug-2009 | New finish_O and init flag behavior
----------------------------------------------------------------------------------------------------
 
--|
28,8 → 29,10
 
--==================================================================================================
-- TO DO
 
 
-- NO Speed up address_counter
-- OK Full test of new architecture
-- OK Fix default value of s_finish signal
 
--==================================================================================================
 
 
99,7 → 102,7
 
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
architecture ARCH20 of ctrl_output_manager is
architecture ARCH22 of ctrl_output_manager is
signal address_counter: std_logic_vector(MEM_ADD_WIDTH - 1 downto 0);
signal enable_read: std_logic;
120,6 → 123,7
--------------------------------------------------------------------------------------------------
-- Status signals
-- there is an init signal because in the first read, address_counter may be = to pause_address_I
enable_read <= '1' when enable_I = '1' and WE_I_port = '0' and s_finish = '0' and
(address_counter /= pause_address_I or init = '1')
else '0';
127,36 → 131,43
enable_count <= CYC_I_port and STB_I_port and ACK_I_mem and enable_read;
finish_O <= s_finish;
s_finish <= '1' when address_counter = initial_address_I and init = '0' else
'0';
 
P_finish: process ( CLK_I, RST_I, address_counter, initial_address_I, load_I)
begin
if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
if RST_I = '1' then
s_finish <= '1';
init <= '0';
elsif load_I = '1' then
s_finish <= '0';
init <= '1';
elsif address_counter + 1 = initial_address_I then
s_finish <= '1';
init <= '0';
else
init <= '0';
end if;
end if;
end process;
-- P_finish: process ( CLK_I, RST_I, address_counter, initial_address_I, load_I)
-- begin
-- if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
-- if RST_I = '1' then
-- --s_finish <= '0'; -- !! enable signal must be '0' until load
-- init <= '0';
-- elsif load_I = '1' then
-- --s_finish <= '0';
-- init <= '1';
-- -- elsif address_counter + 1 = initial_address_I then
-- -- s_finish <= '1';
-- -- init <= '0';
-- elsif enable_count = '1' then
-- init <= '0';
-- end if;
-- end if;
-- end process;
--------------------------------------------------------------------------------------------------
-- Address counter
P_count: process(CLK_I, address_counter, enable_count, load_I)
P_count: process(CLK_I, RST_I, address_counter, enable_count, load_I)
begin
if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
if load_I = '1' then
if RST_I = '1' then
address_counter <= (others => '0');
init <= '1';
elsif load_I = '1' then
address_counter <= initial_address_I;
init <= '1';
elsif enable_count = '1' and address_counter >= biggest_address_I then
address_counter <= (others => '0');
elsif enable_count = '1' then
address_counter <= address_counter + 1;
init <= '0';
end if;
end if;
end process;
/trunk/hdl/epp/eppwbn.vhd
92,7 → 92,7
 
U1: eppwbn_ctrl
U_EPPCTRL: eppwbn_ctrl
port map (
nStrobe => s_ctr_nStrobe,
Data => Data,
113,7 → 113,7
);
 
 
U2: eppwbn_epp_side
U_EPPPORT: eppwbn_epp_side
port map (
epp_mode => s_epp_mode,
 
143,7 → 143,7
);
 
 
U3: eppwbn_wbn_side
U_EPPWBN: eppwbn_wbn_side
port map(
inStrobe => s_wb_nStrobe,
iData => Data,
/trunk/hdl/epp/eppwbn_pkg.vhd
287,32 → 287,32
std_logic) ;
end component A3PE_pll;
 
component dual_port_memory_wb is
port(
-- Puerto A (Higer prioriry)
RST_I_a: in std_logic;
CLK_I_a: in std_logic;
DAT_I_a: in std_logic_vector (15 downto 0);
DAT_O_a: out std_logic_vector (15 downto 0);
ADR_I_a: in std_logic_vector (13 downto 0);
CYC_I_a: in std_logic;
STB_I_a: in std_logic;
ACK_O_a: out std_logic ;
WE_I_a: in std_logic;
-- component dual_port_memory_wb is
-- port(
-- -- Puerto A (Higer prioriry)
-- RST_I_a: in std_logic;
-- CLK_I_a: in std_logic;
-- DAT_I_a: in std_logic_vector (15 downto 0);
-- DAT_O_a: out std_logic_vector (15 downto 0);
-- ADR_I_a: in std_logic_vector (13 downto 0);
-- CYC_I_a: in std_logic;
-- STB_I_a: in std_logic;
-- ACK_O_a: out std_logic ;
-- WE_I_a: in std_logic;
-- Puerto B (Lower prioriry)
RST_I_b: in std_logic;
CLK_I_b: in std_logic;
DAT_I_b: in std_logic_vector (15 downto 0);
DAT_O_b: out std_logic_vector (15 downto 0);
ADR_I_b: in std_logic_vector (13 downto 0);
CYC_I_b: in std_logic;
STB_I_b: in std_logic;
ACK_O_b: out std_logic ;
WE_I_b: in std_logic
);
end component dual_port_memory_wb;
-- -- Puerto B (Lower prioriry)
-- RST_I_b: in std_logic;
-- CLK_I_b: in std_logic;
-- DAT_I_b: in std_logic_vector (15 downto 0);
-- DAT_O_b: out std_logic_vector (15 downto 0);
-- ADR_I_b: in std_logic_vector (13 downto 0);
-- CYC_I_b: in std_logic;
-- STB_I_b: in std_logic;
-- ACK_O_b: out std_logic ;
-- WE_I_b: in std_logic
-- );
-- end component dual_port_memory_wb;
end package eppwbn_pkg;
/trunk/hdl/memory/dual_port_memory_wb.vhd
14,6 → 14,7
--|-------------------------------------------------------------------------------------------------
--| File history:
--| 0.1 | jun-2009 | First testing
--| 0.11 | aug-2009 | Corrected error in ACK_O from port B
----------------------------------------------------------------------------------------------------
 
--|
99,7 → 100,7
to_BLKB <= CYC_I_b and STB_I_b and enable_BLK;
to_BLKA <= CYC_I_a and STB_I_a;
enable_BLK <= '1' when ADR_I_a /= ADR_I_b and to_BLKA = '0' else
enable_BLK <= '1' when ADR_I_a /= ADR_I_b or to_BLKA = '0' else
'0';

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