URL
https://opencores.org/ocsvn/nanoblaze/nanoblaze/trunk
Subversion Repositories nanoblaze
Compare Revisions
- This comparison shows the changes necessary to convert path
/nanoblaze
- from Rev 8 to Rev 9
- ↔ Reverse comparison
Rev 8 → Rev 9
/trunk/Circuit/branchStack.vhd
0,0 → 1,89
--############################################################################## |
-- |
-- branchStack |
-- Stack of branch addresses |
-- |
-- This is where the program counter is pushed upon a subroutine call |
-- and popped on return. |
-- |
-- The stack is coded in a way to be mapped into a Block RAM. |
-- |
-------------------------------------------------------------------------------- |
-- |
-- Versions / Authors |
-- 1.0 Francois Corthay first implementation |
-- |
-- Provided under GNU LGPL licence: <http://www.gnu.org/copyleft/lesser.html> |
-- |
-- by the electronics group of "HES-SO//Valais Wallis", in Switzerland: |
-- <http://www.hevs.ch/en/rad-instituts/institut-systemes-industriels/>. |
-- |
-------------------------------------------------------------------------------- |
-- |
-- Hierarchy |
-- Used by "nanoblaze/nanoProcessor". |
-- |
--############################################################################## |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.numeric_std.all; |
|
ENTITY branchStack IS |
GENERIC( |
programCounterBitNb : positive := 10; |
stackPointerBitNb : positive := 5 |
); |
PORT( |
reset : IN std_ulogic; |
clock : IN std_ulogic; |
progCounter : IN unsigned(programCounterBitNb-1 DOWNTO 0); |
prevPC : IN std_ulogic; |
storePC : IN std_ulogic; |
storedProgCounter : OUT unsigned(programCounterBitNb-1 DOWNTO 0) |
); |
|
END branchStack ; |
|
--============================================================================== |
|
ARCHITECTURE RTL OF branchStack IS |
|
subtype progCounterType is unsigned(progCounter'range); |
type progCounterArrayType is array (0 to 2**stackPointerBitNb) of progCounterType; |
signal progCounterArray : progCounterArrayType; |
|
signal writePointer : unsigned(stackPointerBitNb-1 downto 0); |
signal readPointer : unsigned(stackPointerBitNb-1 downto 0); |
|
BEGIN |
------------------------------------------------------------------------------ |
-- stack pointers |
updateStackPointer: process(reset, clock) |
begin |
if reset = '1' then |
writePointer <= (others => '0'); |
elsif rising_edge(clock) then |
if storePC = '1' then |
writePointer <= writePointer + 1; |
elsif prevPC = '1' then |
writePointer <= writePointer - 1; |
end if; |
end if; |
end process updateStackPointer; |
|
readPointer <= writePointer - 1; |
|
------------------------------------------------------------------------------ |
-- program counters stack |
updateStack: process(reset, clock) |
begin |
if rising_edge(clock) then |
if storePc = '1' then |
progCounterArray(to_integer(writePointer)) <= progCounter; |
end if; |
storedProgCounter <= progCounterArray(to_integer(readPointer)); |
end if; |
end process updateStack; |
|
END ARCHITECTURE RTL; |
trunk/Circuit/branchStack.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/Circuit/controller.vhd
===================================================================
--- trunk/Circuit/controller.vhd (nonexistent)
+++ trunk/Circuit/controller.vhd (revision 9)
@@ -0,0 +1,302 @@
+--##############################################################################
+--
+-- controller
+-- Main processor controller
+--
+-- Controls all other blocks: ALU, program counter, stack, …
+--
+--------------------------------------------------------------------------------
+--
+-- Versions / Authors
+-- 1.0 Francois Corthay first implementation
+--
+-- Provided under GNU LGPL licence:
+--
+-- by the electronics group of "HES-SO//Valais Wallis", in Switzerland:
+-- .
+--
+--------------------------------------------------------------------------------
+--
+-- Hierarchy
+-- Used by "nanoblaze/nanoProcessor".
+--
+--##############################################################################
+
+LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+ USE ieee.numeric_std.all;
+
+ENTITY controller IS
+ GENERIC(
+ intCodeBitNb : positive := 5;
+ branchCondBitNb : positive := 3;
+ opCodeBitNb : positive := 5
+ );
+ PORT(
+ reset : IN std_ulogic;
+ clock : IN std_ulogic;
+ en : IN std_ulogic;
+ opCode : IN std_ulogic_vector(opCodeBitNb-1 DOWNTO 0);
+ twoRegInstr : IN std_ulogic;
+ registerFileSel : OUT std_ulogic;
+ instrDataSel : OUT std_ulogic;
+ portInSel : OUT std_ulogic;
+ scratchpadSel : OUT std_ulogic;
+ regWrite : OUT std_ulogic;
+ readStrobe : OUT std_ulogic;
+ writeStrobe : OUT std_uLogic;
+ scratchpadWrite : OUT std_ulogic;
+ branchCond : IN std_ulogic_vector(branchCondBitNb-1 DOWNTO 0);
+ cOut : IN std_ulogic;
+ zero : IN std_ulogic;
+ cIn : OUT std_ulogic;
+ incPC : OUT std_ulogic;
+ loadInstrAddress : OUT std_ulogic;
+ loadStoredPC : OUT std_ulogic;
+ prevPC : OUT std_ulogic;
+ storePC : OUT std_ulogic;
+ intCode : IN std_ulogic_vector(intCodeBitNb-1 DOWNTO 0);
+ int : IN std_ulogic;
+ intAck : OUT std_ulogic
+ );
+
+END controller ;
+
+--==============================================================================
+
+ARCHITECTURE RTL OF controller IS
+
+ signal en1, enInt: std_ulogic;
+
+ constant opCodeLength : integer := 5;
+ subtype opCodeType is std_ulogic_vector(opCodeLength-1 downto 0);
+ constant opLoad : opCodeType := "00000";
+ constant opInput : opCodeType := "00010";
+ constant opFetch : opCodeType := "00011";
+ constant opAnd : opCodeType := "00101";
+ constant opOr : opCodeType := "00110";
+ constant opXor : opCodeType := "00111";
+ constant opTest : opCodeType := "01001";
+ constant opComp : opCodeType := "01010";
+ constant opAdd : opCodeType := "01100";
+ constant opAddCy : opCodeType := "01101";
+ constant opSub : opCodeType := "01110";
+ constant opSubCy : opCodeType := "01111";
+ constant opShRot : opCodeType := "10000";
+ constant opRet : opCodeType := "10101";
+ constant opOutput: opCodeType := "10110";
+ constant opStore : opCodeType := "10111";
+ constant opCall : opCodeType := "11000";
+ constant opJump : opCodeType := "11010";
+ constant opIntF : opCodeType := "11110";
+
+ constant branchConditionLength : integer := 3;
+ subtype branchConditionType is std_ulogic_vector(branchConditionLength-1 downto 0);
+ constant brAw : branchConditionType := "000";
+ constant brZ : branchConditionType := "100";
+ constant brNZ : branchConditionType := "101";
+ constant brC : branchConditionType := "110";
+ constant brNC : branchConditionType := "111";
+
+ signal aluOpSel: std_ulogic;
+ signal regWriteEn: std_ulogic;
+
+ signal flagsEn, flagsEnable: std_ulogic;
+ signal carrySaved: std_ulogic;
+ signal zeroSaved: std_ulogic;
+
+ signal branchEnable1, branchEnable: std_ulogic;
+ signal discardOpCode: std_ulogic;
+
+ signal updateIntFlag: std_ulogic;
+
+BEGIN
+ ------------------------------------------------------------------------------
+ -- Enable signal
+ buildEnable: process(reset, clock)
+ begin
+ if reset = '1' then
+ en1 <= '0';
+ elsif rising_edge(clock) then
+ en1 <= '1';
+ end if;
+ end process buildEnable;
+
+ enInt <= en1 and en; -- don't enable very first instruction twice
+
+ ------------------------------------------------------------------------------
+ -- ALU controls
+ selectdataSource: process(opCode)
+ begin
+ aluOpSel <= '0';
+ portInSel <= '0';
+ scratchpadSel <= '0';
+ case opCode(opCodeLength-1 downto 0) is
+ when opLoad => aluOpSel <= '1';
+ when opInput => portInSel <= '1';
+ when opFetch => scratchpadSel <= '1';
+ when opAnd => aluOpSel <= '1';
+ when opOr => aluOpSel <= '1';
+ when opXor => aluOpSel <= '1';
+ when opTest => aluOpSel <= '1';
+ when opComp => aluOpSel <= '1';
+ when opAdd => aluOpSel <= '1';
+ when opAddCy => aluOpSel <= '1';
+ when opSub => aluOpSel <= '1';
+ when opSubCy => aluOpSel <= '1';
+ when opShRot => aluOpSel <= '1';
+ when others => aluOpSel <= '-';
+ portInSel <= '-';
+ scratchpadSel <= '-';
+ end case;
+ end process selectdataSource;
+
+ registerFileSel <= aluOpSel and twoRegInstr;
+ instrDataSel <= aluOpSel and (not twoRegInstr);
+
+ regWriteEn <= enInt and (not discardOpCode);
+
+ regWriteTable: process(opCode, regWriteEn)
+ begin
+ case opCode(opCodeLength-1 downto 0) is
+ when opLoad => regWrite <= regWriteEn;
+ when opInput => regWrite <= regWriteEn;
+ when opFetch => regWrite <= regWriteEn;
+ when opAnd => regWrite <= regWriteEn;
+ when opOr => regWrite <= regWriteEn;
+ when opXor => regWrite <= regWriteEn;
+ when opAdd => regWrite <= regWriteEn;
+ when opAddCy => regWrite <= regWriteEn;
+ when opSub => regWrite <= regWriteEn;
+ when opSubCy => regWrite <= regWriteEn;
+ when opShRot => regWrite <= regWriteEn;
+ when others => regWrite <= '0';
+ end case;
+ end process regWriteTable;
+
+ ------------------------------------------------------------------------------
+ -- I/O controls
+ readStrobe <= enInt when (opCode = opInput) and (discardOpCode = '0')
+ else '0';
+ writeStrobe <= enInt when (opCode = opOutput) and (discardOpCode = '0')
+ else '0';
+
+ ------------------------------------------------------------------------------
+ -- scratchpad controls
+ scratchpadWrite <= '1' when opCode = opStore else '0';
+
+ ------------------------------------------------------------------------------
+ -- Carry logic
+ flagsEn <= enInt and (not branchEnable);
+
+ flagsEnableTable: process(opCode, flagsEn)
+ begin
+ case opCode(opCodeLength-1 downto 0) is
+ when opAnd => flagsEnable <= flagsEn;
+ when opOr => flagsEnable <= flagsEn;
+ when opXor => flagsEnable <= flagsEn;
+ when opTest => flagsEnable <= flagsEn;
+ when opComp => flagsEnable <= flagsEn;
+ when opAdd => flagsEnable <= flagsEn;
+ when opAddCy => flagsEnable <= flagsEn;
+ when opSub => flagsEnable <= flagsEn;
+ when opSubCy => flagsEnable <= flagsEn;
+ when opShRot => flagsEnable <= flagsEn;
+ when others => flagsEnable <= '0';
+ end case;
+ end process flagsEnableTable;
+
+ saveCarries: process(reset, clock)
+ begin
+ if reset = '1' then
+ carrySaved <= '0';
+ zeroSaved <= '0';
+ elsif rising_edge(clock) then
+ if flagsEnable = '1' then
+ carrySaved <= cOut;
+ zeroSaved <= zero;
+ end if;
+ end if;
+ end process saveCarries;
+
+ cIn <= carrySaved;
+
+ ------------------------------------------------------------------------------
+ -- Program counter controls
+ checkBranchCondition: process(branchCond, zeroSaved, carrySaved)
+ begin
+ case branchCond(branchConditionLength-1 downto 0) is
+ when brAw => branchEnable1 <= '1';
+ when brZ => branchEnable1 <= zeroSaved;
+ when brNZ => branchEnable1 <= not zeroSaved;
+ when brC => branchEnable1 <= carrySaved;
+ when brNC => branchEnable1 <= not carrySaved;
+ when others => branchEnable1 <= '-';
+ end case;
+ end process checkBranchCondition;
+
+ branchEnableTable: process(opCode, branchEnable1, discardOpCode)
+ begin
+ if discardOpCode = '0' then
+ case opCode(opCodeLength-1 downto 0) is
+ when opRet => branchEnable <= branchEnable1;
+ when opCall => branchEnable <= branchEnable1;
+ when opJump => branchEnable <= branchEnable1;
+ when others => branchEnable <= '0';
+ end case;
+ else
+ branchEnable <= '0';
+ end if;
+ end process branchEnableTable;
+
+ progCounterControlTable: process(opCode, enInt, branchEnable)
+ begin
+ incPC <= enInt;
+ loadInstrAddress <= '0';
+ loadStoredPC <= '0';
+ case opCode(opCodeLength-1 downto 0) is
+ when opRet => incPC <= not branchEnable;
+ loadStoredPC <= enInt and branchEnable;
+ when opCall => incPC <= not branchEnable;
+ loadInstrAddress <= enInt and branchEnable;
+ when opJump => incPC <= not branchEnable;
+ loadInstrAddress <= enInt and branchEnable;
+ when others => null;
+ end case;
+ end process progCounterControlTable;
+
+ -- If a branch condition is met, the next operation has to be discarded.
+ -- This is due to the synchronous operation of the program ROM: the
+ -- instructions are provided one clock period after the program counter.
+ -- so while the branch operation is processed, the next instruction is
+ -- already being fetched.
+ delayBranchEnable: process(reset, clock)
+ begin
+ if reset = '1' then
+ discardOpCode <= '0';
+ elsif rising_edge(clock) then
+ discardOpCode <= branchEnable;
+ end if;
+ end process delayBranchEnable;
+
+ ------------------------------------------------------------------------------
+ -- Stack pointer controls
+ pcStackControlTable: process(discardOpCode, opCode, enInt)
+ begin
+ storePC <= '0';
+ prevPC <= '0';
+ if discardOpCode = '0' then
+ case opCode(opCodeLength-1 downto 0) is
+ when opRet => prevPC <= enInt;
+ when opCall => storePC <= enInt;
+ when others => null;
+ end case;
+ end if;
+ end process pcStackControlTable;
+
+
+ ------------------------------------------------------------------------------
+ -- interrupt control
+ updateIntFlag <= '1' when opCode = opIntF else '0';
+
+END ARCHITECTURE RTL;
trunk/Circuit/controller.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/Circuit/aluAndRegs.vhd
===================================================================
--- trunk/Circuit/aluAndRegs.vhd (nonexistent)
+++ trunk/Circuit/aluAndRegs.vhd (revision 9)
@@ -0,0 +1,174 @@
+--##############################################################################
+--
+-- aluAndRegs
+-- ALU and registers
+--
+-- This describes the processor ALU, together with the register file.
+--
+--------------------------------------------------------------------------------
+--
+-- Versions / Authors
+-- 1.0 Francois Corthay first implementation
+--
+-- Provided under GNU LGPL licence:
+--
+-- by the electronics group of "HES-SO//Valais Wallis", in Switzerland:
+-- .
+--
+--------------------------------------------------------------------------------
+--
+-- Hierarchy
+-- Used by "nanoblaze/nanoProcessor".
+--
+--##############################################################################
+
+LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+ USE ieee.numeric_std.all;
+
+ENTITY aluAndRegs IS
+ GENERIC(
+ registerBitNb : positive := 8;
+ registerAddressBitNb : positive := 4;
+ aluCodeBitNb : positive := 5;
+ portAddressBitNb : positive := 8;
+ scratchpadAddressBitNb : natural := 4
+ );
+ PORT(
+ reset : IN std_ulogic;
+ clock : IN std_ulogic;
+ aluCode : IN std_ulogic_vector(aluCodeBitNb-1 DOWNTO 0);
+ addrA : IN unsigned(registerAddressBitNb-1 DOWNTO 0);
+ addrB : IN unsigned(registerAddressBitNb-1 DOWNTO 0);
+ instrData : IN signed(registerBitNb-1 DOWNTO 0);
+ registerFileSel : IN std_ulogic;
+ instrDataSel : IN std_ulogic;
+ portInSel : IN std_ulogic;
+ scratchpadSel : IN std_ulogic;
+ regWrite : IN std_ulogic;
+ cIn : IN std_ulogic;
+ cOut : OUT std_ulogic;
+ zero : OUT std_ulogic;
+ portAddr : OUT unsigned(portAddressBitNb-1 DOWNTO 0);
+ portOut : OUT signed(registerBitNb-1 DOWNTO 0);
+ portIn : IN signed(registerBitNb-1 DOWNTO 0);
+ scratchpadAddr : OUT unsigned(scratchpadAddressBitNb-1 DOWNTO 0);
+ spadOut : OUT signed(registerBitNb-1 DOWNTO 0);
+ spadIn : IN signed(registerBitNb-1 DOWNTO 0)
+ );
+END aluAndRegs ;
+
+--==============================================================================
+
+ARCHITECTURE struct OF aluAndRegs IS
+
+ SIGNAL aluOut : signed(registerBitNb-1 DOWNTO 0);
+ SIGNAL opA : signed(registerBitNb-1 DOWNTO 0);
+ SIGNAL opB : signed(registerBitNb-1 DOWNTO 0);
+ SIGNAL registerFileIn : signed(registerBitNb-1 DOWNTO 0);
+
+
+ COMPONENT alu
+ GENERIC (
+ aluCodeBitNb : positive := 5;
+ dataBitNb : positive := 8
+ );
+ PORT (
+ aluCode : IN std_ulogic_vector(aluCodeBitNb-1 DOWNTO 0);
+ opA : IN signed(dataBitNb-1 DOWNTO 0);
+ opB : IN signed(dataBitNb-1 DOWNTO 0);
+ cIn : IN std_ulogic;
+ aluOut : OUT signed(dataBitNb-1 DOWNTO 0);
+ cOut : OUT std_ulogic;
+ zero : OUT std_ulogic
+ );
+ END COMPONENT;
+
+ COMPONENT aluBOpSelector
+ GENERIC (
+ registerBitNb : positive := 8
+ );
+ PORT (
+ instrData : IN signed(registerBitNb-1 DOWNTO 0);
+ instrDataSel : IN std_ulogic;
+ portIn : IN signed(registerBitNb-1 DOWNTO 0);
+ portInSel : IN std_ulogic;
+ registerFileIn : IN signed(registerBitNb-1 DOWNTO 0);
+ registerFileSel : IN std_ulogic;
+ scratchpadSel : IN std_ulogic;
+ spadIn : IN signed(registerBitNb-1 DOWNTO 0);
+ opB : OUT signed (registerBitNb-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT registerFile
+ GENERIC (
+ registerAddressBitNb : positive := 4;
+ dataBitNb : positive := 8
+ );
+ PORT (
+ clock : IN std_ulogic;
+ reset : IN std_ulogic;
+ addrA : IN unsigned(registerAddressBitNb-1 DOWNTO 0);
+ addrB : IN unsigned(registerAddressBitNb-1 DOWNTO 0);
+ regWrite : IN std_ulogic;
+ registersIn : IN signed(dataBitNb-1 DOWNTO 0);
+ opA : OUT signed(dataBitNb-1 DOWNTO 0);
+ opB : OUT signed(dataBitNb-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+BEGIN
+ I_ALU : alu
+ GENERIC MAP (
+ aluCodeBitNb => aluCodeBitNb,
+ dataBitNb => registerBitNb
+ )
+ PORT MAP (
+ aluCode => aluCode,
+ opA => opA,
+ opB => opB,
+ cIn => cIn,
+ aluOut => aluOut,
+ cOut => cOut,
+ zero => zero
+ );
+
+ I_bSel : aluBOpSelector
+ GENERIC MAP (
+ registerBitNb => registerBitNb
+ )
+ PORT MAP (
+ instrData => instrData,
+ instrDataSel => instrDataSel,
+ portIn => portIn,
+ portInSel => portInSel,
+ registerFileIn => registerFileIn,
+ registerFileSel => registerFileSel,
+ scratchpadSel => scratchpadSel,
+ spadIn => spadIn,
+ opB => opB
+ );
+
+ I_regs : registerFile
+ GENERIC MAP (
+ registerAddressBitNb => registerAddressBitNb,
+ dataBitNb => registerBitNb
+ )
+ PORT MAP (
+ clock => clock,
+ reset => reset,
+ addrA => addrA,
+ addrB => addrB,
+ regWrite => regWrite,
+ registersIn => aluOut,
+ opA => opA,
+ opB => registerFileIn
+ );
+
+ portAddr <= resize(unsigned(registerFileIn), portAddressBitNb);
+ portOut <= opA;
+ scratchpadAddr <= resize(unsigned(registerFileIn), scratchpadAddressBitNb);
+ spadOut <= opA;
+
+END ARCHITECTURE struct;
trunk/Circuit/aluAndRegs.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/Circuit/instructionDecoder.vhd
===================================================================
--- trunk/Circuit/instructionDecoder.vhd (nonexistent)
+++ trunk/Circuit/instructionDecoder.vhd (revision 9)
@@ -0,0 +1,118 @@
+--##############################################################################
+--
+-- InstructionDecoder
+-- Instriction decoder
+--
+-- Provides different parts of the instruction word to differnent blocks.
+--
+--------------------------------------------------------------------------------
+--
+-- Versions / Authors
+-- 1.0 Francois Corthay first implementation
+--
+-- Provided under GNU LGPL licence:
+--
+-- by the electronics group of "HES-SO//Valais Wallis", in Switzerland:
+-- .
+--
+--------------------------------------------------------------------------------
+--
+-- Hierarchy
+-- Used by "nanoblaze/nanoProcessor".
+--
+--##############################################################################
+
+LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+ USE ieee.numeric_std.all;
+
+ENTITY instructionDecoder IS
+ GENERIC(
+ registerBitNb : positive := 8;
+ registerAddressBitNb : positive := 4;
+ aluCodeBitNb : positive := 5;
+ instructionBitNb : positive := 18;
+ programCounterBitNb : positive := 10;
+ opCodeBitNb : positive := 5;
+ branchCondBitNb : positive := 3;
+ intCodeBitNb : positive := 5;
+ spadAddressBitNb : natural := 4;
+ portAddressBitNb : positive := 8
+ );
+ PORT(
+ instruction : IN std_ulogic_vector(instructionBitNb-1 DOWNTO 0);
+ aluCode : OUT std_ulogic_vector(aluCodeBitNb-1 DOWNTO 0);
+ addrA : OUT unsigned(registerAddressBitNb-1 DOWNTO 0);
+ addrB : OUT unsigned(registerAddressBitNb-1 DOWNTO 0);
+ instrData : OUT signed(registerBitNb-1 DOWNTO 0);
+ instrAddress : OUT unsigned(programCounterBitNb-1 DOWNTO 0);
+ opCode : OUT std_ulogic_vector(opCodeBitNb-1 DOWNTO 0);
+ twoRegInstr : OUT std_ulogic;
+ branchCond : OUT std_ulogic_vector(branchCondBitNb-1 DOWNTO 0);
+ intCode : OUT std_ulogic_vector(intCodeBitNb-1 DOWNTO 0);
+ portIndexedSel : OUT std_ulogic;
+ portAddress : OUT unsigned(portAddressBitNb-1 DOWNTO 0);
+ spadIndexedSel : OUT std_ulogic;
+ spadAddress : OUT unsigned(spadAddressBitNb-1 DOWNTO 0)
+ );
+
+END instructionDecoder ;
+
+--==============================================================================
+
+ARCHITECTURE RTL OF instructionDecoder IS
+
+ constant opCodeIndexH : integer := instruction'high;
+ constant opCodeIndexL : integer := opCodeIndexH - opCodeBitNb + 1;
+
+ constant twoRegInstrIndex : integer := opCodeIndexL - 1;
+ constant ioAddrIndexed : integer := twoRegInstrIndex;
+
+ constant addrAIndexH : integer := twoRegInstrIndex - 1;
+ constant addrAIndexL : integer := addrAIndexH - registerAddressBitNb + 1;
+
+ constant immediateDataIndexH : integer := registerBitNb-1;
+ constant immediateDataIndexL : integer := 0;
+ constant addrBIndexH : integer := addrAIndexL - 1;
+ constant addrBIndexL : integer := addrBIndexH - registerAddressBitNb + 1;
+
+ constant aluCodeIndexH : integer := opCodeIndexH;
+ constant aluCodeIndexL : integer := aluCodeIndexH - aluCodeBitNb + 1;
+
+ constant portAddressH : integer := registerBitNb-1;
+ constant portAddressL : integer := portAddressH-portAddressBitNb+1;
+ constant spadAddressH : integer := registerBitNb-1;
+ constant spadAddressL : integer := spadAddressH-spadAddressBitNb+1;
+
+ constant branchCondH : integer := opCodeIndexL-1;
+ constant branchCondL : integer := branchCondH-branchCondBitNb+1;
+
+BEGIN
+ ------------------------------------------------------------------------------
+ -- ALU control
+ aluCode <=
+ instruction(aluCodeIndexH downto aluCodeIndexL)
+ when instruction(aluCodeIndexH) = '0' else
+ '1' & instruction(aluCodeBitNb-2 downto 0);
+ opCode <= instruction(opCodeIndexH downto opCodeIndexL);
+ twoRegInstr <= instruction(twoRegInstrIndex);
+ addrA <= unsigned(instruction(addrAIndexH downto addrAIndexL));
+ addrB <= unsigned(instruction(addrBIndexH downto addrBIndexL));
+ instrData <= signed(instruction(immediateDataIndexH downto immediateDataIndexL));
+
+ ------------------------------------------------------------------------------
+ -- I/O control
+ portIndexedSel <= instruction(ioAddrIndexed);
+ portAddress <= unsigned(instruction(portAddressH downto portAddressL));
+
+ ------------------------------------------------------------------------------
+ -- scratchpad control
+ spadIndexedSel <= instruction(ioAddrIndexed);
+ spadAddress <= unsigned(instruction(spadAddressH downto spadAddressL));
+
+ ------------------------------------------------------------------------------
+ -- branch control
+ branchCond <= instruction(branchCondH downto branchCondL);
+ instrAddress <= unsigned(instruction(instrAddress'range));
+
+END ARCHITECTURE RTL;
trunk/Circuit/instructionDecoder.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/Circuit/programCounter.vhd
===================================================================
--- trunk/Circuit/programCounter.vhd (nonexistent)
+++ trunk/Circuit/programCounter.vhd (revision 9)
@@ -0,0 +1,72 @@
+--##############################################################################
+--
+-- programCounter
+-- Program counter
+--
+-- Addresses the instruction ROM.
+-- Capable of incrementation, jump and function return
+--
+--------------------------------------------------------------------------------
+--
+-- Versions / Authors
+-- 1.0 Francois Corthay first implementation
+--
+-- Provided under GNU LGPL licence:
+--
+-- by the electronics group of "HES-SO//Valais Wallis", in Switzerland:
+-- .
+--
+--------------------------------------------------------------------------------
+--
+-- Hierarchy
+-- Used by "nanoblaze/nanoProcessor".
+--
+--##############################################################################
+
+LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+ USE ieee.numeric_std.all;
+
+ENTITY programCounter IS
+ GENERIC(
+ programCounterBitNb : positive := 10
+ );
+ PORT(
+ reset : IN std_ulogic;
+ clock : IN std_ulogic;
+ instrAddress : IN unsigned(programCounterBitNb-1 DOWNTO 0);
+ storedProgCounter : IN unsigned(programCounterBitNb-1 DOWNTO 0);
+ incPC : IN std_ulogic;
+ loadInstrAddress : IN std_ulogic;
+ loadStoredPC : IN std_ulogic;
+ progCounter : OUT unsigned(programCounterBitNb-1 DOWNTO 0)
+ );
+
+END programCounter ;
+
+--==============================================================================
+
+ARCHITECTURE RTL OF programCounter IS
+
+ signal pCounter: unsigned(progCounter'range);
+
+BEGIN
+
+ updateProgramCounter: process(reset, clock)
+ begin
+ if reset = '1' then
+ pCounter <= (others => '0');
+ elsif rising_edge(clock) then
+ if incPC = '1' then
+ pCounter <= pCounter + 1;
+ elsif loadInstrAddress = '1' then
+ pCounter <= instrAddress;
+ elsif loadStoredPC = '1' then
+ pCounter <= storedProgCounter;
+ end if;
+ end if;
+ end process updateProgramCounter;
+
+ progCounter <= pCounter;
+
+END ARCHITECTURE RTL;
trunk/Circuit/programCounter.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/Circuit/nanoProcessor.vhd
===================================================================
--- trunk/Circuit/nanoProcessor.vhd (revision 8)
+++ trunk/Circuit/nanoProcessor.vhd (revision 9)
@@ -37,18 +37,18 @@
scratchpadAddressBitNb : natural := 4
);
PORT(
- reset => reset,
- clock => clock,
- en => en,
- progCounter => programCounter,
- instruction => instruction,
- dataAddress => dataAddress,
- dataOut => dataOut,
- dataIn => dataIn,
- readStrobe => readStrobe,
- writeStrobe => writeStrobe,
- int => int,
- intAck => intAck
+ reset : IN std_uLogic;
+ clock : IN std_uLogic;
+ en : IN std_uLogic;
+ progCounter : OUT unsigned(programCounterBitNb-1 DOWNTO 0);
+ instruction : IN std_ulogic_vector(instructionBitNb-1 DOWNTO 0);
+ dataAddress : OUT unsigned(addressBitNb-1 DOWNTO 0);
+ dataOut : OUT std_ulogic_vector(registerBitNb-1 DOWNTO 0);
+ dataIn : IN std_ulogic_vector(registerBitNb-1 DOWNTO 0);
+ readStrobe : OUT std_uLogic;
+ writeStrobe : OUT std_uLogic;
+ int : IN std_uLogic;
+ intAck : OUT std_ulogic
);
END nanoProcessor ;
@@ -109,26 +109,26 @@
scratchpadAddressBitNb : natural := 4
);
PORT (
+ reset : IN std_ulogic;
+ clock : IN std_ulogic;
+ aluCode : IN std_ulogic_vector(aluCodeBitNb-1 DOWNTO 0);
addrA : IN unsigned(registerAddressBitNb-1 DOWNTO 0);
addrB : IN unsigned(registerAddressBitNb-1 DOWNTO 0);
- aluCode : IN std_ulogic_vector(aluCodeBitNb-1 DOWNTO 0);
- cIn : IN std_ulogic;
- clock : IN std_ulogic;
instrData : IN signed(registerBitNb-1 DOWNTO 0);
+ registerFileSel : IN std_ulogic;
instrDataSel : IN std_ulogic;
- portIn : IN signed(registerBitNb-1 DOWNTO 0);
portInSel : IN std_ulogic;
+ scratchpadSel : IN std_ulogic;
regWrite : IN std_ulogic;
- registerFileSel : IN std_ulogic;
- reset : IN std_ulogic;
- scratchpadSel : IN std_ulogic;
- spadIn : IN signed(registerBitNb-1 DOWNTO 0);
+ cIn : IN std_ulogic;
cOut : OUT std_ulogic;
+ zero : OUT std_ulogic;
portAddr : OUT unsigned(portAddressBitNb-1 DOWNTO 0);
portOut : OUT signed(registerBitNb-1 DOWNTO 0);
+ portIn : IN signed(registerBitNb-1 DOWNTO 0);
scratchpadAddr : OUT unsigned(scratchpadAddressBitNb-1 DOWNTO 0);
spadOut : OUT signed(registerBitNb-1 DOWNTO 0);
- zero : OUT std_ulogic
+ spadIn : IN signed(registerBitNb-1 DOWNTO 0)
);
END COMPONENT;
@@ -138,12 +138,12 @@
stackPointerBitNb : positive := 5
);
PORT (
+ reset : IN std_ulogic;
clock : IN std_ulogic;
+ progCounter : IN unsigned(programCounterBitNb-1 DOWNTO 0);
prevPC : IN std_ulogic;
- progCounter : IN unsigned(programCounterBitNb-1 DOWNTO 0);
- reset : IN std_ulogic;
storePC : IN std_ulogic;
- storedProgCounter : OUT unsigned(programCounterBitNb-1 DOWNTO 0 )
+ storedProgCounter : OUT unsigned(programCounterBitNb-1 DOWNTO 0)
);
END COMPONENT;
@@ -154,31 +154,31 @@
opCodeBitNb : positive := 5
);
PORT (
- branchCond : IN std_ulogic_vector(branchCondBitNb-1 DOWNTO 0);
- cOut : IN std_ulogic;
+ reset : IN std_ulogic;
clock : IN std_ulogic;
en : IN std_ulogic;
- int : IN std_ulogic;
- intCode : IN std_ulogic_vector(intCodeBitNb-1 DOWNTO 0);
opCode : IN std_ulogic_vector(opCodeBitNb-1 DOWNTO 0);
- reset : IN std_ulogic;
twoRegInstr : IN std_ulogic;
+ registerFileSel : OUT std_ulogic;
+ instrDataSel : OUT std_ulogic;
+ portInSel : OUT std_ulogic;
+ scratchpadSel : OUT std_ulogic;
+ regWrite : OUT std_ulogic;
+ readStrobe : OUT std_ulogic;
+ writeStrobe : OUT std_uLogic;
+ scratchpadWrite : OUT std_ulogic;
+ branchCond : IN std_ulogic_vector(branchCondBitNb-1 DOWNTO 0);
+ cOut : IN std_ulogic;
zero : IN std_ulogic;
cIn : OUT std_ulogic;
incPC : OUT std_ulogic;
- instrDataSel : OUT std_ulogic;
- intAck : OUT std_ulogic;
loadInstrAddress : OUT std_ulogic;
loadStoredPC : OUT std_ulogic;
- portInSel : OUT std_ulogic;
prevPC : OUT std_ulogic;
- readStrobe : OUT std_ulogic;
- regWrite : OUT std_ulogic;
- registerFileSel : OUT std_ulogic;
- scratchpadSel : OUT std_ulogic;
- scratchpadWrite : OUT std_ulogic;
storePC : OUT std_ulogic;
- writeStrobe : OUT std_uLogic
+ intCode : IN std_ulogic_vector(intCodeBitNb-1 DOWNTO 0);
+ int : IN std_ulogic;
+ intAck : OUT std_ulogic
);
END COMPONENT;
@@ -197,19 +197,19 @@
);
PORT (
instruction : IN std_ulogic_vector(instructionBitNb-1 DOWNTO 0);
+ aluCode : OUT std_ulogic_vector(aluCodeBitNb-1 DOWNTO 0);
addrA : OUT unsigned(registerAddressBitNb-1 DOWNTO 0);
addrB : OUT unsigned(registerAddressBitNb-1 DOWNTO 0);
- aluCode : OUT std_ulogic_vector(aluCodeBitNb-1 DOWNTO 0);
+ instrData : OUT signed(registerBitNb-1 DOWNTO 0);
+ instrAddress : OUT unsigned(programCounterBitNb-1 DOWNTO 0);
+ opCode : OUT std_ulogic_vector(opCodeBitNb-1 DOWNTO 0);
+ twoRegInstr : OUT std_ulogic;
branchCond : OUT std_ulogic_vector(branchCondBitNb-1 DOWNTO 0);
- instrAddress : OUT unsigned(programCounterBitNb-1 DOWNTO 0);
- instrData : OUT signed(registerBitNb-1 DOWNTO 0);
intCode : OUT std_ulogic_vector(intCodeBitNb-1 DOWNTO 0);
- opCode : OUT std_ulogic_vector(opCodeBitNb-1 DOWNTO 0);
+ portIndexedSel : OUT std_ulogic;
portAddress : OUT unsigned(portAddressBitNb-1 DOWNTO 0);
- portIndexedSel : OUT std_ulogic;
- spadAddress : OUT unsigned(spadAddressBitNb-1 DOWNTO 0);
spadIndexedSel : OUT std_ulogic;
- twoRegInstr : OUT std_ulogic
+ spadAddress : OUT unsigned(spadAddressBitNb-1 DOWNTO 0)
);
END COMPONENT;
@@ -218,14 +218,14 @@
programCounterBitNb : positive := 10
);
PORT (
+ reset : IN std_ulogic;
clock : IN std_ulogic;
+ instrAddress : IN unsigned(programCounterBitNb-1 DOWNTO 0);
+ storedProgCounter : IN unsigned(programCounterBitNb-1 DOWNTO 0);
incPC : IN std_ulogic;
- instrAddress : IN unsigned(programCounterBitNb-1 DOWNTO 0);
loadInstrAddress : IN std_ulogic;
loadStoredPC : IN std_ulogic;
- reset : IN std_ulogic;
- storedProgCounter : IN unsigned(programCounterBitNb-1 DOWNTO 0);
- progCounter : OUT unsigned(programCounterBitNb-1 DOWNTO 0 )
+ progCounter : OUT unsigned(programCounterBitNb-1 DOWNTO 0)
);
END COMPONENT;
@@ -235,11 +235,11 @@
spadAddressBitNb : natural := 4
);
PORT (
+ reset : IN std_ulogic;
+ clock : IN std_ulogic;
addr : IN unsigned(spadAddressBitNb-1 DOWNTO 0);
- clock : IN std_ulogic;
+ write : IN std_ulogic;
dataIn : IN signed(registerBitNb-1 DOWNTO 0);
- reset : IN std_ulogic;
- write : IN std_ulogic;
dataOut : OUT signed(registerBitNb-1 DOWNTO 0 )
);
END COMPONENT;
@@ -254,26 +254,26 @@
scratchpadAddressBitNb => scratchpadAddressBitNb
)
PORT MAP (
+ reset => reset,
+ clock => clock,
+ aluCode => aluCode,
addrA => addrA,
addrB => addrB,
- aluCode => aluCode,
- cIn => cIn,
- clock => clock,
instrData => instrData,
+ registerFileSel => registerFileSel,
instrDataSel => instrDataSel,
- portIn => portIn,
portInSel => portInSel,
+ scratchpadSel => scratchpadSel,
regWrite => regWrite,
- registerFileSel => registerFileSel,
- reset => reset,
- scratchpadSel => scratchpadSel,
- spadIn => spadIn,
+ cIn => cIn,
cOut => cOut,
+ zero => zero,
portAddr => portRegAddress,
portOut => portOut,
+ portIn => portIn,
scratchpadAddr => spadRegAddress,
spadOut => spadOut,
- zero => zero
+ spadIn => spadIn
);
I_BR : branchStack
@@ -282,10 +282,10 @@
stackPointerBitNb => stackPointerBitNb
)
PORT MAP (
+ reset => reset,
clock => clock,
+ progCounter => progCounter_int,
prevPC => prevPC,
- progCounter => progCounter_int,
- reset => reset,
storePC => storePC,
storedProgCounter => storedProgCounter
);
@@ -297,31 +297,31 @@
opCodeBitNb => opCodeBitNb
)
PORT MAP (
- branchCond => branchCond,
- cOut => cOut,
+ reset => reset,
clock => clock,
en => en,
- int => int,
- intCode => intCode,
opCode => opCode,
- reset => reset,
twoRegInstr => twoRegInstr,
+ registerFileSel => registerFileSel,
+ instrDataSel => instrDataSel,
+ portInSel => portInSel,
+ scratchpadSel => scratchpadSel,
+ regWrite => regWrite,
+ readStrobe => readStrobe,
+ writeStrobe => writeStrobe
+ scratchpadWrite => scratchpadWrite,
+ branchCond => branchCond,
+ cOut => cOut,
zero => zero,
cIn => cIn,
incPC => incPC,
- instrDataSel => instrDataSel,
- intAck => intAck,
loadInstrAddress => loadInstrAddress,
loadStoredPC => loadStoredPC,
- portInSel => portInSel,
prevPC => prevPC,
- readStrobe => readStrobe,
- regWrite => regWrite,
- registerFileSel => registerFileSel,
- scratchpadSel => scratchpadSel,
- scratchpadWrite => scratchpadWrite,
storePC => storePC,
- writeStrobe => writeStrobe
+ intCode => intCode,
+ int => int,
+ intAck => intAck
);
I_instr : instructionDecoder
@@ -339,19 +339,19 @@
)
PORT MAP (
instruction => instruction,
+ aluCode => aluCode,
addrA => addrA,
addrB => addrB,
- aluCode => aluCode,
+ instrData => instrData,
+ instrAddress => instrAddress,
+ opCode => opCode,
+ twoRegInstr => twoRegInstr,
branchCond => branchCond,
- instrAddress => instrAddress,
- instrData => instrData,
intCode => intCode,
- opCode => opCode,
+ portIndexedSel => portIndexedSel,
portAddress => portInstrAddress,
- portIndexedSel => portIndexedSel,
- spadAddress => spadInstrAddress,
spadIndexedSel => spadIndexedSel,
- twoRegInstr => twoRegInstr
+ spadAddress => spadInstrAddress
);
I_PC : programCounter
@@ -359,13 +359,13 @@
programCounterBitNb => programCounterBitNb
)
PORT MAP (
+ reset => reset,
clock => clock,
+ instrAddress => instrAddress,
+ storedProgCounter => storedProgCounter,
incPC => incPC,
- instrAddress => instrAddress,
loadInstrAddress => loadInstrAddress,
loadStoredPC => loadStoredPC,
- reset => reset,
- storedProgCounter => storedProgCounter,
progCounter => progCounter_int
);
@@ -377,11 +377,11 @@
spadAddressBitNb => scratchpadAddressBitNb
)
PORT MAP (
+ reset => reset,
+ clock => clock,
addr => spadAddress,
- clock => clock,
+ write => scratchpadWrite,
dataIn => spadOut,
- reset => reset,
- write => scratchpadWrite,
dataOut => spadIn
);
END GENERATE generate_scratchpad;
/trunk/Circuit/scratchpad.vhd
0,0 → 1,67
--############################################################################## |
-- |
-- scratchpad |
-- The scratchpad as defined in version 3 |
-- |
-- This corresponds to a simple RAM. |
-- |
-------------------------------------------------------------------------------- |
-- |
-- Versions / Authors |
-- 1.0 Francois Corthay first implementation |
-- |
-- Provided under GNU LGPL licence: <http://www.gnu.org/copyleft/lesser.html> |
-- |
-- by the electronics group of "HES-SO//Valais Wallis", in Switzerland: |
-- <http://www.hevs.ch/en/rad-instituts/institut-systemes-industriels/>. |
-- |
-------------------------------------------------------------------------------- |
-- |
-- Hierarchy |
-- Used by "nanoblaze/nanoProcessor". |
-- |
--############################################################################## |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.numeric_std.all; |
|
ENTITY scratchpad IS |
GENERIC( |
registerBitNb : positive := 8; |
spadAddressBitNb : natural := 4 |
); |
PORT( |
reset : IN std_ulogic; |
clock : IN std_ulogic; |
addr : IN unsigned(spadAddressBitNb-1 DOWNTO 0); |
write : IN std_ulogic; |
dataIn : IN signed(registerBitNb-1 DOWNTO 0); |
dataOut : OUT signed(registerBitNb-1 DOWNTO 0 ) |
); |
|
END scratchpad ; |
|
--============================================================================== |
|
ARCHITECTURE RTL OF scratchpad IS |
|
subtype memoryWordType is signed(dataOut'range); |
type memoryArrayType is array (0 to 2**addr'length-1) of memoryWordType; |
|
signal memoryArray : memoryArrayType; |
|
BEGIN |
|
process (clock) |
begin |
if rising_edge(clock) then |
if write = '1' then |
memoryArray(to_integer(addr)) <= dataIn; |
end if; |
end if; |
end process; |
|
dataOut <= memoryArray(to_integer(addr)); |
|
END ARCHITECTURE RTL; |
trunk/Circuit/scratchpad.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property