Subversion Repositories natalius_8bit_risc

/trunk/impl_prj/impl_prj.gise File deleted

/trunk/impl_prj/impl_prj.xise File deleted

/trunk/impl_prj/iseconfig/pong_top_level.xreport File deleted

/trunk/impl_prj/iseconfig/impl_prj.projectmgr File deleted

/trunk/impl_prj/pong_top_level.bit Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/trunk/impl_prj/pong_top_level.bit

trunk/impl_prj/pong_top_level.bit Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/impl_prj/pong_top_level_summary.html =================================================================== --- trunk/impl_prj/pong_top_level_summary.html (revision 11) +++ trunk/impl_prj/pong_top_level_summary.html (nonexistent) @@ -1,79 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

pong_top_level Project Status
Project File:	impl_prj.xise	Parser Errors:	No Errors
Module Name:	pong_top_level	Implementation State:	New
Target Device:	xc3s1600e-4fg320	Errors:
Product Version:	ISE 12.4	Warnings:
Design Goal:	Balanced	Routing Results:	-
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:		Final Timing Score:

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Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report
Translation Report
Map Report
Place and Route Report
Power Report
Post-PAR Static Timing Report
Bitgen Report

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Secondary Reports			[-]
Report Name	Status	Generated

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Date Generated: 06/04/2012 - 20:49:22 - \ No newline at end of file Index: trunk/impl_prj/_xmsgs/pn_parser.xmsgs =================================================================== --- trunk/impl_prj/_xmsgs/pn_parser.xmsgs (revision 11) +++ trunk/impl_prj/_xmsgs/pn_parser.xmsgs (nonexistent) @@ -1,48 +0,0 @@ - - - - - - - - - - -Analyzing Verilog file \"C:/natalius/mem_video.v\" into library work - - -Analyzing Verilog file \"C:/natalius/memram.v\" into library work - - -Analyzing Verilog file \"C:/natalius/pong_top_level.v\" into library work - - -Analyzing Verilog file \"C:/natalius/processor core/ALU.v\" into library work - - -Analyzing Verilog file \"C:/natalius/processor core/LIFO.v\" into library work - - -Analyzing Verilog file \"C:/natalius/processor core/control_unit.v\" into library work - - -Analyzing Verilog file \"C:/natalius/processor core/data_path.v\" into library work - - -Analyzing Verilog file \"C:/natalius/processor core/instruction_memory.v\" into library work - - -Analyzing Verilog file \"C:/natalius/processor core/natalius_processor.v\" into library work - - -Analyzing Verilog file \"C:/natalius/processor core/regfile.v\" into library work - - -Analyzing Verilog file \"C:/natalius/processor core/shiftbyte.v\" into library work - - -Analyzing Verilog file \"C:/natalius/vga_control.v\" into library work - - - -