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URL https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk

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  • This comparison shows the changes necessary to convert path 
    /oms8051mini/trunk/rtl/8051
    from Rev 11 to Rev 18
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Rev 11 → Rev 18

/oc8051_memory_interface.v
14,7 → 14,9
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//////////////////////////////////////////////////////////////////////
//// v0.0 - Dinesh A, 17th Dec 2016
//// 1. External ROM Interface Removed
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
130,10 → 132,6
//internal
idat_onchip,
 
//external
iack_i,
istb_o,
idat_i,
 
//external data ram
dadr_o,
177,7 → 175,6
sfr,
acc,
sp_w;
input [31:0] idat_i;
 
output bit_out,
mem_wait,
203,7 → 200,6
// rom_addr_sel
//
/////////////////////////////
input iack_i;
input [7:0] des_acc,
des1,
des2;
269,8 → 265,7
 
input [31:0] idat_onchip;
 
output int_ack,
istb_o;
output int_ack;
 
output [7:0] op1_out,
op3_out,
356,12 → 351,9
assign wr_o = wr_i;
assign wr_bit_o = wr_bit_i;
 
//assign mem_wait = dmem_wait || imem_wait || pc_wr_r;
assign mem_wait = dmem_wait || imem_wait || pc_wr_r2;
//assign mem_wait = dmem_wait || imem_wait;
assign istb_o = (istb || (istb_t & !iack_i)) && !dstb_o && !ea_rom_sel;
 
assign pc_wait = rd && (ea_rom_sel || (!istb_t && iack_i));
assign pc_wait = rd ;
 
assign wr_dat = des1;
 
400,7 → 392,7
//
/////////////////////////////
 
always @(rd_sel or sp or ri or rn or imm or dadr_o[15:0] or bank)
always @(*)
begin
case (rd_sel) /* synopsys full_case parallel_case */
`OC8051_RRS_RN : rd_addr = {3'h0, rn};
412,7 → 404,6
`OC8051_RRS_DPTR : rd_addr = `OC8051_SFR_DPTR_LO;
`OC8051_RRS_PSW : rd_addr = `OC8051_SFR_PSW;
`OC8051_RRS_ACC : rd_addr = `OC8051_SFR_ACC;
// default : rd_addr = 2'bxx;
endcase
 
end
420,7 → 411,7
 
//
//
always @(wr_sel or sp_w or rn_r or imm_r or ri_r or imm2_r or op1_r or dadr_o[15:0])
always @(*)
begin
case (wr_sel) /* synopsys full_case parallel_case */
`OC8051_RWS_RN : wr_addr = {3'h0, rn_r};
457,7 → 448,6
// output address is alu destination
// (instructions MOVC)
 
//assign iadr_o = (istb_t & !iack_i) ? iadr_t : pc_out;
assign iadr_o = (istb_t) ? iadr_t : pc_out;
 
 
476,10 → 466,7
imem_wait <= #1 1'b0;
end else if (!imem_wait && istb_t) begin
istb_t <= #1 1'b0;
end else if (iack_i) begin
imem_wait <= #1 1'b0;
idat_ir <= #1 idat_i [23:0];
end
end
end
 
/////////////////////////////
549,8 → 536,8
if (rst) begin
idat_cur <= #1 32'h0;
idat_old <= #1 32'h0;
end else if ((iack_i | ea_rom_sel) & (inc_pc | pc_wr_r2)) begin
idat_cur <= #1 ea_rom_sel ? idat_onchip : idat_i;
end else if (inc_pc || pc_wr_r2) begin
idat_cur <= #1 idat_onchip;
idat_old <= #1 idat_cur;
end
 
562,7 → 549,7
cdata <= #1 8'h00;
cdone <= #1 1'b0;
end else if (istb_t) begin
cdata <= #1 ea_rom_sel ? idat_onchip[7:0] : idat_i[7:0];
cdata <= #1 idat_onchip[7:0] ;
cdone <= #1 1'b1;
end else begin
cdone <= #1 1'b0;
569,7 → 556,7
end
end
 
always @(op_pos or idat_cur or idat_old)
always @(*)
begin
case (op_pos) /* synopsys parallel_case */
3'b000: begin
605,12 → 592,7
endcase
end
 
/*assign op1 = ea_rom_sel ? idat_onchip[7:0] : op1_xt;
assign op2 = ea_rom_sel ? idat_onchip[15:8] : op2_xt;
assign op3 = ea_rom_sel ? idat_onchip[23:16] : op3_xt;*/
 
 
always @(dack_ir or ddat_ir or op1_o or iram_out or cdone or cdata)
always @(*)
if (dack_ir)
op1_out = ddat_ir;
else if (cdone)
621,13 → 603,9
assign op3_out = (rd) ? op3_o : op3_buff;
assign op2_out = (rd) ? op2_o : op2_buff;
 
always @(idat_i or iack_i or idat_ir or rd)
always @(*)
begin
if (iack_i) begin
op1_xt = idat_i[7:0];
op2_xt = idat_i[15:8];
op3_xt = idat_i[23:16];
end else if (!rd) begin
if (!rd) begin
op1_xt = idat_ir[7:0];
op2_xt = idat_ir[15:8];
op3_xt = idat_ir[23:16];
641,9 → 619,9
 
//
// in case of interrupts
always @(op1 or op2 or op3 or int_ack_t or int_vec_buff or iack_i or ea_rom_sel)
always @(*)
begin
if (int_ack_t && (iack_i || ea_rom_sel)) begin
if (int_ack_t) begin
op1_o = `OC8051_LCALL;
op2_o = 8'h00;
op3_o = int_vec_buff;
680,7 → 658,7
//
/////////////////////////////
 
always @(op1_out)
always @(*)
begin
casex (op1_out) /* synopsys parallel_case */
`OC8051_ACALL : op_length = 2'h2;
755,92 → 733,7
endcase
end
 
/*
always @(posedge clk or posedge rst)
begin
if (rst) begin
op_length = 2'h2;
// end else if (pc_wait) begin
end else begin
casex (op1_out)
`OC8051_ACALL : op_length <= #1 2'h2;
`OC8051_AJMP : op_length <= #1 2'h2;
 
//op_code [7:3]
`OC8051_CJNE_R : op_length <= #1 2'h3;
`OC8051_DJNZ_R : op_length <= #1 2'h2;
`OC8051_MOV_DR : op_length <= #1 2'h2;
`OC8051_MOV_CR : op_length <= #1 2'h2;
`OC8051_MOV_RD : op_length <= #1 2'h2;
 
//op_code [7:1]
`OC8051_CJNE_I : op_length <= #1 2'h3;
`OC8051_MOV_ID : op_length <= #1 2'h2;
`OC8051_MOV_DI : op_length <= #1 2'h2;
`OC8051_MOV_CI : op_length <= #1 2'h2;
 
//op_code [7:0]
`OC8051_ADD_D : op_length <= #1 2'h2;
`OC8051_ADD_C : op_length <= #1 2'h2;
`OC8051_ADDC_D : op_length <= #1 2'h2;
`OC8051_ADDC_C : op_length <= #1 2'h2;
`OC8051_ANL_D : op_length <= #1 2'h2;
`OC8051_ANL_C : op_length <= #1 2'h2;
`OC8051_ANL_DD : op_length <= #1 2'h2;
`OC8051_ANL_DC : op_length <= #1 2'h3;
`OC8051_ANL_B : op_length <= #1 2'h2;
`OC8051_ANL_NB : op_length <= #1 2'h2;
`OC8051_CJNE_D : op_length <= #1 2'h3;
`OC8051_CJNE_C : op_length <= #1 2'h3;
`OC8051_CLR_B : op_length <= #1 2'h2;
`OC8051_CPL_B : op_length <= #1 2'h2;
`OC8051_DEC_D : op_length <= #1 2'h2;
`OC8051_DJNZ_D : op_length <= #1 2'h3;
`OC8051_INC_D : op_length <= #1 2'h2;
`OC8051_JB : op_length <= #1 2'h3;
`OC8051_JBC : op_length <= #1 2'h3;
`OC8051_JC : op_length <= #1 2'h2;
`OC8051_JNB : op_length <= #1 2'h3;
`OC8051_JNC : op_length <= #1 2'h2;
`OC8051_JNZ : op_length <= #1 2'h2;
`OC8051_JZ : op_length <= #1 2'h2;
`OC8051_LCALL : op_length <= #1 2'h3;
`OC8051_LJMP : op_length <= #1 2'h3;
`OC8051_MOV_D : op_length <= #1 2'h2;
`OC8051_MOV_C : op_length <= #1 2'h2;
`OC8051_MOV_DA : op_length <= #1 2'h2;
`OC8051_MOV_DD : op_length <= #1 2'h3;
`OC8051_MOV_CD : op_length <= #1 2'h3;
`OC8051_MOV_BC : op_length <= #1 2'h2;
`OC8051_MOV_CB : op_length <= #1 2'h2;
`OC8051_MOV_DP : op_length <= #1 2'h3;
`OC8051_ORL_D : op_length <= #1 2'h2;
`OC8051_ORL_C : op_length <= #1 2'h2;
`OC8051_ORL_AD : op_length <= #1 2'h2;
`OC8051_ORL_CD : op_length <= #1 2'h3;
`OC8051_ORL_B : op_length <= #1 2'h2;
`OC8051_ORL_NB : op_length <= #1 2'h2;
`OC8051_POP : op_length <= #1 2'h2;
`OC8051_PUSH : op_length <= #1 2'h2;
`OC8051_SETB_B : op_length <= #1 2'h2;
`OC8051_SJMP : op_length <= #1 2'h2;
`OC8051_SUBB_D : op_length <= #1 2'h2;
`OC8051_SUBB_C : op_length <= #1 2'h2;
`OC8051_XCH_D : op_length <= #1 2'h2;
`OC8051_XRL_D : op_length <= #1 2'h2;
`OC8051_XRL_C : op_length <= #1 2'h2;
`OC8051_XRL_AD : op_length <= #1 2'h2;
`OC8051_XRL_CD : op_length <= #1 2'h3;
default: op_length <= #1 2'h1;
endcase
//
//in case of instructions that use more than one clock hold current pc
// end else begin
// pc= pc_buf;
end
end
*/
 
assign inc_pc = ((op_pos[2] | (&op_pos[1:0])) & rd) | pc_wr_r2;
 
always @(posedge rst or posedge clk)
848,19 → 741,10
if (rst) begin
op_pos <= #1 3'h0;
end else if (pc_wr_r2) begin
op_pos <= #1 3'h4;// - op_length;////****??????????
/* end else if (inc_pc & rd) begin
op_pos[2] <= #1 op_pos[2] & !op_pos[1] & op_pos[0] & (&op_length);
op_pos[1:0] <= #1 op_pos[1:0] + op_length;
// op_pos <= #1 {1'b0, op_pos[1:0]} + {1'b0, op_length};
end else if (rd) begin
op_pos <= #1 op_pos + {1'b0, op_length};
end*/
op_pos <= #1 3'h4;
end else if (inc_pc & rd) begin
op_pos[2] <= #1 op_pos[2] & !op_pos[1] & op_pos[0] & (&op_length);
op_pos[1:0] <= #1 op_pos[1:0] + op_length;
// op_pos <= #1 {1'b0, op_pos[1:0]} + {1'b0, op_length};
// end else if (istb & rd) begin
end else if (rd) begin
op_pos <= #1 op_pos + {1'b0, op_length};
end
876,7 → 760,7
end else if (intr) begin
int_ack_t <= #1 1'b1;
int_vec_buff <= #1 int_v;
end else if (rd && (ea_rom_sel || iack_i) && !pc_wr_r2) int_ack_t <= #1 1'b0;
end else if (rd && !pc_wr_r2) int_ack_t <= #1 1'b0;
 
always @(posedge clk or posedge rst)
if (rst) int_ack_buff <= #1 1'b0;
922,10 → 806,6
end else pcs_result = pc + {8'h00, pcs_source};
end
 
//assign pc = pc_buf - {13'h0, op_pos[2] | inc_pc_r, op_pos[1:0]}; ////******???
//assign pc = pc_buf - 16'h8 + {13'h0, op_pos}; ////******???
//assign pc = pc_buf - 16'h8 + {13'h0, op_pos} + {14'h0, op_length};
 
always @(posedge clk or posedge rst)
begin
if (rst)
975,160 → 855,6
else if (dack_i)
ddat_ir <= #1 ddat_i;
 
/*
 
always @(pc_buf or op1_out or pc_wait or int_buff or int_buff1 or ea_rom_sel or iack_i)
begin
if (int_buff || int_buff1) begin
//
//in case of interrupt hold valut, to be written to stack
pc= pc_buf;
// end else if (pis_l) begin
// pc = {pc_buf[22:8], alu[7:0]};
end else if (pc_wait) begin
casex (op1_out)
`OC8051_ACALL : pc= pc_buf + 16'h2;
`OC8051_AJMP : pc= pc_buf + 16'h2;
 
//op_code [7:3]
`OC8051_CJNE_R : pc= pc_buf + 16'h3;
`OC8051_DJNZ_R : pc= pc_buf + 16'h2;
`OC8051_MOV_DR : pc= pc_buf + 16'h2;
`OC8051_MOV_CR : pc= pc_buf + 16'h2;
`OC8051_MOV_RD : pc= pc_buf + 16'h2;
 
//op_code [7:1]
`OC8051_CJNE_I : pc= pc_buf + 16'h3;
`OC8051_MOV_ID : pc= pc_buf + 16'h2;
`OC8051_MOV_DI : pc= pc_buf + 16'h2;
`OC8051_MOV_CI : pc= pc_buf + 16'h2;
 
//op_code [7:0]
`OC8051_ADD_D : pc= pc_buf + 16'h2;
`OC8051_ADD_C : pc= pc_buf + 16'h2;
`OC8051_ADDC_D : pc= pc_buf + 16'h2;
`OC8051_ADDC_C : pc= pc_buf + 16'h2;
`OC8051_ANL_D : pc= pc_buf + 16'h2;
`OC8051_ANL_C : pc= pc_buf + 16'h2;
`OC8051_ANL_DD : pc= pc_buf + 16'h2;
`OC8051_ANL_DC : pc= pc_buf + 16'h3;
`OC8051_ANL_B : pc= pc_buf + 16'h2;
`OC8051_ANL_NB : pc= pc_buf + 16'h2;
`OC8051_CJNE_D : pc= pc_buf + 16'h3;
`OC8051_CJNE_C : pc= pc_buf + 16'h3;
`OC8051_CLR_B : pc= pc_buf + 16'h2;
`OC8051_CPL_B : pc= pc_buf + 16'h2;
`OC8051_DEC_D : pc= pc_buf + 16'h2;
`OC8051_DJNZ_D : pc= pc_buf + 16'h3;
`OC8051_INC_D : pc= pc_buf + 16'h2;
`OC8051_JB : pc= pc_buf + 16'h3;
`OC8051_JBC : pc= pc_buf + 16'h3;
`OC8051_JC : pc= pc_buf + 16'h2;
`OC8051_JNB : pc= pc_buf + 16'h3;
`OC8051_JNC : pc= pc_buf + 16'h2;
`OC8051_JNZ : pc= pc_buf + 16'h2;
`OC8051_JZ : pc= pc_buf + 16'h2;
`OC8051_LCALL : pc= pc_buf + 16'h3;
`OC8051_LJMP : pc= pc_buf + 16'h3;
`OC8051_MOV_D : pc= pc_buf + 16'h2;
`OC8051_MOV_C : pc= pc_buf + 16'h2;
`OC8051_MOV_DA : pc= pc_buf + 16'h2;
`OC8051_MOV_DD : pc= pc_buf + 16'h3;
`OC8051_MOV_CD : pc= pc_buf + 16'h3;
`OC8051_MOV_BC : pc= pc_buf + 16'h2;
`OC8051_MOV_CB : pc= pc_buf + 16'h2;
`OC8051_MOV_DP : pc= pc_buf + 16'h3;
`OC8051_ORL_D : pc= pc_buf + 16'h2;
`OC8051_ORL_C : pc= pc_buf + 16'h2;
`OC8051_ORL_AD : pc= pc_buf + 16'h2;
`OC8051_ORL_CD : pc= pc_buf + 16'h3;
`OC8051_ORL_B : pc= pc_buf + 16'h2;
`OC8051_ORL_NB : pc= pc_buf + 16'h2;
`OC8051_POP : pc= pc_buf + 16'h2;
`OC8051_PUSH : pc= pc_buf + 16'h2;
`OC8051_SETB_B : pc= pc_buf + 16'h2;
`OC8051_SJMP : pc= pc_buf + 16'h2;
`OC8051_SUBB_D : pc= pc_buf + 16'h2;
`OC8051_SUBB_C : pc= pc_buf + 16'h2;
`OC8051_XCH_D : pc= pc_buf + 16'h2;
`OC8051_XRL_D : pc= pc_buf + 16'h2;
`OC8051_XRL_C : pc= pc_buf + 16'h2;
`OC8051_XRL_AD : pc= pc_buf + 16'h2;
`OC8051_XRL_CD : pc= pc_buf + 16'h3;
default: pc= pc_buf + 16'h1;
endcase
//
//in case of instructions that use more than one clock hold current pc
end else begin
pc= pc_buf;
end
end
 
 
//
//interrupt buffer
always @(posedge clk or posedge rst)
if (rst) begin
int_buff1 <= #1 1'b0;
end else begin
int_buff1 <= #1 int_buff;
end
 
always @(posedge clk or posedge rst)
if (rst) begin
int_buff <= #1 1'b0;
end else if (intr) begin
int_buff <= #1 1'b1;
end else if (pc_wait)
int_buff <= #1 1'b0;
 
wire [7:0] pcs_source;
reg [15:0] pcs_result;
reg pcs_cy;
 
assign pcs_source = pc_wr_sel[0] ? op3_out : op2_out;
 
always @(pcs_source or pc or pcs_cy)
begin
if (pcs_source[7]) begin
{pcs_cy, pcs_result[7:0]} = {1'b0, pc[7:0]} + {1'b0, pcs_source};
pcs_result[15:8] = pc[15:8] - {7'h0, !pcs_cy};
end else pcs_result = pc + {8'h00, pcs_source};
end
 
 
always @(posedge clk or posedge rst)
begin
if (rst) begin
pc_buf <= #1 `OC8051_RST_PC;
end else begin
if (pc_wr) begin
//
//case of writing new value to pc (jupms)
case (pc_wr_sel)
`OC8051_PIS_ALU: pc_buf <= #1 alu;
`OC8051_PIS_AL: pc_buf[7:0] <= #1 alu[7:0];
`OC8051_PIS_AH: pc_buf[15:8] <= #1 alu[7:0];
`OC8051_PIS_I11: pc_buf[10:0] <= #1 {op1_out[7:5], op2_out};
`OC8051_PIS_I16: pc_buf <= #1 {op2_out, op3_out};
`OC8051_PIS_SO1: pc_buf <= #1 pcs_result;
`OC8051_PIS_SO2: pc_buf <= #1 pcs_result;
endcase
end else
//
//or just remember current
pc_buf <= #1 pc;
end
end
 
 
always @(posedge clk or posedge rst)
if (rst)
ddat_ir <= #1 8'h00;
else if (dack_i)
ddat_ir <= #1 ddat_i;
*/
 
////////////////////////
always @(posedge clk or posedge rst)
if (rst) begin
/oc8051_top.v
15,8 → 15,8
//// - Simon Teran, simont@opencores.org ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//////////////////////////////////////////////////////////////////////
// v0.0 - Dinesh A, 8th Dec 2016
// 1. External ROM Interface Removed
//// v0.0 - Dinesh A, 8th Dec 2016
//// 1. External ROM Interface Removed
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
343,10 → 343,6
 
//
// cpu to cache/wb_interface
wire iack_i,
istb_o,
icyc_o;
wire [31:0] idat_i;
wire [15:0] iadr_o;
 
 
517,7 → 513,6
 
 
 
assign icyc_o = istb_o;
//
//
oc8051_memory_interface oc8051_memory_interface1(
543,10 → 538,7
.iram_out (ram_out ),
 
// external instrauction rom
.iack_i (iack_i ),
.iadr_o (iadr_o ),
.idat_i (idat_i ),
.istb_o (istb_o ),
 
// internal instruction rom
.idat_onchip (idat_onchip ),
694,9 → 686,6
`endif
 
 
// EXTERNAL ROM OPTION is removed
assign idat_i = 'h0 ;
assign iack_i = 'h0 ;
 
`ifdef OC8051_SIMULATION
 

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