URL
https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk
Subversion Repositories oms8051mini
Compare Revisions
- This comparison shows the changes necessary to convert path
/oms8051mini/trunk/rtl/clkgen
- from Rev 2 to Rev 25
- ↔ Reverse comparison
Rev 2 → Rev 25
/clkgen.v
17,6 → 17,9
//// Revision : Nov 26, 2016 //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// v0.0 - Dinesh A, 5th Jan 2017 |
//// 1. Active edge of reset changed from High to Low |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
51,7 → 54,7
xtal_clk , |
clkout , |
gen_resetn , |
risc_reset , |
risc_resetn , |
app_clk , |
uart_ref_clk |
); |
58,13 → 61,13
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input reset_n ; // Async reset signal |
input reset_n ; // Async reset signal |
input fastsim_mode ; // fast sim mode = 1 |
input mastermode ; // 1 : Risc master mode |
input xtal_clk ; // Xtal clock-25Mhx |
input xtal_clk ; // Xtal clock-25Mhx |
output clkout ; // clock output, 250Mhz |
output gen_resetn ; // internally generated reset |
output risc_reset ; // internally generated reset |
output risc_resetn ; // internally generated reset |
output app_clk ; // application clock |
output uart_ref_clk ; // uart 16x Ref clock |
|
75,10 → 78,10
wire run_st ; |
wire slave_run_st ; |
reg pll_done ; |
reg [11:0] pll_count ; |
reg [2:0] clkgen_ps ; |
reg [11:0] pll_count ; |
reg [2:0] clkgen_ps ; |
reg gen_resetn ; // internally generated reset |
reg risc_reset ; // internally generated reset |
reg risc_resetn ; // internally generated reset |
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assign clkout = app_clk; |
141,16 → 144,16
begin |
if (!reset_n) begin |
gen_resetn <= 0; |
risc_reset <= 1; |
risc_resetn <= 0; |
end else if(run_st ) begin |
gen_resetn <= 1; |
risc_reset <= 0; |
risc_resetn <= 1; |
end else if(slave_run_st ) begin |
gen_resetn <= 1; |
risc_reset <= 1; // Keet Risc in Reset |
risc_resetn <= 0; // Keet Risc in Reset |
end else begin |
gen_resetn <= 0; |
risc_reset <= 1; |
risc_resetn <= 0; |
end |
end |
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