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URL https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk

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  • This comparison shows the changes necessary to convert path 
    /oms8051mini/trunk/rtl/core
    from Rev 10 to Rev 11
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  •

Rev 10 → Rev 11

/digital_core.v
1,6 → 1,6
//////////////////////////////////////////////////////////////////////
//// ////
//// OMS 8051 Dgital core Module ////
//// OMS 8051 Digital core Module ////
//// ////
//// This file is part of the OMS 8051 cores project ////
//// http://www.opencores.org/cores/oms8051mini/ ////
23,6 → 23,8
// 1. RAM and ROM are internally connected to interconnect
// 2. Memory Map Change
// 3. Remove the External ROM Option & Enabled Internal ROM
// v0.2 - Dinesh A, 9st Dec 2016
// 1. Bus interface is changed from 32 bit to 8 bit
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
69,7 → 71,6
ext_reg_wr ,
ext_reg_addr ,
ext_reg_wdata ,
ext_reg_be ,
 
// Outputs
ext_reg_rdata ,
117,11 → 118,10
input ext_reg_wr ;
input [3:0] ext_reg_tid ;
input [14:0] ext_reg_addr ;
input [31:0] ext_reg_wdata ;
input [3:0] ext_reg_be ;
input [7:0] ext_reg_wdata ;
 
// Outputs
output [31:0] ext_reg_rdata ;
output [7:0] ext_reg_rdata ;
output ext_reg_ack ;
 
 
149,9 → 149,8
wire wb_xram_ack ; // data-ram acknowlage
wire wb_xram_err ; // data-ram error
wire wb_xram_wr ; // data-ram error
wire [3:0] wb_xram_be ; // Byte enable
wire [31:0] wb_xram_rdata ; // ram data input
wire [31:0] wb_xram_wdata ; // ram data input
wire [7:0] wb_xram_rdata ; // ram data input
wire [7:0] wb_xram_wdata ; // ram data input
 
wire wb_xram_stb ; // data-ram strobe
wire wb_xram_cyc ; // data-ram cycle
161,7 → 160,7
// 8051 Instruction ROM interface
//---------------------------------------------
wire [15:0] wbi_risc_adr;
wire [31:0] wbi_risc_rdata;
wire [7:0] wbi_risc_rdata;
 
 
//-----------------------------
179,18 → 178,15
 
wire [14:0] reg_uart_addr ;
wire [31:0] reg_uart_wdata ;
wire [3:0] reg_uart_be ;
wire [31:0] reg_uart_rdata ;
wire [7:0] reg_uart_wdata ;
wire [7:0] reg_uart_rdata ;
wire reg_uart_ack ;
wire [14:0] reg_spi_addr ;
wire [31:0] reg_spi_wdata ;
wire [3:0] reg_spi_be ;
wire [31:0] reg_spi_rdata ;
wire [7:0] reg_spi_wdata ;
wire [7:0] reg_spi_rdata ;
wire reg_spi_ack ;
 
wire [3:0] wb_xrom_be ;
 
wire [7:0] p0 ;
wire [7:0] p1 ;
198,7 → 194,7
wire [7:0] p3 ;
 
 
wire [31:0] reg_rdata = (reg_uart_ack) ? reg_uart_rdata :
wire [7:0] reg_rdata = (reg_uart_ack) ? reg_uart_rdata :
(reg_spi_ack) ? reg_spi_rdata : 'h0;
 
wire reg_ack = reg_uart_ack | reg_spi_ack;
206,12 → 202,8
 
assign reset_out_n = gen_resetn;
 
 
assign wb_xram_adr[15] = 0;
assign wb_xram_adr[1:0] = 2'b00;
 
assign reg_uart_addr[1:0] = 2'b0;
assign reg_spi_addr[1:0] = 2'b0;
//-------------------------------------------
// clock-gen instantiation
//-------------------------------------------
230,17 → 222,10
 
 
 
wire [31:0] wb_master2_rdata;
wire [7:0] wb_master2_rdata;
 
wire [3:0] wb_master2_be = (wbd_risc_adr[1:0] == 2'b00) ? 4'b0001:
(wbd_risc_adr[1:0] == 2'b01) ? 4'b0010:
(wbd_risc_adr[1:0] == 2'b10) ? 4'b0100: 4'b1000;
assign wbd_risc_rdata = wb_master2_rdata[7:0];
 
assign wbd_risc_rdata = (wbd_risc_adr[1:0] == 2'b00) ? wb_master2_rdata[7:0]:
(wbd_risc_adr[1:0] == 2'b01) ? wb_master2_rdata[15:8]:
(wbd_risc_adr[1:0] == 2'b10) ? wb_master2_rdata[23:16]:
wb_master2_rdata[31:24];
 
//------------------------------
// 8051 Data Memory Map
// 0x0000 to 0x7FFFF - Data Memory
259,9 → 244,9
 
wb_crossbar #(.WB_MASTER(3),
.WB_SLAVE(3),
.D_WD(32),
.BE_WD(4),
.ADR_WD(13),
.D_WD(8),
.BE_WD(1),
.ADR_WD(15),
.TAR_WD(4))
u_wb_crossbar (
 
274,11 → 259,8
wbd_tar_id,
ext_reg_tid }),
 
.wbd_din_master ({32'h0 ,
{wbd_risc_wdata[7:0],
.wbd_din_master ({8'h0 ,
wbd_risc_wdata[7:0],
wbd_risc_wdata[7:0],
wbd_risc_wdata[7:0]},
ext_reg_wdata }
),
 
286,14 → 268,11
wb_master2_rdata,
ext_reg_rdata}),
 
.wbd_adr_master ({wbi_risc_adr[12:0],
wbd_risc_adr[14:2],
ext_reg_addr[14:2]}),
.wbd_adr_master ({wbi_risc_adr[14:0],
wbd_risc_adr[14:0],
ext_reg_addr[14:0]}),
 
.wbd_be_master ({4'b1111,
wb_master2_be,
ext_reg_be }
),
.wbd_be_master ({1'b1,1'b1,1'b1}),
 
.wbd_we_master ({1'b0,wbd_risc_we,ext_reg_wr } ),
 
320,18 → 299,15
 
.wbd_dout_slave ({reg_uart_rdata,
reg_spi_rdata,
{wb_xram_rdata}
wb_xram_rdata
}),
 
.wbd_adr_slave ({reg_uart_addr[14:2],
reg_spi_addr[14:2],
wb_xram_adr[14:2]}
.wbd_adr_slave ({reg_uart_addr[14:0],
reg_spi_addr[14:0],
wb_xram_adr[14:0]}
),
 
.wbd_be_slave ({reg_uart_be,
reg_spi_be,
wb_xram_be }
),
.wbd_be_slave (),
 
.wbd_we_slave ({reg_uart_wr,
reg_spi_wr,
368,9 → 344,9
// Reg Bus Interface Signal
. reg_cs (reg_uart_cs ),
. reg_wr (reg_uart_wr ),
. reg_addr (reg_uart_addr[5:2] ),
. reg_addr (reg_uart_addr[3:0] ),
. reg_wdata (reg_uart_wdata ),
. reg_be (reg_uart_be ),
. reg_be (1'b1 ),
 
// Outputs
. reg_rdata (reg_uart_rdata ),
398,9 → 374,9
// Reg Bus Interface Signal
. reg_cs (reg_spi_cs ),
. reg_wr (reg_spi_wr ),
. reg_addr (reg_spi_addr[5:2] ),
. reg_addr (reg_spi_addr[3:0] ),
. reg_wdata (reg_spi_wdata ),
. reg_be (reg_spi_be ),
. reg_be (1'b1 ),
 
// Outputs
. reg_rdata (reg_spi_rdata ),
420,14 → 396,6
. wb_rst_i (risc_reset ),
. wb_clk_i (app_clk ),
 
//interface to instruction rom
. wbi_adr_o (wbi_risc_adr ),
. wbi_dat_i (wbi_risc_rdata ),
. wbi_stb_o (wbi_risc_stb ),
. wbi_ack_i (wbi_risc_ack ),
. wbi_cyc_o (wbi_risc_cyc ),
. wbi_err_i (wbi_risc_err ),
 
//interface to data ram
. wbd_dat_i (wbd_risc_rdata ),
. wbd_dat_o (wbd_risc_wdata ),
502,7 → 470,6
.clk (app_clk ),
.rst (!reset_n ),
.wr (wb_xram_wr ),
.be (wb_xram_be ),
.addr (wb_xram_adr ),
.data_in (wb_xram_wdata ),
.data_out (wb_xram_rdata ),

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