URL
https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk
Subversion Repositories oms8051mini
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- This comparison shows the changes necessary to convert path
/oms8051mini/trunk
- from Rev 19 to Rev 20
- ↔ Reverse comparison
Rev 19 → Rev 20
/rtl/8051/oc8051_memory_interface.v
14,9 → 14,7
//// Author(s): //// |
//// - Simon Teran, simont@opencores.org //// |
//// - Dinesh Annayya, dinesha@opencores.org //// |
////////////////////////////////////////////////////////////////////// |
//// v0.0 - Dinesh A, 17th Dec 2016 |
//// 1. External ROM Interface Removed |
//// - Dinesh Annayya, dinesha@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
132,6 → 130,10
//internal |
idat_onchip, |
|
//external |
iack_i, |
istb_o, |
idat_i, |
|
//external data ram |
dadr_o, |
175,6 → 177,7
sfr, |
acc, |
sp_w; |
input [31:0] idat_i; |
|
output bit_out, |
mem_wait, |
200,6 → 203,7
// rom_addr_sel |
// |
///////////////////////////// |
input iack_i; |
input [7:0] des_acc, |
des1, |
des2; |
265,7 → 269,8
|
input [31:0] idat_onchip; |
|
output int_ack; |
output int_ack, |
istb_o; |
|
output [7:0] op1_out, |
op3_out, |
351,9 → 356,12
assign wr_o = wr_i; |
assign wr_bit_o = wr_bit_i; |
|
//assign mem_wait = dmem_wait || imem_wait || pc_wr_r; |
assign mem_wait = dmem_wait || imem_wait || pc_wr_r2; |
//assign mem_wait = dmem_wait || imem_wait; |
assign istb_o = (istb || (istb_t & !iack_i)) && !dstb_o && !ea_rom_sel; |
|
assign pc_wait = rd ; |
assign pc_wait = rd && (ea_rom_sel || (!istb_t && iack_i)); |
|
assign wr_dat = des1; |
|
392,7 → 400,7
// |
///////////////////////////// |
|
always @(*) |
always @(rd_sel or sp or ri or rn or imm or dadr_o[15:0] or bank) |
begin |
case (rd_sel) /* synopsys full_case parallel_case */ |
`OC8051_RRS_RN : rd_addr = {3'h0, rn}; |
404,6 → 412,7
`OC8051_RRS_DPTR : rd_addr = `OC8051_SFR_DPTR_LO; |
`OC8051_RRS_PSW : rd_addr = `OC8051_SFR_PSW; |
`OC8051_RRS_ACC : rd_addr = `OC8051_SFR_ACC; |
// default : rd_addr = 2'bxx; |
endcase |
|
end |
411,7 → 420,7
|
// |
// |
always @(*) |
always @(wr_sel or sp_w or rn_r or imm_r or ri_r or imm2_r or op1_r or dadr_o[15:0]) |
begin |
case (wr_sel) /* synopsys full_case parallel_case */ |
`OC8051_RWS_RN : wr_addr = {3'h0, rn_r}; |
448,6 → 457,7
// output address is alu destination |
// (instructions MOVC) |
|
//assign iadr_o = (istb_t & !iack_i) ? iadr_t : pc_out; |
assign iadr_o = (istb_t) ? iadr_t : pc_out; |
|
|
466,7 → 476,10
imem_wait <= #1 1'b0; |
end else if (!imem_wait && istb_t) begin |
istb_t <= #1 1'b0; |
end |
end else if (iack_i) begin |
imem_wait <= #1 1'b0; |
idat_ir <= #1 idat_i [23:0]; |
end |
end |
|
///////////////////////////// |
536,8 → 549,8
if (rst) begin |
idat_cur <= #1 32'h0; |
idat_old <= #1 32'h0; |
end else if (inc_pc || pc_wr_r2) begin |
idat_cur <= #1 idat_onchip; |
end else if ((iack_i | ea_rom_sel) & (inc_pc | pc_wr_r2)) begin |
idat_cur <= #1 ea_rom_sel ? idat_onchip : idat_i; |
idat_old <= #1 idat_cur; |
end |
|
549,7 → 562,7
cdata <= #1 8'h00; |
cdone <= #1 1'b0; |
end else if (istb_t) begin |
cdata <= #1 idat_onchip[7:0] ; |
cdata <= #1 ea_rom_sel ? idat_onchip[7:0] : idat_i[7:0]; |
cdone <= #1 1'b1; |
end else begin |
cdone <= #1 1'b0; |
556,7 → 569,7
end |
end |
|
always @(*) |
always @(op_pos or idat_cur or idat_old) |
begin |
case (op_pos) /* synopsys parallel_case */ |
3'b000: begin |
592,7 → 605,8
endcase |
end |
|
always @(*) |
|
always @(dack_ir or ddat_ir or op1_o or iram_out or cdone or cdata) |
if (dack_ir) |
op1_out = ddat_ir; |
else if (cdone) |
603,9 → 617,13
assign op3_out = (rd) ? op3_o : op3_buff; |
assign op2_out = (rd) ? op2_o : op2_buff; |
|
always @(*) |
always @(idat_i or iack_i or idat_ir or rd) |
begin |
if (!rd) begin |
if (iack_i) begin |
op1_xt = idat_i[7:0]; |
op2_xt = idat_i[15:8]; |
op3_xt = idat_i[23:16]; |
end else if (!rd) begin |
op1_xt = idat_ir[7:0]; |
op2_xt = idat_ir[15:8]; |
op3_xt = idat_ir[23:16]; |
619,9 → 637,9
|
// |
// in case of interrupts |
always @(*) |
always @(op1 or op2 or op3 or int_ack_t or int_vec_buff or iack_i or ea_rom_sel) |
begin |
if (int_ack_t) begin |
if (int_ack_t && (iack_i || ea_rom_sel)) begin |
op1_o = `OC8051_LCALL; |
op2_o = 8'h00; |
op3_o = int_vec_buff; |
658,7 → 676,7
// |
///////////////////////////// |
|
always @(*) |
always @(op1_out) |
begin |
casex (op1_out) /* synopsys parallel_case */ |
`OC8051_ACALL : op_length = 2'h2; |
741,7 → 759,7
if (rst) begin |
op_pos <= #1 3'h0; |
end else if (pc_wr_r2) begin |
op_pos <= #1 3'h4; |
op_pos <= #1 3'h4;// - op_length;////****?????????? |
end else if (inc_pc & rd) begin |
op_pos[2] <= #1 op_pos[2] & !op_pos[1] & op_pos[0] & (&op_length); |
op_pos[1:0] <= #1 op_pos[1:0] + op_length; |
760,7 → 778,7
end else if (intr) begin |
int_ack_t <= #1 1'b1; |
int_vec_buff <= #1 int_v; |
end else if (rd && !pc_wr_r2) int_ack_t <= #1 1'b0; |
end else if (rd && (ea_rom_sel || iack_i) && !pc_wr_r2) int_ack_t <= #1 1'b0; |
|
always @(posedge clk or posedge rst) |
if (rst) int_ack_buff <= #1 1'b0; |
806,6 → 824,7
end else pcs_result = pc + {8'h00, pcs_source}; |
end |
|
|
always @(posedge clk or posedge rst) |
begin |
if (rst) |
855,6 → 874,7
else if (dack_i) |
ddat_ir <= #1 ddat_i; |
|
|
//////////////////////// |
always @(posedge clk or posedge rst) |
if (rst) begin |
/rtl/8051/oc8051_ram_256x8_two_bist.v
95,7 → 95,7
|
|
`ifdef OC8051_RAM_XILINX |
xilinx_ram_dp xilinx_ram( |
xilinx_ram_dp u_ram( |
// read port |
.CLKA(clk), |
.RSTA(rst), |
123,7 → 123,7
|
`elsif OC8051_RAM_ACTEL |
|
oc8051_actel_ram_256x8 oc8051_ram1( |
oc8051_actel_ram_256x8 u_ram( |
.RWCLK ( clk ), |
.RESET ( rst ), |
.REN ( rd_en ), |
138,7 → 138,7
|
`elsif OC8051_RAM_GENERIC |
|
generic_dpram #(8, 8) oc8051_ram1( |
generic_dpram #(8, 8) u_ram( |
.rclk ( clk ), |
.rrst ( rst ), |
.rce ( rd_en ), |
/rtl/8051/oc8051_ram_64x32_dual_bist.v
104,7 → 104,7
|
|
`ifdef OC8051_RAM_XILINX |
xilinx_ram_dp xilinx_ram( |
xilinx_ram_dp u_ram_dp( |
// read port |
.CLKA(clk), |
.RSTA(rst), |
136,7 → 136,7
|
`ifdef OC8051_RAM_GENERIC |
|
generic_dpram #(ADR_WIDTH, 32) oc8051_ram1( |
generic_dpram #(ADR_WIDTH, 32) u_ram_dp( |
.rclk ( clk ), |
.rrst ( rst ), |
.rce ( en0 ), |
/rtl/8051/oc8051_ram_top.v
142,7 → 142,7
assign rd_data = rd_en_r ? wr_data_r: rd_data_m; |
assign rd_en = (rd_addr_m == wr_addr_m) & wr; |
|
oc8051_ram_256x8_two_bist oc8051_idata( |
oc8051_ram_256x8_two_bist u_ram_idata( |
.clk ( clk ), |
.rst ( rst ), |
.rd_addr ( rd_addr_m ), |
/rtl/8051/oc8051_top.v
348,7 → 348,7
|
// |
// decoder |
oc8051_decoder oc8051_decoder1( |
oc8051_decoder u_decoder( |
.clk (wb_clk_i ), |
.rst (wb_rst_i ), |
.op_in (op1_n ), |
382,7 → 382,7
wire [7:0] sub_result; |
// |
//alu |
oc8051_alu oc8051_alu1( |
oc8051_alu u_alu( |
.rst (wb_rst_i ), |
.clk (wb_clk_i ), |
.op_code (alu_op ), |
403,7 → 403,7
|
// |
//data ram |
oc8051_ram_top oc8051_ram_top1( |
oc8051_ram_top u_ram_top( |
.clk (wb_clk_i ), |
.rst (wb_rst_i ), |
.rd_addr (rd_addr ), |
427,7 → 427,7
|
// |
|
oc8051_alu_src_sel oc8051_alu_src_sel1( |
oc8051_alu_src_sel u_alu_src_sel( |
.clk (wb_clk_i ), |
.rst (wb_rst_i ), |
.rd (rd ), |
452,7 → 452,7
|
// |
// |
oc8051_comp oc8051_comp1( |
oc8051_comp u_comp( |
.sel (comp_sel ), |
.eq (eq ), |
.b_in (bit_out ), |
465,7 → 465,7
// |
//program rom |
`ifdef OC8051_ROM |
oc8051_rom oc8051_rom1( |
oc8051_rom u_rom( |
.rst (wb_rst_i ), |
.clk (wb_clk_i ), |
.ea_int (ea_int ), |
491,7 → 491,7
|
// |
// |
oc8051_cy_select oc8051_cy_select1( |
oc8051_cy_select u_cy_select( |
.cy_sel (cy_sel ), |
.cy_in (cy ), |
.data_in (bit_out ), |
499,7 → 499,7
); |
// |
// |
oc8051_indi_addr oc8051_indi_addr1 ( |
oc8051_indi_addr u_indi_addr ( |
.clk (wb_clk_i ), |
.rst (wb_rst_i ), |
.wr_addr (wr_addr ), |
515,7 → 515,7
|
// |
// |
oc8051_memory_interface oc8051_memory_interface1( |
oc8051_memory_interface u_memory_interface( |
.clk (wb_clk_i ), |
.rst (wb_rst_i ), |
// internal ram |
593,7 → 593,7
// |
// |
|
oc8051_sfr oc8051_sfr1( |
oc8051_sfr u_sfr( |
.rst (wb_rst_i ), |
.clk (wb_clk_i ), |
.adr0 (rd_addr[7:0] ), |