URL
https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk
Subversion Repositories oms8051mini
Compare Revisions
- This comparison shows the changes necessary to convert path
/oms8051mini
- from Rev 31 to Rev 32
- ↔ Reverse comparison
Rev 31 → Rev 32
/trunk/rtl/core/digital_core.v
492,7 → 492,7
/****************************************************** |
* I2C Master Core |
* ***************************************************/ |
i2cm_top i_i2cm ( |
i2cm_top i_i2cm_core ( |
// wishbone signals |
.wb_clk_i (app_clk ), |
.sresetn (gen_resetn ), |
/trunk/verif/glog/modelsim/complie.log
1,17 → 1,18
-
-Model Technology ModelSim ACTEL vlog 10.1b Compiler 2012.04 Apr 27 2012
+Model Technology ModelSim Microsemi vlog 10.4c Compiler 2015.07 Aug 12 2015
+Start time: 11:08:32 on Jan 08,2017
+vlog -work work "+define+SFLASH_SPDUP" -sv -f filelist_top.f
-- Compiling module tb_top
+-- Compiling module delay
-- Compiling module tb_glbl
-- Compiling module uart_agent
+-- Compiling module i2c_slave_model
-- Compiling module AT45DB321
-- Compiling module acdc_check
-- Compiling module internal_logic
-- Compiling module memory_access
-- Compiling module m25p20
--- Compiling module oc8051_xram
--- Compiling module oc8051_xrom
-- Compiling module digital_core
+-- Compiling module async_fifo
-- Compiling module g_dpath_ctrl
-- Compiling module spi_core
-- Compiling module spi_ctl
@@ -21,6 +22,7 @@
-- Compiling module uart_txfsm
-- Compiling module uart_core
-- Compiling module uart_cfg
+-- Compiling module uart_core_nf
-- Compiling module clkgen
-- Compiling module clk_ctl
-- Compiling module wb_crossbar
@@ -50,6 +52,13 @@
-- Compiling module oc8051_tc2
-- Compiling module oc8051_sfr
-- Compiling module oc8051_ram_256x8_two_bist
+-- Compiling module oc8051_xram
+-- Compiling module oc8051_xrom
+-- Compiling module msg_handler
+-- Compiling module msg_handler_top
+-- Compiling module i2cm_bit_ctrl
+-- Compiling module i2cm_byte_ctrl
+-- Compiling module i2cm_top
-- Scanning library file '../../rtl/lib/registers.v'
-- Compiling module req_register
-- Compiling module stat_register
@@ -59,7 +68,6 @@
-- Scanning library file '../../rtl/lib/double_sync_low.v'
-- Compiling module double_sync_low
-- Scanning library file '../../rtl/lib/async_fifo.v'
--- Compiling module async_fifo
-- Scanning library file '../../rtl/lib/registers.v'
-- Compiling module bit_register
-- Scanning library file '../../rtl/lib/stat_counter.v'
@@ -66,11 +74,26 @@
-- Scanning library file '../../rtl/lib/toggle_sync.v'
-- Scanning library file '../../rtl/lib/double_sync_low.v'
-- Scanning library file '../../rtl/lib/async_fifo.v'
+-- Scanning library file '../../rtl/lib/registers.v'
+-- Scanning library file '../../rtl/lib/stat_counter.v'
+-- Scanning library file '../../rtl/lib/toggle_sync.v'
+-- Scanning library file '../../rtl/lib/double_sync_low.v'
+-- Scanning library file '../../rtl/lib/async_fifo.v'
+-- Scanning library file '../../rtl/lib/registers.v'
+-- Scanning library file '../../rtl/lib/stat_counter.v'
+-- Scanning library file '../../rtl/lib/toggle_sync.v'
+-- Scanning library file '../../rtl/lib/double_sync_low.v'
+-- Scanning library file '../../rtl/lib/async_fifo.v'
+Referenced (but uncompiled) modules or primitives:
+ delay
+
Top level modules:
tb_top
g_dpath_ctrl
wb_rd_mem2mem
wb_wr_mem2mem
- oc8051_rom
oc8051_uart
+ oc8051_xrom
+End time: 11:08:33 on Jan 08,2017, Elapsed time: 0:00:01
+Errors: 0, Warnings: 0
/trunk/verif/glog/modelsim/ext_cast.log
1,16 → 1,22
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl |
Reading J:/Microsemi/Libero_SoC_v11.7/Model/tcl/vsim/pref.tcl |
|
# 10.1b |
# 10.4c |
|
# vsim +EXTERNAL_ROM -do run.do -c tb_top |
# // ModelSim ACTEL 10.1b Apr 27 2012 |
# vsim -do "run.do" -c tb_top "+INTERNAL_ROM" |
# Start time: 06:22:46 on Jan 01,2017 |
# // ModelSim Microsemi 10.4c Aug 12 2015 |
# // |
# // Copyright 1991-2012 Mentor Graphics Corporation |
# // Copyright 1991-2015 Mentor Graphics Corporation |
# // All Rights Reserved. |
# // |
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION |
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS |
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS. |
# // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL |
# // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM |
# // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552. |
# // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER |
# // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905. |
# // |
# Loading sv_std.std |
# Loading work.tb_top |
17,15 → 23,18
# Loading work.digital_core |
# Loading work.clkgen |
# Loading work.clk_ctl |
# Loading work.msg_handler_top |
# Loading work.uart_core_nf |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.double_sync_low |
# Loading work.msg_handler |
# Loading work.wb_crossbar |
# Loading work.uart_core |
# Loading work.uart_cfg |
# Loading work.generic_register |
# Loading work.stat_register |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.async_fifo |
# Loading work.double_sync_low |
# Loading work.spi_core |
# Loading work.spi_if |
# Loading work.spi_ctl |
40,6 → 49,7
# Loading work.oc8051_ram_256x8_two_bist |
# Loading work.oc8051_alu_src_sel |
# Loading work.oc8051_comp |
# Loading work.oc8051_rom |
# Loading work.oc8051_cy_select |
# Loading work.oc8051_indi_addr |
# Loading work.oc8051_memory_interface |
53,7 → 63,6
# Loading work.oc8051_int |
# Loading work.oc8051_tc |
# Loading work.oc8051_tc2 |
# Loading work.oc8051_xrom |
# Loading work.oc8051_xram |
# Loading work.uart_agent |
# Loading work.m25p20 |
63,48 → 72,40
# Loading work.AT45DB321 |
# Loading work.tb_glbl |
# Loading work.bit_register |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38. |
# |
# Region: /tb_top/u_core |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'. |
# |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_rxfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_txfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'. |
# |
# do run.do |
# i : 02 |
# i : 00 |
# i : 08 |
# i : 12 |
# i : 00 |
# i : 65 |
# i : 80 |
# i : fe |
# i : 75 |
# i : 81 |
# ** Warning: (vsim-3017) ../tb/tb_top.v(134): [TFMPC] - Too few port connections. Expected 24, found 22. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core File: ../../rtl/core/digital_core.v |
# ** Warning: (vsim-3722) ../tb/tb_top.v(134): [TFMPC] - Missing connection for port 'scan_mode'. |
# ** Warning: (vsim-3722) ../tb/tb_top.v(134): [TFMPC] - Missing connection for port 'scan_enable'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(233): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_rxfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(249): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_txfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Too few port connections. Expected 55, found 52. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_8051_core/u_memory_interface File: ../../rtl/8051/oc8051_memory_interface.v |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Missing connection for port 'iack_i'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Missing connection for port 'istb_o'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Missing connection for port 'idat_i'. |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(241): [TOFD] - System task or function '$shm_open' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(242): [TOFD] - System task or function '$shm_probe' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# do run.do |
# NOTE : Load memory with Initial delivery content |
# NOTE : Initial Load End |
# --> Dumpping the design |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(241): Cannot execute undefined system task/function '$shm_open' |
# |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(242): Cannot execute undefined system task/function '$shm_probe' |
# |
# NOTE: COMMUNICATION (RE)STARTED |
################################ |
# TEST STATUS : PASSED |
################################ |
# ** Note: $finish : ../tb/tb_top.v(288) |
# Time: 29636 ps Iteration: 0 Instance: /tb_top |
# End time: 06:22:47 on Jan 01,2017, Elapsed time: 0:00:01 |
# Errors: 2, Warnings: 15 |
/trunk/verif/glog/modelsim/ext_divmul.log
1,16 → 1,22
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl |
Reading J:/Microsemi/Libero_SoC_v11.7/Model/tcl/vsim/pref.tcl |
|
# 10.1b |
# 10.4c |
|
# vsim +EXTERNAL_ROM -do run.do -c tb_top |
# // ModelSim ACTEL 10.1b Apr 27 2012 |
# vsim -do "run.do" -c tb_top "+INTERNAL_ROM" |
# Start time: 06:22:36 on Jan 01,2017 |
# // ModelSim Microsemi 10.4c Aug 12 2015 |
# // |
# // Copyright 1991-2012 Mentor Graphics Corporation |
# // Copyright 1991-2015 Mentor Graphics Corporation |
# // All Rights Reserved. |
# // |
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION |
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS |
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS. |
# // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL |
# // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM |
# // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552. |
# // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER |
# // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905. |
# // |
# Loading sv_std.std |
# Loading work.tb_top |
17,15 → 23,18
# Loading work.digital_core |
# Loading work.clkgen |
# Loading work.clk_ctl |
# Loading work.msg_handler_top |
# Loading work.uart_core_nf |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.double_sync_low |
# Loading work.msg_handler |
# Loading work.wb_crossbar |
# Loading work.uart_core |
# Loading work.uart_cfg |
# Loading work.generic_register |
# Loading work.stat_register |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.async_fifo |
# Loading work.double_sync_low |
# Loading work.spi_core |
# Loading work.spi_if |
# Loading work.spi_ctl |
40,6 → 49,7
# Loading work.oc8051_ram_256x8_two_bist |
# Loading work.oc8051_alu_src_sel |
# Loading work.oc8051_comp |
# Loading work.oc8051_rom |
# Loading work.oc8051_cy_select |
# Loading work.oc8051_indi_addr |
# Loading work.oc8051_memory_interface |
53,7 → 63,6
# Loading work.oc8051_int |
# Loading work.oc8051_tc |
# Loading work.oc8051_tc2 |
# Loading work.oc8051_xrom |
# Loading work.oc8051_xram |
# Loading work.uart_agent |
# Loading work.m25p20 |
63,48 → 72,40
# Loading work.AT45DB321 |
# Loading work.tb_glbl |
# Loading work.bit_register |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38. |
# |
# Region: /tb_top/u_core |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'. |
# |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_rxfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_txfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'. |
# |
# do run.do |
# i : 02 |
# i : 00 |
# i : 08 |
# i : 12 |
# i : 00 |
# i : 64 |
# i : 80 |
# i : fe |
# i : 75 |
# i : 81 |
# ** Warning: (vsim-3017) ../tb/tb_top.v(134): [TFMPC] - Too few port connections. Expected 24, found 22. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core File: ../../rtl/core/digital_core.v |
# ** Warning: (vsim-3722) ../tb/tb_top.v(134): [TFMPC] - Missing connection for port 'scan_mode'. |
# ** Warning: (vsim-3722) ../tb/tb_top.v(134): [TFMPC] - Missing connection for port 'scan_enable'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(233): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_rxfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(249): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_txfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Too few port connections. Expected 55, found 52. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_8051_core/u_memory_interface File: ../../rtl/8051/oc8051_memory_interface.v |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Missing connection for port 'iack_i'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Missing connection for port 'istb_o'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Missing connection for port 'idat_i'. |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(241): [TOFD] - System task or function '$shm_open' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(242): [TOFD] - System task or function '$shm_probe' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# do run.do |
# NOTE : Load memory with Initial delivery content |
# NOTE : Initial Load End |
# --> Dumpping the design |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(241): Cannot execute undefined system task/function '$shm_open' |
# |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(242): Cannot execute undefined system task/function '$shm_probe' |
# |
# NOTE: COMMUNICATION (RE)STARTED |
################################ |
# TEST STATUS : PASSED |
################################ |
# ** Note: $finish : ../tb/tb_top.v(288) |
# Time: 46076 ps Iteration: 0 Instance: /tb_top |
# End time: 06:22:37 on Jan 01,2017, Elapsed time: 0:00:01 |
# Errors: 2, Warnings: 15 |
/trunk/verif/glog/modelsim/ext_fib.log
1,16 → 1,22
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl |
Reading J:/Microsemi/Libero_SoC_v11.7/Model/tcl/vsim/pref.tcl |
|
# 10.1b |
# 10.4c |
|
# vsim +EXTERNAL_ROM -do run.do -c tb_top |
# // ModelSim ACTEL 10.1b Apr 27 2012 |
# vsim -do "run.do" -c tb_top "+INTERNAL_ROM" |
# Start time: 06:22:33 on Jan 01,2017 |
# // ModelSim Microsemi 10.4c Aug 12 2015 |
# // |
# // Copyright 1991-2012 Mentor Graphics Corporation |
# // Copyright 1991-2015 Mentor Graphics Corporation |
# // All Rights Reserved. |
# // |
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION |
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS |
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS. |
# // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL |
# // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM |
# // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552. |
# // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER |
# // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905. |
# // |
# Loading sv_std.std |
# Loading work.tb_top |
17,15 → 23,18
# Loading work.digital_core |
# Loading work.clkgen |
# Loading work.clk_ctl |
# Loading work.msg_handler_top |
# Loading work.uart_core_nf |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.double_sync_low |
# Loading work.msg_handler |
# Loading work.wb_crossbar |
# Loading work.uart_core |
# Loading work.uart_cfg |
# Loading work.generic_register |
# Loading work.stat_register |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.async_fifo |
# Loading work.double_sync_low |
# Loading work.spi_core |
# Loading work.spi_if |
# Loading work.spi_ctl |
40,6 → 49,7
# Loading work.oc8051_ram_256x8_two_bist |
# Loading work.oc8051_alu_src_sel |
# Loading work.oc8051_comp |
# Loading work.oc8051_rom |
# Loading work.oc8051_cy_select |
# Loading work.oc8051_indi_addr |
# Loading work.oc8051_memory_interface |
53,7 → 63,6
# Loading work.oc8051_int |
# Loading work.oc8051_tc |
# Loading work.oc8051_tc2 |
# Loading work.oc8051_xrom |
# Loading work.oc8051_xram |
# Loading work.uart_agent |
# Loading work.m25p20 |
63,48 → 72,40
# Loading work.AT45DB321 |
# Loading work.tb_glbl |
# Loading work.bit_register |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38. |
# |
# Region: /tb_top/u_core |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'. |
# |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_rxfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_txfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'. |
# |
# do run.do |
# i : 02 |
# i : 00 |
# i : 08 |
# i : 12 |
# i : 01 |
# i : 51 |
# i : 80 |
# i : fe |
# i : 75 |
# i : 81 |
# ** Warning: (vsim-3017) ../tb/tb_top.v(134): [TFMPC] - Too few port connections. Expected 24, found 22. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core File: ../../rtl/core/digital_core.v |
# ** Warning: (vsim-3722) ../tb/tb_top.v(134): [TFMPC] - Missing connection for port 'scan_mode'. |
# ** Warning: (vsim-3722) ../tb/tb_top.v(134): [TFMPC] - Missing connection for port 'scan_enable'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(233): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_rxfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(249): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_txfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Too few port connections. Expected 55, found 52. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_8051_core/u_memory_interface File: ../../rtl/8051/oc8051_memory_interface.v |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Missing connection for port 'iack_i'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Missing connection for port 'istb_o'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Missing connection for port 'idat_i'. |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(241): [TOFD] - System task or function '$shm_open' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(242): [TOFD] - System task or function '$shm_probe' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# do run.do |
# NOTE : Load memory with Initial delivery content |
# NOTE : Initial Load End |
# --> Dumpping the design |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(241): Cannot execute undefined system task/function '$shm_open' |
# |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(242): Cannot execute undefined system task/function '$shm_probe' |
# |
# NOTE: COMMUNICATION (RE)STARTED |
################################ |
# TEST STATUS : PASSED |
################################ |
# ** Note: $finish : ../tb/tb_top.v(288) |
# Time: 62316 ps Iteration: 0 Instance: /tb_top |
# End time: 06:22:35 on Jan 01,2017, Elapsed time: 0:00:02 |
# Errors: 2, Warnings: 15 |
/trunk/verif/glog/modelsim/ext_gcd.log
1,16 → 1,22
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl |
Reading J:/Microsemi/Libero_SoC_v11.7/Model/tcl/vsim/pref.tcl |
|
# 10.1b |
# 10.4c |
|
# vsim +EXTERNAL_ROM -do run.do -c tb_top |
# // ModelSim ACTEL 10.1b Apr 27 2012 |
# vsim -do "run.do" -c tb_top "+INTERNAL_ROM" |
# Start time: 06:22:43 on Jan 01,2017 |
# // ModelSim Microsemi 10.4c Aug 12 2015 |
# // |
# // Copyright 1991-2012 Mentor Graphics Corporation |
# // Copyright 1991-2015 Mentor Graphics Corporation |
# // All Rights Reserved. |
# // |
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION |
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS |
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS. |
# // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL |
# // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM |
# // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552. |
# // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER |
# // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905. |
# // |
# Loading sv_std.std |
# Loading work.tb_top |
17,15 → 23,18
# Loading work.digital_core |
# Loading work.clkgen |
# Loading work.clk_ctl |
# Loading work.msg_handler_top |
# Loading work.uart_core_nf |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.double_sync_low |
# Loading work.msg_handler |
# Loading work.wb_crossbar |
# Loading work.uart_core |
# Loading work.uart_cfg |
# Loading work.generic_register |
# Loading work.stat_register |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.async_fifo |
# Loading work.double_sync_low |
# Loading work.spi_core |
# Loading work.spi_if |
# Loading work.spi_ctl |
40,6 → 49,7
# Loading work.oc8051_ram_256x8_two_bist |
# Loading work.oc8051_alu_src_sel |
# Loading work.oc8051_comp |
# Loading work.oc8051_rom |
# Loading work.oc8051_cy_select |
# Loading work.oc8051_indi_addr |
# Loading work.oc8051_memory_interface |
53,7 → 63,6
# Loading work.oc8051_int |
# Loading work.oc8051_tc |
# Loading work.oc8051_tc2 |
# Loading work.oc8051_xrom |
# Loading work.oc8051_xram |
# Loading work.uart_agent |
# Loading work.m25p20 |
63,48 → 72,40
# Loading work.AT45DB321 |
# Loading work.tb_glbl |
# Loading work.bit_register |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38. |
# |
# Region: /tb_top/u_core |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'. |
# |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_rxfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_txfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'. |
# |
# do run.do |
# i : 02 |
# i : 00 |
# i : 08 |
# i : 12 |
# i : 00 |
# i : 64 |
# i : 80 |
# i : fe |
# i : 75 |
# i : 81 |
# ** Warning: (vsim-3017) ../tb/tb_top.v(134): [TFMPC] - Too few port connections. Expected 24, found 22. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core File: ../../rtl/core/digital_core.v |
# ** Warning: (vsim-3722) ../tb/tb_top.v(134): [TFMPC] - Missing connection for port 'scan_mode'. |
# ** Warning: (vsim-3722) ../tb/tb_top.v(134): [TFMPC] - Missing connection for port 'scan_enable'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(233): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_rxfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(249): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_txfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Too few port connections. Expected 55, found 52. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_8051_core/u_memory_interface File: ../../rtl/8051/oc8051_memory_interface.v |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Missing connection for port 'iack_i'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Missing connection for port 'istb_o'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Missing connection for port 'idat_i'. |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(241): [TOFD] - System task or function '$shm_open' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(242): [TOFD] - System task or function '$shm_probe' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# do run.do |
# NOTE : Load memory with Initial delivery content |
# NOTE : Initial Load End |
# --> Dumpping the design |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(241): Cannot execute undefined system task/function '$shm_open' |
# |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(242): Cannot execute undefined system task/function '$shm_probe' |
# |
# NOTE: COMMUNICATION (RE)STARTED |
################################ |
# TEST STATUS : PASSED |
################################ |
# ** Note: $finish : ../tb/tb_top.v(288) |
# Time: 33876 ps Iteration: 0 Instance: /tb_top |
# End time: 06:22:44 on Jan 01,2017, Elapsed time: 0:00:01 |
# Errors: 2, Warnings: 15 |
/trunk/verif/glog/modelsim/ext_sort.log
1,16 → 1,22
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl |
Reading J:/Microsemi/Libero_SoC_v11.7/Model/tcl/vsim/pref.tcl |
|
# 10.1b |
# 10.4c |
|
# vsim +EXTERNAL_ROM -do run.do -c tb_top |
# // ModelSim ACTEL 10.1b Apr 27 2012 |
# vsim -do "run.do" -c tb_top "+INTERNAL_ROM" |
# Start time: 06:22:39 on Jan 01,2017 |
# // ModelSim Microsemi 10.4c Aug 12 2015 |
# // |
# // Copyright 1991-2012 Mentor Graphics Corporation |
# // Copyright 1991-2015 Mentor Graphics Corporation |
# // All Rights Reserved. |
# // |
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION |
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS |
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS. |
# // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL |
# // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM |
# // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552. |
# // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER |
# // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905. |
# // |
# Loading sv_std.std |
# Loading work.tb_top |
17,15 → 23,18
# Loading work.digital_core |
# Loading work.clkgen |
# Loading work.clk_ctl |
# Loading work.msg_handler_top |
# Loading work.uart_core_nf |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.double_sync_low |
# Loading work.msg_handler |
# Loading work.wb_crossbar |
# Loading work.uart_core |
# Loading work.uart_cfg |
# Loading work.generic_register |
# Loading work.stat_register |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.async_fifo |
# Loading work.double_sync_low |
# Loading work.spi_core |
# Loading work.spi_if |
# Loading work.spi_ctl |
40,6 → 49,7
# Loading work.oc8051_ram_256x8_two_bist |
# Loading work.oc8051_alu_src_sel |
# Loading work.oc8051_comp |
# Loading work.oc8051_rom |
# Loading work.oc8051_cy_select |
# Loading work.oc8051_indi_addr |
# Loading work.oc8051_memory_interface |
53,7 → 63,6
# Loading work.oc8051_int |
# Loading work.oc8051_tc |
# Loading work.oc8051_tc2 |
# Loading work.oc8051_xrom |
# Loading work.oc8051_xram |
# Loading work.uart_agent |
# Loading work.m25p20 |
63,48 → 72,40
# Loading work.AT45DB321 |
# Loading work.tb_glbl |
# Loading work.bit_register |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38. |
# |
# Region: /tb_top/u_core |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'. |
# |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_rxfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_txfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'. |
# |
# do run.do |
# i : 02 |
# i : 00 |
# i : 08 |
# i : 12 |
# i : 01 |
# i : 1f |
# i : 80 |
# i : fe |
# i : 75 |
# i : 81 |
# ** Warning: (vsim-3017) ../tb/tb_top.v(134): [TFMPC] - Too few port connections. Expected 24, found 22. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core File: ../../rtl/core/digital_core.v |
# ** Warning: (vsim-3722) ../tb/tb_top.v(134): [TFMPC] - Missing connection for port 'scan_mode'. |
# ** Warning: (vsim-3722) ../tb/tb_top.v(134): [TFMPC] - Missing connection for port 'scan_enable'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(233): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_rxfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(249): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_txfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Too few port connections. Expected 55, found 52. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_8051_core/u_memory_interface File: ../../rtl/8051/oc8051_memory_interface.v |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Missing connection for port 'iack_i'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Missing connection for port 'istb_o'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Missing connection for port 'idat_i'. |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(241): [TOFD] - System task or function '$shm_open' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(242): [TOFD] - System task or function '$shm_probe' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# do run.do |
# NOTE : Load memory with Initial delivery content |
# NOTE : Initial Load End |
# --> Dumpping the design |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(241): Cannot execute undefined system task/function '$shm_open' |
# |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(242): Cannot execute undefined system task/function '$shm_probe' |
# |
# NOTE: COMMUNICATION (RE)STARTED |
################################ |
# TEST STATUS : PASSED |
################################ |
# ** Note: $finish : ../tb/tb_top.v(288) |
# Time: 184536 ps Iteration: 0 Instance: /tb_top |
# End time: 06:22:41 on Jan 01,2017, Elapsed time: 0:00:02 |
# Errors: 2, Warnings: 15 |
/trunk/verif/glog/modelsim/ext_xram.log
1,16 → 1,22
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl |
Reading J:/Microsemi/Libero_SoC_v11.7/Model/tcl/vsim/pref.tcl |
|
# 10.1b |
# 10.4c |
|
# vsim +EXTERNAL_ROM -do run.do -c tb_top |
# // ModelSim ACTEL 10.1b Apr 27 2012 |
# vsim -do "run.do" -c tb_top "+INTERNAL_ROM" |
# Start time: 06:22:49 on Jan 01,2017 |
# // ModelSim Microsemi 10.4c Aug 12 2015 |
# // |
# // Copyright 1991-2012 Mentor Graphics Corporation |
# // Copyright 1991-2015 Mentor Graphics Corporation |
# // All Rights Reserved. |
# // |
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION |
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS |
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS. |
# // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL |
# // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM |
# // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552. |
# // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER |
# // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905. |
# // |
# Loading sv_std.std |
# Loading work.tb_top |
17,15 → 23,18
# Loading work.digital_core |
# Loading work.clkgen |
# Loading work.clk_ctl |
# Loading work.msg_handler_top |
# Loading work.uart_core_nf |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.double_sync_low |
# Loading work.msg_handler |
# Loading work.wb_crossbar |
# Loading work.uart_core |
# Loading work.uart_cfg |
# Loading work.generic_register |
# Loading work.stat_register |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.async_fifo |
# Loading work.double_sync_low |
# Loading work.spi_core |
# Loading work.spi_if |
# Loading work.spi_ctl |
40,6 → 49,7
# Loading work.oc8051_ram_256x8_two_bist |
# Loading work.oc8051_alu_src_sel |
# Loading work.oc8051_comp |
# Loading work.oc8051_rom |
# Loading work.oc8051_cy_select |
# Loading work.oc8051_indi_addr |
# Loading work.oc8051_memory_interface |
53,7 → 63,6
# Loading work.oc8051_int |
# Loading work.oc8051_tc |
# Loading work.oc8051_tc2 |
# Loading work.oc8051_xrom |
# Loading work.oc8051_xram |
# Loading work.uart_agent |
# Loading work.m25p20 |
63,48 → 72,40
# Loading work.AT45DB321 |
# Loading work.tb_glbl |
# Loading work.bit_register |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38. |
# |
# Region: /tb_top/u_core |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'. |
# |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_rxfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_txfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'. |
# |
# do run.do |
# i : 02 |
# i : 00 |
# i : 08 |
# i : 12 |
# i : 00 |
# i : 64 |
# i : 80 |
# i : fe |
# i : 75 |
# i : 81 |
# ** Warning: (vsim-3017) ../tb/tb_top.v(134): [TFMPC] - Too few port connections. Expected 24, found 22. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core File: ../../rtl/core/digital_core.v |
# ** Warning: (vsim-3722) ../tb/tb_top.v(134): [TFMPC] - Missing connection for port 'scan_mode'. |
# ** Warning: (vsim-3722) ../tb/tb_top.v(134): [TFMPC] - Missing connection for port 'scan_enable'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(233): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_rxfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(249): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_txfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Too few port connections. Expected 55, found 52. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_8051_core/u_memory_interface File: ../../rtl/8051/oc8051_memory_interface.v |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Missing connection for port 'iack_i'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Missing connection for port 'istb_o'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(518): [TFMPC] - Missing connection for port 'idat_i'. |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(241): [TOFD] - System task or function '$shm_open' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(242): [TOFD] - System task or function '$shm_probe' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# do run.do |
# NOTE : Load memory with Initial delivery content |
# NOTE : Initial Load End |
# --> Dumpping the design |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(241): Cannot execute undefined system task/function '$shm_open' |
# |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(242): Cannot execute undefined system task/function '$shm_probe' |
# |
# NOTE: COMMUNICATION (RE)STARTED |
################################ |
# TEST STATUS : PASSED |
################################ |
# ** Note: $finish : ../tb/tb_top.v(288) |
# Time: 4411916 ps Iteration: 0 Instance: /tb_top |
# End time: 06:23:18 on Jan 01,2017, Elapsed time: 0:00:29 |
# Errors: 2, Warnings: 15 |
/trunk/verif/glog/modelsim/int_cast.log
1,36 → 1,51
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl |
Reading J:/Microsemi/Libero_SoC_v11.7/Model/tcl/vsim/pref.tcl |
|
# 10.1b |
# 10.4c |
|
# vsim +INTERNAL_ROM -do run.do -c tb_top |
# // ModelSim ACTEL 10.1b Apr 27 2012 |
# vsim -do "run.do" -c tb_top "+cast" "+INTERNAL_ROM" |
# Start time: 11:09:21 on Jan 08,2017 |
# // ModelSim Microsemi 10.4c Aug 12 2015 |
# // |
# // Copyright 1991-2012 Mentor Graphics Corporation |
# // Copyright 1991-2015 Mentor Graphics Corporation |
# // All Rights Reserved. |
# // |
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION |
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS |
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS. |
# // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL |
# // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM |
# // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552. |
# // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER |
# // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905. |
# // |
# Loading sv_std.std |
# Loading work.tb_top |
# ** Error: (vsim-7) Failed to open data file "F:/Yagna-Product/VLSI/opencores/oms8051mini/trunk/verif/run/work/delay/_primary.dat" in read mode. |
# |
# No such file or directory. (errno = ENOENT) |
# Loading work.digital_core |
# Loading work.clkgen |
# Loading work.clk_ctl |
# Loading work.msg_handler_top |
# Loading work.uart_core_nf |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.double_sync_low |
# Loading work.msg_handler |
# Loading work.wb_crossbar |
# Loading work.uart_core |
# Loading work.uart_cfg |
# Loading work.generic_register |
# Loading work.stat_register |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.async_fifo |
# Loading work.double_sync_low |
# Loading work.spi_core |
# Loading work.spi_if |
# Loading work.spi_ctl |
# Loading work.spi_cfg |
# Loading work.req_register |
# Loading work.i2cm_top |
# Loading work.i2cm_byte_ctrl |
# Loading work.i2cm_bit_ctrl |
# Loading work.oc8051_top |
# Loading work.oc8051_decoder |
# Loading work.oc8051_alu |
40,6 → 55,7
# Loading work.oc8051_ram_256x8_two_bist |
# Loading work.oc8051_alu_src_sel |
# Loading work.oc8051_comp |
# Loading work.oc8051_rom |
# Loading work.oc8051_cy_select |
# Loading work.oc8051_indi_addr |
# Loading work.oc8051_memory_interface |
53,8 → 69,8
# Loading work.oc8051_int |
# Loading work.oc8051_tc |
# Loading work.oc8051_tc2 |
# Loading work.oc8051_xrom |
# Loading work.oc8051_xram |
# Loading work.i2c_slave_model |
# Loading work.uart_agent |
# Loading work.m25p20 |
# Loading work.memory_access |
63,48 → 79,41
# Loading work.AT45DB321 |
# Loading work.tb_glbl |
# Loading work.bit_register |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38. |
# |
# Region: /tb_top/u_core |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'. |
# |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_rxfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_txfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'. |
# |
# do run.do |
# i : 02 |
# i : 00 |
# i : 08 |
# i : 12 |
# i : 00 |
# i : 65 |
# i : 80 |
# i : fe |
# i : 75 |
# i : 81 |
# ** Warning: (vsim-3017) ../tb/tb_top.v(135): [TFMPC] - Too few port connections. Expected 30, found 28. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core File: ../../rtl/core/digital_core.v |
# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_mode'. |
# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_enable'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(233): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_rxfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(249): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_txfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Too few port connections. Expected 56, found 53. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_8051_core/u_memory_interface File: ../../rtl/8051/oc8051_memory_interface.v |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'iack_i'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'istb_o'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'idat_i'. |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(266): [TOFD] - System task or function '$shm_open' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(267): [TOFD] - System task or function '$shm_probe' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# do run.do |
# NOTE : Load memory with Initial delivery content |
# NOTE : Initial Load End |
# --> Dumpping the design |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(266): Cannot execute undefined system task/function '$shm_open' |
# |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(267): Cannot execute undefined system task/function '$shm_probe' |
# |
# NOTE: COMMUNICATION (RE)STARTED |
# DEBUG i2c_slave; stop condition detected at 101 |
################################ |
# TEST STATUS : PASSED |
################################ |
# ** Note: $finish : ../tb/tb_top.v(315) |
# Time: 29636 ps Iteration: 0 Instance: /tb_top |
# End time: 11:09:22 on Jan 08,2017, Elapsed time: 0:00:01 |
# Errors: 3, Warnings: 15 |
/trunk/verif/glog/modelsim/int_divmul.log
1,36 → 1,51
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl |
Reading J:/Microsemi/Libero_SoC_v11.7/Model/tcl/vsim/pref.tcl |
|
# 10.1b |
# 10.4c |
|
# vsim +INTERNAL_ROM -do run.do -c tb_top |
# // ModelSim ACTEL 10.1b Apr 27 2012 |
# vsim -do "run.do" -c tb_top "+divmul" "+INTERNAL_ROM" |
# Start time: 11:09:11 on Jan 08,2017 |
# // ModelSim Microsemi 10.4c Aug 12 2015 |
# // |
# // Copyright 1991-2012 Mentor Graphics Corporation |
# // Copyright 1991-2015 Mentor Graphics Corporation |
# // All Rights Reserved. |
# // |
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION |
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS |
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS. |
# // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL |
# // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM |
# // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552. |
# // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER |
# // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905. |
# // |
# Loading sv_std.std |
# Loading work.tb_top |
# ** Error: (vsim-7) Failed to open data file "F:/Yagna-Product/VLSI/opencores/oms8051mini/trunk/verif/run/work/delay/_primary.dat" in read mode. |
# |
# No such file or directory. (errno = ENOENT) |
# Loading work.digital_core |
# Loading work.clkgen |
# Loading work.clk_ctl |
# Loading work.msg_handler_top |
# Loading work.uart_core_nf |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.double_sync_low |
# Loading work.msg_handler |
# Loading work.wb_crossbar |
# Loading work.uart_core |
# Loading work.uart_cfg |
# Loading work.generic_register |
# Loading work.stat_register |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.async_fifo |
# Loading work.double_sync_low |
# Loading work.spi_core |
# Loading work.spi_if |
# Loading work.spi_ctl |
# Loading work.spi_cfg |
# Loading work.req_register |
# Loading work.i2cm_top |
# Loading work.i2cm_byte_ctrl |
# Loading work.i2cm_bit_ctrl |
# Loading work.oc8051_top |
# Loading work.oc8051_decoder |
# Loading work.oc8051_alu |
40,6 → 55,7
# Loading work.oc8051_ram_256x8_two_bist |
# Loading work.oc8051_alu_src_sel |
# Loading work.oc8051_comp |
# Loading work.oc8051_rom |
# Loading work.oc8051_cy_select |
# Loading work.oc8051_indi_addr |
# Loading work.oc8051_memory_interface |
53,8 → 69,8
# Loading work.oc8051_int |
# Loading work.oc8051_tc |
# Loading work.oc8051_tc2 |
# Loading work.oc8051_xrom |
# Loading work.oc8051_xram |
# Loading work.i2c_slave_model |
# Loading work.uart_agent |
# Loading work.m25p20 |
# Loading work.memory_access |
63,48 → 79,41
# Loading work.AT45DB321 |
# Loading work.tb_glbl |
# Loading work.bit_register |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38. |
# |
# Region: /tb_top/u_core |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'. |
# |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_rxfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_txfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'. |
# |
# do run.do |
# i : 02 |
# i : 00 |
# i : 08 |
# i : 12 |
# i : 00 |
# i : 64 |
# i : 80 |
# i : fe |
# i : 75 |
# i : 81 |
# ** Warning: (vsim-3017) ../tb/tb_top.v(135): [TFMPC] - Too few port connections. Expected 30, found 28. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core File: ../../rtl/core/digital_core.v |
# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_mode'. |
# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_enable'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(233): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_rxfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(249): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_txfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Too few port connections. Expected 56, found 53. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_8051_core/u_memory_interface File: ../../rtl/8051/oc8051_memory_interface.v |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'iack_i'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'istb_o'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'idat_i'. |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(266): [TOFD] - System task or function '$shm_open' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(267): [TOFD] - System task or function '$shm_probe' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# do run.do |
# NOTE : Load memory with Initial delivery content |
# NOTE : Initial Load End |
# --> Dumpping the design |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(266): Cannot execute undefined system task/function '$shm_open' |
# |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(267): Cannot execute undefined system task/function '$shm_probe' |
# |
# NOTE: COMMUNICATION (RE)STARTED |
# DEBUG i2c_slave; stop condition detected at 101 |
################################ |
# TEST STATUS : PASSED |
################################ |
# ** Note: $finish : ../tb/tb_top.v(315) |
# Time: 46076 ps Iteration: 0 Instance: /tb_top |
# End time: 11:09:13 on Jan 08,2017, Elapsed time: 0:00:02 |
# Errors: 3, Warnings: 15 |
/trunk/verif/glog/modelsim/int_fib.log
1,36 → 1,51
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl |
Reading J:/Microsemi/Libero_SoC_v11.7/Model/tcl/vsim/pref.tcl |
|
# 10.1b |
# 10.4c |
|
# vsim +INTERNAL_ROM -do run.do -c tb_top |
# // ModelSim ACTEL 10.1b Apr 27 2012 |
# vsim -do "run.do" -c tb_top "+fib" "+INTERNAL_ROM" |
# Start time: 11:09:08 on Jan 08,2017 |
# // ModelSim Microsemi 10.4c Aug 12 2015 |
# // |
# // Copyright 1991-2012 Mentor Graphics Corporation |
# // Copyright 1991-2015 Mentor Graphics Corporation |
# // All Rights Reserved. |
# // |
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION |
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS |
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS. |
# // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL |
# // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM |
# // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552. |
# // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER |
# // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905. |
# // |
# Loading sv_std.std |
# Loading work.tb_top |
# ** Error: (vsim-7) Failed to open data file "F:/Yagna-Product/VLSI/opencores/oms8051mini/trunk/verif/run/work/delay/_primary.dat" in read mode. |
# |
# No such file or directory. (errno = ENOENT) |
# Loading work.digital_core |
# Loading work.clkgen |
# Loading work.clk_ctl |
# Loading work.msg_handler_top |
# Loading work.uart_core_nf |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.double_sync_low |
# Loading work.msg_handler |
# Loading work.wb_crossbar |
# Loading work.uart_core |
# Loading work.uart_cfg |
# Loading work.generic_register |
# Loading work.stat_register |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.async_fifo |
# Loading work.double_sync_low |
# Loading work.spi_core |
# Loading work.spi_if |
# Loading work.spi_ctl |
# Loading work.spi_cfg |
# Loading work.req_register |
# Loading work.i2cm_top |
# Loading work.i2cm_byte_ctrl |
# Loading work.i2cm_bit_ctrl |
# Loading work.oc8051_top |
# Loading work.oc8051_decoder |
# Loading work.oc8051_alu |
40,6 → 55,7
# Loading work.oc8051_ram_256x8_two_bist |
# Loading work.oc8051_alu_src_sel |
# Loading work.oc8051_comp |
# Loading work.oc8051_rom |
# Loading work.oc8051_cy_select |
# Loading work.oc8051_indi_addr |
# Loading work.oc8051_memory_interface |
53,8 → 69,8
# Loading work.oc8051_int |
# Loading work.oc8051_tc |
# Loading work.oc8051_tc2 |
# Loading work.oc8051_xrom |
# Loading work.oc8051_xram |
# Loading work.i2c_slave_model |
# Loading work.uart_agent |
# Loading work.m25p20 |
# Loading work.memory_access |
63,48 → 79,41
# Loading work.AT45DB321 |
# Loading work.tb_glbl |
# Loading work.bit_register |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38. |
# |
# Region: /tb_top/u_core |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'. |
# |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_rxfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_txfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'. |
# |
# do run.do |
# i : 02 |
# i : 00 |
# i : 08 |
# i : 12 |
# i : 01 |
# i : 51 |
# i : 80 |
# i : fe |
# i : 75 |
# i : 81 |
# ** Warning: (vsim-3017) ../tb/tb_top.v(135): [TFMPC] - Too few port connections. Expected 30, found 28. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core File: ../../rtl/core/digital_core.v |
# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_mode'. |
# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_enable'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(233): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_rxfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(249): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_txfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Too few port connections. Expected 56, found 53. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_8051_core/u_memory_interface File: ../../rtl/8051/oc8051_memory_interface.v |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'iack_i'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'istb_o'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'idat_i'. |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(266): [TOFD] - System task or function '$shm_open' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(267): [TOFD] - System task or function '$shm_probe' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# do run.do |
# NOTE : Load memory with Initial delivery content |
# NOTE : Initial Load End |
# --> Dumpping the design |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(266): Cannot execute undefined system task/function '$shm_open' |
# |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(267): Cannot execute undefined system task/function '$shm_probe' |
# |
# NOTE: COMMUNICATION (RE)STARTED |
# DEBUG i2c_slave; stop condition detected at 101 |
################################ |
# TEST STATUS : PASSED |
################################ |
# ** Note: $finish : ../tb/tb_top.v(315) |
# Time: 62316 ps Iteration: 0 Instance: /tb_top |
# End time: 11:09:10 on Jan 08,2017, Elapsed time: 0:00:02 |
# Errors: 3, Warnings: 15 |
/trunk/verif/glog/modelsim/int_gcd.log
1,36 → 1,51
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl |
Reading J:/Microsemi/Libero_SoC_v11.7/Model/tcl/vsim/pref.tcl |
|
# 10.1b |
# 10.4c |
|
# vsim +INTERNAL_ROM -do run.do -c tb_top |
# // ModelSim ACTEL 10.1b Apr 27 2012 |
# vsim -do "run.do" -c tb_top "+gcd" "+INTERNAL_ROM" |
# Start time: 11:09:18 on Jan 08,2017 |
# // ModelSim Microsemi 10.4c Aug 12 2015 |
# // |
# // Copyright 1991-2012 Mentor Graphics Corporation |
# // Copyright 1991-2015 Mentor Graphics Corporation |
# // All Rights Reserved. |
# // |
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION |
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS |
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS. |
# // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL |
# // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM |
# // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552. |
# // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER |
# // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905. |
# // |
# Loading sv_std.std |
# Loading work.tb_top |
# ** Error: (vsim-7) Failed to open data file "F:/Yagna-Product/VLSI/opencores/oms8051mini/trunk/verif/run/work/delay/_primary.dat" in read mode. |
# |
# No such file or directory. (errno = ENOENT) |
# Loading work.digital_core |
# Loading work.clkgen |
# Loading work.clk_ctl |
# Loading work.msg_handler_top |
# Loading work.uart_core_nf |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.double_sync_low |
# Loading work.msg_handler |
# Loading work.wb_crossbar |
# Loading work.uart_core |
# Loading work.uart_cfg |
# Loading work.generic_register |
# Loading work.stat_register |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.async_fifo |
# Loading work.double_sync_low |
# Loading work.spi_core |
# Loading work.spi_if |
# Loading work.spi_ctl |
# Loading work.spi_cfg |
# Loading work.req_register |
# Loading work.i2cm_top |
# Loading work.i2cm_byte_ctrl |
# Loading work.i2cm_bit_ctrl |
# Loading work.oc8051_top |
# Loading work.oc8051_decoder |
# Loading work.oc8051_alu |
40,6 → 55,7
# Loading work.oc8051_ram_256x8_two_bist |
# Loading work.oc8051_alu_src_sel |
# Loading work.oc8051_comp |
# Loading work.oc8051_rom |
# Loading work.oc8051_cy_select |
# Loading work.oc8051_indi_addr |
# Loading work.oc8051_memory_interface |
53,8 → 69,8
# Loading work.oc8051_int |
# Loading work.oc8051_tc |
# Loading work.oc8051_tc2 |
# Loading work.oc8051_xrom |
# Loading work.oc8051_xram |
# Loading work.i2c_slave_model |
# Loading work.uart_agent |
# Loading work.m25p20 |
# Loading work.memory_access |
63,48 → 79,41
# Loading work.AT45DB321 |
# Loading work.tb_glbl |
# Loading work.bit_register |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38. |
# |
# Region: /tb_top/u_core |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'. |
# |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_rxfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_txfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'. |
# |
# do run.do |
# i : 02 |
# i : 00 |
# i : 08 |
# i : 12 |
# i : 00 |
# i : 64 |
# i : 80 |
# i : fe |
# i : 75 |
# i : 81 |
# ** Warning: (vsim-3017) ../tb/tb_top.v(135): [TFMPC] - Too few port connections. Expected 30, found 28. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core File: ../../rtl/core/digital_core.v |
# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_mode'. |
# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_enable'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(233): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_rxfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(249): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_txfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Too few port connections. Expected 56, found 53. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_8051_core/u_memory_interface File: ../../rtl/8051/oc8051_memory_interface.v |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'iack_i'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'istb_o'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'idat_i'. |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(266): [TOFD] - System task or function '$shm_open' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(267): [TOFD] - System task or function '$shm_probe' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# do run.do |
# NOTE : Load memory with Initial delivery content |
# NOTE : Initial Load End |
# --> Dumpping the design |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(266): Cannot execute undefined system task/function '$shm_open' |
# |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(267): Cannot execute undefined system task/function '$shm_probe' |
# |
# NOTE: COMMUNICATION (RE)STARTED |
# DEBUG i2c_slave; stop condition detected at 101 |
################################ |
# TEST STATUS : PASSED |
################################ |
# ** Note: $finish : ../tb/tb_top.v(315) |
# Time: 33876 ps Iteration: 0 Instance: /tb_top |
# End time: 11:09:20 on Jan 08,2017, Elapsed time: 0:00:02 |
# Errors: 3, Warnings: 15 |
/trunk/verif/glog/modelsim/int_i2cm_burst_wrrd.log
0,0 → 1,140
Reading J:/Microsemi/Libero_SoC_v11.7/Model/tcl/vsim/pref.tcl |
|
# 10.4c |
|
# vsim -do "run.do" -c tb_top "+i2cm_burst_wrrd" "+INTERNAL_ROM" |
# Start time: 11:10:00 on Jan 08,2017 |
# // ModelSim Microsemi 10.4c Aug 12 2015 |
# // |
# // Copyright 1991-2015 Mentor Graphics Corporation |
# // All Rights Reserved. |
# // |
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION |
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS |
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS. |
# // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL |
# // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM |
# // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552. |
# // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER |
# // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905. |
# // |
# Loading sv_std.std |
# Loading work.tb_top |
# ** Error: (vsim-7) Failed to open data file "F:/Yagna-Product/VLSI/opencores/oms8051mini/trunk/verif/run/work/delay/_primary.dat" in read mode. |
# |
# No such file or directory. (errno = ENOENT) |
# Loading work.digital_core |
# Loading work.clkgen |
# Loading work.clk_ctl |
# Loading work.msg_handler_top |
# Loading work.uart_core_nf |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.double_sync_low |
# Loading work.msg_handler |
# Loading work.wb_crossbar |
# Loading work.uart_core |
# Loading work.uart_cfg |
# Loading work.generic_register |
# Loading work.stat_register |
# Loading work.async_fifo |
# Loading work.spi_core |
# Loading work.spi_if |
# Loading work.spi_ctl |
# Loading work.spi_cfg |
# Loading work.req_register |
# Loading work.i2cm_top |
# Loading work.i2cm_byte_ctrl |
# Loading work.i2cm_bit_ctrl |
# Loading work.oc8051_top |
# Loading work.oc8051_decoder |
# Loading work.oc8051_alu |
# Loading work.oc8051_multiply |
# Loading work.oc8051_divide |
# Loading work.oc8051_ram_top |
# Loading work.oc8051_ram_256x8_two_bist |
# Loading work.oc8051_alu_src_sel |
# Loading work.oc8051_comp |
# Loading work.oc8051_rom |
# Loading work.oc8051_cy_select |
# Loading work.oc8051_indi_addr |
# Loading work.oc8051_memory_interface |
# Loading work.oc8051_sfr |
# Loading work.oc8051_acc |
# Loading work.oc8051_b_register |
# Loading work.oc8051_sp |
# Loading work.oc8051_dptr |
# Loading work.oc8051_psw |
# Loading work.oc8051_ports |
# Loading work.oc8051_int |
# Loading work.oc8051_tc |
# Loading work.oc8051_tc2 |
# Loading work.oc8051_xram |
# Loading work.i2c_slave_model |
# Loading work.uart_agent |
# Loading work.m25p20 |
# Loading work.memory_access |
# Loading work.acdc_check |
# Loading work.internal_logic |
# Loading work.AT45DB321 |
# Loading work.tb_glbl |
# Loading work.bit_register |
# ** Warning: (vsim-3017) ../tb/tb_top.v(135): [TFMPC] - Too few port connections. Expected 30, found 28. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core File: ../../rtl/core/digital_core.v |
# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_mode'. |
# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_enable'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(233): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_rxfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(249): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_txfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Too few port connections. Expected 56, found 53. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_8051_core/u_memory_interface File: ../../rtl/8051/oc8051_memory_interface.v |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'iack_i'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'istb_o'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'idat_i'. |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(266): [TOFD] - System task or function '$shm_open' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(267): [TOFD] - System task or function '$shm_probe' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# do run.do |
# NOTE : Load memory with Initial delivery content |
# NOTE : Initial Load End |
# --> Dumpping the design |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(266): Cannot execute undefined system task/function '$shm_open' |
# |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(267): Cannot execute undefined system task/function '$shm_probe' |
# |
# NOTE: COMMUNICATION (RE)STARTED |
# DEBUG i2c_slave; stop condition detected at 101 |
# DEBUG i2c_slave; start condition detected at 44116 |
# DEBUG i2c_slave; command byte received (write) at 228138 |
# DEBUG i2c_slave; address received. adr=66, ack=1 |
# DEBUG i2c_slave; data block write 12 to address 66 |
# DEBUG i2c_slave; data block write 34 to address 67 |
# DEBUG i2c_slave; data block write 56 to address 68 |
# DEBUG i2c_slave; data block write 78 to address 69 |
# DEBUG i2c_slave; stop condition detected at 1262136 |
# DEBUG i2c_slave; start condition detected at 1278136 |
# DEBUG i2c_slave; command byte received (write) at 1462138 |
# DEBUG i2c_slave; address received. adr=66, ack=1 |
# DEBUG i2c_slave; stop condition detected at 1704136 |
# DEBUG i2c_slave; start condition detected at 1720136 |
# DEBUG i2c_slave; command byte received (read) at 1904138 |
# DEBUG i2c_slave; data block read 12 from address 66 (1) |
# DEBUG i2c_slave; memcheck [66]=12 |
# DEBUG i2c_slave; data block read 34 from address 67 (2) |
# DEBUG i2c_slave; data block read 56 from address 68 (2) |
# DEBUG i2c_slave; data block read 78 from address 69 (2) |
# DEBUG i2c_slave; data block read xx from address 6a (2) |
# DEBUG i2c_slave; stop condition detected at 2740136 |
################################ |
# TEST STATUS : PASSED |
################################ |
# ** Note: $finish : ../tb/tb_top.v(315) |
# Time: 2741016 ps Iteration: 0 Instance: /tb_top |
# End time: 11:10:21 on Jan 08,2017, Elapsed time: 0:00:21 |
# Errors: 3, Warnings: 15 |
/trunk/verif/glog/modelsim/int_sort.log
1,36 → 1,51
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl |
Reading J:/Microsemi/Libero_SoC_v11.7/Model/tcl/vsim/pref.tcl |
|
# 10.1b |
# 10.4c |
|
# vsim +INTERNAL_ROM -do run.do -c tb_top |
# // ModelSim ACTEL 10.1b Apr 27 2012 |
# vsim -do "run.do" -c tb_top "+sort" "+INTERNAL_ROM" |
# Start time: 11:09:14 on Jan 08,2017 |
# // ModelSim Microsemi 10.4c Aug 12 2015 |
# // |
# // Copyright 1991-2012 Mentor Graphics Corporation |
# // Copyright 1991-2015 Mentor Graphics Corporation |
# // All Rights Reserved. |
# // |
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION |
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS |
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS. |
# // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL |
# // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM |
# // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552. |
# // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER |
# // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905. |
# // |
# Loading sv_std.std |
# Loading work.tb_top |
# ** Error: (vsim-7) Failed to open data file "F:/Yagna-Product/VLSI/opencores/oms8051mini/trunk/verif/run/work/delay/_primary.dat" in read mode. |
# |
# No such file or directory. (errno = ENOENT) |
# Loading work.digital_core |
# Loading work.clkgen |
# Loading work.clk_ctl |
# Loading work.msg_handler_top |
# Loading work.uart_core_nf |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.double_sync_low |
# Loading work.msg_handler |
# Loading work.wb_crossbar |
# Loading work.uart_core |
# Loading work.uart_cfg |
# Loading work.generic_register |
# Loading work.stat_register |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.async_fifo |
# Loading work.double_sync_low |
# Loading work.spi_core |
# Loading work.spi_if |
# Loading work.spi_ctl |
# Loading work.spi_cfg |
# Loading work.req_register |
# Loading work.i2cm_top |
# Loading work.i2cm_byte_ctrl |
# Loading work.i2cm_bit_ctrl |
# Loading work.oc8051_top |
# Loading work.oc8051_decoder |
# Loading work.oc8051_alu |
40,6 → 55,7
# Loading work.oc8051_ram_256x8_two_bist |
# Loading work.oc8051_alu_src_sel |
# Loading work.oc8051_comp |
# Loading work.oc8051_rom |
# Loading work.oc8051_cy_select |
# Loading work.oc8051_indi_addr |
# Loading work.oc8051_memory_interface |
53,8 → 69,8
# Loading work.oc8051_int |
# Loading work.oc8051_tc |
# Loading work.oc8051_tc2 |
# Loading work.oc8051_xrom |
# Loading work.oc8051_xram |
# Loading work.i2c_slave_model |
# Loading work.uart_agent |
# Loading work.m25p20 |
# Loading work.memory_access |
63,48 → 79,41
# Loading work.AT45DB321 |
# Loading work.tb_glbl |
# Loading work.bit_register |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38. |
# |
# Region: /tb_top/u_core |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'. |
# |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_rxfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_txfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'. |
# |
# do run.do |
# i : 02 |
# i : 00 |
# i : 08 |
# i : 12 |
# i : 01 |
# i : 1f |
# i : 80 |
# i : fe |
# i : 75 |
# i : 81 |
# ** Warning: (vsim-3017) ../tb/tb_top.v(135): [TFMPC] - Too few port connections. Expected 30, found 28. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core File: ../../rtl/core/digital_core.v |
# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_mode'. |
# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_enable'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(233): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_rxfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(249): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_txfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Too few port connections. Expected 56, found 53. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_8051_core/u_memory_interface File: ../../rtl/8051/oc8051_memory_interface.v |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'iack_i'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'istb_o'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'idat_i'. |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(266): [TOFD] - System task or function '$shm_open' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(267): [TOFD] - System task or function '$shm_probe' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# do run.do |
# NOTE : Load memory with Initial delivery content |
# NOTE : Initial Load End |
# --> Dumpping the design |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(266): Cannot execute undefined system task/function '$shm_open' |
# |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(267): Cannot execute undefined system task/function '$shm_probe' |
# |
# NOTE: COMMUNICATION (RE)STARTED |
# DEBUG i2c_slave; stop condition detected at 101 |
################################ |
# TEST STATUS : PASSED |
################################ |
# ** Note: $finish : ../tb/tb_top.v(315) |
# Time: 184536 ps Iteration: 0 Instance: /tb_top |
# End time: 11:09:17 on Jan 08,2017, Elapsed time: 0:00:03 |
# Errors: 3, Warnings: 15 |
/trunk/verif/glog/modelsim/int_uart_lb.log
0,0 → 1,387
Reading J:/Microsemi/Libero_SoC_v11.7/Model/tcl/vsim/pref.tcl |
|
# 10.4c |
|
# vsim -do "run.do" -c tb_top "+uart_lb" "+INTERNAL_ROM" |
# Start time: 11:09:03 on Jan 08,2017 |
# // ModelSim Microsemi 10.4c Aug 12 2015 |
# // |
# // Copyright 1991-2015 Mentor Graphics Corporation |
# // All Rights Reserved. |
# // |
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION |
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS |
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS. |
# // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL |
# // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM |
# // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552. |
# // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER |
# // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905. |
# // |
# Loading sv_std.std |
# Loading work.tb_top |
# ** Error: (vsim-7) Failed to open data file "F:/Yagna-Product/VLSI/opencores/oms8051mini/trunk/verif/run/work/delay/_primary.dat" in read mode. |
# |
# No such file or directory. (errno = ENOENT) |
# Loading work.digital_core |
# Loading work.clkgen |
# Loading work.clk_ctl |
# Loading work.msg_handler_top |
# Loading work.uart_core_nf |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.double_sync_low |
# Loading work.msg_handler |
# Loading work.wb_crossbar |
# Loading work.uart_core |
# Loading work.uart_cfg |
# Loading work.generic_register |
# Loading work.stat_register |
# Loading work.async_fifo |
# Loading work.spi_core |
# Loading work.spi_if |
# Loading work.spi_ctl |
# Loading work.spi_cfg |
# Loading work.req_register |
# Loading work.i2cm_top |
# Loading work.i2cm_byte_ctrl |
# Loading work.i2cm_bit_ctrl |
# Loading work.oc8051_top |
# Loading work.oc8051_decoder |
# Loading work.oc8051_alu |
# Loading work.oc8051_multiply |
# Loading work.oc8051_divide |
# Loading work.oc8051_ram_top |
# Loading work.oc8051_ram_256x8_two_bist |
# Loading work.oc8051_alu_src_sel |
# Loading work.oc8051_comp |
# Loading work.oc8051_rom |
# Loading work.oc8051_cy_select |
# Loading work.oc8051_indi_addr |
# Loading work.oc8051_memory_interface |
# Loading work.oc8051_sfr |
# Loading work.oc8051_acc |
# Loading work.oc8051_b_register |
# Loading work.oc8051_sp |
# Loading work.oc8051_dptr |
# Loading work.oc8051_psw |
# Loading work.oc8051_ports |
# Loading work.oc8051_int |
# Loading work.oc8051_tc |
# Loading work.oc8051_tc2 |
# Loading work.oc8051_xram |
# Loading work.i2c_slave_model |
# Loading work.uart_agent |
# Loading work.m25p20 |
# Loading work.memory_access |
# Loading work.acdc_check |
# Loading work.internal_logic |
# Loading work.AT45DB321 |
# Loading work.tb_glbl |
# Loading work.bit_register |
# ** Warning: (vsim-3017) ../tb/tb_top.v(135): [TFMPC] - Too few port connections. Expected 30, found 28. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core File: ../../rtl/core/digital_core.v |
# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_mode'. |
# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_enable'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(233): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_rxfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(249): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_txfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Too few port connections. Expected 56, found 53. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_8051_core/u_memory_interface File: ../../rtl/8051/oc8051_memory_interface.v |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'iack_i'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'istb_o'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'idat_i'. |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(266): [TOFD] - System task or function '$shm_open' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(267): [TOFD] - System task or function '$shm_probe' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# do run.do |
# NOTE : Load memory with Initial delivery content |
# NOTE : Initial Load End |
# --> Dumpping the design |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(266): Cannot execute undefined system task/function '$shm_open' |
# |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(267): Cannot execute undefined system task/function '$shm_probe' |
# |
# NOTE: COMMUNICATION (RE)STARTED |
# DEBUG i2c_slave; stop condition detected at 101 |
# |
# ... Writing char 24 ... |
# ... Write data 24 to UART done cnt : 1 ... |
# |
# |
# ... Writing char 81 ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 24 |
# ... Read Data from UART done cnt : 1... |
# ... Write data 81 to UART done cnt : 2 ... |
# |
# |
# ... Writing char 09 ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 81 |
# ... Read Data from UART done cnt : 2... |
# ... Write data 09 to UART done cnt : 3 ... |
# |
# |
# ... Writing char 63 ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 09 |
# ... Read Data from UART done cnt : 3... |
# ... Write data 63 to UART done cnt : 4 ... |
# |
# |
# ... Writing char 0d ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 63 |
# ... Read Data from UART done cnt : 4... |
# ... Write data 0d to UART done cnt : 5 ... |
# |
# |
# ... Writing char 8d ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 0d |
# ... Read Data from UART done cnt : 5... |
# ... Write data 8d to UART done cnt : 6 ... |
# |
# |
# ... Writing char 65 ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 8d |
# ... Read Data from UART done cnt : 6... |
# ... Write data 65 to UART done cnt : 7 ... |
# |
# |
# ... Writing char 12 ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 65 |
# ... Read Data from UART done cnt : 7... |
# ... Write data 12 to UART done cnt : 8 ... |
# |
# |
# ... Writing char 01 ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 12 |
# ... Read Data from UART done cnt : 8... |
# ... Write data 01 to UART done cnt : 9 ... |
# |
# |
# ... Writing char 0d ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 01 |
# ... Read Data from UART done cnt : 9... |
# ... Write data 0d to UART done cnt : 10 ... |
# |
# |
# ... Writing char 76 ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 0d |
# ... Read Data from UART done cnt : 10... |
# ... Write data 76 to UART done cnt : 11 ... |
# |
# |
# ... Writing char 3d ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 76 |
# ... Read Data from UART done cnt : 11... |
# ... Write data 3d to UART done cnt : 12 ... |
# |
# |
# ... Writing char ed ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 3d |
# ... Read Data from UART done cnt : 12... |
# ... Write data ed to UART done cnt : 13 ... |
# |
# |
# ... Writing char 8c ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match ed |
# ... Read Data from UART done cnt : 13... |
# ... Write data 8c to UART done cnt : 14 ... |
# |
# |
# ... Writing char f9 ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 8c |
# ... Read Data from UART done cnt : 14... |
# ... Write data f9 to UART done cnt : 15 ... |
# |
# |
# ... Writing char c6 ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match f9 |
# ... Read Data from UART done cnt : 15... |
# ... Write data c6 to UART done cnt : 16 ... |
# |
# |
# ... Writing char c5 ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match c6 |
# ... Read Data from UART done cnt : 16... |
# ... Write data c5 to UART done cnt : 17 ... |
# |
# |
# ... Writing char aa ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match c5 |
# ... Read Data from UART done cnt : 17... |
# ... Write data aa to UART done cnt : 18 ... |
# |
# |
# ... Writing char e5 ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match aa |
# ... Read Data from UART done cnt : 18... |
# ... Write data e5 to UART done cnt : 19 ... |
# |
# |
# ... Writing char 77 ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match e5 |
# ... Read Data from UART done cnt : 19... |
# ... Write data 77 to UART done cnt : 20 ... |
# |
# |
# ... Writing char 12 ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 77 |
# ... Read Data from UART done cnt : 20... |
# ... Write data 12 to UART done cnt : 21 ... |
# |
# |
# ... Writing char 8f ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 12 |
# ... Read Data from UART done cnt : 21... |
# ... Write data 8f to UART done cnt : 22 ... |
# |
# |
# ... Writing char f2 ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 8f |
# ... Read Data from UART done cnt : 22... |
# ... Write data f2 to UART done cnt : 23 ... |
# |
# |
# ... Writing char ce ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match f2 |
# ... Read Data from UART done cnt : 23... |
# ... Write data ce to UART done cnt : 24 ... |
# |
# |
# ... Writing char e8 ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match ce |
# ... Read Data from UART done cnt : 24... |
# ... Write data e8 to UART done cnt : 25 ... |
# |
# |
# ... Writing char c5 ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match e8 |
# ... Read Data from UART done cnt : 25... |
# ... Write data c5 to UART done cnt : 26 ... |
# |
# |
# ... Writing char 5c ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match c5 |
# ... Read Data from UART done cnt : 26... |
# ... Write data 5c to UART done cnt : 27 ... |
# |
# |
# ... Writing char bd ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 5c |
# ... Read Data from UART done cnt : 27... |
# ... Write data bd to UART done cnt : 28 ... |
# |
# |
# ... Writing char 2d ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match bd |
# ... Read Data from UART done cnt : 28... |
# ... Write data 2d to UART done cnt : 29 ... |
# |
# |
# ... Writing char 65 ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 2d |
# ... Read Data from UART done cnt : 29... |
# ... Write data 65 to UART done cnt : 30 ... |
# |
# |
# ... Writing char 63 ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 65 |
# ... Read Data from UART done cnt : 30... |
# ... Write data 63 to UART done cnt : 31 ... |
# |
# |
# ... Writing char 0a ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 63 |
# ... Read Data from UART done cnt : 31... |
# ... Write data 0a to UART done cnt : 32 ... |
# |
# |
# ... Writing char 80 ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 0a |
# ... Read Data from UART done cnt : 32... |
# ... Write data 80 to UART done cnt : 33 ... |
# |
# |
# ... Writing char 20 ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 80 |
# ... Read Data from UART done cnt : 33... |
# ... Write data 20 to UART done cnt : 34 ... |
# |
# |
# ... Writing char aa ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 20 |
# ... Read Data from UART done cnt : 34... |
# ... Write data aa to UART done cnt : 35 ... |
# |
# |
# ... Writing char 9d ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match aa |
# ... Read Data from UART done cnt : 35... |
# ... Write data 9d to UART done cnt : 36 ... |
# |
# |
# ... Writing char 96 ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 9d |
# ... Read Data from UART done cnt : 36... |
# ... Write data 96 to UART done cnt : 37 ... |
# |
# |
# ... Writing char 13 ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 96 |
# ... Read Data from UART done cnt : 37... |
# ... Write data 13 to UART done cnt : 38 ... |
# |
# |
# ... Writing char 0d ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 13 |
# ... Read Data from UART done cnt : 38... |
# ... Write data 0d to UART done cnt : 39 ... |
# |
# |
# ... Writing char 53 ... |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 0d |
# ... Read Data from UART done cnt : 39... |
# ... Write data 53 to UART done cnt : 40 ... |
# |
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 53 |
# ... Read Data from UART done cnt : 40... |
# -------------------- Reporting Configuration -------------------- |
# Data bit number setting is : 8 |
# Stop bit number setting is : 1 |
# Divisor of Uart clock is : 15 |
# Parity is disable |
# Even parity setting |
# FIFO mode is disable |
# ----------------------------------------------------------------- |
# -------------------- Reporting Status -------------------- |
# |
# Number of character received is : 40 |
# Number of character sent is : 40 |
# Number of parity error rxd is : 0 |
# Number of stop1 error rxd is : 0 |
# Number of stop2 error rxd is : 0 |
# Number of timeout error is : 0 |
# Number of error is : 0 |
# ----------------------------------------------------------------- |
# |
# ------------------------------------------------- |
# Test Status |
# warnings: 0, errors: 0 |
# |
# ------------------------------------------------- |
# Test Status |
# warnings: 0, errors: 0 |
# |
# ========= |
# Test Status: TEST PASSED |
# ========= |
# |
# ** Note: $finish : ../lib/tb_glbl.v(70) |
# Time: 329091 ps Iteration: 0 Instance: /tb_top |
# End time: 11:09:07 on Jan 08,2017, Elapsed time: 0:00:04 |
# Errors: 3, Warnings: 15 |
/trunk/verif/glog/modelsim/int_xram.log
1,36 → 1,51
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl |
Reading J:/Microsemi/Libero_SoC_v11.7/Model/tcl/vsim/pref.tcl |
|
# 10.1b |
# 10.4c |
|
# vsim +INTERNAL_ROM -do run.do -c tb_top |
# // ModelSim ACTEL 10.1b Apr 27 2012 |
# vsim -do "run.do" -c tb_top "+xram" "+INTERNAL_ROM" |
# Start time: 11:09:24 on Jan 08,2017 |
# // ModelSim Microsemi 10.4c Aug 12 2015 |
# // |
# // Copyright 1991-2012 Mentor Graphics Corporation |
# // Copyright 1991-2015 Mentor Graphics Corporation |
# // All Rights Reserved. |
# // |
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION |
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS |
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS. |
# // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL |
# // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM |
# // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552. |
# // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER |
# // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905. |
# // |
# Loading sv_std.std |
# Loading work.tb_top |
# ** Error: (vsim-7) Failed to open data file "F:/Yagna-Product/VLSI/opencores/oms8051mini/trunk/verif/run/work/delay/_primary.dat" in read mode. |
# |
# No such file or directory. (errno = ENOENT) |
# Loading work.digital_core |
# Loading work.clkgen |
# Loading work.clk_ctl |
# Loading work.msg_handler_top |
# Loading work.uart_core_nf |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.double_sync_low |
# Loading work.msg_handler |
# Loading work.wb_crossbar |
# Loading work.uart_core |
# Loading work.uart_cfg |
# Loading work.generic_register |
# Loading work.stat_register |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.async_fifo |
# Loading work.double_sync_low |
# Loading work.spi_core |
# Loading work.spi_if |
# Loading work.spi_ctl |
# Loading work.spi_cfg |
# Loading work.req_register |
# Loading work.i2cm_top |
# Loading work.i2cm_byte_ctrl |
# Loading work.i2cm_bit_ctrl |
# Loading work.oc8051_top |
# Loading work.oc8051_decoder |
# Loading work.oc8051_alu |
40,6 → 55,7
# Loading work.oc8051_ram_256x8_two_bist |
# Loading work.oc8051_alu_src_sel |
# Loading work.oc8051_comp |
# Loading work.oc8051_rom |
# Loading work.oc8051_cy_select |
# Loading work.oc8051_indi_addr |
# Loading work.oc8051_memory_interface |
53,8 → 69,8
# Loading work.oc8051_int |
# Loading work.oc8051_tc |
# Loading work.oc8051_tc2 |
# Loading work.oc8051_xrom |
# Loading work.oc8051_xram |
# Loading work.i2c_slave_model |
# Loading work.uart_agent |
# Loading work.m25p20 |
# Loading work.memory_access |
63,48 → 79,41
# Loading work.AT45DB321 |
# Loading work.tb_glbl |
# Loading work.bit_register |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38. |
# |
# Region: /tb_top/u_core |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'. |
# |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_rxfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_txfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'. |
# |
# do run.do |
# i : 02 |
# i : 00 |
# i : 08 |
# i : 12 |
# i : 00 |
# i : 64 |
# i : 80 |
# i : fe |
# i : 75 |
# i : 81 |
# ** Warning: (vsim-3017) ../tb/tb_top.v(135): [TFMPC] - Too few port connections. Expected 30, found 28. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core File: ../../rtl/core/digital_core.v |
# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_mode'. |
# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_enable'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(233): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_rxfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(249): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_txfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Too few port connections. Expected 56, found 53. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_8051_core/u_memory_interface File: ../../rtl/8051/oc8051_memory_interface.v |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'iack_i'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'istb_o'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'idat_i'. |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(266): [TOFD] - System task or function '$shm_open' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(267): [TOFD] - System task or function '$shm_probe' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# do run.do |
# NOTE : Load memory with Initial delivery content |
# NOTE : Initial Load End |
# --> Dumpping the design |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(266): Cannot execute undefined system task/function '$shm_open' |
# |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(267): Cannot execute undefined system task/function '$shm_probe' |
# |
# NOTE: COMMUNICATION (RE)STARTED |
# DEBUG i2c_slave; stop condition detected at 101 |
################################ |
# TEST STATUS : PASSED |
################################ |
# ** Note: $finish : ../tb/tb_top.v(315) |
# Time: 4411916 ps Iteration: 0 Instance: /tb_top |
# End time: 11:09:58 on Jan 08,2017, Elapsed time: 0:00:34 |
# Errors: 3, Warnings: 15 |
/trunk/verif/glog/modelsim/spi_test_1.log
1,36 → 1,51
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl |
Reading J:/Microsemi/Libero_SoC_v11.7/Model/tcl/vsim/pref.tcl |
|
# 10.1b |
# 10.4c |
|
# vsim +spi_test_1 +INTERNAL_ROM -do run.do -c tb_top |
# // ModelSim ACTEL 10.1b Apr 27 2012 |
# vsim -do "run.do" -c tb_top "+spi_test_1" "+INTERNAL_ROM" |
# Start time: 11:08:35 on Jan 08,2017 |
# // ModelSim Microsemi 10.4c Aug 12 2015 |
# // |
# // Copyright 1991-2012 Mentor Graphics Corporation |
# // Copyright 1991-2015 Mentor Graphics Corporation |
# // All Rights Reserved. |
# // |
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION |
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS |
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS. |
# // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL |
# // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM |
# // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552. |
# // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER |
# // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905. |
# // |
# Loading sv_std.std |
# Loading work.tb_top |
# ** Error: (vsim-7) Failed to open data file "F:/Yagna-Product/VLSI/opencores/oms8051mini/trunk/verif/run/work/delay/_primary.dat" in read mode. |
# |
# No such file or directory. (errno = ENOENT) |
# Loading work.digital_core |
# Loading work.clkgen |
# Loading work.clk_ctl |
# Loading work.msg_handler_top |
# Loading work.uart_core_nf |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.double_sync_low |
# Loading work.msg_handler |
# Loading work.wb_crossbar |
# Loading work.uart_core |
# Loading work.uart_cfg |
# Loading work.generic_register |
# Loading work.stat_register |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.async_fifo |
# Loading work.double_sync_low |
# Loading work.spi_core |
# Loading work.spi_if |
# Loading work.spi_ctl |
# Loading work.spi_cfg |
# Loading work.req_register |
# Loading work.i2cm_top |
# Loading work.i2cm_byte_ctrl |
# Loading work.i2cm_bit_ctrl |
# Loading work.oc8051_top |
# Loading work.oc8051_decoder |
# Loading work.oc8051_alu |
40,6 → 55,7
# Loading work.oc8051_ram_256x8_two_bist |
# Loading work.oc8051_alu_src_sel |
# Loading work.oc8051_comp |
# Loading work.oc8051_rom |
# Loading work.oc8051_cy_select |
# Loading work.oc8051_indi_addr |
# Loading work.oc8051_memory_interface |
53,8 → 69,8
# Loading work.oc8051_int |
# Loading work.oc8051_tc |
# Loading work.oc8051_tc2 |
# Loading work.oc8051_xrom |
# Loading work.oc8051_xram |
# Loading work.i2c_slave_model |
# Loading work.uart_agent |
# Loading work.m25p20 |
# Loading work.memory_access |
63,399 → 79,388
# Loading work.AT45DB321 |
# Loading work.tb_glbl |
# Loading work.bit_register |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38. |
# |
# Region: /tb_top/u_core |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'. |
# |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_rxfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_txfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'. |
# |
# do run.do |
# i : 02 |
# i : 00 |
# i : 08 |
# i : 12 |
# i : 00 |
# i : 64 |
# i : 80 |
# i : fe |
# i : 75 |
# i : 81 |
# ** Warning: (vsim-3017) ../tb/tb_top.v(135): [TFMPC] - Too few port connections. Expected 30, found 28. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core File: ../../rtl/core/digital_core.v |
# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_mode'. |
# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_enable'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(233): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_rxfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(249): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_txfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Too few port connections. Expected 56, found 53. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_8051_core/u_memory_interface File: ../../rtl/8051/oc8051_memory_interface.v |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'iack_i'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'istb_o'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'idat_i'. |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(266): [TOFD] - System task or function '$shm_open' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(267): [TOFD] - System task or function '$shm_probe' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# do run.do |
# NOTE : Load memory with Initial delivery content |
# NOTE : Initial Load End |
# --> Dumpping the design |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(266): Cannot execute undefined system task/function '$shm_open' |
# |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(267): Cannot execute undefined system task/function '$shm_probe' |
# |
# NOTE: COMMUNICATION (RE)STARTED |
# DEBUG i2c_slave; stop condition detected at 101 |
############################################ |
# Testing ST Flash Read/Write Access |
############################################ |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 06000000 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80020240 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = d8000000 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0201 |
# 6775 : tb_top.spi_sector_errase : Sending Sector Errase for Address : 000000 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 06000000 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 80020240 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = d8000000 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0201 |
# 7995 : tb_top.spi_sector_errase : Sending Sector Errase for Address : 000000 |
# NOTE : Sector erase cycle has begun |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 05000000 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80020200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 05000000 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 80020200 |
# NOTE : Only a Read Status Register instruction will be valid |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80220240 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 80220240 |
# Total time Elapsed: 0(us): tb_top.spi_wait_busy : Checking the SPI RDStatus : 03000000 |
# NOTE : Sector erase cycle is finished |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 05000000 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80020200 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80220240 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 05000000 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 80020200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 80220240 |
# Total time Elapsed: 0(us): tb_top.spi_wait_busy : Checking the SPI RDStatus : 00000000 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 06000000 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80020240 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 02000000 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 00010203 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 06000000 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 80020240 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 02000000 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 00010203 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 00010203 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 04050607 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 04050607 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 04050607 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 08090a0b |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 08090a0b |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 08090a0b |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 0c0d0e0f |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 0c0d0e0f |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 0c0d0e0f |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 10111213 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 10111213 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 10111213 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 14151617 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 14151617 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 14151617 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 18191a1b |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 18191a1b |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 18191a1b |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 1c1d1e1f |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 1c1d1e1f |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 1c1d1e1f |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 20212223 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 20212223 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 20212223 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 24252627 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 24252627 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 24252627 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 28292a2b |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 28292a2b |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 28292a2b |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 2c2d2e2f |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 2c2d2e2f |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 2c2d2e2f |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 30313233 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 30313233 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 30313233 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 34353637 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 34353637 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 34353637 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 38393a3b |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 38393a3b |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 38393a3b |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 3c3d3e3f |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 3c3d3e3f |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 3c3d3e3f |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 40414243 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 40414243 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 40414243 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 44454647 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 44454647 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 44454647 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 48494a4b |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 48494a4b |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 48494a4b |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 4c4d4e4f |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 4c4d4e4f |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 4c4d4e4f |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 50515253 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 50515253 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 50515253 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 54555657 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 54555657 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 54555657 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 58595a5b |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 58595a5b |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 58595a5b |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 5c5d5e5f |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 5c5d5e5f |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 5c5d5e5f |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 60616263 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 60616263 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 60616263 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 64656667 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 64656667 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 64656667 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 68696a6b |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 68696a6b |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 68696a6b |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 6c6d6e6f |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 6c6d6e6f |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 6c6d6e6f |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 70717273 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 70717273 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 70717273 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 74757677 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 74757677 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 74757677 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 78797a7b |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 78797a7b |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 78797a7b |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 7c7d7e7f |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 7c7d7e7f |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 7c7d7e7f |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 80818283 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 80818283 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 80818283 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 84858687 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 84858687 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 84858687 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 88898a8b |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 88898a8b |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 88898a8b |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 8c8d8e8f |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 8c8d8e8f |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 8c8d8e8f |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 90919293 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 90919293 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 90919293 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 94959697 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 94959697 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 94959697 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 98999a9b |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 98999a9b |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 98999a9b |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 9c9d9e9f |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 9c9d9e9f |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : 9c9d9e9f |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = a0a1a2a3 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = a0a1a2a3 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : a0a1a2a3 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = a4a5a6a7 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = a4a5a6a7 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : a4a5a6a7 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = a8a9aaab |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = a8a9aaab |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : a8a9aaab |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = acadaeaf |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = acadaeaf |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : acadaeaf |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = b0b1b2b3 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = b0b1b2b3 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : b0b1b2b3 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = b4b5b6b7 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = b4b5b6b7 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : b4b5b6b7 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = b8b9babb |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = b8b9babb |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : b8b9babb |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = bcbdbebf |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = bcbdbebf |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : bcbdbebf |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = c0c1c2c3 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = c0c1c2c3 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : c0c1c2c3 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = c4c5c6c7 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = c4c5c6c7 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : c4c5c6c7 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = c8c9cacb |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = c8c9cacb |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : c8c9cacb |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = cccdcecf |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = cccdcecf |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : cccdcecf |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = d0d1d2d3 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = d0d1d2d3 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : d0d1d2d3 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = d4d5d6d7 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = d4d5d6d7 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : d4d5d6d7 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = d8d9dadb |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = d8d9dadb |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : d8d9dadb |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = dcdddedf |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = dcdddedf |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : dcdddedf |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = e0e1e2e3 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = e0e1e2e3 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : e0e1e2e3 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = e4e5e6e7 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = e4e5e6e7 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : e4e5e6e7 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = e8e9eaeb |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = e8e9eaeb |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : e8e9eaeb |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = ecedeeef |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = ecedeeef |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : ecedeeef |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = f0f1f2f3 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = f0f1f2f3 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : f0f1f2f3 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = f4f5f6f7 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = f4f5f6f7 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : f4f5f6f7 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = f8f9fafb |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = f8f9fafb |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# tb_top.spi_page_write : Writing Data : f8f9fafb |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = fcfdfeff |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0201 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = fcfdfeff |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0201 |
# NOTE : Page program cycle is started |
# tb_top.spi_page_write : Writing Data : fcfdfeff |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 05000000 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80020200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 05000000 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 80020200 |
# NOTE : Only a Read Status Register instruction will be valid |
# NOTE : Page program cycle is finished |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80220240 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 80220240 |
# Total time Elapsed: 0(us): tb_top.spi_wait_busy : Checking the SPI RDStatus : 00000000 |
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 03000000 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0004, Cfg. Data = 03000000 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 801a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 00010203 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 04050607 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 08090a0b |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 0c0d0e0f |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 10111213 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 14151617 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 18191a1b |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 1c1d1e1f |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 20212223 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 24252627 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 28292a2b |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 2c2d2e2f |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 30313233 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 34353637 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 38393a3b |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 3c3d3e3f |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 40414243 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 44454647 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 48494a4b |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 4c4d4e4f |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 50515253 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 54555657 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 58595a5b |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 5c5d5e5f |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 60616263 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 64656667 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 68696a6b |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 6c6d6e6f |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 70717273 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 74757677 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 78797a7b |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 7c7d7e7f |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 80818283 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 84858687 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 88898a8b |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 8c8d8e8f |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 90919293 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 94959697 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 98999a9b |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : 9c9d9e9f |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : a0a1a2a3 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : a4a5a6a7 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : a8a9aaab |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : acadaeaf |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : b0b1b2b3 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : b4b5b6b7 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : b8b9babb |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : bcbdbebf |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : c0c1c2c3 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : c4c5c6c7 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : c8c9cacb |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : cccdcecf |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : d0d1d2d3 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : d4d5d6d7 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : d8d9dadb |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : dcdddedf |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : e0e1e2e3 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : e4e5e6e7 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : e8e9eaeb |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : ecedeeef |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : f0f1f2f3 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : f4f5f6f7 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : f8f9fafb |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200 |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 803a0200 |
# tb_top.spi_page_read_verify : STATUS : Data Matched : fcfdfeff |
############################# |
# Test Statistic |
474,3 → 479,7
# Test Status: TEST PASSED |
# ========= |
# |
# ** Note: $finish : ../lib/tb_glbl.v(70) |
# Time: 3038956 ps Iteration: 0 Instance: /tb_top |
# End time: 11:09:01 on Jan 08,2017, Elapsed time: 0:00:26 |
# Errors: 3, Warnings: 15 |
/trunk/verif/glog/modelsim/uart_test_1.log
1,36 → 1,51
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl |
Reading J:/Microsemi/Libero_SoC_v11.7/Model/tcl/vsim/pref.tcl |
|
# 10.1b |
# 10.4c |
|
# vsim +uart_test_1 +INTERNAL_ROM -do run.do -c tb_top |
# // ModelSim ACTEL 10.1b Apr 27 2012 |
# vsim -do "run.do" -c tb_top "+uart_test_1" "+INTERNAL_ROM" |
# Start time: 16:29:19 on Jan 07,2017 |
# // ModelSim Microsemi 10.4c Aug 12 2015 |
# // |
# // Copyright 1991-2012 Mentor Graphics Corporation |
# // Copyright 1991-2015 Mentor Graphics Corporation |
# // All Rights Reserved. |
# // |
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION |
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS |
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS. |
# // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL |
# // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM |
# // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552. |
# // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER |
# // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905. |
# // |
# Loading sv_std.std |
# Loading work.tb_top |
# ** Error: (vsim-7) Failed to open data file "F:/Yagna-Product/VLSI/opencores/oms8051mini/trunk/verif/run/work/delay/_primary.dat" in read mode. |
# |
# No such file or directory. (errno = ENOENT) |
# Loading work.digital_core |
# Loading work.clkgen |
# Loading work.clk_ctl |
# Loading work.msg_handler_top |
# Loading work.uart_core_nf |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.double_sync_low |
# Loading work.msg_handler |
# Loading work.wb_crossbar |
# Loading work.uart_core |
# Loading work.uart_cfg |
# Loading work.generic_register |
# Loading work.stat_register |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.async_fifo |
# Loading work.double_sync_low |
# Loading work.spi_core |
# Loading work.spi_if |
# Loading work.spi_ctl |
# Loading work.spi_cfg |
# Loading work.req_register |
# Loading work.i2cm_top |
# Loading work.i2cm_byte_ctrl |
# Loading work.i2cm_bit_ctrl |
# Loading work.oc8051_top |
# Loading work.oc8051_decoder |
# Loading work.oc8051_alu |
40,6 → 55,7
# Loading work.oc8051_ram_256x8_two_bist |
# Loading work.oc8051_alu_src_sel |
# Loading work.oc8051_comp |
# Loading work.oc8051_rom |
# Loading work.oc8051_cy_select |
# Loading work.oc8051_indi_addr |
# Loading work.oc8051_memory_interface |
53,8 → 69,8
# Loading work.oc8051_int |
# Loading work.oc8051_tc |
# Loading work.oc8051_tc2 |
# Loading work.oc8051_xrom |
# Loading work.oc8051_xram |
# Loading work.i2c_slave_model |
# Loading work.uart_agent |
# Loading work.m25p20 |
# Loading work.memory_access |
63,49 → 79,38
# Loading work.AT45DB321 |
# Loading work.tb_glbl |
# Loading work.bit_register |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38. |
# |
# Region: /tb_top/u_core |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'. |
# |
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_rxfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_txfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'. |
# |
# do run.do |
# i : 02 |
# i : 00 |
# i : 08 |
# i : 12 |
# i : 00 |
# i : 64 |
# i : 80 |
# i : fe |
# i : 75 |
# i : 81 |
# ** Warning: (vsim-3017) ../tb/tb_top.v(135): [TFMPC] - Too few port connections. Expected 30, found 28. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core File: ../../rtl/core/digital_core.v |
# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_mode'. |
# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_enable'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(233): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_rxfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(249): [TFMPC] - Too few port connections. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_txfifo File: ../../rtl/lib/async_fifo.v |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-3017) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Too few port connections. Expected 56, found 53. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_8051_core/u_memory_interface File: ../../rtl/8051/oc8051_memory_interface.v |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'iack_i'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'istb_o'. |
# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'idat_i'. |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(266): [TOFD] - System task or function '$shm_open' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(267): [TOFD] - System task or function '$shm_probe' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v |
# do run.do |
# NOTE : Load memory with Initial delivery content |
# NOTE : Initial Load End |
# --> Dumpping the design |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(266): Cannot execute undefined system task/function '$shm_open' |
# |
# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(267): Cannot execute undefined system task/function '$shm_probe' |
# |
# NOTE: COMMUNICATION (RE)STARTED |
# Config-Write: Id: 3 Addr = 0000, Cfg. Data = 00000007 |
# DEBUG i2c_slave; stop condition detected at 101 |
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 07 |
# |
# ... Writing char 24 ... |
# ... Write data 24 to UART done cnt : 1 ... |
377,3 → 382,7
# Test Status: TEST PASSED |
# ========= |
# |
# ** Note: $finish : ../lib/tb_glbl.v(70) |
# Time: 310291 ps Iteration: 0 Instance: /tb_top |
# End time: 16:29:23 on Jan 07,2017, Elapsed time: 0:00:04 |
# Errors: 3, Warnings: 15 |
/trunk/verif/run/run_irun
12,8 → 12,8
set all_testsi = 0; |
set all_testsx = 0; |
|
set misc_tests=(uart_test_1 spi_test_1 i2cm_test_1) |
set risc_int_tests=(fib divmul sort gcd cast xram i2cm_burst_wrrd) |
set misc_tests=(spi_test_1) |
set risc_int_tests=(uart_lb fib divmul sort gcd cast xram i2cm_burst_wrrd) |
|
|
echo " Compiling with cadence tools - irun " |
91,7 → 91,7
#echo "" |
|
\cp ../testcase/dat/${risc_int_test}.dat ./dat/oc8051_xrom.in |
$ELAB +DUMP +INTERNAL_ROM -l ../log/run.log |
$ELAB +DUMP +${risc_int_test} +INTERNAL_ROM -l ../log/run.log |
if ($status != 0) then |
cat ../log/run.log |
exit |
/trunk/verif/run/run_modelsim
8,10 → 8,10
set all_testsm = 0; |
set all_testsi = 0; |
|
set misc_tests=(uart_test_1 spi_test_1) |
set misc_tests=(spi_test_1) |
#set misc_tests=( ) |
|
set risc_int_tests=(fib divmul sort gcd cast xram i2cm_burst_wrrd) |
set risc_int_tests=(uart_lb fib divmul sort gcd cast xram i2cm_burst_wrrd) |
#set risc_int_tests=(fib divmul sort gcd cast xram all_instr) |
|
echo " Compiling with MODELSIM " |
90,7 → 90,7
#echo "" |
|
\cp ../testcase/dat/${risc_int_test}.dat ./dat/oc8051_xrom.in |
vsim -do run.do -c tb_top +INTERNAL_ROM | tee ../log/run.log |
vsim -do run.do -c tb_top +${risc_int_test} +INTERNAL_ROM | tee ../log/run.log |
if ($status != 0) then |
cat ../log/run.log |
exit |
/trunk/verif/tb/tb_top.v
285,8 → 285,8
|
#1000 wait(reset_out_n == 1); |
|
if ( $test$plusargs("uart_test_1") ) |
uart_test1(); |
if ( $test$plusargs("uart_lb") ) |
uart_lb(); |
else if ( $test$plusargs("spi_test_1") ) |
spi_test1(); |
else if ( $test$plusargs("i2cm_test_1") ) |
336,7 → 336,7
endmodule |
|
|
`include "uart_test1.v" |
`include "uart_lb.v" |
`include "spi_test1.v" |
`include "i2cm_test1.v" |
`include "tb_tasks.v" |
/trunk/verif/testcase/uart_test1.v
File deleted
trunk/verif/testcase/uart_test1.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/verif/testcase/uart_lb.v
===================================================================
--- trunk/verif/testcase/uart_lb.v (nonexistent)
+++ trunk/verif/testcase/uart_lb.v (revision 32)
@@ -0,0 +1,61 @@
+task uart_lb;
+
+reg [1:0] data_bit ;
+reg stop_bits ; // 0: 1 stop bit; 1: 2 stop bit;
+reg stick_parity ; // 1: force even parity
+reg parity_en ; // parity enable
+reg even_odd_parity ; // 0: odd parity; 1: even parity
+
+reg [7:0] data;
+reg [15:0] divisor ; // divided by n * 16
+reg [15:0] timeout ;// wait time limit
+
+reg [15:0] rx_nu;
+reg [15:0] tx_nu;
+reg [7:0] write_data [0:39];
+reg fifo_enable ; // fifo mode disable
+integer i,j;
+begin
+ data_bit = 2'b11;
+ stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
+ stick_parity = 0; // 1: force even parity
+ parity_en = 0; // parity enable
+ even_odd_parity = 1; // 0: odd parity; 1: even parity
+ divisor = 15;// divided by n * 16
+ timeout = 500;// wait time limit
+ fifo_enable = 0; // fifo mode disable
+
+ repeat (2000) @(posedge app_clk); // wait for Processor Get Ready
+ tb_uart.uart_init;
+ //tb_top.cpu_byte_write(`ADDR_SPACE_UART,8'h0,{3'h0,2'b00,1'b1,1'b1,1'b1});
+
+
+ for (i=0; i<40; i=i+1)
+ write_data[i] = $random;
+
+
+ tb_top.tb_uart.control_setup (data_bit, stop_bits, parity_en, even_odd_parity, stick_parity, timeout, divisor, fifo_enable);
+
+
+ fork
+ begin
+ for (i=0; i<40; i=i+1)
+ begin
+ $display ("\n... Writing char %x ...", write_data[i]);
+ tb_top.tb_uart.write_char (write_data[i]);
+ end
+ end
+
+ begin
+ for (j=0; j<40; j=j+1)
+ begin
+ tb_top.tb_uart.read_char_chk(write_data[j]);
+ end
+ end
+ join
+
+ #100
+ tb_top.tb_uart.report_status(rx_nu, tx_nu);
+
+end
+endtask
trunk/verif/testcase/uart_lb.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property