URL
https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk
Subversion Repositories oms8051mini
Compare Revisions
- This comparison shows the changes necessary to convert path
/oms8051mini
- from Rev 6 to Rev 7
- ↔ Reverse comparison
Rev 6 → Rev 7
/trunk/rtl/uart/uart_cfg.v
359,13 → 359,13
assign reg_3[31:0] = {30'h0,rx_fifo_empty,tx_fifo_full}; |
|
// reg_4 is tx_fifo wr |
assign tx_fifo_wr_en = sw_wr_en_4; |
assign tx_fifo_wr_en = sw_wr_en_4 & reg_ack; |
assign tx_fifo_data = reg_wdata[7:0]; |
|
// reg_5 is rx_fifo read |
// rx_fifo read data |
assign reg_5[31:0] = {24'h0,rx_fifo_data}; |
assign rx_fifo_rd_en = sw_rd_en_5; |
assign rx_fifo_rd_en = sw_rd_en_5 & reg_ack; |
|
|
endmodule |
/trunk/verif/agents/uart/uart_agent.v
1,4 → 1,5
|
`include "tb_defines.v" |
|
module uart_agent ( |
test_clk, |
47,7 → 48,7
|
integer timeout_count; |
integer data_bit_number; |
reg [2:0] clk_count; |
reg [15:0] clk_count; |
|
reg error_ind; // 1 indicate error |
|
65,10 → 66,12
|
always @(posedge test_clk) |
begin |
if (clk_count == 3'h0) |
test_tx_clk = ~test_tx_clk; |
|
clk_count = clk_count + 1; |
if (clk_count == 'h0) begin |
test_tx_clk = ~test_tx_clk; |
clk_count = control_setup.divisor; |
end else begin |
clk_count = clk_count - 1; |
end |
end |
assign test_rx_clk = ~test_tx_clk; |
|
107,8 → 110,9
|
|
always @error_detected begin |
error_ind = 1; |
err_cnt = err_cnt + 1; |
error_ind = 1; |
err_cnt = err_cnt + 1; |
`TB_GLBL.test_err; |
end |
|
|
117,8 → 121,8
begin |
read = 0; |
write = 0; |
tx_count = 0; |
rx_count = 0; |
tx_count = 0; |
rx_count = 0; |
stop_err_check = 0; |
par_err_count = 0; |
stop_err1_cnt = 0; |
307,6 → 311,7
input fifo_enable; |
|
begin |
clk_count = divisor; |
data_bit_number = data_bit_set + 5; |
end |
endtask |
/trunk/verif/run/run_modelsim
44,7 → 44,11
#echo "" |
echo "### Running test ${i}: ${misc_test}" |
|
vsim -do run.do -c tb_top +${misc_test} | tee ../log/run.log |
if (${misc_test} == "uart_test_1") then |
\cp ../testcase/dat/uart_lb.dat ./dat/oc8051_xrom.in |
endif |
|
vsim -do run.do -c tb_top +${misc_test} +INTERNAL_ROM | tee ../log/run.log |
if ($status != 0) then |
cat ../log/run.log |
exit |
92,7 → 96,7
if ($status != 0) then |
cat ../log/run.log |
exit |
else if (`tail ../log/run.log | grep Passed` == "") then |
else if (`tail ../log/run.log | grep PASSED` == "") then |
echo "### test ${i}: ${risc_ext_test} --> FAILED" |
@ failedx += 1; |
@ all_testsx += 1; |
123,7 → 127,7
if ($status != 0) then |
cat ../log/run.log |
exit |
else if (`tail ../log/run.log | grep Passed` == "") then |
else if (`tail ../log/run.log | grep PASSED` == "") then |
echo "### test ${i}: ${risc_int_test} --> FAILED" |
@ failedi += 1; |
@ all_testsi += 1; |
/trunk/verif/sw/C/uart_lb.c
11,11 → 11,11
char cErrCnt; |
/*---------------------------------------------------------------------------*/ |
|
__xdata __at (0x3000) unsigned char uart_reg0; |
__xdata __at (0x3008) unsigned char uart_reg2; |
__xdata __at (0x300C) unsigned char uart_reg3; |
__xdata __at (0x3010) unsigned char uart_tdata; |
__xdata __at (0x3014) unsigned char uart_rdata; |
__xdata __at (0x9000) unsigned char uart_reg0; |
__xdata __at (0x9008) unsigned char uart_reg2; |
__xdata __at (0x900C) unsigned char uart_reg3; |
__xdata __at (0x9010) unsigned char uart_tdata; |
__xdata __at (0x9014) unsigned char uart_rdata; |
__xdata unsigned long *rx_des_base; |
__xdata unsigned long *tx_des_base; |
|
/trunk/verif/sw/hex/uart_lb.hex
0,0 → 1,15
:03000000020008F3 |
:0300610002000397 |
:0500030012006480FE04 |
:100064009090007407F0909008E4F0E490900CE015 |
:0F007400FA20E1F8909014E0FA909010F080EDEF |
:06003700E478FFF6D8FD9D |
:100015007900E94400601B7A00900087780075A09C |
:1000250000E493F2A308B8000205A0D9F4DAF2754A |
:02003500A0FF2A |
:10003D007800E84400600A790075A000E4F309D85F |
:10004D00FC7800E84400600C7900900000E4F0A317 |
:04005D00D8FCD9FAF8 |
:0D00080075810C120083E582600302000385 |
:040083007582002260 |
:00000001FF |
/trunk/verif/testcase/dat/uart_lb.dat
0,0 → 1,135
02 |
00 |
08 |
12 |
00 |
64 |
80 |
FE |
75 |
81 |
0C |
12 |
00 |
83 |
E5 |
82 |
60 |
03 |
02 |
00 |
03 |
79 |
00 |
E9 |
44 |
00 |
60 |
1B |
7A |
00 |
90 |
00 |
87 |
78 |
00 |
75 |
A0 |
00 |
E4 |
93 |
F2 |
A3 |
08 |
B8 |
00 |
02 |
05 |
A0 |
D9 |
F4 |
DA |
F2 |
75 |
A0 |
FF |
E4 |
78 |
FF |
F6 |
D8 |
FD |
78 |
00 |
E8 |
44 |
00 |
60 |
0A |
79 |
00 |
75 |
A0 |
00 |
E4 |
F3 |
09 |
D8 |
FC |
78 |
00 |
E8 |
44 |
00 |
60 |
0C |
79 |
00 |
90 |
00 |
00 |
E4 |
F0 |
A3 |
D8 |
FC |
D9 |
FA |
02 |
00 |
03 |
90 |
90 |
00 |
74 |
07 |
F0 |
90 |
90 |
08 |
E4 |
F0 |
E4 |
90 |
90 |
0C |
E0 |
FA |
20 |
E1 |
F8 |
90 |
90 |
14 |
E0 |
FA |
90 |
90 |
10 |
F0 |
80 |
ED |
75 |
82 |
00 |
22 |
trunk/verif/testcase/dat/uart_lb.dat
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/verif/testcase/uart_test1.v
===================================================================
--- trunk/verif/testcase/uart_test1.v (revision 6)
+++ trunk/verif/testcase/uart_test1.v (revision 7)
@@ -19,14 +19,14 @@
data_bit = 2'b11;
stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
stick_parity = 0; // 1: force even parity
- parity_en = 1; // parity enable
+ parity_en = 0; // parity enable
even_odd_parity = 1; // 0: odd parity; 1: even parity
- divisor = 3; // divided by n * 16
+ divisor = 15;// divided by n * 16
timeout = 500;// wait time limit
fifo_enable = 0; // fifo mode disable
tb_uart.uart_init;
- tb_top.cpu_write('h3,8'h0,{27'h0,2'b10,1'b1,1'b1,1'b1});
+ tb_top.cpu_write('h3,8'h0,{27'h0,2'b00,1'b1,1'b1,1'b1});
for (i=0; i<40; i=i+1)