URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/open8_urisc
- from Rev 319 to Rev 320
- ↔ Reverse comparison
Rev 319 → Rev 320
/trunk/VHDL/o8_async_serial.vhd
49,6 → 49,7
-- Seth Henry 04/10/20 Code cleanup and register documentation |
-- Seth Henry 04/16/20 Modified to use Open8 bus record |
-- Seth Henry 05/18/20 Added write qualification input |
-- Seth Henry 6/06/23 Inverted flow control signals for standard EIA-232 |
|
library ieee; |
use ieee.std_logic_1164.all; |
75,7 → 76,7
Rd_Data : out DATA_TYPE; |
-- |
TX_Out : out std_logic; |
CTS_In : in std_logic := '1'; |
CTS_In : in std_logic := '0'; |
RX_In : in std_logic := '1'; |
RTS_Out : out std_logic |
); |
179,7 → 180,7
if( Rd_En_q = '1' and Reg_Sel_q = '0' )then |
Rd_Data <= RX_FIFO_Rd_Data; |
end if; |
RTS_Out <= not RX_FIFO_AFull; |
RTS_Out <= RX_FIFO_AFull; |
|
end if; |
end process; |
218,7 → 219,7
elsif( rising_edge(Clock) )then |
TX_Xmit <= '0'; |
TX_FIFO_Rd_En <= '0'; |
CTS_sr <= CTS_sr(2 downto 0) & CTS_In; |
CTS_sr <= CTS_sr(2 downto 0) & (not CTS_In); |
|
case( TX_Ctrl )is |
when IDLE => |