OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /open8_urisc
    from Rev 333 to Rev 334
    ↔ Reverse comparison
  •

Rev 333 → Rev 334

/trunk/VHDL/o8_version.vhd
28,6 → 28,8
-- Offset Bitfield Description Read/Write
-- 0x00 AAAAAAAA Minor Version (RO)
-- 0x01 AAAAAAAA Major Version (RO)
-- 0x02 AAAAAAAA SoC Version (RO)
-- 0x03 AAAAAAAA Hardware Version (RO)
--
-- Revision History
-- Author Date Change
47,6 → 49,8
generic(
Minor_Version : DATA_TYPE := x"00";
Major_Version : DATA_TYPE := x"00";
SoC_Version : DATA_TYPE := x"00";
Hardware_Version : DATA_TYPE := x"00";
Address : ADDRESS_TYPE
);
port(
60,13 → 64,13
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
 
constant User_Addr : std_logic_vector(15 downto 1)
:= Address(15 downto 1);
alias Comp_Addr is Open8_Bus.Address(15 downto 1);
constant User_Addr : std_logic_vector(15 downto 2)
:= Address(15 downto 2);
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
signal Addr_Match : std_logic;
 
alias Reg_Sel_d is Open8_Bus.Address(0);
signal Reg_Sel_q : std_logic := '0';
alias Reg_Sel_d is Open8_Bus.Address(1 downto 0);
signal Reg_Sel_q : std_logic_vector(1 downto 0) := "00";
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
78,7 → 82,7
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Reg_Sel_q <= '0';
Reg_Sel_q <= (others => '0');
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge( Clock ) )then
88,11 → 92,19
Rd_En_q <= Rd_En_d;
 
if( Rd_En_q = '1' )then
if( Reg_Sel_q = '0')then
Rd_Data <= Minor_Version;
else
Rd_Data <= Major_Version;
end if;
case( Reg_Sel_q )is
when "00" =>
Rd_Data <= Minor_Version;
when "01" =>
Rd_Data <= Major_Version;
when "10" =>
Rd_Data <= Soc_Version;
when "11" =>
Rd_Data <= Hardware_Version;
when others =>
null;
end case;
 
end if;
end if;
end process;
/trunk/VHDL/rom_8k_core.vhd
0,0 → 1,143
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
 
-- ============================================================
-- File Name: rom_8k_core.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
 
 
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
 
ENTITY rom_8k_core IS
PORT
(
address : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END rom_8k_core;
 
 
ARCHITECTURE SYN OF rom_8k_core IS
 
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
 
BEGIN
q <= sub_wire0(7 DOWNTO 0);
 
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "ROMTAPE/romtape.hex",
intended_device_family => "Cyclone IV GX",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=RTP0",
lpm_type => "altsyncram",
numwords_a => 8192,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
widthad_a => 13,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "RTP0"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "ROMTAPE/romtape.hex"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "ROMTAPE/romtape.hex"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=RTP0"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_8k_core.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_8k_core.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_8k_core.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_8k_core.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_8k_core_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.