OpenCores
URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

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  • This comparison shows the changes necessary to convert path 
    /opencpu32/trunk/hdl/opencpu32
    from Rev 27 to Rev 28
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  •

Rev 27 → Rev 28

/opencpu32.xise
20,18 → 20,18
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="Alu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="testAlu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="50"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="50"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="TriStateBuffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="testTriStateBuffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
40,8 → 40,8
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="75"/>
</file>
<file xil_pn:name="RegisterFile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="testRegisterFile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
50,18 → 50,18
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="146"/>
</file>
<file xil_pn:name="DataPath.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="testDataPath.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="137"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="137"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="137"/>
</file>
<file xil_pn:name="Multiplexer4_1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="testMultiplexer4_1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
71,7 → 71,7
</file>
<file xil_pn:name="ControlUnit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="testControlUnit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
80,8 → 80,8
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="219"/>
</file>
<file xil_pn:name="Multiplexer3_1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
</files>
 
188,9 → 188,9
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|ControlUnit|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="ControlUnit.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/ControlUnit" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|DataPath|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="DataPath.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/DataPath" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
248,7 → 248,7
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="ControlUnit" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="DataPath" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
260,10 → 260,10
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="ControlUnit_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="ControlUnit_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="ControlUnit_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="ControlUnit_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="DataPath_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="DataPath_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="DataPath_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="DataPath_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
283,7 → 283,7
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="ControlUnit" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="DataPath" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
307,8 → 307,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testDataPath" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testDataPath" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testAlu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testAlu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
324,7 → 324,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testDataPath" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testAlu" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
374,7 → 374,7
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testDataPath|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testAlu|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="opencpu32" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
/ControlUnit.vhd
19,24 → 19,24
entity ControlUnit is
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
FlagsDp : in STD_LOGIC_VECTOR (n downto 0);
DataDp : in STD_LOGIC_VECTOR (n downto 0);
MuxDp : out STD_LOGIC_VECTOR (2 downto 0);
clk : in STD_LOGIC; --! Main system clock
FlagsDp : in STD_LOGIC_VECTOR (n downto 0); --! Flags comming from the Datapath
DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath
MuxDp : out STD_LOGIC_VECTOR (2 downto 0); --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
ImmDp : out STD_LOGIC_VECTOR (n downto 0);
ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath
DpAluOp : out aluOps; --! Alu operations
DpRegFileWriteAddr : out generalRegisters;
DpRegFileWriteEn : out STD_LOGIC;
DpRegFileReadAddrA : out generalRegisters;
DpRegFileReadAddrB : out generalRegisters;
DpRegFileReadEnA : out STD_LOGIC;
DpRegFileReadEnB : out STD_LOGIC;
MemoryDataRead : out std_logic;
MemoryDataWrite : out std_logic;
MemoryDataInput : in STD_LOGIC_VECTOR (n downto 0);
MemoryDataAddr : out STD_LOGIC_VECTOR (n downto 0);
MemoryDataOut : out STD_LOGIC_VECTOR (n downto 0));
DpRegFileWriteAddr : out generalRegisters; --! General register address to write
DpRegFileWriteEn : out STD_LOGIC; --! Enable register write
DpRegFileReadAddrA : out generalRegisters; --! General register address to read
DpRegFileReadAddrB : out generalRegisters; --! General register address to read
DpRegFileReadEnA : out STD_LOGIC; --! Enable register read (PortA)
DpRegFileReadEnB : out STD_LOGIC; --! Enable register read (PortB)
MemoryDataReadEn : out std_logic; --! Enable Main memory read
MemoryDataWriteEn: out std_logic; --! Enable Main memory write
MemoryDataInput : in STD_LOGIC_VECTOR (n downto 0); --! Incoming data from main memory
MemoryDataAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory write address
MemoryDataOut : out STD_LOGIC_VECTOR (n downto 0)); --! Data to write on main memory
end ControlUnit;
 
--! @brief ControlUnit http://en.wikipedia.org/wiki/Control_unit
88,8 → 88,8
PC <= (others => '0');
IR <= (others => '0');
MemoryDataAddr <= (others => '0');
MemoryDataRead <= '0';
MemoryDataWrite <= '0';
MemoryDataReadEn <= '0';
MemoryDataWriteEn <= '0';
MemoryDataAddr <= (others => '0');
nextCpuState <= fetch;
99,13 → 99,13
PC <= PC + conv_std_logic_vector(1, nBits);
MemoryDataAddr <= PC; -- Warning PC is not 1 yet...
IR <= MemoryDataInput;
MemoryDataRead <= '1';
MemoryDataReadEn <= '1';
nextCpuState <= decode;
-- Detect with instruction came from memory, set the number of cycles to execute...
when decode =>
MemoryDataRead <= '0';
MemoryDataWrite <= '0';
MemoryDataReadEn <= '0';
MemoryDataWriteEn <= '0';
-- The high attribute points to the highes bit position
case opcodeIR is
/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/ControlUnit.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/testAlu.vhd&quot; into library work</arg>
</msg>
 
</messages>
/pkgOpenCPU32.vhd
27,7 → 27,13
type dpMuxInputs is (fromMemory, fromImediate, fromRegFileA, fromRegFileB, fromAlu);
type dpMuxAluIn is (fromMemory, fromImediate, fromRegFileA);
type controlUnitStates is (initial, fetch, decode, execute, executing);
type executionStates is (initInstructionExecution, writeRegister, releaseWriteRead, s3, s4);
type executionStates is (initInstructionExecution, writeRegister, releaseWriteRead, s3, s4);
 
--! Flags positions
-- Posicoes em bits dos flags (8 bits)
constant flag_sign : integer := 2;
constant flag_zero : integer := 1;
constant flag_carry : integer := 0;
 
function reg2Num (a: generalRegisters) return integer;
function Num2reg (a: integer) return generalRegisters;
/Alu.vhd
14,11 → 14,12
 
--! ALU is a digital circuit that performs arithmetic and logical operations. It's the fundamental part of the CPU
entity Alu is
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 1
B : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 2
S : out STD_LOGIC_VECTOR (n downto 0); --! Alu Output
sel : in aluOps); --! Select operation
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 1
B : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 2
S : out STD_LOGIC_VECTOR (n downto 0); --! Alu Output
flagsOut : out STD_LOGIC_VECTOR(2 downto 0); --! Flags from current operation
sel : in aluOps); --! Select operation
end Alu;
 
--! @brief Arithmetic logic unit, refer to this page for more information http://en.wikipedia.org/wiki/Arithmetic_logic_unit
30,56 → 31,87
--! Behavior description of combinational circuit (Can not infer any FF(Flip flop)) of the Alu
process (A,B,sel) is
variable mulResult : std_logic_vector(((nBits*2) - 1)downto 0);
variable FLAG_CARRY, FLAG_ZERO , FLAG_SIGN : STD_LOGIC;
variable intermediate_S : STD_LOGIC_VECTOR(nBits downto 0); -- One more bit to detect overflows...
begin
case sel is
when alu_pass =>
--Pass operation
S <= A;
intermediate_S := '0' & A;
when alu_passB =>
--Pass operation
S <= B;
intermediate_S := '0' & B;
when alu_sum =>
--Sum operation
S <= A + B;
intermediate_S := ('0' & A) + ('0' & B);
when alu_sub =>
--Subtraction operation
S <= A - B;
intermediate_S := ('0' & A) - ('0' & B);
when alu_inc =>
--Increment operation
S <= A + conv_std_logic_vector(1, n+1);
intermediate_S := ('0' & A) + conv_std_logic_vector(1, nBits);
when alu_dec =>
--Decrement operation
S <= A - conv_std_logic_vector(1, n+1);
intermediate_S := ('0' & A) - conv_std_logic_vector(1, nBits);
when alu_mul =>
--Multiplication operation
mulResult := A * B;
S <= mulResult((nBits - 1) downto 0);
intermediate_S := mulResult(nBits downto 0);
when alu_and =>
--And operation
S <= A and B;
intermediate_S := '0' & (A and B);
when alu_or =>
--Or operation
S <= A or B;
intermediate_S := '0' & (A or B);
when alu_xor =>
--Xor operation
S <= A xor B;
intermediate_S := '0' & (A xor B);
when alu_not =>
--Not operation
S <= not A;
intermediate_S := not ('0' & A);
when alu_shfLt =>
-- Shift left operand A (Get current value bring to left and add a zero to the right)
intermediate_S := '0' & (A((A'HIGH - 1) downto 0) & '0'); -- "&" is the concatenate operator
when alu_shfRt =>
-- Shift right operand A (Add a zero to the left and copy the current value to the right)
intermediate_S := '0' & ('0' & A(A'HIGH downto 1)); -- "&" is the concatenate operator
when alu_roRt =>
-- Rotate right operand A (Get the lowest bit of A, and concatenate with the others bits, taking out the latest one...)
intermediate_S := '0' & (A(A'LOW) & A(A'HIGH downto 1)); -- If A is (7 downto 0) A'LOW is 0, and A'HIGH is 7
when alu_roLt =>
-- Rotate left operand A (Get the the bits from the second highest and concatenate in the end with the highest one...)
intermediate_S := '0' & (A((A'HIGH - 1) downto 0) & A(A'HIGH));
when others =>
S <= (others => 'Z');
end case;
intermediate_S := (others => 'Z');
end case;
-- Get flags
if (intermediate_S = 0) then
FLAG_ZERO := '1';
else
FLAG_ZERO := '0';
end if;
FLAG_SIGN := intermediate_S(intermediate_S'HIGH - 1);
FLAG_CARRY := intermediate_S(intermediate_S'HIGH);
-- Pass output
S <= intermediate_S(S'RANGE); -- S'RANGE == S(31 downto 0);
flagsOut <= FLAG_SIGN & FLAG_ZERO & FLAG_CARRY;
end process;
 
end Behavioral;
/testAlu.vhd
21,11 → 21,12
--! Component declaration to instantiate the Alu circuit
COMPONENT Alu
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 1
B : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 2
S : out STD_LOGIC_VECTOR (n downto 0); --! Alu Output
sel : in aluOps); --! Select operation
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 1
B : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 2
S : out STD_LOGIC_VECTOR (n downto 0); --! Alu Output
flagsOut : out STD_LOGIC_VECTOR(2 downto 0); --! Flags from current operation
sel : in aluOps); --! Select operation --! Select operation
END COMPONENT;
 
36,6 → 37,7
 
--Outputs
signal S : std_logic_vector((nBits - 1) downto 0); --! Wire to connect Test signal to component
signal flagsOut : std_logic_vector(2 downto 0); --! Wire to connect Test signal to component
BEGIN
44,6 → 46,7
A => A,
B => B,
S => S,
flagsOut => flagsOut,
sel => sel
);
 
138,6 → 141,52
B <= (others => 'X');
wait for 1 ns; -- Wait to stabilize the response
assert S = (not A) report "Invalid NOT output" severity FAILURE;
-- Shift left---------------------------------------------------------------------
wait for 1 ns;
REPORT "Shift left 2" SEVERITY NOTE;
sel <= alu_shfLt;
A <= conv_std_logic_vector(2, nBits);
B <= (others => 'X');
wait for 1 ns; -- Wait to stabilize the response
assert S = conv_std_logic_vector(4, nBits) report "Invalid shift left output expected " severity FAILURE;
-- Shift right---------------------------------------------------------------------
wait for 1 ns;
REPORT "Shift right 4" SEVERITY NOTE;
sel <= alu_shfRt;
A <= conv_std_logic_vector(4, nBits);
B <= (others => 'X');
wait for 1 ns; -- Wait to stabilize the response
assert S = conv_std_logic_vector(2, nBits) report "Invalid shift left output expected " severity FAILURE;
-- Test flag zero ------------------------------------------------------------------
wait for 1 ps;
REPORT "Test zero flag 10 sub 10" SEVERITY NOTE;
sel <= alu_sub;
A <= conv_std_logic_vector(10, nBits);
B <= conv_std_logic_vector(10, nBits);
wait for 1 ns; -- Wait to stabilize the response
assert flagsOut(flag_zero) = '1' report "Invalid zero flag" severity FAILURE;
-- Test flag carry ------------------------------------------------------------------
wait for 1 ps;
REPORT "Test carry flag 4294967056 sum 4294967056" SEVERITY NOTE;
sel <= alu_sum;
A <= "11111111111111111111111100010000";
B <= "11111111111111111111111100010000";
wait for 1 ns; -- Wait to stabilize the response
assert flagsOut(flag_carry) = '1' report "Invalid carry flag" severity FAILURE;
-- Test flag sign ------------------------------------------------------------------
wait for 1 ps;
REPORT "Test sign flag -4 sub 4" SEVERITY NOTE;
sel <= alu_sub;
A <= conv_std_logic_vector(-4, nBits);
B <= conv_std_logic_vector(4, nBits);
wait for 1 ns; -- Wait to stabilize the response
assert flagsOut(flag_sign) = '1' report "Invalid sign flag" severity FAILURE;
assert S = conv_std_logic_vector(-8, nBits) report "Invalid Sub" severity FAILURE;
 
-- Finish simulation
assert false report "NONE. End of simulation." severity failure;
/opencpu32.gise
184,20 → 184,14
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testAlu_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testAlu_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testAlu_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testControlUnit_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testControlUnit_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testControlUnit_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testDataPath_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testDataPath_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testDataPath_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testMultiplexer2_1_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testMultiplexer4_1_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testRegisterFile_beh.prj"/>
211,17 → 205,13
</files>
 
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1333309985" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1333309985">
<transform xil_pn:end_ts="1333906140" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1333906140">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333727207" xil_pn:in_ck="300726481020074607" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1333727207">
<transform xil_pn:end_ts="1333907765" xil_pn:in_ck="300726481020074607" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1333907765">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="Alu.vhd"/>
<outfile xil_pn:name="ControlUnit.vhd"/>
<outfile xil_pn:name="DataPath.vhd"/>
237,27 → 227,21
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1333726377" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-3798934868497889219" xil_pn:start_ts="1333726377">
<transform xil_pn:end_ts="1333906140" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-892635403352863368" xil_pn:start_ts="1333906140">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333726377" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-6007724738129030273" xil_pn:start_ts="1333726377">
<transform xil_pn:end_ts="1333906140" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7876831410930882182" xil_pn:start_ts="1333906140">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333726377" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-8650728850620515758" xil_pn:start_ts="1333726377">
<transform xil_pn:end_ts="1333906140" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-8650728850620515758" xil_pn:start_ts="1333906140">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
</transform>
<transform xil_pn:end_ts="1333727207" xil_pn:in_ck="300726481020074607" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1333727207">
<transform xil_pn:end_ts="1333907765" xil_pn:in_ck="300726481020074607" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1333907765">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="Alu.vhd"/>
<outfile xil_pn:name="ControlUnit.vhd"/>
<outfile xil_pn:name="DataPath.vhd"/>
273,73 → 257,64
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1333727210" xil_pn:in_ck="300726481020074607" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="4679725895911349372" xil_pn:start_ts="1333727207">
<status xil_pn:value="SuccessfullyRun"/>
<transform xil_pn:end_ts="1333907768" xil_pn:in_ck="300726481020074607" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="3692595343167413970" xil_pn:start_ts="1333907765">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testDataPath_beh.prj"/>
<outfile xil_pn:name="testDataPath_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1333727210" xil_pn:in_ck="4949781681609100681" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-6046575149236642790" xil_pn:start_ts="1333727210">
<status xil_pn:value="SuccessfullyRun"/>
<transform xil_pn:end_ts="1333906575" xil_pn:in_ck="4949781681609100681" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-8428607755353741456" xil_pn:start_ts="1333906574">
<status xil_pn:value="AbortedRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutOfDateForced"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testDataPath_isim_beh.wdb"/>
<outfile xil_pn:name="testAlu_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1333309884" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1333309884">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333733415" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8285396302157201690" xil_pn:start_ts="1333733415">
<transform xil_pn:end_ts="1333904187" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1242172528803053708" xil_pn:start_ts="1333904187">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333733415" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5240233618384058996" xil_pn:start_ts="1333733415">
<transform xil_pn:end_ts="1333904187" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8650728850620515758" xil_pn:start_ts="1333904187">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333733415" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1333733415">
<transform xil_pn:end_ts="1333904187" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1333904187">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333733415" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="133276131416554340" xil_pn:start_ts="1333733415">
<transform xil_pn:end_ts="1333904187" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5860233878951780918" xil_pn:start_ts="1333904187">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333733415" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1333733415">
<transform xil_pn:end_ts="1333904187" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1333904187">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333733415" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="7762239953561819094" xil_pn:start_ts="1333733415">
<transform xil_pn:end_ts="1333904187" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-154095565103849252" xil_pn:start_ts="1333904187">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333733421" xil_pn:in_ck="-296793447880885961" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="4317106340405143849" xil_pn:start_ts="1333733415">
<transform xil_pn:end_ts="1333905707" xil_pn:in_ck="-296793447880885961" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="924943614754068847" xil_pn:start_ts="1333905699">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name=".lso"/>
<outfile xil_pn:name="ControlUnit.lso"/>
<outfile xil_pn:name="ControlUnit.ngc"/>
<outfile xil_pn:name="ControlUnit.ngr"/>
<outfile xil_pn:name="ControlUnit.prj"/>
<outfile xil_pn:name="ControlUnit.stx"/>
<outfile xil_pn:name="ControlUnit.syr"/>
<outfile xil_pn:name="ControlUnit.xst"/>
<outfile xil_pn:name="ControlUnit_vhdl.prj"/>
<outfile xil_pn:name="ControlUnit_xst.xrpt"/>
<outfile xil_pn:name="Alu.ngr"/>
<outfile xil_pn:name="DataPath.lso"/>
<outfile xil_pn:name="DataPath.ngc"/>
<outfile xil_pn:name="DataPath.ngr"/>
<outfile xil_pn:name="DataPath.prj"/>
<outfile xil_pn:name="DataPath.stx"/>
<outfile xil_pn:name="DataPath.syr"/>
<outfile xil_pn:name="DataPath.xst"/>
<outfile xil_pn:name="DataPath_vhdl.prj"/>
<outfile xil_pn:name="DataPath_xst.xrpt"/>
<outfile xil_pn:name="RegisterFile.ngr"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>

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