OpenCores
URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /opencpu32/trunk/hdl/opencpu32
    from Rev 29 to Rev 30
    ↔ Reverse comparison
  •

Rev 29 → Rev 30

/opencpu32.xise
71,7 → 71,7
</file>
<file xil_pn:name="ControlUnit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="testControlUnit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
83,9 → 83,15
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="openCpu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="214"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
</files>
 
<properties>
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
99,6 → 105,8
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
115,12 → 123,19
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Busy" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin CS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin DIn" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin RdWr" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
131,6 → 146,7
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
139,6 → 155,7
<property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
145,20 → 162,30
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="Spartan-3E Starter Board" xil_pn:valueState="non-default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Fallback Reconfiguration" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
182,15 → 209,18
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ICAP Select" xil_pn:value="Top" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|DataPath|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="DataPath.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/DataPath" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|openCpu|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="openCpu.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/openCpu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
202,7 → 232,11
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG to System Monitor Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
214,20 → 248,23
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
248,7 → 285,7
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="DataPath" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="openCpu" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
258,14 → 295,20
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="DataPath_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="DataPath_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="DataPath_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="DataPath_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="openCpu_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="openCpu_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="openCpu_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="openCpu_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
276,14 → 319,17
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="DataPath" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="openCpu" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
305,6 → 351,7
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testDataPath" xil_pn:valueState="non-default"/>
313,7 → 360,9
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="200 ns" xil_pn:valueState="non-default"/>
329,6 → 378,9
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Address for Fallback Configuration virtex6" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
355,12 → 407,15
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
367,7 → 422,13
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value virtex5" xil_pn:value="0x000000" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
/openCpu.vhd
0,0 → 1,133
--! @file
--! @brief Arithmetic logic unit http://en.wikipedia.org/wiki/Arithmetic_logic_unit
 
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
--! Use CPU Definitions package
use work.pkgOpenCPU32.all;
 
--! Cpu top level file
 
--! Include the Control Unit and datapath
entity openCpu is
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
Port ( rst : in STD_LOGIC; --! Reset signal
clk : in STD_LOGIC; --! Clock signal
mem_rd : out STD_LOGIC; --! Main memory Read enable
mem_rd_addr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Read address
mem_wr : out STD_LOGIC; --! Main memory Write enable
mem_wr_addr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address
mem_data_in : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from main memory
mem_data_out : out STD_LOGIC_VECTOR (n downto 0) --! Data to main memory
);
end openCpu;
 
--! @brief Cpu http://en.wikipedia.org/wiki/Central_processing_unit
--! @details This description will instantiate the components ControlUnit and DataPath
architecture Behavioral of openCpu is
COMPONENT DataPath is
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
Port ( inputMm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from main memory
inputImm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from imediate value (instructions...)
clk : in STD_LOGIC; --! Clock signal
outEn : in typeEnDis; --! Enable/Disable datapath output
aluOp : in aluOps; --! Alu operations
muxSel : in STD_LOGIC_VECTOR (2 downto 0); --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
muxRegFile : in STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
regFileWriteAddr : in generalRegisters; --! General register write address
regFileWriteEn : in STD_LOGIC; --! RegisterFile write enable signal
regFileReadAddrA : in generalRegisters; --! General register read address (PortA)
regFileReadAddrB : in generalRegisters; --! General register read address (PortB)
regFileEnA : in STD_LOGIC; --! Enable RegisterFile PortA
regFileEnB : in STD_LOGIC; --! Enable RegisterFile PortB
outputDp : out STD_LOGIC_VECTOR (n downto 0); --! DataPath Output
dpFlags : out STD_LOGIC_VECTOR (2 downto 0)); --! Alu Flags
end COMPONENT;
 
COMPONENT ControlUnit is
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC; --! Main system clock
FlagsDp : in STD_LOGIC_VECTOR (2 downto 0); --! Flags comming from the Datapath
DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath
MuxDp : out STD_LOGIC_VECTOR (2 downto 0); --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath
DpAluOp : out aluOps; --! Alu operations
DpRegFileWriteAddr : out generalRegisters; --! General register address to write
DpRegFileWriteEn : out STD_LOGIC; --! Enable register write
DpRegFileReadAddrA : out generalRegisters; --! General register address to read
DpRegFileReadAddrB : out generalRegisters; --! General register address to read
DpRegFileReadEnA : out STD_LOGIC; --! Enable register read (PortA)
DpRegFileReadEnB : out STD_LOGIC; --! Enable register read (PortB)
MemoryDataReadEn : out std_logic; --! Enable Main memory read
MemoryDataWriteEn: out std_logic; --! Enable Main memory write
MemoryDataInput : in STD_LOGIC_VECTOR (n downto 0); --! Incoming data from main memory
MemoryDataRdAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Read address
MemoryDataWrAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address
MemoryDataOut : out STD_LOGIC_VECTOR (n downto 0)); --! Data to write on main memory
end COMPONENT;
 
signal InputImediate : STD_LOGIC_VECTOR (n downto 0);
signal enableOutputDp : typeEnDis;
signal aluOperations : aluOps;
signal InputDataPathSelector : STD_LOGIC_VECTOR (2 downto 0);
signal InputDataPathAluASelector : STD_LOGIC_VECTOR (1 downto 0);
signal registerFileWriteAddress : generalRegisters;
signal registerFileWriteEnable : STD_LOGIC;
signal registerFileReadAddressA : generalRegisters;
signal registerFileReadAddressB : generalRegisters;
signal registerFileReadEnableA : STD_LOGIC;
signal registerFileReadEnableB : STD_LOGIC;
signal dataPathOutput : STD_LOGIC_VECTOR (n downto 0);
signal dataPathFlags : STD_LOGIC_VECTOR (2 downto 0);
begin
--! Instantiate the Datapath
uDataPath: DataPath PORT MAP (
inputMm => InputImediate,
inputImm => mem_data_in,
clk => clk,
outEn => enableOutputDp,
aluOp => aluOperations,
muxSel => InputDataPathSelector,
muxRegFile => InputDataPathAluASelector,
regFileWriteAddr => registerFileWriteAddress,
regFileWriteEn => registerFileWriteEnable,
regFileReadAddrA => registerFileReadAddressA,
regFileReadAddrB => registerFileReadAddressB,
regFileEnA => registerFileReadEnableA,
regFileEnB => registerFileReadEnableB,
outputDp => dataPathOutput,
dpFlags => dataPathFlags
);
--! Instantiate the control unit
uControlUnit: ControlUnit PORT MAP (
reset => rst,
clk => clk,
FlagsDp => dataPathFlags,
DataDp => dataPathOutput,
MuxDp => InputDataPathSelector,
MuxRegDp => InputDataPathAluASelector,
ImmDp => InputImediate,
DpAluOp => aluOperations,
DpRegFileWriteAddr => registerFileWriteAddress,
DpRegFileWriteEn => registerFileWriteEnable,
DpRegFileReadAddrA => registerFileReadAddressA,
DpRegFileReadAddrB => registerFileReadAddressB,
DpRegFileReadEnA => registerFileReadEnableA,
DpRegFileReadEnB => registerFileReadEnableB,
MemoryDataReadEn => mem_rd,
MemoryDataWriteEn => mem_wr,
MemoryDataInput => mem_data_in,
MemoryDataRdAddr => mem_rd_addr,
MemoryDataWrAddr => mem_wr_addr,
MemoryDataOut => mem_data_out
);
 
end Behavioral;
 
/ControlUnit.vhd
20,7 → 20,7
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC; --! Main system clock
FlagsDp : in STD_LOGIC_VECTOR (n downto 0); --! Flags comming from the Datapath
FlagsDp : in STD_LOGIC_VECTOR (2 downto 0); --! Flags comming from the Datapath
DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath
MuxDp : out STD_LOGIC_VECTOR (2 downto 0); --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
35,7 → 35,8
MemoryDataReadEn : out std_logic; --! Enable Main memory read
MemoryDataWriteEn: out std_logic; --! Enable Main memory write
MemoryDataInput : in STD_LOGIC_VECTOR (n downto 0); --! Incoming data from main memory
MemoryDataAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory write address
MemoryDataRdAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Read address
MemoryDataWrAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address
MemoryDataOut : out STD_LOGIC_VECTOR (n downto 0)); --! Data to write on main memory
end ControlUnit;
 
91,10 → 92,9
cyclesExecute := 0;
PC <= (others => '0');
IR <= (others => '0');
MemoryDataAddr <= (others => '0');
MemoryDataRdAddr <= (others => '0');
MemoryDataReadEn <= '0';
MemoryDataWriteEn <= '0';
MemoryDataAddr <= (others => '0');
MemoryDataWriteEn <= '0';
nextCpuState <= fetch;
-- Fetch state (Go to memory and get a instruction)
101,7 → 101,7
when fetch =>
-- Increment program counter (Remember that PC will be update only on the next cycle...
PC <= PC + conv_std_logic_vector(1, nBits);
MemoryDataAddr <= PC; -- Warning PC is not 1 yet...
MemoryDataRdAddr <= PC; -- Warning PC is not 1 yet...
IR <= MemoryDataInput;
MemoryDataReadEn <= '1';
nextCpuState <= decode;
/_xmsgs/pn_parser.xmsgs
8,8 → 8,32
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/testDataPath.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/Alu.vhd&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/ControlUnit.vhd&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/DataPath.vhd&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/Multiplexer3_1.vhd&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/Multiplexer4_1.vhd&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/RegisterFile.vhd&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/TriStateBuffer.vhd&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/openCpu.vhd&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/pkgOpenCPU32.vhd&quot; into library work</arg>
</msg>
 
</messages>
 
/opencpu32.gise
188,6 → 188,17
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="openCpu.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="openCpu.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="openCpu.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="openCpu.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="openCpu.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="openCpu.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="openCpu.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="openCpu.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="openCpu_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="openCpu_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="openCpu_xst.xrpt"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testAlu_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testControlUnit_beh.prj"/>
209,130 → 220,55
</files>
 
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1333906140" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1333906140">
<transform xil_pn:end_ts="1333971566" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1333971566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333912779" xil_pn:in_ck="300726481020074607" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1333912779">
<transform xil_pn:end_ts="1333971566" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6268642977942111103" xil_pn:start_ts="1333971566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
<outfile xil_pn:name="ControlUnit.vhd"/>
<outfile xil_pn:name="DataPath.vhd"/>
<outfile xil_pn:name="Multiplexer3_1.vhd"/>
<outfile xil_pn:name="Multiplexer4_1.vhd"/>
<outfile xil_pn:name="RegisterFile.vhd"/>
<outfile xil_pn:name="TriStateBuffer.vhd"/>
<outfile xil_pn:name="pkgOpenCPU32.vhd"/>
<outfile xil_pn:name="testAlu.vhd"/>
<outfile xil_pn:name="testControlUnit.vhd"/>
<outfile xil_pn:name="testDataPath.vhd"/>
<outfile xil_pn:name="testMultiplexer4_1.vhd"/>
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1333912779" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-3798934868497889219" xil_pn:start_ts="1333912779">
<transform xil_pn:end_ts="1333971566" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-553081000213050619" xil_pn:start_ts="1333971566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333912779" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-6007724738129030273" xil_pn:start_ts="1333912779">
<transform xil_pn:end_ts="1333971566" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1333971566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333906140" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-8650728850620515758" xil_pn:start_ts="1333906140">
<transform xil_pn:end_ts="1333971566" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5126426351813824259" xil_pn:start_ts="1333971566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333912779" xil_pn:in_ck="300726481020074607" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1333912779">
<transform xil_pn:end_ts="1333971566" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1333971566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
<outfile xil_pn:name="ControlUnit.vhd"/>
<outfile xil_pn:name="DataPath.vhd"/>
<outfile xil_pn:name="Multiplexer3_1.vhd"/>
<outfile xil_pn:name="Multiplexer4_1.vhd"/>
<outfile xil_pn:name="RegisterFile.vhd"/>
<outfile xil_pn:name="TriStateBuffer.vhd"/>
<outfile xil_pn:name="pkgOpenCPU32.vhd"/>
<outfile xil_pn:name="testAlu.vhd"/>
<outfile xil_pn:name="testControlUnit.vhd"/>
<outfile xil_pn:name="testDataPath.vhd"/>
<outfile xil_pn:name="testMultiplexer4_1.vhd"/>
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1333912784" xil_pn:in_ck="300726481020074607" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="4679725895911349372" xil_pn:start_ts="1333912779">
<transform xil_pn:end_ts="1333971566" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-4767545221551224753" xil_pn:start_ts="1333971566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testDataPath_beh.prj"/>
<outfile xil_pn:name="testDataPath_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1333912784" xil_pn:in_ck="4949781681609100681" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-6046575149236642790" xil_pn:start_ts="1333912784">
<transform xil_pn:end_ts="1333971575" xil_pn:in_ck="-3059529097558291903" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-1259764691931299582" xil_pn:start_ts="1333971566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testDataPath_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1333309884" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1333309884">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333912739" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1242172528803053708" xil_pn:start_ts="1333912739">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333912739" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8650728850620515758" xil_pn:start_ts="1333912739">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333912739" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1333912739">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333912739" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5860233878951780918" xil_pn:start_ts="1333912739">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333912739" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1333912739">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333912739" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-154095565103849252" xil_pn:start_ts="1333912739">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333912747" xil_pn:in_ck="-296793447880885961" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="924943614754068847" xil_pn:start_ts="1333912739">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name=".lso"/>
<outfile xil_pn:name="Alu.ngr"/>
<outfile xil_pn:name="DataPath.lso"/>
<outfile xil_pn:name="DataPath.ngc"/>
<outfile xil_pn:name="ControlUnit.ngr"/>
<outfile xil_pn:name="DataPath.ngr"/>
<outfile xil_pn:name="DataPath.prj"/>
<outfile xil_pn:name="DataPath.stx"/>
<outfile xil_pn:name="DataPath.syr"/>
<outfile xil_pn:name="DataPath.xst"/>
<outfile xil_pn:name="DataPath_vhdl.prj"/>
<outfile xil_pn:name="DataPath_xst.xrpt"/>
<outfile xil_pn:name="RegisterFile.ngr"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="openCpu.lso"/>
<outfile xil_pn:name="openCpu.ngc"/>
<outfile xil_pn:name="openCpu.ngr"/>
<outfile xil_pn:name="openCpu.prj"/>
<outfile xil_pn:name="openCpu.stx"/>
<outfile xil_pn:name="openCpu.syr"/>
<outfile xil_pn:name="openCpu.xst"/>
<outfile xil_pn:name="openCpu_vhdl.prj"/>
<outfile xil_pn:name="openCpu_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1333275886" xil_pn:in_ck="3590950097743327443" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="2103587220659863231" xil_pn:start_ts="1333275886">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="InputRemoved"/>
</transform>
</transforms>
 
</generated_project>

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