URL
https://opencores.org/ocsvn/opencpu32/opencpu32/trunk
Subversion Repositories opencpu32
Compare Revisions
- This comparison shows the changes necessary to convert path
/opencpu32/trunk/hdl/opencpu32
- from Rev 35 to Rev 36
- ↔ Reverse comparison
Rev 35 → Rev 36
/opencpu32.xise
20,7 → 20,7
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> |
</file> |
<file xil_pn:name="Alu.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> |
</file> |
<file xil_pn:name="testAlu.vhd" xil_pn:type="FILE_VHDL"> |
30,7 → 30,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="50"/> |
</file> |
<file xil_pn:name="TriStateBuffer.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
</file> |
<file xil_pn:name="testTriStateBuffer.vhd" xil_pn:type="FILE_VHDL"> |
40,7 → 40,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="75"/> |
</file> |
<file xil_pn:name="RegisterFile.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
</file> |
<file xil_pn:name="testRegisterFile.vhd" xil_pn:type="FILE_VHDL"> |
50,7 → 50,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="146"/> |
</file> |
<file xil_pn:name="DataPath.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="7"/> |
</file> |
<file xil_pn:name="testDataPath.vhd" xil_pn:type="FILE_VHDL"> |
60,7 → 60,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="137"/> |
</file> |
<file xil_pn:name="Multiplexer4_1.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> |
</file> |
<file xil_pn:name="testMultiplexer4_1.vhd" xil_pn:type="FILE_VHDL"> |
70,23 → 70,29
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="138"/> |
</file> |
<file xil_pn:name="ControlUnit.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="8"/> |
</file> |
<file xil_pn:name="testControlUnit.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="219"/> |
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="219"/> |
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="219"/> |
</file> |
<file xil_pn:name="Multiplexer3_1.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="5"/> |
</file> |
<file xil_pn:name="openCpu.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="9"/> |
</file> |
<file xil_pn:name="testOpenCpu.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> |
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="218"/> |
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="218"/> |
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="218"/> |
</file> |
</files> |
|
<properties> |
316,8 → 322,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testControlUnit" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testControlUnit" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testOpenCpu" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testOpenCpu" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
333,7 → 339,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testControlUnit" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testOpenCpu" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> |
383,7 → 389,7
<!-- --> |
<!-- The following properties are for internal use only. These should not be modified.--> |
<!-- --> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testControlUnit|behavior" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testOpenCpu|behavior" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DesignName" xil_pn:value="opencpu32" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |
/testOpenCpu.vhd
0,0 → 1,97
--! @file |
--! @brief Testbench for OpenCpu top design |
|
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith) |
LIBRARY ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_arith.all; |
|
--! Use CPU Definitions package |
use work.pkgOpenCPU32.all; |
|
--! Adding library for File I/O (Synposys Text I/O package) |
use std.textio.ALL; |
use ieee.std_logic_textio.all; |
|
ENTITY testOpenCpu IS |
END testOpenCpu; |
|
--! @brief openCpu Testbench file |
--! @details This is the top-level test... |
ARCHITECTURE behavior OF testOpenCpu IS |
|
--! Component declaration to instantiate the Multiplexer circuit |
COMPONENT openCpu |
PORT( |
rst : IN std_logic; |
clk : IN std_logic; |
mem_rd : OUT std_logic; |
mem_rd_addr : OUT std_logic_vector(31 downto 0); |
mem_wr : OUT std_logic; |
mem_wr_addr : OUT std_logic_vector(31 downto 0); |
mem_data_in : IN std_logic_vector(31 downto 0); |
mem_data_out : OUT std_logic_vector(31 downto 0) |
); |
END COMPONENT; |
|
|
--Inputs |
signal rst : std_logic := '0'; |
signal clk : std_logic := '0'; |
signal mem_data_in : std_logic_vector(31 downto 0) := (others => '0'); |
|
--Outputs |
signal mem_rd : std_logic; |
signal mem_rd_addr : std_logic_vector(31 downto 0); |
signal mem_wr : std_logic; |
signal mem_wr_addr : std_logic_vector(31 downto 0); |
signal mem_data_out : std_logic_vector(31 downto 0); |
|
-- Clock period definitions |
constant clk_period : time := 10 ns; |
|
BEGIN |
|
--!Instantiate the Unit Under Test (openCpu) (Doxygen bug if it's not commented!) |
uut: openCpu PORT MAP ( |
rst => rst, |
clk => clk, |
mem_rd => mem_rd, |
mem_rd_addr => mem_rd_addr, |
mem_wr => mem_wr, |
mem_wr_addr => mem_wr_addr, |
mem_data_in => mem_data_in, |
mem_data_out => mem_data_out |
); |
|
-- Clock process definitions |
clk_process :process |
begin |
clk <= '0'; |
wait for clk_period/2; |
clk <= '1'; |
wait for clk_period/2; |
end process; |
|
|
-- Stimulus process |
stim_proc: process |
begin |
-- Reset operation |
REPORT "RESET" SEVERITY NOTE; |
rst <= '1'; |
wait for 2 ns; |
rst <= '0'; |
wait for 2 ns; |
|
wait for clk_period*10; |
|
-- insert stimulus here |
|
-- Finish simulation |
assert false report "NONE. End of simulation." severity failure; |
wait; |
end process; |
|
END; |
/_xmsgs/pn_parser.xmsgs
8,8 → 8,5
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
|
<messages> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "E:/opencpu32/hdl/opencpu32/ControlUnit.vhd" into library work</arg> |
</msg> |
|
</messages> |
|
/opencpu32.gise
202,12 → 202,13
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="openCpu_xst.xrpt"/> |
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testAlu_isim_beh.exe"/> |
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testControlUnit_beh.prj"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testControlUnit_isim_beh.exe"/> |
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testControlUnit_isim_beh.wdb"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testDataPath_isim_beh.exe"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testMultiplexer2_1_isim_beh.exe"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testMultiplexer4_1_isim_beh.exe"/> |
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testOpenCpu_beh.prj"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testOpenCpu_isim_beh.exe"/> |
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testOpenCpu_isim_beh.wdb"/> |
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testRegisterFile_beh.prj"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testRegisterFile_isim_beh.exe"/> |
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testRegisterFile_isim_beh.wdb"/> |
223,13 → 224,9
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1334439044" xil_pn:in_ck="5551394544742288633" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334439044"> |
<transform xil_pn:end_ts="1334496821" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334496821"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="Alu.vhd"/> |
<outfile xil_pn:name="ControlUnit.vhd"/> |
<outfile xil_pn:name="DataPath.vhd"/> |
243,14 → 240,15
<outfile xil_pn:name="testControlUnit.vhd"/> |
<outfile xil_pn:name="testDataPath.vhd"/> |
<outfile xil_pn:name="testMultiplexer4_1.vhd"/> |
<outfile xil_pn:name="testOpenCpu.vhd"/> |
<outfile xil_pn:name="testRegisterFile.vhd"/> |
<outfile xil_pn:name="testTriStateBuffer.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1334421105" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-2363811655998989481" xil_pn:start_ts="1334421105"> |
<transform xil_pn:end_ts="1334487070" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8309380896524256912" xil_pn:start_ts="1334487070"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1334421105" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="5020574084039002393" xil_pn:start_ts="1334421105"> |
<transform xil_pn:end_ts="1334487070" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7964109342171924334" xil_pn:start_ts="1334487070"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
258,14 → 256,9
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1334439044" xil_pn:in_ck="5551394544742288633" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334439044"> |
<transform xil_pn:end_ts="1334496821" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334496821"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="Alu.vhd"/> |
<outfile xil_pn:name="ControlUnit.vhd"/> |
<outfile xil_pn:name="DataPath.vhd"/> |
279,33 → 272,26
<outfile xil_pn:name="testControlUnit.vhd"/> |
<outfile xil_pn:name="testDataPath.vhd"/> |
<outfile xil_pn:name="testMultiplexer4_1.vhd"/> |
<outfile xil_pn:name="testOpenCpu.vhd"/> |
<outfile xil_pn:name="testRegisterFile.vhd"/> |
<outfile xil_pn:name="testTriStateBuffer.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1334439047" xil_pn:in_ck="5551394544742288633" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-2461943258679370096" xil_pn:start_ts="1334439044"> |
<transform xil_pn:end_ts="1334496823" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6846524775138479362" xil_pn:start_ts="1334496821"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="fuse.log"/> |
<outfile xil_pn:name="isim"/> |
<outfile xil_pn:name="isim.log"/> |
<outfile xil_pn:name="testControlUnit_beh.prj"/> |
<outfile xil_pn:name="testControlUnit_isim_beh.exe"/> |
<outfile xil_pn:name="testOpenCpu_beh.prj"/> |
<outfile xil_pn:name="testOpenCpu_isim_beh.exe"/> |
<outfile xil_pn:name="xilinxsim.ini"/> |
</transform> |
<transform xil_pn:end_ts="1334439047" xil_pn:in_ck="4949781681609100681" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="5692602031942061840" xil_pn:start_ts="1334439047"> |
<transform xil_pn:end_ts="1334496824" xil_pn:in_ck="-7416607345915100494" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-1487094935924008414" xil_pn:start_ts="1334496823"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="isim.cmd"/> |
<outfile xil_pn:name="isim.log"/> |
<outfile xil_pn:name="testControlUnit_isim_beh.wdb"/> |
<outfile xil_pn:name="testOpenCpu_isim_beh.wdb"/> |
</transform> |
<transform xil_pn:end_ts="1333971566" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1333971566"> |
<status xil_pn:value="SuccessfullyRun"/> |
339,23 → 325,12
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name=".lso"/> |
<outfile xil_pn:name="Alu.ngr"/> |
<outfile xil_pn:name="ControlUnit.ngr"/> |
<outfile xil_pn:name="DataPath.ngr"/> |
<outfile xil_pn:name="RegisterFile.ngr"/> |
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/> |
<outfile xil_pn:name="openCpu.lso"/> |
<outfile xil_pn:name="openCpu.ngc"/> |
<outfile xil_pn:name="openCpu.ngr"/> |
<outfile xil_pn:name="openCpu.prj"/> |
<outfile xil_pn:name="openCpu.stx"/> |
<outfile xil_pn:name="openCpu.syr"/> |
<outfile xil_pn:name="openCpu.xst"/> |
<outfile xil_pn:name="openCpu_vhdl.prj"/> |
<outfile xil_pn:name="openCpu_xst.xrpt"/> |
<outfile xil_pn:name="webtalk_pn.xml"/> |
<outfile xil_pn:name="xst"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputAdded"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="InputRemoved"/> |
<status xil_pn:value="OutputRemoved"/> |
</transform> |
</transforms> |
|