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URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

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  • This comparison shows the changes necessary to convert path 
    /opencpu32/trunk/hdl
    from Rev 47 to Rev 48
    ↔ Reverse comparison
  •

Rev 47 → Rev 48

/opencpu32/opencpu32.xise
20,7 → 20,7
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="Alu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="testAlu.vhd" xil_pn:type="FILE_VHDL">
30,7 → 30,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="TriStateBuffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="testTriStateBuffer.vhd" xil_pn:type="FILE_VHDL">
40,7 → 40,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="75"/>
</file>
<file xil_pn:name="RegisterFile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="testRegisterFile.vhd" xil_pn:type="FILE_VHDL">
50,7 → 50,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="146"/>
</file>
<file xil_pn:name="DataPath.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="testDataPath.vhd" xil_pn:type="FILE_VHDL">
60,7 → 60,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="137"/>
</file>
<file xil_pn:name="Multiplexer4_1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="testMultiplexer4_1.vhd" xil_pn:type="FILE_VHDL">
70,25 → 70,25
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="138"/>
</file>
<file xil_pn:name="ControlUnit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="testControlUnit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="219"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="219"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="219"/>
</file>
<file xil_pn:name="Multiplexer3_1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="openCpu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="testOpenCpu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="218"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="218"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="218"/>
322,8 → 322,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testOpenCpu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testOpenCpu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testControlUnit" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testControlUnit" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
339,7 → 339,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testOpenCpu" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testControlUnit" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
389,7 → 389,7
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testOpenCpu|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testControlUnit|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="opencpu32" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
/opencpu32/testOpenCpu.vhd
110,7 → 110,11
wait until mem_rd = '0';
end loop;
wait until mem_rd = '0';
wait until mem_rd = '0';
wait for CLK_period; -- Execute
wait for CLK_period; -- Execute
wait for CLK_period; -- Execute
wait for CLK_period; -- Execute
 
-- Finish simulation
assert false report "NONE. End of simulation." severity failure;
/opencpu32/openCpu.vhd
18,9 → 18,9
Port ( rst : in STD_LOGIC; --! Reset signal
clk : in STD_LOGIC; --! Clock signal
mem_rd : out STD_LOGIC; --! Main memory Read enable
mem_rd_addr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Read address
mem_rd_addr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Read address
mem_wr : out STD_LOGIC; --! Main memory Write enable
mem_wr_addr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address
mem_wr_addr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address
mem_data_in : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from main memory
mem_data_out : out STD_LOGIC_VECTOR (n downto 0) --! Data to main memory
);
/opencpu32/testControlUnit.vhd
36,7 → 36,7
DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath
outEnDp : out typeEnDis; --! Enable/Disable datapath output
MuxDp : out dpMuxInputs; --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
MuxRegDp : out dpMuxAluIn; --! Select Alu InputA (Memory,Imediate,RegFileA)
ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath
DpAluOp : out aluOps; --! Alu operations
DpRegFileWriteAddr : out generalRegisters; --! General register address to write
64,7 → 64,7
--Outputs
signal outEnDp : typeEnDis; --! Wire to connect Test signal to component
signal MuxDp : dpMuxInputs; --! Wire to connect Test signal to component
signal MuxRegDp : std_logic_vector(1 downto 0); --! Wire to connect Test signal to component
signal MuxRegDp : dpMuxAluIn; --! Wire to connect Test signal to component
signal ImmDp : std_logic_vector(n downto 0); --! Wire to connect Test signal to component
signal DpAluOp : aluOps; --! Wire to connect Test signal to component
signal DpRegFileWriteAddr : generalRegisters; --! Wire to connect Test signal to component
247,7 → 247,7
assert DpAluOp = alu_sum report "Invalid value" severity FAILURE;
assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;
assert DpRegFileReadEnA = '1' report "Invalid value" severity FAILURE;
assert MuxRegDp = muxRegPos(fromRegFileA) report "Invalid value" severity FAILURE;
assert MuxRegDp = fromRegFileA report "Invalid value" severity FAILURE;
wait for CLK_period; -- Executing ... 1
-- State writing on the registers
279,7 → 279,7
assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
assert DpAluOp = alu_sum report "Invalid value" severity FAILURE;
assert MuxDp = fromAlu report "Invalid value" severity FAILURE;
assert MuxRegDp = muxRegPos(fromImediate) report "Invalid value" severity FAILURE;
assert MuxRegDp = fromImediate report "Invalid value" severity FAILURE;
assert DpRegFileReadAddrB = r2 report "Invalid value" severity FAILURE;
assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;
346,8 → 346,44
wait for CLK_period; -- Executing ... 4
wait for CLK_period; -- Executing ... 4
--wait for CLK_period; -- Executing ... 4
-------------------------------------------------------------------------------------------------
-- jmp 0 (Jump to position 0)--------------------------------------------------------------------
REPORT "jmp 0" SEVERITY NOTE;
MemoryDataInput <= jmp_val & conv_std_logic_vector(0,4) & conv_std_logic_vector(0, 22);
wait for CLK_period; -- Fetch
wait for CLK_period; -- Decode
wait for CLK_period; -- Execute
-- Write the command to a file (This will be usefull for the top Testing later)
WRITE (line_out, MemoryDataInput);
WRITELINE (cmdfile, line_out);
--wait for CLK_period; -- Executing ... 1
--assert MemoryDataRdAddr = conv_std_logic_vector(0, 32) report "Invalid value" severity FAILURE;
--wait for CLK_period; -- Executing ... 2
-------------------------------------------------------------------------------------------------
-- jmpr 3 (Jump to position Current + 3)--------------------------------------------------------------------
REPORT "jmpr 3" SEVERITY NOTE;
MemoryDataInput <= jmpr_val & conv_std_logic_vector(0,4) & conv_std_logic_vector(3, 22);
wait for CLK_period; -- Fetch
wait for CLK_period; -- Decode
wait for CLK_period; -- Execute
-- Write the command to a file (This will be usefull for the top Testing later)
WRITE (line_out, MemoryDataInput);
WRITELINE (cmdfile, line_out);
wait for CLK_period; -- Executing ... 1
--assert MemoryDataRdAddr = conv_std_logic_vector(3, 32) report "Invalid value" severity FAILURE;
--wait for CLK_period; -- Executing ... 2
-------------------------------------------------------------------------------------------------
 
-- Close file
/opencpu32/ControlUnit.vhd
141,10 → 141,12
case opcodeIR is
when jmp_val =>
PC <= "0000000000" & operand_imm;
PC <= "0000000000" & operand_imm;
nextCpuState <= fetch;
when jmpr_val =>
PC <= PC + ("0000000000" & operand_imm);
PC <= PC + ("0000000000" & operand_imm);
nextCpuState <= fetch;
-- ld r5,20 (Load into r5 register the content of the memory at address 20)
when ld_val =>
/opencpu32/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/laraujo/work/opencpu32/hdl/opencpu32/ControlUnit.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/laraujo/work/opencpu32/hdl/opencpu32/testControlUnit.vhd&quot; into library work</arg>
</msg>
 
</messages>
/opencpu32/opencpu32.gise
235,13 → 235,13
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="openCpu_xst.xrpt"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testAlu_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testControlUnit_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testControlUnit_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testControlUnit_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testDataPath_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testMultiplexer2_1_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testMultiplexer4_1_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testOpenCpu_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testOpenCpu_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testOpenCpu_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testRegisterFile_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testTriStateBuffer_isim_beh.exe"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
255,7 → 255,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334733522" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334733522">
<transform xil_pn:end_ts="1334761313" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334761313">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
275,11 → 275,11
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1334733522" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8309380896524256912" xil_pn:start_ts="1334733522">
<transform xil_pn:end_ts="1334761328" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-2363811655998989481" xil_pn:start_ts="1334761328">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334733522" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7964109342171924334" xil_pn:start_ts="1334733522">
<transform xil_pn:end_ts="1334761328" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="5020574084039002393" xil_pn:start_ts="1334761328">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
287,7 → 287,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334733522" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334733522">
<transform xil_pn:end_ts="1334761313" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334761313">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
307,7 → 307,7
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1334733524" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6846524775138479362" xil_pn:start_ts="1334733522">
<transform xil_pn:end_ts="1334761330" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-2461943258679370096" xil_pn:start_ts="1334761328">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
315,16 → 315,16
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testOpenCpu_beh.prj"/>
<outfile xil_pn:name="testOpenCpu_isim_beh.exe"/>
<outfile xil_pn:name="testControlUnit_beh.prj"/>
<outfile xil_pn:name="testControlUnit_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1334733525" xil_pn:in_ck="-3218109590739612736" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-2257473906977297968" xil_pn:start_ts="1334733524">
<transform xil_pn:end_ts="1334761330" xil_pn:in_ck="-3218109590739612736" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-5135146925621150594" xil_pn:start_ts="1334761330">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testOpenCpu_isim_beh.wdb"/>
<outfile xil_pn:name="testControlUnit_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1333971566" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1333971566">
<status xil_pn:value="SuccessfullyRun"/>
358,6 → 358,8
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name=".lso"/>
<outfile xil_pn:name="Alu.ngr"/>
<outfile xil_pn:name="ControlUnit.ngr"/>
/opencpu32/testCode/testCodeBin.dat
5,5 → 5,5
01110000100000000000000000000010
00001100100000000000000000110010
00010101010000000000000000010100
00000100000000000000000000001010
00000100000000000000000000001010
00011000000000000000000000000000
00011100000000000000000000000011

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