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URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

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  • This comparison shows the changes necessary to convert path 
    /opencpu32/trunk
    from Rev 32 to Rev 33
    ↔ Reverse comparison
  •

Rev 32 → Rev 33

/hdl/opencpu32/opencpu32.xise
20,7 → 20,7
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="Alu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="testAlu.vhd" xil_pn:type="FILE_VHDL">
30,7 → 30,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="TriStateBuffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="testTriStateBuffer.vhd" xil_pn:type="FILE_VHDL">
40,7 → 40,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="75"/>
</file>
<file xil_pn:name="RegisterFile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="testRegisterFile.vhd" xil_pn:type="FILE_VHDL">
50,17 → 50,17
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="146"/>
</file>
<file xil_pn:name="DataPath.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="testDataPath.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="137"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="137"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="137"/>
</file>
<file xil_pn:name="Multiplexer4_1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="testMultiplexer4_1.vhd" xil_pn:type="FILE_VHDL">
70,17 → 70,17
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="138"/>
</file>
<file xil_pn:name="ControlUnit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="testControlUnit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="219"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="219"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="219"/>
</file>
<file xil_pn:name="Multiplexer3_1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="openCpu.vhd" xil_pn:type="FILE_VHDL">
316,8 → 316,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testDataPath" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testDataPath" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testControlUnit" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testControlUnit" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
333,7 → 333,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testDataPath" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testControlUnit" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
383,7 → 383,7
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testDataPath|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testControlUnit|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="opencpu32" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
/hdl/opencpu32/ControlUnit.vhd
70,7 → 70,7
-- Next state logic (Execution states)
process (clk, currentCpuState)
begin
if ( (currentCpuState /= execute) and (currentCpuState /= executing) ) then
if (reset = '1') then
currentExState <= initInstructionExecution;
elsif rising_edge(clk) then
currentExState <= nextExState;
187,7 → 187,13
-- Select the instruction and init it's execution
case currentExState is
when initInstructionExecution =>
case opcodeIR is
nextExState <= waitToExecute;
when waitToExecute =>
if ( (currentCpuState /= execute) and (currentCpuState /= executing) ) then
nextExState <= initInstructionExecution;
else
case opcodeIR is
-- MOV r2,r1 (See the testDatapath to see how to drive the datapath for this function)
when mov_reg =>
MuxDp <= muxPos(fromRegFileB);
244,7 → 250,8
when others =>
null;
end case;
end case;
end if;
-- Write something on the register files
when writeRegister =>
266,7 → 273,9
DpRegFileReadEnB <= '0';
DpRegFileReadEnA <= '0';
DpRegFileWriteEn <= '0';
outEnDp <= disable;
outEnDp <= disable;
-- Come back to waiting state
nextExState <= waitToExecute;
when others =>
null;
/hdl/opencpu32/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/testDataPath.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/testControlUnit.vhd&quot; into library work</arg>
</msg>
 
</messages>
/hdl/opencpu32/pkgOpenCPU32.vhd
27,7 → 27,7
type dpMuxInputs is (fromMemory, fromImediate, fromRegFileA, fromRegFileB, fromAlu);
type dpMuxAluIn is (fromMemory, fromImediate, fromRegFileA);
type controlUnitStates is (initial, fetch, decode, execute, executing);
type executionStates is (initInstructionExecution, writeRegister, releaseWriteRead, readRegisterA, readRegisterB, releaseRead);
type executionStates is (initInstructionExecution, waitToExecute, writeRegister, releaseWriteRead, readRegisterA, readRegisterB, releaseRead);
 
--! Flags positions
constant flag_sign : integer := 2;
/hdl/opencpu32/testControlUnit.vhd
122,9 → 122,23
reset <= '0';
wait for 2 ns;
 
-- MOV r0,10d ---------------------------------------------------------------------------------
-- MOV r0,10d (Compare control unit outputs with Datapath)--------------------------------------
REPORT "MOV r0,10" SEVERITY NOTE;
wait for CLK_period;
MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r0),4) & conv_std_logic_vector(10, 22);
wait for CLK_period; -- Fetch
wait for CLK_period; -- Decode
wait for CLK_period; -- Execute
wait for CLK_period; -- Executing ... 1
wait for CLK_period; -- Executing ... 2
-- MOV r1,20d (Compare control unit outputs with Datapath)--------------------------------------
REPORT "MOV r1,20" SEVERITY NOTE;
MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r1),4) & conv_std_logic_vector(20, 22);
wait for CLK_period; -- Fetch
wait for CLK_period; -- Decode
wait for CLK_period; -- Execute
wait for CLK_period; -- Executing ... 1
wait for CLK_period; -- Executing ... 2
 
wait;
end process;
/hdl/opencpu32/opencpu32.gise
201,10 → 201,10
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="openCpu_xst.xrpt"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testAlu_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testControlUnit_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testControlUnit_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testDataPath_beh.prj"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testControlUnit_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testDataPath_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testDataPath_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testMultiplexer2_1_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testMultiplexer4_1_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testRegisterFile_beh.prj"/>
222,7 → 222,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334403814" xil_pn:in_ck="5551394544742288633" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334403814">
<transform xil_pn:end_ts="1334428831" xil_pn:in_ck="5551394544742288633" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334428831">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
241,11 → 241,11
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1334403814" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-3798934868497889219" xil_pn:start_ts="1334403814">
<transform xil_pn:end_ts="1334421105" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-2363811655998989481" xil_pn:start_ts="1334421105">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334403814" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-6007724738129030273" xil_pn:start_ts="1334403814">
<transform xil_pn:end_ts="1334421105" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="5020574084039002393" xil_pn:start_ts="1334421105">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
253,7 → 253,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334403814" xil_pn:in_ck="5551394544742288633" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334403814">
<transform xil_pn:end_ts="1334428831" xil_pn:in_ck="5551394544742288633" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334428831">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
272,22 → 272,22
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1334403817" xil_pn:in_ck="5551394544742288633" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="4679725895911349372" xil_pn:start_ts="1334403814">
<transform xil_pn:end_ts="1334428834" xil_pn:in_ck="5551394544742288633" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-2461943258679370096" xil_pn:start_ts="1334428831">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testDataPath_beh.prj"/>
<outfile xil_pn:name="testDataPath_isim_beh.exe"/>
<outfile xil_pn:name="testControlUnit_beh.prj"/>
<outfile xil_pn:name="testControlUnit_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1334403818" xil_pn:in_ck="4949781681609100681" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-6046575149236642790" xil_pn:start_ts="1334403817">
<transform xil_pn:end_ts="1334428834" xil_pn:in_ck="4949781681609100681" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="7818598284332786958" xil_pn:start_ts="1334428834">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testDataPath_isim_beh.wdb"/>
<outfile xil_pn:name="testControlUnit_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1333971566" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1333971566">
<status xil_pn:value="SuccessfullyRun"/>
321,6 → 321,8
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name=".lso"/>
<outfile xil_pn:name="Alu.ngr"/>
<outfile xil_pn:name="ControlUnit.ngr"/>

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