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URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

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  • This comparison shows the changes necessary to convert path 
    /opencpu32
    from Rev 45 to Rev 46
    ↔ Reverse comparison
  •

Rev 45 → Rev 46

/trunk/hdl/opencpu32/opencpu32.xise
331,7 → 331,7
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="400 ns" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="2000 ns" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
/trunk/hdl/opencpu32/testControlUnit.vhd
322,10 → 322,32
-- Verify memory strobe signal
assert MemoryDataWriteEn = '1' report "Invalid value" severity FAILURE;
-------------------------------------------------------------------------------------------------
-- ld r5,20 (Load into r5 register the content of the memory at address 20)----------------------
REPORT "ld r5,20" SEVERITY NOTE;
MemoryDataInput <= ld_val & conv_std_logic_vector(reg2Num(r5),4) & conv_std_logic_vector(20, 22);
wait for CLK_period; -- Fetch
wait for CLK_period; -- Decode
wait for CLK_period; -- Execute
-- Write the command to a file (This will be usefull for the top Testing later)
WRITE (line_out, MemoryDataInput);
WRITELINE (cmdfile, line_out);
assert MemoryDataRdAddr = conv_std_logic_vector(20, 32) report "Invalid value" severity FAILURE;
wait for CLK_period; -- Executing ... 1
wait for CLK_period; -- Executing ... 2
wait for CLK_period; -- Executing ... 3
assert MemoryDataWriteEn = '0' report "Invalid value" severity FAILURE;
wait for CLK_period; -- Executing ... 4
wait for CLK_period; -- Executing ... 4
-------------------------------------------------------------------------------------------------
 
-- Close file
/trunk/hdl/opencpu32/ControlUnit.vhd
146,9 → 146,13
when jmpr_val =>
PC <= PC + ("0000000000" & operand_imm);
-- ld r5,20 (Load into r5 register the content of the memory at address 20)
when ld_val =>
MemoryDataRdAddr <= "0000000000" & operand_imm;
MemoryDataReadEn <= '1';
MemoryDataReadEn <= '1';
if cyclesExecute = 0 then
MemoryDataReadEn <= '0';
end if;
-- STORE r1,10 (Store the value 10 on memory address pointed by r1)
when stom_val =>
/trunk/hdl/opencpu32/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/laraujo/work/opencpu32/hdl/opencpu32/testOpenCpu.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/laraujo/work/opencpu32/hdl/opencpu32/testControlUnit.vhd&quot; into library work</arg>
</msg>
 
</messages>
/trunk/hdl/opencpu32/opencpu32.gise
219,9 → 219,7
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testOpenCpu_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testOpenCpu_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testOpenCpu_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testRegisterFile_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testRegisterFile_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testRegisterFile_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testTriStateBuffer_isim_beh.exe"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
234,7 → 232,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334674245" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334674245">
<transform xil_pn:end_ts="1334678325" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334678325">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
254,11 → 252,11
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1334674301" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8309380896524256912" xil_pn:start_ts="1334674301">
<transform xil_pn:end_ts="1334678810" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8309380896524256912" xil_pn:start_ts="1334678810">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334674301" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7964109342171924334" xil_pn:start_ts="1334674301">
<transform xil_pn:end_ts="1334678810" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7964109342171924334" xil_pn:start_ts="1334678810">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
266,7 → 264,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334674245" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334674245">
<transform xil_pn:end_ts="1334678325" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334678325">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
286,7 → 284,7
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1334674303" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6846524775138479362" xil_pn:start_ts="1334674301">
<transform xil_pn:end_ts="1334678812" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6846524775138479362" xil_pn:start_ts="1334678810">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
298,9 → 296,11
<outfile xil_pn:name="testOpenCpu_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1334674303" xil_pn:in_ck="-3218109590739612736" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-1487094935924008414" xil_pn:start_ts="1334674303">
<transform xil_pn:end_ts="1334678812" xil_pn:in_ck="-3218109590739612736" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-2257473906977297968" xil_pn:start_ts="1334678812">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testOpenCpu_isim_beh.wdb"/>
/trunk/hdl/opencpu32/testCode/testCodeBin.dat
4,3 → 4,6
01101100100000000000000000000000
01110000100000000000000000000010
00001100100000000000000000110010
00010101010000000000000000010100
00000100000000000000000000001010
00000100000000000000000000001010

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