URL
https://opencores.org/ocsvn/openfpu64/openfpu64/trunk
Subversion Repositories openfpu64
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/tags/at_deadline/eis_helpers.vhd
0,0 → 1,76
------------------------------------------------------------------------------- |
-- Title : Helpers |
-- Project : openFPU64 |
------------------------------------------------------------------------------- |
-- File : eis_helpers.vhd |
-- Author : Prof. Dr. Gundolf Kiefer <gundolf.kiefer@hs-augsburg.de> |
-- Company : University of Applied Sciences, Augsburg |
-- Last update: 2010-04-22 |
-- Platform : |
-- Standard : VHDL'87 |
------------------------------------------------------------------------------- |
-- Description: This package contains neat some helper functions that ease |
-- printing out std_logic, std_logic_vector, unsigned and integer |
-- values. This package is especially handy for Testbenches. |
------------------------------------------------------------------------------- |
-- Copyright (c) 2010 |
------------------------------------------------------------------------------- |
-- License : GPL v3 -- see gpl.txt |
------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
use IEEE.numeric_std.all; |
|
library STD; |
use STD.textio.all; |
|
|
|
package helpers is |
function to_character (val : in std_logic) return character; |
function to_string (val : in std_logic_vector) return string; |
function to_string (val: in unsigned) return string; |
function to_string (val: in integer) return string; |
end helpers; |
|
|
package body helpers is |
|
-- Testbench helpers... |
function to_character (val : in std_logic) return character is |
begin |
case val is |
when '0' => return '0'; |
when '1' => return '1'; |
when 'U' => return 'u'; |
when 'Z' => return 'z'; |
when others => return 'x'; |
end case; |
end to_character; |
|
function to_string (val : in std_logic_vector) return string is |
variable str: string (1 to val'length); |
alias val_norm : std_logic_vector (1 to val'length) is val; |
variable n: integer; |
begin |
for i in str'range loop |
str(i) := to_character(val_norm(i)); |
end loop; |
return str; |
end to_string; |
|
function to_string (val: in unsigned) return string is |
begin |
return to_string (std_logic_vector (val)); |
end to_string; |
|
function to_string (val: in integer) return string is |
variable retLine: line; |
begin |
write (retLine, val); |
return retLine(1 to retLine'length); |
end to_string; |
|
|
end helpers; |
/tags/at_deadline/fpu_mul_single.vhd
0,0 → 1,309
------------------------------------------------------------------------------- |
-- Project : openFPU64 Multiplier Component |
------------------------------------------------------------------------------- |
-- File : fpu_mul.vhd |
-- Author : Peter Huewe <peterhuewe@gmx.de> |
-- Created : 2010-04-19 |
-- Last update: 2010-04-19 |
-- Standard : VHDL'87 |
-- Status : ALPHA! - Bugs exists! |
------------------------------------------------------------------------------- |
-- Description: double precision floating point multiplier component |
-- for openFPU64, includes rounding and normalization |
-- Uses only one embedded 18x18 multiplier |
-- Note : Last few bits are wrong, perhaps related to stickybit /rounding |
-- issues |
------------------------------------------------------------------------------- |
-- Copyright (c) 2010 |
------------------------------------------------------------------------------- |
-- License: gplv3, see licence.txt |
------------------------------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
use work.helpers.all; |
use work.fpu_package.all; |
------------------------------------------------------------------------------- |
|
entity fpu_mul is |
port ( |
clk, reset_n : in std_logic; -- reset = standard active low |
cs : in std_logic; -- mode: 0 = add , 1= sub |
sign_a, sign_b : in std_logic; -- sign bits |
exponent_a, exponent_b : in std_logic_vector (11 downto 0); -- exponents of the operands |
mantissa_a, mantissa_b : in std_logic_vector (57 downto 0); -- mantissa of operands |
--enable : in std_logic; -- enable this submodule |
sign_res : out std_logic; |
exponent_res : out std_logic_vector(11 downto 0); |
mantissa_res : out std_logic_vector (57 downto 0); |
rounding_needed : out std_logic; |
-- result : out std_logic_vector (63 downto 0); |
-- ready : out std_logic; -- entspricht waitrequest_n |
valid : out std_logic |
); |
|
end fpu_mul; |
|
------------------------------------------------------------------------------- |
|
architecture rtl of fpu_mul is |
|
----------------------------------------------------------------------------- |
-- Internal signal declarations |
----------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
--signal mul_a, mul_b : std_logic_vector(53 downto 0); -- inputs for multiplier |
--signal mul_result: std_logic_vector(57 downto 0); -- result of multiplier |
signal add_result, add_op_a : unsigned (39 downto 0); |
signal add_op_b : unsigned (35 downto 0); |
signal mul_result : unsigned(35 downto 0); |
signal mul_op_a, mul_op_b : unsigned(17 downto 0); |
type t_state is (s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s12a, s12b,s12c,s12d); -- possible states |
signal state : t_state; -- current state |
|
signal exponent_out : std_logic_vector(11 downto 0); |
signal tmp_result : std_logic_vector (57 downto 0); |
|
|
alias a : std_logic_vector(17 downto 0) is mantissa_a(56 downto 39); |
alias b : std_logic_vector(17 downto 0) is mantissa_a(38 downto 21); |
alias c : std_logic_vector(17 downto 0) is mantissa_a(20 downto 3); |
alias d : std_logic_vector(17 downto 0) is mantissa_b(56 downto 39); |
alias e : std_logic_vector(17 downto 0) is mantissa_b(38 downto 21); |
alias f : std_logic_vector(17 downto 0) is mantissa_b(20 downto 3); |
|
|
signal a_is_normal, b_is_normal : std_logic; |
signal sticky_bit : std_logic; |
signal sticky_bit_enabled : std_logic; |
----------------------------------------------------------------------------- |
-- Component declarations |
----------------------------------------------------------------------------- |
begin |
---------------------------------------------------------------- |
-- Component instantiations |
----------------------------------------------------------------------------- |
|
-- purpose: calculates the result of a multiplication |
-- type : combinational |
-- inputs : sign_a, sign_b, exponent_a, exponent_b, mantissa_a, mantissa_b |
-- outputs: result |
|
add_result <= add_op_a + add_op_b; |
mul_result <= unsigned(mul_op_a) * unsigned(mul_op_b); |
a_is_normal <= '0' when unsigned(exponent_a(10 downto 0)) = ALL_ZEROS else '1'; |
b_is_normal <= '0' when unsigned(exponent_b(10 downto 0)) = ALL_ZEROS else '1'; |
sticky_bit <= sticky_bit_enabled when add_result(18 downto 0) /= ZEROS(18 downto 0) else '0'; |
|
state_trans : process (clk, reset_n, cs) |
variable tmp : unsigned(57 downto 0); |
begin -- process state_trans |
rounding_needed <= '1'; |
if reset_n = '0' or cs = '0' then |
state <= s1; |
sign_res <= '0'; |
valid <= '0'; |
sticky_bit_enabled <= '0'; |
-- result <= (others => '0'); |
exponent_res <= (others => '0'); |
mantissa_res <= (others => '0'); |
-- tmp := (others => '0'); |
tmp_result <= (others => '0'); |
elsif rising_edge(clk) then |
sign_res <= sign_a xor sign_b; |
valid <= '0'; |
-- result <= (others => '0'); |
exponent_res <= exponent_out; |
mantissa_res <= (others => '0'); |
mantissa_res <= tmp_result; |
tmp_result <= tmp_result; |
add_op_a <= (others => '0'); |
add_op_b <= (others => '0'); |
mul_op_a <= (others => '0'); |
mul_op_b <= (others => '0'); |
sticky_bit_enabled <= sticky_bit_enabled; |
|
case state is |
when s1 => |
add_op_a <= (others => '0'); |
add_op_b <= (others => '0'); |
add_op_a(10 downto 0) <= unsigned(exponent_a(10 downto 0)); |
add_op_b(10 downto 0) <= unsigned(exponent_b(10 downto 0)); |
|
mul_op_a <= unsigned(c); |
mul_op_b <= unsigned(f); |
state <= s2; |
when s2 => |
--assert false report "Test" & to_string(std_logic_vector(add_result(13 downto 0))) severity warning; |
add_op_a (11 downto 0) <= add_result(11 downto 0); |
add_op_b (11 downto 0) <= DOUBLE_BIAS_2COMPLEMENT(11 downto 0); |
tmp_result(35 downto 0) <= std_logic_vector(mul_result); |
|
mul_op_a <= unsigned(b); |
mul_op_b <= unsigned(f); |
|
|
state <= s3; |
when s3 => |
-- assert false report "Test" & to_string(std_logic_vector(add_result(13 downto 0))) severity warning; |
-- assert false report "ea" & to_string(exponent_a) & "eb" & to_string(exponent_b) &"xx"& to_string(std_logic_vector(DOUBLE_BIAS_2COMPLEMENT)) severity warning; |
-- if either the result is a subnormal/zero or both operands are zero |
-- set exponent to zero |
if (add_result(12) = '1' and (a_is_normal = '0' or b_is_normal = '0')) |
or (a_is_normal = '0' and b_is_normal = '0') |
then |
exponent_out <= (others => '0'); |
else |
exponent_out <= std_logic_vector(add_result(11 downto 0)); |
end if; |
sticky_bit_enabled <= '1'; -- since we start adding up values, |
-- sticky bit has to be calculated |
assert sticky_bit = '0' report "sticky3"&to_string(std_logic_vector(add_result))severity note; |
|
if unsigned(tmp_result(18 downto 0)) = (ZEROS(18 downto 0))then |
add_op_a <= unsigned(tmp_result(57 downto 19))&'0'; |
|
else |
add_op_a <= unsigned(tmp_result(57 downto 18)); |
end if; |
|
add_op_b <= mul_result; |
|
mul_op_a <= unsigned(c); |
mul_op_b <= unsigned(e); |
|
state <= s4; |
when s4 => |
assert sticky_bit = '0' report "sticky4"&to_string(std_logic_vector(add_result))severity note; |
add_op_a <= add_result; |
add_op_b <= mul_result; |
|
mul_op_a <= unsigned(a); |
mul_op_b <= unsigned(f); |
|
state <= s5; |
when s5 => |
assert sticky_bit = '0' report "sticky5"&to_string(std_logic_vector(add_result))severity note; |
add_op_a <= "00"&x"0000"& add_result(39 downto 19)&sticky_bit; |
add_op_b <= mul_result; |
|
mul_op_a <= unsigned(b); |
mul_op_b <= unsigned(e); |
|
state <= s6; |
when s6 => |
assert sticky_bit = '0' report "sticky6"&to_string(std_logic_vector(add_result))severity note; |
add_op_a <= add_result; |
add_op_b <= mul_result; |
|
mul_op_a <= unsigned(c); |
mul_op_b <= unsigned(d); |
|
|
|
state <= s7; |
when s7 => |
assert sticky_bit = '0' report "sticky7"&to_string(std_logic_vector(add_result))severity note; |
add_op_a <= add_result; |
add_op_b <= mul_result; |
mul_op_a <= unsigned(a); |
mul_op_b <= unsigned(e); |
|
state <= s8; |
when s8 => |
assert sticky_bit = '0' report "sticky8"&to_string(std_logic_vector(add_result))severity note; |
add_op_a <= "00"&x"0000"& add_result(39 downto 18);--&sticky_bit; |
add_op_b <= mul_result; |
|
mul_op_a <= unsigned(b); |
mul_op_b <= unsigned(d); |
|
|
state <= s9; |
when s9 => |
assert sticky_bit = '0' report "sticky9"&to_string(std_logic_vector(add_result))severity note; |
add_op_a <= add_result; |
add_op_b <= mul_result; |
mul_op_a <= unsigned(a); |
mul_op_b <= unsigned(d); |
tmp_result <= (others => '0'); |
assert false report "bla" & to_string(std_logic_vector(add_result)) severity warning; |
assert false report "bla" & to_string(std_logic_vector(add_result(39 downto 30))) severity warning; |
tmp_result (4 downto 0) <= std_logic_vector(add_result(39 downto 36))&sticky_bit; -- |
-- driving me crazy! |
|
state <= s10; |
when s10 => |
assert sticky_bit = '0' report "sticky10"&to_string(std_logic_vector(add_result))severity note; |
assert false report "bla1" & to_string(std_logic_vector(add_result)) severity warning; |
add_op_a <= "00"&x"0000"& add_result(39 downto 18); |
add_op_b <= mul_result; |
|
tmp_result(22 downto 5) <= std_logic_vector(add_result(17 downto 0)); |
|
|
state <= s11; |
when s11 => |
assert false report "bla2" & to_string(std_logic_vector(add_result)) severity warning; |
tmp_result (57 downto 23) <= std_logic_vector(add_result(34 downto 0)); |
state <= s12b; |
if add_result (33) = '1' then |
state <= s12a; |
end if; |
-- VALID <= '1'; |
|
when s12a=> |
assert false report "shift"&to_string(tmp_result) severity note; |
assert false report "ungleich" severity note; |
tmp_result(57 downto 1) <= '0'&tmp_result(57 downto 2); |
tmp_result(0) <= tmp_result(1) or tmp_result(0); |
exponent_out <= std_logic_vector(unsigned(exponent_out)+"1"); |
state <= s12b; |
|
when s12b=> |
assert false report "vorrund"&to_string(tmp_result) severity note; |
case tmp_result(3 downto 0) is |
when "0101" => tmp_result(3) <= '1'; |
when "0110" => tmp_result(3) <= '1'; |
when "0111" => tmp_result(3) <= '1'; |
|
when "1100" => tmp_result(57 downto 3) <= std_logic_vector(unsigned(tmp_result(57 downto 3))+"1"); |
when "1101" => tmp_result(57 downto 3) <= std_logic_vector(unsigned(tmp_result(57 downto 3))+"1"); |
when "1110" => tmp_result(57 downto 3) <= std_logic_vector(unsigned(tmp_result(57 downto 3))+"1"); |
when "1111" => tmp_result(57 downto 3) <= std_logic_vector(unsigned(tmp_result (57 downto 3))+"1"); |
|
|
when others => null; -- others remain unchanged |
end case; |
|
state <= s12c; |
when s12c=> |
state <= s12; |
if tmp_result(56) ='1' then |
state <= s12d; |
|
end if; |
|
when s12d=> |
assert false report "ungleich" severity note; |
tmp_result(57 downto 1) <= '0'&tmp_result(57 downto 2); |
tmp_result(0) <= tmp_result(1) or tmp_result(0); |
exponent_out <= std_logic_vector(unsigned(exponent_out)+"1"); |
state <= s12; |
|
|
when s12 => |
assert false report "ttt"&to_string(tmp_result) severity note; |
state <= s12; |
valid <= '1'; |
|
when others => null; |
end case; |
end if; |
|
end process state_trans; |
|
end rtl; |
|
------------------------------------------------------------------------------- |
/tags/at_deadline/tests.tar.bz2
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tags/at_deadline/tests.tar.bz2
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+application/octet-stream
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Index: tags/at_deadline/gpl.txt
===================================================================
--- tags/at_deadline/gpl.txt (nonexistent)
+++ tags/at_deadline/gpl.txt (revision 6)
@@ -0,0 +1,674 @@
+ GNU GENERAL PUBLIC LICENSE
+ Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc.
+ Copyright (C)
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see Copyright (C)
+ This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+ This is free software, and you are welcome to redistribute it
+ under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License. Of course, your program's commands
+might be different; for a GUI interface, you would use an "about box".
+
+ You should also get your employer (if you work as a programmer) or school,
+if any, to sign a "copyright disclaimer" for the program, if necessary.
+For more information on this, and how to apply and follow the GNU GPL, see
+.
Index: tags/at_deadline/licence.txt
===================================================================
--- tags/at_deadline/licence.txt (nonexistent)
+++ tags/at_deadline/licence.txt (revision 6)
@@ -0,0 +1 @@
+see gpl.txt :)
Index: tags/at_deadline/fpu_add.vhd
===================================================================
--- tags/at_deadline/fpu_add.vhd (nonexistent)
+++ tags/at_deadline/fpu_add.vhd (revision 6)
@@ -0,0 +1,367 @@
+-------------------------------------------------------------------------------
+-- Project : openFPU64 Add/Sub Component
+-------------------------------------------------------------------------------
+-- File : fpu_add.vhd
+-- Author : Peter Huewe
+-- Created : 2010-04-19
+-- Last update: 2010-04-19
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: double precision floating point adder/subtractor component
+-- for openFPU64, includes rounding and normalization
+--
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010
+-------------------------------------------------------------------------------
+-- License: gplv3, see licence.txt
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.fpu_package.all;
+
+entity fpu_add is
+ port (
+ clk, reset_n : in std_logic; -- reset = standard active low
+ mode : in std_logic; -- mode: 0 = add , 1= sub
+ cs : in std_logic; -- chip select active high
+ -- in operands
+ sign_a, sign_b : in std_logic; -- sign bits
+ exponent_a, exponent_b : in std_logic_vector (11 downto 0); -- exponents of the operands
+ mantissa_a, mantissa_b : in std_logic_vector (57 downto 0); -- mantissa of operands
+-- out result
+ sign_res : out std_logic;
+ exponent_res : out std_logic_vector(11 downto 0);
+ mantissa_res : out std_logic_vector (57 downto 0);
+
+ rounding_needed : out std_logic; -- FUTURE wether rounding is needed or not
+ valid : out std_logic
+ );
+end fpu_add;
+architecture rtl of fpu_add is
+ -- controller part
+
+
+
+ type t_state is (
+ s_reset,
+ s_load_wait,
+ s_a_is_nan,
+ s_b_is_nan,
+ s_swap_a_and_b,
+ s_invalid_operation_inf_minus_inf,
+ s_get_result,
+ s_fix_sub_borrow,
+ s_normalize_right,
+ s_result_is_inf,
+ s_normalize_left,
+ s_prepare_round_ceiling,
+ s_post_normalization,
+ s_finished,
+ s_zero,
+ s_correction_and_round,
+ s_prepare_operation,
+ s_check_result,
+ s_wait_on_normalize_right,
+ s_align_b_to_a
+ );
+ signal state : t_state;
+
+ signal a_s, b_s : std_logic := '0';
+ signal a_e, b_e : unsigned(11 downto 0) := (others => '0');
+ signal a_m, b_m : unsigned(57 downto 0) := (others => '0');
+ signal alu_result, alu_op_a, alu_op_b : unsigned(57 downto 0) := (others => '0');
+ -- Switches adder between Addition and Subtraction, helps to infer 1 big addsub by synthesis tools
+ signal alu_mode : std_logic := '0';
+
+ -- status bits generated automatically
+ signal a_is_a_denormalized_number, a_is_lesser_than_b, a_is_inf_or_nan, a_is_inf : std_logic := '0';
+ signal b_is_unaligned, addition_mode, rounding_case_is_to_ceiling : std_logic := '0';
+ signal b_is_inf, b_is_inf_or_nan, or_signal : std_logic := '0';
+
+
+
+ alias result_is_inf : std_logic is a_is_inf_or_nan; -- result is stored in a
+ alias signs_are_equal : std_logic is addition_mode;
+ alias a_e_all_ones : std_logic is a_is_inf_or_nan; -- if exponent 111...111 then a is either INF or NAN
+ alias b_e_all_ones : std_logic is b_is_inf_or_nan; -- if exponent 111...111 then b is either INF or NAN
+ alias a_e_all_zeros : std_logic is a_is_a_denormalized_number; -- if exponent of a, a is either zero or a denormalized number
+
+begin
+ -- FUTURE
+ rounding_needed <= '0';
+
+
+ -- generate internal status signals
+
+ a_is_a_denormalized_number <= '1' when a_e = ZEROS(10 downto 0) else '0';
+ a_is_inf_or_nan <= '1' when a_e = ONES (10 downto 0) else '0';
+ b_is_inf_or_nan <= '1' when b_e = ONES(10 downto 0) else '0';
+ b_is_inf <= '1' when b_m (54 downto 1) = ZEROS(54 downto 1) else '0'; -- if mantissa is zero and exponent is 11..111 b is inf
+ a_is_inf <= '1' when a_m (54 downto 1) = ZEROS(54 downto 1) else '0'; -- if mantissa is zero and exponent is 11..111 a is inf
+ a_is_lesser_than_b <= '1' when a_e(10 downto 0) < b_e(10 downto 0) else '0'; -- a should be >= b
+ b_is_unaligned <= '1' when a_e /= b_e else '0'; -- exponents of a and b have to be the same before addition
+ addition_mode <= '1' when a_s = b_s else '0';
+
+ -- this line has this meaning
+ -- case a_m (3 downto 0)
+ -- when "1100" => add 1 to a_m(57 downto 3)
+ -- when "1101" => add 1 to a_m(57 downto 3)
+ -- when "1110" => add 1 to a_m(57 downto 3)
+ -- when "1111" => add 1 to a_m(57 downto 3)
+ rounding_case_is_to_ceiling <= '1' when a_m(3 downto 0) = "1100" or (a_m(2) = '1' and (a_m(1) = '1' or a_m(0) = '1')) else '0';
+
+ -- Big ADD/SUB, has to be preloaded for each result
+ alu_result <= alu_op_a+alu_op_b when alu_mode = '1' else alu_op_a-alu_op_b;
+
+ state_trans : process (clk, reset_n) -- clock, reset_n, chipselect
+ begin
+ if reset_n = '0' then
+ a_m <= (others => '0');
+ a_e <= (others => '0');
+ a_s <= '0';
+ b_m <= (others => '0');
+ b_e <= (others => '0');
+ b_s <= '0';
+ valid <= '0';
+
+ sign_res <= '0';
+ exponent_res <= (others => '0');
+ mantissa_res <= (others => '0');
+ alu_op_a <= (others => '0');
+ alu_op_b <= (others => '0');
+ alu_mode <= '0';
+ state <= s_reset; -- reset hat vorrang
+ elsif rising_edge(clk) then
+ if cs = '0' then
+ a_m <= (others => '0');
+ a_e <= (others => '0');
+ a_s <= '0';
+ b_m <= (others => '0');
+ b_e <= (others => '0');
+ b_s <= '0';
+ valid <= '0';
+
+ sign_res <= '0';
+ exponent_res <= (others => '0');
+ mantissa_res <= (others => '0');
+ alu_op_a <= (others => '0');
+ alu_op_b <= (others => '0');
+ alu_mode <= '0';
+ state <= s_reset; -- reset hat vorrang
+ else
+
+ -- keep values
+ a_m <= a_m;
+ a_e <= a_e;
+ a_s <= a_s;
+ b_m <= b_m;
+ b_e <= b_e;
+ b_s <= b_s;
+ valid <= '0';
+ sign_res <= a_s;
+ exponent_res <= std_logic_vector(a_e);
+ mantissa_res <= std_logic_vector(a_m);
+ alu_op_a <= alu_op_a;
+ alu_op_b <= alu_op_b;
+ alu_mode <= alu_mode;
+ state <= state; -- keep state if nothing else specified.
+
+
+ case state is
+ -- reset state, if chipselect is 1 load operands
+ when s_reset =>
+ if cs = '1' then
+ a_s <= sign_a;
+ b_s <= sign_b xor mode; -- "sorts operations"
+ a_m <= unsigned(mantissa_a);
+ b_m <= unsigned(mantissa_b);
+ a_e <= unsigned(exponent_a);
+ b_e <= unsigned(exponent_b);
+
+ state <= s_load_wait;
+ end if;
+
+ -- check operands if they are valid (!= nan), if operation is allowed
+ -- or if operands need to be swapped
+ when s_load_wait =>
+ if a_is_inf_or_nan = '1' and a_is_inf = '0' then state <= s_a_is_nan;
+ elsif b_is_inf_or_nan = '1' and b_is_inf = '0' then state <= s_b_is_nan;
+ --if a and b are infinity and signs are not equal this is an invalid operation
+ elsif a_is_inf_or_nan = '1' and b_is_inf_or_nan = '1' and signs_are_equal = '0' then state <= s_invalid_operation_inf_minus_inf;
+ -- if only a is infinity then nothing is left to be done
+ elsif a_is_inf_or_nan = '1' and a_is_inf = '1' then state <= s_finished;
+ elsif a_is_lesser_than_b = '1' then state <= s_swap_a_and_b;
+ else state <= s_prepare_operation;
+ end if;
+
+ --operand a is NaN, set sign and finish
+ when s_a_is_nan =>
+ a_s <= b_s or mode;
+
+ state <= s_finished;
+
+ --operand b is NaN set result=b and finish
+ when s_b_is_nan =>
+ a_e <= b_e;
+ a_m <= b_m;
+ a_s <= b_s or mode;
+
+ state <= s_finished;
+
+ -- operands a and b have to be swapped
+ when s_swap_a_and_b =>
+ a_s <= b_s;
+ b_s <= a_s;
+ a_e <= b_e;
+ b_e <= a_e;
+ a_m <= b_m;
+ b_m <= a_m;
+
+ state <= s_prepare_operation;
+
+ -- load adder for add/sub
+ -- check if b has to be aligned
+ when s_prepare_operation =>
+ alu_mode <= addition_mode; -- load alu for s_get_result
+ alu_op_a <= a_m;
+ alu_op_b <= b_m;
+
+ if b_is_unaligned = '1' then state <= s_align_b_to_a;
+ else state <= s_get_result;
+ end if;
+
+ -- INF - INF or similar is an invalid operation
+ when s_invalid_operation_inf_minus_inf =>
+ a_m(54) <= '1'; a_s <= '1';
+
+ state <= s_finished;
+
+ -- align b to a so that a_e=b_e
+ when s_align_b_to_a =>
+ alu_mode <= addition_mode; -- load alu for s_get_result
+ alu_op_a <= a_m;
+ alu_op_b <= b_m;
+
+ state <= s_get_result; -- if a_e=b_e or b_m = 0...00x start calculation
+ if b_is_unaligned = '1' then -- otherwise align b to a
+ b_m(56 downto 0) <= '0' & b_m (56 downto 2) & (b_m(1) or b_m(0));
+ alu_op_b <= '0'&'0' & b_m (56 downto 2) & (b_m(1) or b_m(0));
+ b_e <= b_e +1;
+ if b_m(56 downto 1) /= 0 then
+ -- still not alligned
+ state <= s_align_b_to_a;
+ end if;
+ end if;
+
+
+ -- assign calculation result
+ when s_get_result =>
+ b_e <= a_e; -- in case some steps were skipped due to b_m = 0...00x
+ a_m <= alu_result;
+
+ state <= s_check_result;
+
+-- check result:
+-- sub borrow occured?
+ -- normalization needed?
+ -- result is zero?
+ -- result is in?
+ -- rounding needed?
+ when s_check_result =>
+ alu_mode <= '1'; -- load alu for s_fix_sub_borrow
+ alu_op_a <= not(a_m);
+ alu_op_b <= (57 downto 1 => '0')&'1';
+
+ if a_m(57) = '1' then state <= s_fix_sub_borrow;
+ elsif a_m(56) = '1' then state <= s_normalize_right; -- a_m(56)='1' -> normalization to the right is needed
+ elsif result_is_inf = '1' then state <= s_result_is_inf;
+ elsif a_m(55) = '0' and a_is_inf = '1' then state <= s_zero;
+ else state <= s_correction_and_round;
+ end if;
+
+ -- sub borrow occured, fix it by *-1 (adder loaded in previous state)
+ when s_fix_sub_borrow =>
+ a_s <= not a_s;
+ a_m <= alu_result;
+
+ if a_m(56) = '1' then state <= s_normalize_right; -- a_m(56)='1' -> normalization to the right is needed
+ elsif result_is_inf = '1' then state <= s_result_is_inf;
+ elsif a_m(55) = '0' and a_is_inf = '1' then state <= s_zero;
+ else state <= s_correction_and_round;
+ end if;
+
+ -- Normalize right
+ when s_normalize_right =>
+ a_m(56 downto 0) <= '0' & a_m(56 downto 2)& (a_m(0) or a_m(1));
+ a_e <= a_e +1;
+
+ state <= s_wait_on_normalize_right;
+
+ -- check result of Normalization to the right
+ when s_wait_on_normalize_right =>
+ if a_is_inf_or_nan = '1' then state <= s_result_is_inf;
+ else state <= s_correction_and_round;
+ end if;
+
+ -- result is infinity
+ when s_result_is_inf =>
+ a_m <= (others => '0');
+
+ state <= s_finished;
+
+ --
+ when s_correction_and_round =>
+ alu_mode <= '1'; -- load alu for s_prepare_round_ceiling
+ alu_op_a <= a_m;
+ alu_op_b <= (57 downto 4 => '0')&"1000";
+ if a_m(55) = '0' and a_e_all_zeros = '0' then state <= s_normalize_left;
+ elsif rounding_case_is_to_ceiling = '1' then state <= s_prepare_round_ceiling;
+ elsif a_m(56) = '1' then state <= s_post_normalization; -- a_m(56)='1' -> postnormalization is needed
+
+ else state <= s_finished; end if;
+
+ -- shift (possible) leading 1 to correct position
+ when s_normalize_left=>
+ a_m(55 downto 0) <= a_m(54 downto 0) & a_m(0);
+ a_e <= a_e -1;
+ alu_mode <= '1'; -- load alu for s_prepare_round_ceiling
+ alu_op_a <= a_m(57 downto 56) & a_m(54 downto 0) & a_m(0);
+ alu_op_b <= (57 downto 4 => '0')&"1000";
+
+
+ if a_m(54) = '0' and a_e_all_zeros = '0' then state <= s_normalize_left;
+ elsif a_m(2 downto 0) = "110" or (a_m(1) = '1' and a_m(0) = '1') then state <= s_prepare_round_ceiling;
+ elsif a_m(56) = '1' then state <= s_post_normalization; -- a_m(56)='1' -> postnormalization is needed
+ else state <= s_finished; end if;
+
+
+ when s_prepare_round_ceiling =>
+ a_m <= alu_result;
+ if alu_result(56) = '1' then state <= s_post_normalization; -- a_m(56)='1' -> postnormalization is needed
+ else state <= s_finished; end if;
+
+ -- shift leading 1 to correct position
+ when s_post_normalization =>
+ a_m(56 downto 1) <= '0' & a_m(56 downto 2);
+ a_e <= a_e +1;
+ state <= s_finished;
+
+ -- result is zero
+ when s_zero =>
+ a_s <= '0'; -- im add/sub fall bei allen rundungsmodi ausser round to -inf ist dies richtig!
+ a_e <= (others => '0');
+ a_m <= (others => '0');
+
+ state <= s_finished;
+ -- finished
+ when s_finished =>
+ valid <= '1';
+ state <= s_finished; -- done here.
+
+ end case;
+ end if;
+ end if;
+ end process;
+end rtl;
+
Index: tags/at_deadline/openfpu64_tb.tail.vhd
===================================================================
--- tags/at_deadline/openfpu64_tb.tail.vhd (nonexistent)
+++ tags/at_deadline/openfpu64_tb.tail.vhd (revision 6)
@@ -0,0 +1,3 @@
+ wait; --
+ end process;
+end;
Index: tags/at_deadline/openfpu64_hw.tcl
===================================================================
--- tags/at_deadline/openfpu64_hw.tcl (nonexistent)
+++ tags/at_deadline/openfpu64_hw.tcl (revision 6)
@@ -0,0 +1,111 @@
+# TCL File Generated by Component Editor 9.1sp2
+# Mon Apr 19 13:47:02 CEST 2010
+# DO NOT MODIFY
+
+
+# +-----------------------------------
+# |
+# | openfpu64 "openfpu64" v1.9
+# | Peter Huewe 2010.04.19.13:47:02
+# | open source double precision FPU
+# |
+# | /data/hardware/projects/gps410_v2_r3_dpfpu/openfpu64.vhd
+# |
+# | ./fpu_package.vhd syn
+# | ./openfpu64.vhd syn
+# | ./fpu_add.vhd syn
+# | ./fpu_mul.vhd syn
+# |
+# +-----------------------------------
+
+# +-----------------------------------
+# | request TCL package from ACDS 9.1
+# |
+package require -exact sopc 9.1
+# |
+# +-----------------------------------
+
+# +-----------------------------------
+# | module openfpu64
+# |
+set_module_property DESCRIPTION "open source double precision FPU"
+set_module_property NAME openfpu64
+set_module_property VERSION 1.9
+set_module_property INTERNAL false
+set_module_property GROUP ""
+set_module_property AUTHOR "Peter Huewe"
+set_module_property DISPLAY_NAME openfpu64
+set_module_property TOP_LEVEL_HDL_FILE openfpu64.vhd
+set_module_property TOP_LEVEL_HDL_MODULE openfpu64
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property ANALYZE_HDL TRUE
+# |
+# +-----------------------------------
+
+# +-----------------------------------
+# | files
+# |
+add_file fpu_package.vhd SYNTHESIS
+add_file openfpu64.vhd SYNTHESIS
+add_file fpu_add.vhd SYNTHESIS
+add_file fpu_mul.vhd SYNTHESIS
+# |
+# +-----------------------------------
+
+# +-----------------------------------
+# | parameters
+# |
+# |
+# +-----------------------------------
+
+# +-----------------------------------
+# | display items
+# |
+# |
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point clock_reset
+# |
+add_interface clock_reset clock end
+
+set_interface_property clock_reset ENABLED true
+
+add_interface_port clock_reset reset_n reset_n Input 1
+add_interface_port clock_reset clk clk Input 1
+# |
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point avalon_slave_0
+# |
+add_interface avalon_slave_0 avalon end
+set_interface_property avalon_slave_0 addressAlignment DYNAMIC
+set_interface_property avalon_slave_0 associatedClock clock_reset
+set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave_0 explicitAddressSpan 0
+set_interface_property avalon_slave_0 holdTime 0
+set_interface_property avalon_slave_0 isMemoryDevice false
+set_interface_property avalon_slave_0 isNonVolatileStorage false
+set_interface_property avalon_slave_0 linewrapBursts false
+set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
+set_interface_property avalon_slave_0 printableDevice false
+set_interface_property avalon_slave_0 readLatency 0
+set_interface_property avalon_slave_0 readWaitTime 1
+set_interface_property avalon_slave_0 setupTime 0
+set_interface_property avalon_slave_0 timingUnits Cycles
+set_interface_property avalon_slave_0 writeWaitTime 0
+
+set_interface_property avalon_slave_0 ASSOCIATED_CLOCK clock_reset
+set_interface_property avalon_slave_0 ENABLED true
+
+add_interface_port avalon_slave_0 read read Input 1
+add_interface_port avalon_slave_0 write write Input 1
+add_interface_port avalon_slave_0 address address Input 5
+add_interface_port avalon_slave_0 readdata readdata Output 32
+add_interface_port avalon_slave_0 writedata writedata Input 32
+add_interface_port avalon_slave_0 waitrequest waitrequest Output 1
+add_interface_port avalon_slave_0 begintransfer begintransfer Input 1
+# |
+# +-----------------------------------
Index: tags/at_deadline/openfpu64.vhd
===================================================================
--- tags/at_deadline/openfpu64.vhd (nonexistent)
+++ tags/at_deadline/openfpu64.vhd (revision 6)
@@ -0,0 +1,346 @@
+-------------------------------------------------------------------------------
+-- Project : openFPU64 - a double precision FPU (Toplevel Modul for Avalon)
+-------------------------------------------------------------------------------
+-- File : openfpu64.vhd
+-- Author : Peter Huewe
+-- Created : 2010-02-09
+-- Last update: 2010-04-19
+-- Platform : CycloneII, CycloneIII.
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: This module contains the bus logic for the Avalon Interface of
+-- the openFPU64.
+-- the openFPU64 currently features:
+-- - double precision
+-- - Addition/Subtraction
+-- - Multiplication
+-- - rounding (to nearest even)
+-- - subnormals/denormals
+-- - verified against IEEE754
+-- New algorithms can be added easily, just modify the code marked
+-- with ADD_ALGORITHMS_HERE
+-- Everything marked with FUTURE is not yet implemented,
+-- but already added for easier transition.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010
+-------------------------------------------------------------------------------
+-- Licence: gpl v3 - see licence.txt
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.fpu_package.all; -- contains import defines.
+
+-------------------------------------------------------------------------------
+
+entity openFPU64 is
+ port(
+ reset_n : in std_logic := '0'; -- reset, active low
+ read : in std_logic := '0'; -- indicates a read transfer (from fpu)
+ write : in std_logic := '1'; -- indicates a write tranfer (to fpu)
+
+ -- address register, specifies where data comes from or is written to, #
+ -- and also contains the desired operation while writing first operands high word
+ -- see constants in fpu_package for more details
+ address : in std_logic_vector (4 downto 0) := (others => '0');
+
+ --readdata result (FUTURE: and exceptions), transfers hi and low words in 2 cycles
+ readdata : out std_logic_vector(31 downto 0) := (others => '0');
+ writedata : in std_logic_vector(31 downto 0) := (others => '0'); --operands and operator,2 cycles
+
+ -- this signal indicates whether slave is stilly busy. When signal is asserted, bus signals have to remain stable
+ -- CAUTION: Master may initiate a transfer though!
+ waitrequest : out std_logic := '0';
+ begintransfer : in std_logic := '0'; -- Master initiates a new transfer
+ clk : in std_logic := '0' -- clock
+ );
+end openFPU64;
+
+-------------------------------------------------------------------------------
+
+architecture rtl of openFPU64 is
+ -----------------------------------------------------------------------------
+ -- Internal signal declarations
+ -----------------------------------------------------------------------------
+ -- Internal Floating Point format S eEEE EEEE EEEE bOhM....MRGt
+ -- S Sign bit
+ -- e xtra Exponent bit (12)
+ -- E biased exponent (11 downto 0)
+ -- b borrow for Subtraction (57)
+ -- O Overflow (56)
+ -- h Hiddenbit (55)
+ -- M Mantissa bits (54 downto 3)
+ -- R Round bit (2)
+ -- G Guard bit (1)
+ -- t Sticky bit (0)
+
+
+ signal sign_a, sign_b : std_logic; -- signs of first/second operand
+ signal exponent_a, exponent_b : std_logic_vector (11 downto 0); -- exponents of first/second operand
+ signal mantissa_a, mantissa_b : std_logic_vector (57 downto 0); -- mantissas of first/second operand
+ signal iwaitrequest : std_logic; -- internal signal waitrequest, is connected to waitrequest.
+ signal started : std_logic; -- calculation can begin
+ signal rounding_needed_1, rounding_needed_2 : std_logic; -- FUTURE signal which indicates if rounding is necessary.
+
+ signal opmode : std_logic_vector (2 downto 0); -- keeps value of operation.
+ -- The operation is encoded in the address, for better readability we define two aliases to split the
+ -- register address from the desired operation
+ alias operation : std_logic_vector (2 downto 0) is address(4 downto 2); -- desired operation -> fpu_package.vhd
+ alias op_register : std_logic_vector (1 downto 0) is address (1 downto 0); -- register address of operand
+
+
+ -- the next few signals are used for connecting components,
+ -- if you like to add your own algorithm, please specify the necessary signals here,
+ -- and document their usage.
+ -- Notes: Add/Sub are one component, so some signals are shared.
+ -- By using this technique a tristate bus for the components is avoided
+-- ADD_ALGORITHMS_HERE --
+ signal mode_1 : std_logic; -- ADD/SUB, switches between Addition ('0') and Subtraction ('1')
+ signal cs_1, cs_2 : std_logic; -- chip select for each operation
+ signal valid_1, valid_2 : std_logic; -- operation asserts this if it has finished its calculation
+ signal sign_res_1, sign_res_2 : std_logic; -- sign of result for each operation.
+ signal exponent_res_1, exponent_res_2 : std_logic_vector (11 downto 0); -- exponent of result for each operation
+ signal mantissa_res_1, mantissa_res_2 : std_logic_vector(57 downto 0); -- mantissa of result, for each operation
+-- ADD_ALGORITHMS_HERE_END--
+
+
+ -----------------------------------------------------------------------------
+ -- Component declarations
+ -----------------------------------------------------------------------------
+
+ -- Add/Sub component, reset active low
+ component fpu_add
+ port (
+ -- input operands
+ sign_a, sign_b : in std_logic;
+ exponent_a, exponent_b : in std_logic_vector (11 downto 0);
+ mantissa_a, mantissa_b : in std_logic_vector (57 downto 0);
+ -- output result
+ sign_res : out std_logic;
+ exponent_res : out std_logic_vector(11 downto 0);
+ mantissa_res : out std_logic_vector (57 downto 0);
+ -- misc signals
+ rounding_needed : out std_logic; -- FUTURE
+ mode : in std_logic; -- Switch mode Add=0 Sub=1
+ cs : in std_logic; -- Chip Select
+ valid : out std_logic; -- calculation is finished
+ clk : in std_logic; -- Clock
+ reset_n : in std_logic); -- reset active low
+ end component;
+
+ -- Multiplication unit
+ -- FUTURE: can be replaced by other implementations of Multiplication,
+ -- e.g. one that uses only one embedded Multiplier, see fpu_mul_single.vhd
+ -- Interface should remain stable for all implementations
+ component fpu_mul
+ port (
+ -- input operands
+ sign_a, sign_b : in std_logic;
+ exponent_a, exponent_b : in std_logic_vector (11 downto 0);
+ mantissa_a, mantissa_b : in std_logic_vector (57 downto 0);
+ -- output results
+ sign_res : out std_logic;
+ exponent_res : out std_logic_vector(11 downto 0);
+ mantissa_res : out std_logic_vector (57 downto 0);
+-- misc signals
+ rounding_needed : out std_logic; -- FUTURE
+ valid : out std_logic; -- calculation is finished
+ cs : in std_logic; -- Chip Select
+ clk : in std_logic; -- Clock
+ reset_n : in std_logic); -- Reset active low
+ end component;
+
+
+-----------------------------------------------------------------------------
+-- Component instantiations
+-- connect everything
+-----------------------------------------------------------------------------
+begin
+ fpu_addsub_1 : fpu_add
+ port map (
+ sign_a => sign_a,
+ sign_b => sign_b,
+ exponent_a => exponent_a,
+ exponent_b => exponent_b,
+ mantissa_a => mantissa_a,
+ mantissa_b => mantissa_b,
+ sign_res => sign_res_1,
+ exponent_res => exponent_res_1,
+ mantissa_res => mantissa_res_1,
+ rounding_needed => rounding_needed_1,
+ mode => mode_1,
+ cs => cs_1,
+ valid => valid_1,
+ clk => clk,
+ reset_n => reset_n);
+
+ fpu_mul_1 : fpu_mul
+ port map (
+ clk => clk,
+ reset_n => reset_n,
+ cs => cs_2,
+ sign_a => sign_a,
+ sign_b => sign_b,
+ exponent_a => exponent_a,
+ exponent_b => exponent_b,
+ mantissa_a => mantissa_a,
+ mantissa_b => mantissa_b,
+ sign_res => sign_res_2,
+ exponent_res => exponent_res_2,
+ mantissa_res => mantissa_res_2,
+ rounding_needed => rounding_needed_2,
+ valid => valid_2);
+
+-- purpose: Implements the Avalon logic and transfers data from/to submodules
+-- inputs : clk, reset_n,read, write, address, writedata, begintransfer
+-- outputs: readdata, waitrequest
+-- Note: Process is not coded using states on purpose in order to prevent
+-- lockups in case of bus resets or undefined accesses
+ avalon_bus_logic : process (clk, reset_n)
+ begin
+ if reset_n = '0' then -- active low, switch of subcomponents, reset everything
+ cs_1 <= '0';
+ cs_2 <= '0';
+ iwaitrequest <= '0';
+ started <= '0';
+ opmode <= (others => '0');
+ mantissa_a <= (others => '0');
+ mantissa_b <= (others => '0');
+ exponent_a <= (others => '0');
+ exponent_b <= (others => '0');
+ sign_a <= '0';
+ sign_b <= '0';
+ readdata <= x"AAAAC0C0";
+ elsif rising_edge(clk) then
+ waitrequest <= iwaitrequest;
+ cs_1 <= cs_1;
+ cs_2 <= cs_2;
+ opmode <= opmode;
+ mantissa_a <= mantissa_a;
+ mantissa_b <= mantissa_b;
+ exponent_a <= exponent_a;
+ exponent_b <= exponent_b;
+ sign_a <= sign_a;
+ sign_b <= sign_b;
+
+ -- Dummy value which indicates wrong reads, deadbeef was already taken
+ readdata <= x"AAAAC0C0";
+ started <= started;
+
+ if started = '0' -- calculation is in progress, keep signals
+ then
+ iwaitrequest <= '0';
+ else
+ iwaitrequest <= '1';
+ end if;
+
+ if begintransfer = '1' and write = '1' then -- new write transfert
+ case op_register is
+ -- hi word is written, populate first operand and set opmode to desired operation
+ when addr_a_hi =>
+ sign_a <= writedata(31);
+ exponent_a <= '0' & writedata(30 downto 20);
+ -- check for denormals, if not, set _h_idden bit in internal format.
+ if unsigned(writedata(30 downto 20)) = ZEROS(30 downto 20) then
+ mantissa_a(57 downto 35) <= "000" & writedata(19 downto 0);
+ else
+ mantissa_a(57 downto 35) <= "001" & writedata(19 downto 0);
+ end if;
+ opmode <= operation;
+
+ -- lo word is written, populate rest of mantissa with clear RGS
+ when addr_a_lo =>
+ mantissa_a(34 downto 0) <= writedata(31 downto 0) & "000";
+
+ -- hi word of second operand, populate fields
+ when addr_b_hi =>
+ sign_b <= writedata(31);
+ exponent_b <= '0' & writedata(30 downto 20);
+ -- check for denormals, if not, set _h_idden bit in internal format.
+ if unsigned(writedata(30 downto 20)) = ZEROS(30 downto 20) then
+ mantissa_b(57 downto 35) <= "000" & writedata(19 downto 0);
+ else
+ mantissa_b(57 downto 35) <= "001" & writedata(19 downto 0);
+ end if;
+
+
+ -- lo word is written, populate rest of mantissa with clear RGS
+ -- after low word is written, calculation starts
+ when addr_b_lo =>
+ mantissa_b(34 downto 0) <= writedata(31 downto 0) & "000";
+ -- perform calculation by enabling component
+ case opmode is
+ -- ADD_ALGORITHMS_HERE
+ when mode_add =>
+ cs_1 <= '1';
+ mode_1 <= '0';
+ when mode_sub =>
+ cs_1 <= '1';
+ mode_1 <= '1';
+ opmode <= mode_add; -- result will be read from same location
+ when mode_mul =>
+ cs_2 <= '1';
+-- when mode_div => -- FUTURE not implemented yet
+-- cs_3 <= '1'; -- FUTURE
+ -- ADD_ALGORITHMS_HERE_END
+ when others => null;
+ end case;
+ started <= '1'; -- calculation has started
+ when others => null;
+ end case;
+ end if;
+
+ -- results requested
+ if read = '1' and started = '1' then
+ if begintransfer = '1' then
+ iwaitrequest <= '1';
+ waitrequest <= '1';
+ end if;
+ -- ADD_ALGORITHMS_HERE --
+ -- if any of the operation returns with a valid result
+ if valid_1 = '1' or valid_2 = '1' then
+ -- ADD_ALGORITHMS_HERE_END--
+ iwaitrequest <= '1';
+ waitrequest <= '0';
+
+ -- read hi word of result
+ if op_register = addr_result_hi then
+ case opmode is
+ -- ADD_ALGORITHMS_HERE --
+ -- generate result, skip internal format bits.
+ when mode_add => readdata <= sign_res_1 & exponent_res_1 (10 downto 0) & mantissa_res_1(54 downto 35); -- ADD and SUB
+ when mode_mul => readdata <= sign_res_2 & exponent_res_2 (10 downto 0) & mantissa_res_2(54 downto 35);
+ -- when mode_div => readdata <= result_2(63 downto 32); -- not implemented yet
+ -- ADD_ALGORITHMS_HERE_END--
+ when others => null;
+ end case;
+
+ -- read low word of result
+ else -- op_register = add_result_lo
+ case opmode is
+ -- ADD_ALGORITHMS_HERE --
+ when mode_add => readdata <= mantissa_res_1(34 downto 3); -- ADD and SUB
+ when mode_mul => readdata <= mantissa_res_2(34 downto 3);
+ -- when mode_div => readdata <= result_2(31 downto 0); --Not implemented yet
+ -- ADD_ALGORITHMS_HERE_END --
+ when others => null;
+ end case;
+
+ -- read is finished, return to "reset_state"
+ -- ADD_ALGORITHMS_HERE --
+ cs_1 <= '0';
+ cs_2 <= '0';
+ mode_1 <= '0';
+ -- ADD_ALGORITHMS_HERE_END --
+ started <= '0';
+ opmode <= (others => '0');
+ end if;
+ else
+ end if;
+ end if;
+ end if;
+ end process avalon_bus_logic;
+end rtl;
+
+-------------------------------------------------------------------------------
Index: tags/at_deadline/fpu_mul.vhd
===================================================================
--- tags/at_deadline/fpu_mul.vhd (nonexistent)
+++ tags/at_deadline/fpu_mul.vhd (revision 6)
@@ -0,0 +1,281 @@
+--------------------------------------------------------------------------------
+-- Project : openFPU64 Multiplier Component
+-------------------------------------------------------------------------------
+-- File : fpu_mul.vhd
+-- Author : Peter Huewe
+-- Created : 2010-04-19
+-- Last update: 2010-04-19
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: double precision floating point multiplier component
+-- for openFPU64, includes rounding and normalization
+--
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010
+-------------------------------------------------------------------------------
+-- License: gplv3, see licence.txt
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.fpu_package.all;
+-------------------------------------------------------------------------------
+
+entity fpu_mul is
+ port (
+ clk, reset_n : in std_logic; -- reset = standard active low
+ cs : in std_logic; -- mode: 0 = add , 1= sub
+ sign_a, sign_b : in std_logic; -- sign bits
+ exponent_a, exponent_b : in std_logic_vector (11 downto 0); -- exponents of the operands
+ mantissa_a, mantissa_b : in std_logic_vector (57 downto 0); -- mantissa of operands
+ sign_res : out std_logic;
+ exponent_res : out std_logic_vector(11 downto 0);
+ mantissa_res : out std_logic_vector (57 downto 0);
+ rounding_needed : out std_logic;
+ valid : out std_logic
+ );
+
+end fpu_mul;
+
+-------------------------------------------------------------------------------
+
+architecture rtl of fpu_mul is
+ -----------------------------------------------------------------------------
+ -- Internal signal declarations
+ -----------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+ signal add_result, add_op_a : unsigned (54 downto 0);
+ signal add_op_b : unsigned (12 downto 0);
+-- signal mul_result : unsigned(35 downto 0);
+-- signal mul_op_a, mul_op_b : unsigned(17 downto 0);
+ type t_state is (s_calc1, s_calc2, s_calc3, s_finished, s_normalize_right_1, s_load_for_round, s_round, s_load_normalizer_right_2, s_normalize_right_2, s_normalize_left); -- possible states
+ signal state : t_state; -- current state
+
+ signal exponent_out : std_logic_vector(11 downto 0);
+ signal tmp_result : std_logic_vector (57 downto 0);
+ signal tmp_result2 : std_logic_vector (107 downto 0);
+
+ signal a_is_normal, b_is_normal : std_logic;
+-----------------------------------------------------------------------------
+-- Component declarations
+-----------------------------------------------------------------------------
+begin
+----------------------------------------------------------------
+ -- Component instantiations
+ -----------------------------------------------------------------------------
+
+ -- purpose: calculates the result of a multiplication
+ -- type : combinational
+ -- inputs : sign_a, sign_b, exponent_a, exponent_b, mantissa_a, mantissa_b
+ -- outputs: result
+
+ add_result <= add_op_a + add_op_b;
+ a_is_normal <= '0' when unsigned(exponent_a(10 downto 0)) = ALL_ZEROS else '1';
+ b_is_normal <= '0' when unsigned(exponent_b(10 downto 0)) = ALL_ZEROS else '1';
+
+ state_trans : process (clk, reset_n, cs)
+ variable tmp : unsigned(57 downto 0);
+ begin -- process state_trans
+ rounding_needed <= '1';
+ if reset_n = '0' then
+ state <= s_calc1;
+ sign_res <= '0';
+ valid <= '0';
+ exponent_res <= (others => '0');
+ mantissa_res <= (others => '0');
+ tmp_result <= (others => '0');
+ tmp_result2 <= (others => '0');
+ add_op_a <= (others => '0');
+ add_op_b <= (others => '0');
+ elsif rising_edge(clk) then
+ if cs = '0' then
+ state <= s_calc1;
+ sign_res <= '0';
+ valid <= '0';
+ exponent_res <= (others => '0');
+ mantissa_res <= (others => '0');
+ tmp_result <= (others => '0');
+ tmp_result2 <= (others => '0');
+ add_op_a <= (others => '0');
+ add_op_b <= (others => '0');
+
+ else
+ sign_res <= sign_a xor sign_b;
+ valid <= '0';
+ -- result <= (others => '0');
+ exponent_res <= exponent_out(11 downto 0);
+ mantissa_res <= (others => '0');
+ mantissa_res <= tmp_result;
+ tmp_result <= tmp_result;
+ tmp_result2 <= tmp_result2;
+ case state is
+
+ -- calculate new exponent and load multiplier
+ when s_calc1 =>
+ add_op_a <= (others => '0');
+ add_op_b <= (others => '0');
+ add_op_a(10 downto 0) <= unsigned(exponent_a(10 downto 0));
+ add_op_b(10 downto 0) <= unsigned(exponent_b(10 downto 0));
+ tmp_result2 <= std_logic_vector(unsigned(mantissa_a(56 downto 3)) * unsigned(mantissa_b(56 downto 3)));
+
+ state <= s_calc2;
+ -- check if one of the operands is zero
+ if (unsigned(exponent_a (10 downto 0)) = ZEROS(10 downto 0) and unsigned(mantissa_a (56 downto 3)) = ZEROS(56 downto 3))
+ or (unsigned(exponent_b (10 downto 0)) = ZEROS(10 downto 0) and unsigned(mantissa_b (56 downto 3)) = ZEROS(56 downto 3))
+ then
+ exponent_out <= (others => '0');
+ tmp_result <= (others => '0');
+ state <= s_finished;
+ end if;
+
+ -- Nan bu Nan :) is A NotANumber
+ if (unsigned(exponent_a (10 downto 0)) = ONES(10 downto 0) and unsigned(mantissa_a (56 downto 3)) /= ZEROS(56 downto 3))
+ then
+ exponent_out <= (others => '1');
+ tmp_result <= mantissa_a;
+ state <= s_finished;
+ end if;
+ -- is B NotANumber
+ if (unsigned(exponent_b (10 downto 0)) = ONES(10 downto 0) and unsigned(mantissa_b (56 downto 3)) /= ZEROS(56 downto 3))
+ then
+ exponent_out <= (others => '1');
+ tmp_result <= mantissa_b;
+ state <= s_finished;
+ end if;
+
+
+ -- calculate new exponent, part II, subtract bias
+ when s_calc2 =>
+ add_op_a (12 downto 0) <= '0'&add_result(11 downto 0);
+ add_op_b (12 downto 0) <= DOUBLE_BIAS_2COMPLEMENT(12 downto 0);
+
+ state <= s_calc3;
+
+ -- check if new exponent has to be zero, this happens if result is zero or subnormal
+ -- also select upper 57 bits of multiplication and generate stickybit of lower result
+ when s_calc3 =>
+ state <= s_load_for_round;
+ -- if lower bits != zero, sticky bit is 1
+ if (unsigned(tmp_result2(49 downto 0)) /= ZEROS(49 downto 0))
+ then
+ tmp_result <= std_logic_vector(tmp_result2(106 downto 50)) &'1';
+ else
+ tmp_result <= std_logic_vector(tmp_result2(106 downto 50)) &'0';
+ end if;
+
+ -- Is normalization needed?
+ if tmp_result2 (105) = '1' then
+ state <= s_normalize_right_1;
+ end if;
+
+
+ -- check if exponent is out of range
+ -- if it is in preload adder, maybe we need exponent +1 in next state
+ exponent_out <= std_logic_vector(add_result(11 downto 0));
+ add_op_a <= (others => '0');
+ add_op_b <= (others => '0');
+
+ add_op_a(11 downto 0) <= add_result(11 downto 0);
+ add_op_b(0) <= '1';
+ -- overflow
+ if (add_result(12) = '0' and add_result(11) = '1')
+ then
+ exponent_out <= (others => '1');
+ tmp_result <= (others => '0');
+ state <= s_finished;
+ end if;
+ -- lower than subnormal - underflow to zero
+ if (add_result(12) = '1')
+ --and (a_is_normal = '0' or b_is_normal = '0'))
+ or (a_is_normal = '0' and b_is_normal = '0')
+ then
+ exponent_out <= (others => '0');
+ add_op_a <= (others => '0');
+ add_op_b <= (others => '0');
+ add_op_b(0) <= '1';
+ tmp_result <= (others => '0');
+ state <= s_finished;
+ else
+ end if;
+
+
+
+ --Normalization is necessary
+ when s_normalize_right_1=>
+ tmp_result(57 downto 1) <= '0'&tmp_result(57 downto 2);
+ tmp_result(0) <= tmp_result(1) or tmp_result(0);
+ exponent_out <= std_logic_vector(add_result(11 downto 0));
+
+ state <= s_load_for_round;
+
+ -- preload adder with mantissa and 1, maybe we need this for rounding next step
+ when s_load_for_round =>
+ add_op_a <= unsigned(tmp_result(57 downto 3));
+ add_op_b <= (others => '0');
+ add_op_b(0) <= '1';
+ state <= s_normalize_left;
+
+ -- shift leading one to correct position
+ when s_normalize_left=>
+ state <= s_round;
+ if tmp_result(55) = '0' and unsigned(exponent_out(11 downto 0)) /= ZEROS(11 downto 0)
+ then
+ tmp_result(55 downto 0) <= tmp_result(54 downto 0) & tmp_result(0);
+ exponent_out <= std_logic_vector(unsigned(exponent_out) - "1");
+ state <= s_normalize_left;
+ end if;
+
+ --round if necessary
+ when s_round=>
+ case tmp_result(3 downto 0) is
+ when "0101" => tmp_result(3) <= '1';
+ when "0110" => tmp_result(3) <= '1';
+ when "0111" => tmp_result(3) <= '1';
+
+ when "1100" => tmp_result(57 downto 3) <= std_logic_vector(add_result);
+ when "1101" => tmp_result(57 downto 3) <= std_logic_vector(add_result);
+ when "1110" => tmp_result(57 downto 3) <= std_logic_vector(add_result);
+ when "1111" => tmp_result(57 downto 3) <= std_logic_vector(add_result);
+
+ when others => null; -- others remain unchanged
+ end case;
+
+
+ state <= s_load_normalizer_right_2;
+
+
+ -- Check again if Normalization needed, preload adder
+ when s_load_normalizer_right_2=>
+ add_op_a <= (others => '0');
+ add_op_b <= (others => '0');
+ add_op_a(11 downto 0) <= unsigned(exponent_out(11 downto 0));
+ add_op_b(0) <= '1';
+
+ state <= s_finished;
+ if tmp_result(56) = '1' then
+ state <= s_normalize_right_2;
+ end if;
+
+
+ -- .Normalize
+ when s_normalize_right_2=>
+ tmp_result(57 downto 1) <= '0'&tmp_result(57 downto 2);
+ tmp_result(0) <= tmp_result(1) or tmp_result(0);
+ exponent_out <= std_logic_vector(add_result(11 downto 0));
+ state <= s_finished;
+
+
+ -- finished
+ when s_finished =>
+ state <= s_finished;
+ valid <= '1';
+
+ when others => null;
+ end case;
+ end if;
+ end if;
+ end process state_trans;
+end rtl;
+
+-------------------------------------------------------------------------------
Index: tags/at_deadline/openfpu64_tb.head.vhd
===================================================================
--- tags/at_deadline/openfpu64_tb.head.vhd (nonexistent)
+++ tags/at_deadline/openfpu64_tb.head.vhd (revision 6)
@@ -0,0 +1,209 @@
+------------------------------------------------------------------------------
+-- Project : openFPU64 - Testbench for Avalon Bus
+-------------------------------------------------------------------------------
+-- File : openfpu64_tb.vhd
+-- Author : Peter Huewe
+-- Created : 2010-04-19
+-- Last update: 2010-04-19
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: Testbench for openFPU64, Avalon Bus interface.
+--
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010
+-------------------------------------------------------------------------------
+-- License: gplv3, see licence.txt
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.helpers.all;
+use work.fpu_package.all;
+-------------------------------------------------------------------------------
+
+entity openFPU64_tb is
+
+end openFPU64_tb;
+
+-------------------------------------------------------------------------------
+
+architecture openFPU64_tb of openFPU64_tb is
+
+ component openFPU64
+ port (
+ reset_n : in std_logic := '0';
+ read : in std_logic := '0';
+ write : in std_logic := '1';
+ address : in std_logic_vector (4 downto 0) := (others => '0');
+ readdata : out std_logic_vector(31 downto 0) := (others => '0');
+ writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ waitrequest : out std_logic := '0';
+ begintransfer : in std_logic := '0';
+ -- out_port : out std_logic_vector(9 downto 0);
+ clk : in std_logic := '0');
+ end component;
+
+ -- component ports
+ signal reset_n : std_logic := '0';
+ signal read : std_logic := '0';
+ signal write : std_logic := '1';
+ signal address : std_logic_vector (4 downto 0) := (others => '0');
+ signal readdata : std_logic_vector(31 downto 0) := (others => '0');
+ signal writedata : std_logic_vector(31 downto 0) := (others => '0');
+-- signal data_in_a : std_logic_vector(63 downto 0) := x"AFAFAFAFEFEFEFEF";
+-- signal data_in_b : std_logic_vector(63 downto 0) := x"BFBFBFBFCFCFCFCF";
+ signal data_in_a : std_logic_vector(63 downto 0) := "0011111111110000000000000000000000000000000000000000000000000000";
+ signal data_in_b : std_logic_vector(63 downto 0) := "0100000000000000000000000000000000000000000000000000000000000000";
+
+
+ signal data_out : std_logic_vector(63 downto 0);
+ signal readback : std_logic_vector(31 downto 0) := (others => '0');
+ signal waitrequest : std_logic := '0';
+ signal begintransfer : std_logic := '0';
+ signal clk : std_logic := '0';
+ signal out_port : std_logic_vector(9 downto 0);
+ -- clock
+ -- signal Clk : std_logic := '1';
+ constant clk_period : time := 10 ns;
+ constant mem_delay : time := 10 ns;
+begin -- openFPU64_tb
+
+ -- component instantiation
+ DUT : openFPU64
+ port map (
+ reset_n => reset_n,
+ read => read,
+ write => write,
+ address => address,
+ readdata => readdata,
+ writedata => writedata,
+ waitrequest => waitrequest,
+ begintransfer => begintransfer,
+ clk => clk);
+
+ -- clock generation
+
+
+
+ -- waveform generation
+ tb : process
+ procedure run_cycle
+ (
+ count : inout integer -- cycle count for statistical purposes
+ )
+ is
+ begin
+ clk <= '0';
+ wait for clk_period / 2;
+ clk <= '1';
+ wait for clk_period / 2;
+ count := count+1;
+ end procedure;
+
+ procedure testcase
+ (
+ number : in integer; -- Testcase number, will be reported
+ operand_a : in std_logic_vector(63 downto 0); -- first operand
+ operand_b : in std_logic_vector (63 downto 0); -- second operand
+ expected : in std_logic_vector(63 downto 0); -- expected result
+ operation : in std_logic_vector (2 downto 0) -- desired operation
+ )
+ is
+ variable i : integer;
+ variable denormalA_n : std_logic;
+ variable denormalB_n : std_logic;
+ begin
+ i :=0;
+
+
+
+
+ -- reset the fpu
+ begintransfer <= '0';
+ reset_n <= '0';
+ run_cycle(i);
+ reset_n <= '1';
+ run_cycle(i);
+ -- begin transfer of first 32bit (MSB..) of first operand
+ -- and specify operation (encoded in address, see fpu_package.vhd for details
+ write <= '1';
+ begintransfer <= '1';
+ writedata <= operand_a(63 downto 32);
+ address <= operation & addr_a_hi;
+ run_cycle(i);
+ begintransfer <= '0'; --all other signals irrelevant/unstable
+ run_cycle(i);
+
+-- begin transfer of second 32bits (..LSB) of first operand
+ write <= '1';
+ begintransfer <= '1';
+ address <= operation& addr_a_lo;
+ writedata <= operand_a(31 downto 0);
+ run_cycle(i);
+ begintransfer <= '0';
+ run_cycle(i);
+
+ -- begin transfer of first 32bits (MSB..) of second operand
+ write <= '1';
+ address <= operation& addr_b_hi;
+ writedata <= operand_b(63 downto 32);
+ begintransfer <= '1';
+ run_cycle(i);
+ begintransfer <= '0';
+ run_cycle(i);
+
+ -- begin transfer of second 32bits (..LSB) of second operand
+ address <= operation& addr_b_lo;
+ writedata <= operand_b(31 downto 0);
+ begintransfer <= '1';
+ run_cycle(i);
+ begintransfer <= '0';
+ write <= '0';
+ run_cycle(i);
+
+-- begin reading first 32bits of result
+-- blocking read, all signals have to remain stable until waitrequest is deasserted
+ read <= '1';
+ begintransfer <= '1';
+ address <= operation & addr_result_hi;
+ run_cycle(i);
+ begintransfer <= '0';
+ L : while waitrequest = '1' loop
+ run_cycle(i);
+ end loop;
+ data_out(63 downto 32) <= readdata;
+ run_cycle(i);
+
+ -- begin reading second 32bits of result
+ -- blocking read, all signals have to remain stable until waitrequest is deasserted
+ -- in practice waitrequest is already deasserted.
+ read <= '1';
+ begintransfer <= '1';
+ address <= operation & addr_result_lo;
+ run_cycle(i);
+ begintransfer <= '0';
+ K :while waitrequest = '1' loop
+ run_cycle(i);
+ end loop;
+ data_out(31 downto 0) <= readdata;
+ run_cycle(i);
+-- Bus transfers complete
+
+-- compare actual result with expected result
+ assert data_out = expected report "doh "&integer'image(number)&" result was"&
+ " S:"&std_logic'image(data_out(63)) &
+ " E:"&to_string(data_out(62 downto 52)) &
+ " M:"&to_string(data_out(51 downto 0)) &
+ " expected" &
+ " S:"&std_logic'image(expected(63)) &
+ " E:"&to_string(expected(62 downto 52)) &
+ " M:"&to_string(expected(51 downto 0)) severity error;
+-- print out statistics
+ assert false report "Testcases "&integer'image(number)&" needed " &integer'image(i) &" cycles" severity note;
+ end procedure;
+ variable i : integer;
+ begin
Index: tags/at_deadline/Makefile
===================================================================
--- tags/at_deadline/Makefile (nonexistent)
+++ tags/at_deadline/Makefile (revision 6)
@@ -0,0 +1,54 @@
+# Set GHDL in environment
+GHDL=ghdl
+GHDLFLAGS = --workdir=work -Wl,-lm -Wc,-m32 -Wl,-m32 -Wa,--32 --ieee=synopsys -fexplicit
+XST= eis-xst
+GHDLA:=$(GHDL) -a $(GHDLFLAGS)
+GHDLE:=$(GHDL) -e $(GHDLFLAGS)
+#XST= echo
+#prevent make from deleting the .o files
+.PRECIOUS: work/%.o
+all: clean work/eis_helpers.o work/fpu_package.o work/fpu_mul.o work/fpu_add.o work/simple.o openfpu64_tb
+
+ #fpu_avalon_func
+
+showme_%: %
+ ./$< --wave=$<.ghw --stop-time=1ms
+ gtkwave $<.ghw $<.sav
+
+work/%.o: %.vhd
+ $(GHDLA) $<
+
+%_tb: eis_helpers.vhd work/eis_helpers.o %.vhd work/%.o %_tb.vhd work/%_tb.o
+ $(GHDLE) $@
+
+%: %.vhd work/%.o
+ $(GHDLE) $@
+
+addsub_testsuite:
+ cat openfpu64_tb.head.vhd tests/openfpu64_tb.addsub.inc.vhd openfpu64_tb.tail.vhd > openfpu64_tb.vhd
+
+custom_testsuite:
+ cat openfpu64_tb.head.vhd tests/openfpu64_tb.custom.inc.vhd openfpu64_tb.tail.vhd > openfpu64_tb.vhd
+
+add_testsuite:
+ cat openfpu64_tb.head.vhd tests/openfpu64_tb.add.inc.txt openfpu64_tb.tail.vhd > openfpu64_tb.vhd
+
+sub_testsuite:
+ cat openfpu64_tb.head.vhd tests/openfpu64_tb.sub.inc.txt openfpu64_tb.tail.vhd > openfpu64_tb.vhd
+
+mul_testsuite:
+ cat openfpu64_tb.head.vhd tests/openfpu64_tb.mul.inc.txt openfpu64_tb.tail.vhd > openfpu64_tb.vhd
+
+clean:
+ $(GHDL) --clean --workdir=work
+ rm -rfv *.ghw *.cf *.log *.ngc *.ngr *.prj *.xrpt *.ifn *.ise xst_work xlnx_auto_0_xdb implement_viscy viscy.bit
+
+get:
+ export PATH=/data/opt/eis/bin/:/usr/local/Simili31/tcl/bin:/usr/local/bin:/usr/bin:/bin:/opt/bin:/usr/x86_64-pc-linux-gnu/arm-unknown-linux-gnu/gcc-bin/4.1.2:/usr/x86_64-pc-linux-gnu/avr/gcc-bin/3.4.6:/usr/x86_64-pc-linux-gnu/gcc-bin/4.1.2:/opt/sourcenav/bin:/usr/kde/3.5/bin:/usr/qt/3/bin:/usr/x86_64-pc-linux-gnu/gnat-gcc-bin/4.2:/usr/libexec/gnat-gcc/x86_64-pc-linux-gnu/4.2:/usr/games/bin:/opt/vmware/player/bin:/sbin:/home/peter/taihu/eldk/bin:/home/peter/taihu/eldk/usr/bin
+ . /opt/Xilinx/11.1/settings32.sh
+ sh /opt/Xilinx/11.1/settings32.sh
+ export PATH=/data/opt/eis/bin/:/usr/local/Simili31/tcl/bin:/usr/local/bin:/usr/bin:/bin:/opt/bin:/usr/x86_64-pc-linux-gnu/arm-unknown-linux-gnu/gcc-bin/4.1.2:/usr/x86_64-pc-linux-gnu/avr/gcc-bin/3.4.6:/usr/x86_64-pc-linux-gnu/gcc-bin/4.1.2:/opt/sourcenav/bin:/usr/kde/3.5/bin:/usr/qt/3/bin:/usr/x86_64-pc-linux-gnu/gnat-gcc-bin/4.2:/usr/libexec/gnat-gcc/x86_64-pc-linux-gnu/4.2:/usr/games/bin:/opt/vmware/player/bin:/sbin:/home/peter/taihu/eldk/bin:/home/peter/taihu/eldk/usr/bin
+ . /opt/Xilinx/11.1/settings32.sh
+ sh /opt/Xilinx/11.1/settings32.sh
+
+
Index: tags/at_deadline/README
===================================================================
--- tags/at_deadline/README (nonexistent)
+++ tags/at_deadline/README (revision 6)
@@ -0,0 +1,3 @@
+Todo: add some description.
+
+Meanwhile, for questions contact me at peterhuewe@gmx.de and I'm glad to help you out