URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430/trunk/core/rtl
- from Rev 154 to Rev 174
- ↔ Reverse comparison
Rev 154 → Rev 174
/verilog/omsp_execution_unit.v
324,23 → 324,26
//============================================================================= |
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// Detect memory read/write access |
assign mb_en = ((e_state==`E_IRQ_1) & ~inst_irq_rst) | |
((e_state==`E_IRQ_3) & ~inst_irq_rst) | |
((e_state==`E_SRC_RD) & ~inst_as[`IMM]) | |
(e_state==`E_SRC_WR) | |
wire mb_rd_det = ((e_state==`E_SRC_RD) & ~inst_as[`IMM]) | |
((e_state==`E_EXEC) & inst_so[`RETI]) | |
((e_state==`E_DST_RD) & ~inst_type[`INST_SO] |
& ~inst_mov) | |
(e_state==`E_DST_WR); |
& ~inst_mov); |
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wire mb_wr_det = ((e_state==`E_IRQ_1) & ~inst_irq_rst) | |
((e_state==`E_IRQ_3) & ~inst_irq_rst) | |
((e_state==`E_DST_WR) & ~inst_so[`RETI]) | |
(e_state==`E_SRC_WR); |
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wire [1:0] mb_wr_msk = inst_alu[`EXEC_NO_WR] ? 2'b00 : |
~inst_bw ? 2'b11 : |
alu_out_add[0] ? 2'b10 : 2'b01; |
assign mb_wr = ({2{(e_state==`E_IRQ_1)}} | |
{2{(e_state==`E_IRQ_3)}} | |
{2{(e_state==`E_DST_WR)}} | |
{2{(e_state==`E_SRC_WR)}}) & mb_wr_msk; |
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assign mb_en = mb_rd_det | mb_wr_det; |
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assign mb_wr = ({2{mb_wr_det}}) & mb_wr_msk; |
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// Memory address bus |
assign mab = alu_out_add[15:0]; |
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