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URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

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  • This comparison shows the changes necessary to convert path 
    /openmsp430/trunk/core/sim/rtl_sim/src
    from Rev 180 to Rev 186
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  •

Rev 180 → Rev 186

/mpy_basic.s43
629,7 → 629,7
nop
nop
 
/* -------------- RD/WR ACCESS OPERANDS --------------- */
/* -------------- 16-BIT RD/WR ACCESS OPERANDS --------------- */
 
mov #0x1234, &MPY
mov #0x5678, &OP2
691,6 → 691,65
nop
nop
 
/* -------------- 8-BIT RD/WR ACCESS OPERANDS --------------- */
 
mov #0x1234, &MPY
mov &MPY, r10
mov.b #0xab, &MPY
mov &MPY, r11
nop
mov #0x0001, r15
nop
 
mov #0x5678, &MPYS
mov &MPYS, r10
mov.b #0xbc, &MPYS
mov &MPYS, r11
nop
mov #0x0002, r15
nop
 
mov #0x9abc, &MAC
mov &MAC, r10
mov.b #0xde, &MAC
mov &MAC, r11
nop
mov #0x0003, r15
nop
 
mov #0xdef0, &MACS
mov &MACS, r10
mov.b #0xed, &MACS
mov &MACS, r11
nop
mov #0x0004, r15
nop
 
mov #0x4321, &OP2
mov &OP2, r10
mov.b #0xdc, &OP2
mov &OP2, r11
nop
mov #0x0005, r15
nop
 
mov #0x8765, &RESLO
mov &RESLO, r10
mov.b #0xcb, &RESLO
mov &RESLO, r11
nop
mov #0x0006, r15
nop
 
mov #0xcba9, &RESHI
mov &RESHI, r10
mov.b #0xba, &RESHI
mov &RESHI, r11
nop
mov #0x0007, r15
nop
 
 
/* ---------------------- END OF TEST --------------- */
end_of_test:
nop
/mpy_basic.v
252,41 → 252,75
$display("Signed Multiply Accumulate test completed (MACS mode)");
 
 
// RD/WR ACCESS OPERANDS
// 16-BIT RD/WR ACCESS OPERANDS
//--------------------------------------------------------
 
@(r15===16'h0001);
if (r10 !== 16'h1234) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPY (1) =====");
if (r11 !== 16'h1234) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPYS (1) =====");
if (r12 !== 16'h1234) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MAC (1) =====");
if (r13 !== 16'h1234) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MACS (1) =====");
if (r14 !== 16'h5678) tb_error("====== RD/WR ACCESS OPERANDS: OP2 (1) =====");
if (r10 !== 16'h1234) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPY (1) =====");
if (r11 !== 16'h1234) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (1) =====");
if (r12 !== 16'h1234) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MAC (1) =====");
if (r13 !== 16'h1234) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MACS (1) =====");
if (r14 !== 16'h5678) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP2 (1) =====");
 
@(r15===16'h0002);
if (r10 !== 16'h4321) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPY (2) =====");
if (r11 !== 16'h4321) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPYS (2) =====");
if (r12 !== 16'h4321) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MAC (2) =====");
if (r13 !== 16'h4321) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MACS (2) =====");
if (r14 !== 16'h8765) tb_error("====== RD/WR ACCESS OPERANDS: OP2 (2) =====");
if (r10 !== 16'h4321) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPY (2) =====");
if (r11 !== 16'h4321) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (2) =====");
if (r12 !== 16'h4321) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MAC (2) =====");
if (r13 !== 16'h4321) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MACS (2) =====");
if (r14 !== 16'h8765) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP2 (2) =====");
 
@(r15===16'h0003);
if (r10 !== 16'h9ABC) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPY (3) =====");
if (r11 !== 16'h9ABC) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPYS (3) =====");
if (r12 !== 16'h9ABC) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MAC (3) =====");
if (r13 !== 16'h9ABC) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MACS (3) =====");
if (r14 !== 16'hDEF0) tb_error("====== RD/WR ACCESS OPERANDS: OP2 (3) =====");
if (r10 !== 16'h9ABC) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPY (3) =====");
if (r11 !== 16'h9ABC) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (3) =====");
if (r12 !== 16'h9ABC) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MAC (3) =====");
if (r13 !== 16'h9ABC) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MACS (3) =====");
if (r14 !== 16'hDEF0) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP2 (3) =====");
 
@(r15===16'h0004);
if (r10 !== 16'hCBA9) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPY (4) =====");
if (r11 !== 16'hCBA9) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPYS (4) =====");
if (r12 !== 16'hCBA9) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MAC (4) =====");
if (r13 !== 16'hCBA9) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MACS (4) =====");
if (r14 !== 16'h0FED) tb_error("====== RD/WR ACCESS OPERANDS: OP2 (4) =====");
if (r10 !== 16'hCBA9) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPY (4) =====");
if (r11 !== 16'hCBA9) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (4) =====");
if (r12 !== 16'hCBA9) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MAC (4) =====");
if (r13 !== 16'hCBA9) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MACS (4) =====");
if (r14 !== 16'h0FED) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP2 (4) =====");
 
 
$display("RD/WR Access operands test completed");
$display("16-BIT RD/WR Access operands test completed");
 
// 8-BIT RD/WR ACCESS OPERANDS
//--------------------------------------------------------
 
@(r15===16'h0001);
if (r10 !== 16'h1234) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MPY (1) =====");
if (r11 !== 16'h00ab) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MPY (2) =====");
 
@(r15===16'h0002);
if (r10 !== 16'h5678) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (1) =====");
if (r11 !== 16'h00bc) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (2) =====");
 
@(r15===16'h0003);
if (r10 !== 16'h9abc) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MAC (1) =====");
if (r11 !== 16'h00de) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MAC (2) =====");
 
@(r15===16'h0004);
if (r10 !== 16'hdef0) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MACS (1) =====");
if (r11 !== 16'h00ed) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MACS (2) =====");
 
@(r15===16'h0005);
if (r10 !== 16'h4321) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP2 (1) =====");
if (r11 !== 16'h00dc) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP2 (2) =====");
 
@(r15===16'h0006);
if (r10 !== 16'h8765) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: RESLO (1) =====");
if (r11 !== 16'h00cb) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: RESLO (2) =====");
 
@(r15===16'h0007);
if (r10 !== 16'hcba9) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: RESHI (1) =====");
if (r11 !== 16'h00ba) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: RESHI (2) =====");
 
 
$display("8-BIT RD/WR Access operands test completed");
 
 
stimulus_done = 1;
`else
 

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