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  • This comparison shows the changes necessary to convert path 
    /openmsp430/trunk/fpga
    from Rev 179 to Rev 181
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  •

Rev 179 → Rev 181

/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_register_file.v
209,7 → 209,7
wire mclk_r2 = mclk;
`endif
 
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef CPUOFF_EN
wire [15:0] cpuoff_mask = 16'h0010;
`else
/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_sfr.v
299,7 → 299,7
// Pulse capture and synchronization
//-----------------------------------
`ifdef SYNC_NMI
`ifdef ASIC
`ifdef ASIC_CLOCKING
// Glitch free reset for the event capture
reg nmi_capture_rst;
always @(posedge mclk or posedge puc_rst)
351,7 → 351,7
wire nmi_pnd = nmiifg & nmie;
 
// NMI wakeup
`ifdef ASIC
`ifdef ASIC_CLOCKING
wire nmi_wkup;
omsp_and_gate and_nmi_wkup (.y(nmi_wkup), .a(nmi_capture ^ nmi_dly), .b(nmie));
`else
/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_clock_module.v
194,7 → 194,7
wire bcsctl1_wr = BCSCTL1[0] ? reg_hi_wr[BCSCTL1] : reg_lo_wr[BCSCTL1];
wire [7:0] bcsctl1_nxt = BCSCTL1[0] ? per_din[15:8] : per_din[7:0];
 
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef ACLK_DIVIDER
wire [7:0] divax_mask = 8'h30;
`else
225,7 → 225,7
`else
wire [7:0] divmx_mask = 8'h00;
`endif
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef SMCLK_MUX
wire [7:0] sels_mask = 8'h08;
`else
263,7 → 263,7
// 5) DCO_CLK / LFXT_CLK INTERFACES (WAKEUP, ENABLE, ...)
//=============================================================================
 
`ifdef ASIC
`ifdef ASIC_CLOCKING
wire cpuoff_and_mclk_enable;
omsp_and_gate and_cpuoff_mclk_en (.y(cpuoff_and_mclk_enable), .a(cpuoff), .b(mclk_enable));
`endif
376,7 → 376,7
// Note: unlike the original MSP430 specification,
// we allow to switch off the LFXT even
// if it is selected by MCLK or SMCLK.
`ifdef ASIC
`ifdef ASIC_CLOCKING
 
`ifdef OSCOFF_EN
 
526,7 → 526,7
// Synchronize CPU_EN signal to the SMCLK domain
//----------------------------------------------
// Note: the synchronizer is only required if there is a SMCLK_MUX
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef SMCLK_MUX
wire cpu_en_sm_s;
omsp_sync_cell sync_cell_cpu_sm_en (
625,7 → 625,7
 
// ASIC MODE
//----------------------------
`ifdef ASIC
`ifdef ASIC_CLOCKING
 
`ifdef ACLK_DIVIDER
`ifdef LFXT_DOMAIN
758,7 → 758,7
 
// ASIC MODE
//----------------------------
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef SMCLK_MUX
 
// Synchronizers
916,7 → 916,7
// Serial Debug Interface Clock gate
//------------------------------------------------
`ifdef DBG_EN
`ifdef ASIC
`ifdef ASIC_CLOCKING
omsp_clock_gate clock_gate_dbg_clk (
.gclk (dbg_clk),
.clk (mclk),
/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_watchdog.v
176,7 → 176,7
parameter [7:0] WDTNMIES_MASK = 8'h00;
`endif
 
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef WATCHDOG_MUX
parameter [7:0] WDTSSEL_MASK = 8'h04;
`else
229,7 → 229,7
//=============================================================================
// 5) WATCHDOG TIMER (ASIC IMPLEMENTATION)
//=============================================================================
`ifdef ASIC
`ifdef ASIC_CLOCKING
 
// Watchdog clock source selection
//---------------------------------
/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430_defines.v
132,7 → 132,7
`define WATCHDOG
 
 
///-------------------------------------------------------
//-------------------------------------------------------
// Include/Exclude Non-Maskable-Interrupt support
//-------------------------------------------------------
`define NMI
315,6 → 315,20
 
 
//===============================================================
// ASIC CLOCKING
//===============================================================
 
//-------------------------------------------------------
// When uncommented, this define will enable the ASIC
// architectural clock gating as well as the advanced low
// power modes support (most common).
// Comment this out in order to get FPGA-like clocking.
//-------------------------------------------------------
`define ASIC_CLOCKING
 
 
`ifdef ASIC_CLOCKING
//===============================================================
// LFXT CLOCK DOMAIN
//===============================================================
 
437,8 → 451,8
`define OSCOFF_EN
 
 
 
`endif
`endif
 
//==========================================================================//
//==========================================================================//
/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430_undefines.v
263,6 → 263,11
// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
//----------------------------------------------------------------------------
 
// ASIC/FPGA-like clocking
`ifdef ASIC_CLOCKING
`undef ASIC_CLOCKING
`endif
 
// Fine grained clock gating
`ifdef CLOCK_GATING
`undef CLOCK_GATING
/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_register_file.v
209,7 → 209,7
wire mclk_r2 = mclk;
`endif
 
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef CPUOFF_EN
wire [15:0] cpuoff_mask = 16'h0010;
`else
/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sfr.v
299,7 → 299,7
// Pulse capture and synchronization
//-----------------------------------
`ifdef SYNC_NMI
`ifdef ASIC
`ifdef ASIC_CLOCKING
// Glitch free reset for the event capture
reg nmi_capture_rst;
always @(posedge mclk or posedge puc_rst)
351,7 → 351,7
wire nmi_pnd = nmiifg & nmie;
 
// NMI wakeup
`ifdef ASIC
`ifdef ASIC_CLOCKING
wire nmi_wkup;
omsp_and_gate and_nmi_wkup (.y(nmi_wkup), .a(nmi_capture ^ nmi_dly), .b(nmie));
`else
/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_clock_module.v
194,7 → 194,7
wire bcsctl1_wr = BCSCTL1[0] ? reg_hi_wr[BCSCTL1] : reg_lo_wr[BCSCTL1];
wire [7:0] bcsctl1_nxt = BCSCTL1[0] ? per_din[15:8] : per_din[7:0];
 
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef ACLK_DIVIDER
wire [7:0] divax_mask = 8'h30;
`else
225,7 → 225,7
`else
wire [7:0] divmx_mask = 8'h00;
`endif
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef SMCLK_MUX
wire [7:0] sels_mask = 8'h08;
`else
263,7 → 263,7
// 5) DCO_CLK / LFXT_CLK INTERFACES (WAKEUP, ENABLE, ...)
//=============================================================================
 
`ifdef ASIC
`ifdef ASIC_CLOCKING
wire cpuoff_and_mclk_enable;
omsp_and_gate and_cpuoff_mclk_en (.y(cpuoff_and_mclk_enable), .a(cpuoff), .b(mclk_enable));
`endif
376,7 → 376,7
// Note: unlike the original MSP430 specification,
// we allow to switch off the LFXT even
// if it is selected by MCLK or SMCLK.
`ifdef ASIC
`ifdef ASIC_CLOCKING
 
`ifdef OSCOFF_EN
 
526,7 → 526,7
// Synchronize CPU_EN signal to the SMCLK domain
//----------------------------------------------
// Note: the synchronizer is only required if there is a SMCLK_MUX
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef SMCLK_MUX
wire cpu_en_sm_s;
omsp_sync_cell sync_cell_cpu_sm_en (
625,7 → 625,7
 
// ASIC MODE
//----------------------------
`ifdef ASIC
`ifdef ASIC_CLOCKING
 
`ifdef ACLK_DIVIDER
`ifdef LFXT_DOMAIN
758,7 → 758,7
 
// ASIC MODE
//----------------------------
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef SMCLK_MUX
 
// Synchronizers
916,7 → 916,7
// Serial Debug Interface Clock gate
//------------------------------------------------
`ifdef DBG_EN
`ifdef ASIC
`ifdef ASIC_CLOCKING
omsp_clock_gate clock_gate_dbg_clk (
.gclk (dbg_clk),
.clk (mclk),
/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_watchdog.v
176,7 → 176,7
parameter [7:0] WDTNMIES_MASK = 8'h00;
`endif
 
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef WATCHDOG_MUX
parameter [7:0] WDTSSEL_MASK = 8'h04;
`else
229,7 → 229,7
//=============================================================================
// 5) WATCHDOG TIMER (ASIC IMPLEMENTATION)
//=============================================================================
`ifdef ASIC
`ifdef ASIC_CLOCKING
 
// Watchdog clock source selection
//---------------------------------
/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v
132,7 → 132,7
`define WATCHDOG
 
 
///-------------------------------------------------------
//-------------------------------------------------------
// Include/Exclude Non-Maskable-Interrupt support
//-------------------------------------------------------
`define NMI
315,6 → 315,20
 
 
//===============================================================
// ASIC CLOCKING
//===============================================================
 
//-------------------------------------------------------
// When uncommented, this define will enable the ASIC
// architectural clock gating as well as the advanced low
// power modes support (most common).
// Comment this out in order to get FPGA-like clocking.
//-------------------------------------------------------
`define ASIC_CLOCKING
 
 
`ifdef ASIC_CLOCKING
//===============================================================
// LFXT CLOCK DOMAIN
//===============================================================
 
437,8 → 451,8
`define OSCOFF_EN
 
 
 
`endif
`endif
 
//==========================================================================//
//==========================================================================//
/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v
263,6 → 263,11
// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
//----------------------------------------------------------------------------
 
// ASIC/FPGA-like clocking
`ifdef ASIC_CLOCKING
`undef ASIC_CLOCKING
`endif
 
// Fine grained clock gating
`ifdef CLOCK_GATING
`undef CLOCK_GATING
/altera_de1_board/rtl/verilog/openmsp430/omsp_register_file.v
209,7 → 209,7
wire mclk_r2 = mclk;
`endif
 
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef CPUOFF_EN
wire [15:0] cpuoff_mask = 16'h0010;
`else
/altera_de1_board/rtl/verilog/openmsp430/omsp_sfr.v
299,7 → 299,7
// Pulse capture and synchronization
//-----------------------------------
`ifdef SYNC_NMI
`ifdef ASIC
`ifdef ASIC_CLOCKING
// Glitch free reset for the event capture
reg nmi_capture_rst;
always @(posedge mclk or posedge puc_rst)
351,7 → 351,7
wire nmi_pnd = nmiifg & nmie;
 
// NMI wakeup
`ifdef ASIC
`ifdef ASIC_CLOCKING
wire nmi_wkup;
omsp_and_gate and_nmi_wkup (.y(nmi_wkup), .a(nmi_capture ^ nmi_dly), .b(nmie));
`else
/altera_de1_board/rtl/verilog/openmsp430/omsp_clock_module.v
194,7 → 194,7
wire bcsctl1_wr = BCSCTL1[0] ? reg_hi_wr[BCSCTL1] : reg_lo_wr[BCSCTL1];
wire [7:0] bcsctl1_nxt = BCSCTL1[0] ? per_din[15:8] : per_din[7:0];
 
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef ACLK_DIVIDER
wire [7:0] divax_mask = 8'h30;
`else
225,7 → 225,7
`else
wire [7:0] divmx_mask = 8'h00;
`endif
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef SMCLK_MUX
wire [7:0] sels_mask = 8'h08;
`else
263,7 → 263,7
// 5) DCO_CLK / LFXT_CLK INTERFACES (WAKEUP, ENABLE, ...)
//=============================================================================
 
`ifdef ASIC
`ifdef ASIC_CLOCKING
wire cpuoff_and_mclk_enable;
omsp_and_gate and_cpuoff_mclk_en (.y(cpuoff_and_mclk_enable), .a(cpuoff), .b(mclk_enable));
`endif
376,7 → 376,7
// Note: unlike the original MSP430 specification,
// we allow to switch off the LFXT even
// if it is selected by MCLK or SMCLK.
`ifdef ASIC
`ifdef ASIC_CLOCKING
 
`ifdef OSCOFF_EN
 
526,7 → 526,7
// Synchronize CPU_EN signal to the SMCLK domain
//----------------------------------------------
// Note: the synchronizer is only required if there is a SMCLK_MUX
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef SMCLK_MUX
wire cpu_en_sm_s;
omsp_sync_cell sync_cell_cpu_sm_en (
625,7 → 625,7
 
// ASIC MODE
//----------------------------
`ifdef ASIC
`ifdef ASIC_CLOCKING
 
`ifdef ACLK_DIVIDER
`ifdef LFXT_DOMAIN
758,7 → 758,7
 
// ASIC MODE
//----------------------------
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef SMCLK_MUX
 
// Synchronizers
916,7 → 916,7
// Serial Debug Interface Clock gate
//------------------------------------------------
`ifdef DBG_EN
`ifdef ASIC
`ifdef ASIC_CLOCKING
omsp_clock_gate clock_gate_dbg_clk (
.gclk (dbg_clk),
.clk (mclk),
/altera_de1_board/rtl/verilog/openmsp430/omsp_watchdog.v
176,7 → 176,7
parameter [7:0] WDTNMIES_MASK = 8'h00;
`endif
 
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef WATCHDOG_MUX
parameter [7:0] WDTSSEL_MASK = 8'h04;
`else
229,7 → 229,7
//=============================================================================
// 5) WATCHDOG TIMER (ASIC IMPLEMENTATION)
//=============================================================================
`ifdef ASIC
`ifdef ASIC_CLOCKING
 
// Watchdog clock source selection
//---------------------------------
/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v
132,7 → 132,7
`define WATCHDOG
 
 
///-------------------------------------------------------
//-------------------------------------------------------
// Include/Exclude Non-Maskable-Interrupt support
//-------------------------------------------------------
`define NMI
315,6 → 315,20
 
 
//===============================================================
// ASIC CLOCKING
//===============================================================
 
//-------------------------------------------------------
// When uncommented, this define will enable the ASIC
// architectural clock gating as well as the advanced low
// power modes support (most common).
// Comment this out in order to get FPGA-like clocking.
//-------------------------------------------------------
`define ASIC_CLOCKING
 
 
`ifdef ASIC_CLOCKING
//===============================================================
// LFXT CLOCK DOMAIN
//===============================================================
 
437,8 → 451,8
`define OSCOFF_EN
 
 
 
`endif
`endif
 
//==========================================================================//
//==========================================================================//
/altera_de1_board/rtl/verilog/openmsp430/openMSP430_undefines.v
263,6 → 263,11
// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
//----------------------------------------------------------------------------
 
// ASIC/FPGA-like clocking
`ifdef ASIC_CLOCKING
`undef ASIC_CLOCKING
`endif
 
// Fine grained clock gating
`ifdef CLOCK_GATING
`undef CLOCK_GATING
/altera_de1_board/software/bin/mifwrite Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_register_file.v
36,9 → 36,9
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 130 $
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2012-03-01 22:45:40 +0100 (Thu, 01 Mar 2012) $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
209,7 → 209,7
wire mclk_r2 = mclk;
`endif
 
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef CPUOFF_EN
wire [15:0] cpuoff_mask = 16'h0010;
`else
/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sfr.v
37,9 → 37,9
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 154 $
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2012-10-15 22:44:20 +0200 (Mon, 15 Oct 2012) $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
299,7 → 299,7
// Pulse capture and synchronization
//-----------------------------------
`ifdef SYNC_NMI
`ifdef ASIC
`ifdef ASIC_CLOCKING
// Glitch free reset for the event capture
reg nmi_capture_rst;
always @(posedge mclk or posedge puc_rst)
351,7 → 351,7
wire nmi_pnd = nmiifg & nmie;
 
// NMI wakeup
`ifdef ASIC
`ifdef ASIC_CLOCKING
wire nmi_wkup;
omsp_and_gate and_nmi_wkup (.y(nmi_wkup), .a(nmi_capture ^ nmi_dly), .b(nmie));
`else
/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v
194,7 → 194,7
wire bcsctl1_wr = BCSCTL1[0] ? reg_hi_wr[BCSCTL1] : reg_lo_wr[BCSCTL1];
wire [7:0] bcsctl1_nxt = BCSCTL1[0] ? per_din[15:8] : per_din[7:0];
 
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef ACLK_DIVIDER
wire [7:0] divax_mask = 8'h30;
`else
225,7 → 225,7
`else
wire [7:0] divmx_mask = 8'h00;
`endif
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef SMCLK_MUX
wire [7:0] sels_mask = 8'h08;
`else
263,7 → 263,7
// 5) DCO_CLK / LFXT_CLK INTERFACES (WAKEUP, ENABLE, ...)
//=============================================================================
 
`ifdef ASIC
`ifdef ASIC_CLOCKING
wire cpuoff_and_mclk_enable;
omsp_and_gate and_cpuoff_mclk_en (.y(cpuoff_and_mclk_enable), .a(cpuoff), .b(mclk_enable));
`endif
376,7 → 376,7
// Note: unlike the original MSP430 specification,
// we allow to switch off the LFXT even
// if it is selected by MCLK or SMCLK.
`ifdef ASIC
`ifdef ASIC_CLOCKING
 
`ifdef OSCOFF_EN
 
526,7 → 526,7
// Synchronize CPU_EN signal to the SMCLK domain
//----------------------------------------------
// Note: the synchronizer is only required if there is a SMCLK_MUX
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef SMCLK_MUX
wire cpu_en_sm_s;
omsp_sync_cell sync_cell_cpu_sm_en (
625,7 → 625,7
 
// ASIC MODE
//----------------------------
`ifdef ASIC
`ifdef ASIC_CLOCKING
 
`ifdef ACLK_DIVIDER
`ifdef LFXT_DOMAIN
758,7 → 758,7
 
// ASIC MODE
//----------------------------
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef SMCLK_MUX
 
// Synchronizers
916,7 → 916,7
// Serial Debug Interface Clock gate
//------------------------------------------------
`ifdef DBG_EN
`ifdef ASIC
`ifdef ASIC_CLOCKING
omsp_clock_gate clock_gate_dbg_clk (
.gclk (dbg_clk),
.clk (mclk),
/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_watchdog.v
176,7 → 176,7
parameter [7:0] WDTNMIES_MASK = 8'h00;
`endif
 
`ifdef ASIC
`ifdef ASIC_CLOCKING
`ifdef WATCHDOG_MUX
parameter [7:0] WDTSSEL_MASK = 8'h04;
`else
229,7 → 229,7
//=============================================================================
// 5) WATCHDOG TIMER (ASIC IMPLEMENTATION)
//=============================================================================
`ifdef ASIC
`ifdef ASIC_CLOCKING
 
// Watchdog clock source selection
//---------------------------------
/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v
132,7 → 132,7
`define WATCHDOG
 
 
///-------------------------------------------------------
//-------------------------------------------------------
// Include/Exclude Non-Maskable-Interrupt support
//-------------------------------------------------------
`define NMI
315,6 → 315,20
 
 
//===============================================================
// ASIC CLOCKING
//===============================================================
 
//-------------------------------------------------------
// When uncommented, this define will enable the ASIC
// architectural clock gating as well as the advanced low
// power modes support (most common).
// Comment this out in order to get FPGA-like clocking.
//-------------------------------------------------------
`define ASIC_CLOCKING
 
 
`ifdef ASIC_CLOCKING
//===============================================================
// LFXT CLOCK DOMAIN
//===============================================================
 
437,8 → 451,8
`define OSCOFF_EN
 
 
 
`endif
`endif
 
//==========================================================================//
//==========================================================================//
/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_undefines.v
263,6 → 263,11
// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
//----------------------------------------------------------------------------
 
// ASIC/FPGA-like clocking
`ifdef ASIC_CLOCKING
`undef ASIC_CLOCKING
`endif
 
// Fine grained clock gating
`ifdef CLOCK_GATING
`undef CLOCK_GATING

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