OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /openmsp430/trunk/fpga
    from Rev 186 to Rev 188
    Reverse comparison

Rev 186 → Rev 188

/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_dbg_i2c.v
464,3 → 464,8
dbg_dout[7:0];
 
endmodule
 
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_wakeup_cell.v
40,6 → 40,10
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
 
module omsp_wakeup_cell (
 
103,6 → 107,7
 
endmodule // omsp_wakeup_cell
 
 
 
 
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_i2c.v
464,3 → 464,8
dbg_dout[7:0];
 
endmodule
 
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_wakeup_cell.v
40,6 → 40,10
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
 
module omsp_wakeup_cell (
 
103,6 → 107,7
 
endmodule // omsp_wakeup_cell
 
 
 
 
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_i2c.v
464,3 → 464,8
dbg_dout[7:0];
 
endmodule
 
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
/altera_de1_board/rtl/verilog/openmsp430/omsp_wakeup_cell.v
40,6 → 40,10
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
 
module omsp_wakeup_cell (
 
103,6 → 107,7
 
endmodule // omsp_wakeup_cell
 
 
 
 
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_i2c.v
464,3 → 464,8
dbg_dout[7:0];
 
endmodule
 
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_wakeup_cell.v
40,6 → 40,10
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
 
module omsp_wakeup_cell (
 
103,6 → 107,7
 
endmodule // omsp_wakeup_cell
 
 
 
 
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.