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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/or1ksim/cpu
    from Rev 460 to Rev 472
    ↔ Reverse comparison
  •

Rev 460 → Rev 472

/or32/execute.c
806,11 → 806,12
 
if ((physical_pc = peek_into_itlb (cpu_state.iqueue.insn_addr)))
{
disassemble_instr (physical_pc);
disassemble_instr (physical_pc, cpu_state.iqueue.insn_addr,
cpu_state.iqueue.insn);
}
else
{
PRINTF ("INTERNAL SIMULATOR ERROR: no trace available\n");
PRINTF ("Instruction address translation failed: no trace available\n");
}
} /* trace_instr () */
 
/common/abstract.c
1226,8 → 1226,9
This is a simpler form of disassemble_memory for GDB instruction tracing.
 
Output format is symbolic disassembly, one instruction per line. Start each
line with its hex address. At the end print the value of any destination
register, the flag and the number of cycles executed.
line with a flag to indicate supervisor or user mode then its hex address
(physical and/or virtual in that order). At the end print the value of any
destination register, the flag and the number of cycles executed.
 
There are all sorts of ways to trip this up, but they are unlikely. The
validity of a memory area is taken from the address of the start of a line
1234,86 → 1235,95
to be printed, so assumes the following 3 bytes are present. This could be
fooled by ridiculous memory declarations.
 
@param[in] addr Address of the instruction to trace */
@param[in] phyaddr Physical address of the instruction to trace
@param[in] virtaddr Virtual address of the instruction to trace
@param[in] insn The instruction just fetched and possibly executed. */
/*---------------------------------------------------------------------------*/
void
disassemble_instr (oraddr_t addr)
disassemble_instr (oraddr_t phyaddr,
oraddr_t virtaddr,
uint32_t insn)
{
PRINTF ("%" PRIxADDR ": ", addr);
/* Log whether we are supervisor mode */
printf ("%c ",
(SPR_SR_SM == (cpu_state.sprs[SPR_SR] & SPR_SR_SM)) ? 'S' : 'U');
/* The address */
if (runtime.sim.trace_phy)
{
PRINTF ("%" PRIxADDR ": ", phyaddr);
}
 
if (verify_memoryarea (addr))
if (runtime.sim.trace_virt)
{
uint32_t insn = eval_direct32 (addr, 0, 0);
int index = or1ksim_insn_decode (insn);
PRINTF ("%" PRIxADDR ": ", virtaddr);
}
 
PRINTF ("%08" PRIx32 " ", insn);
/* The instruction details */
int index = or1ksim_insn_decode (insn);
 
if (index >= 0)
PRINTF ("%08" PRIx32 " ", insn);
 
if (index >= 0)
{
or1ksim_disassemble_trace_index (insn, index);
PRINTF ("%-24s", or1ksim_disassembled);
 
/* Put either the register assignment, SPR value, or store */
if (-1 != trace_dest_spr)
{
or1ksim_disassemble_trace_index (insn, index);
PRINTF ("%-24s", or1ksim_disassembled);
PRINTF ("SPR[%04x] = %08x", (trace_dest_spr |
evalsim_reg (trace_dest_reg)),
cpu_state.sprs[(trace_dest_spr |
evalsim_reg (trace_dest_reg))]);
 
/* Put either the register assignment, SPR value, or store */
if (-1 != trace_dest_spr)
{
PRINTF ("SPR[%04x] = %08x", (trace_dest_spr |
evalsim_reg (trace_dest_reg)),
cpu_state.sprs[(trace_dest_spr |
evalsim_reg (trace_dest_reg))]);
 
}
else if (-1 != trace_dest_reg)
}
else if (-1 != trace_dest_reg)
{
PRINTF ("r%-2u = %" PRIxREG "", trace_dest_reg,
evalsim_reg (trace_dest_reg));
}
else
{
uorreg_t store_val = 0;
oraddr_t store_addr = 0;
if (0 != trace_store_width)
{
PRINTF ("r%-2u = %" PRIxREG "", trace_dest_reg,
evalsim_reg (trace_dest_reg));
store_val = evalsim_reg (trace_store_val_reg);
store_addr = evalsim_reg (trace_store_addr_reg) +
trace_store_imm;
}
else
 
switch (trace_store_width)
{
uorreg_t store_val = 0;
oraddr_t store_addr = 0;
case 1:
PRINTF ("[%" PRIxADDR "] = %02x ", store_addr,
store_val);
break;
if (0 != trace_store_width)
{
store_val = evalsim_reg (trace_store_val_reg);
store_addr = evalsim_reg (trace_store_addr_reg) +
trace_store_imm;
}
 
switch (trace_store_width)
{
case 1:
PRINTF ("[%" PRIxADDR "] = %02x ", store_addr,
store_val);
break;
case 2:
PRINTF ("[%" PRIxADDR "] = %04x ", store_addr, store_val);
break;
case 2:
PRINTF ("[%" PRIxADDR "] = %04x ", store_addr, store_val);
break;
case 4:
PRINTF ("[%" PRIxADDR "] = %08x", store_addr, store_val);
break;
case 4:
PRINTF ("[%" PRIxADDR "] = %08x", store_addr, store_val);
break;
default:
PRINTF (" ");
break;
}
default:
PRINTF (" ");
break;
}
}
 
/* Print the flag */
PRINTF (" flag: %u\n", cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0);
/* Print the flag */
PRINTF (" flag: %u\n", cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0);
 
}
else
{
PRINTF ("<invalid>\n");
}
}
else
{
/* Not a valid memory area. Print Xs as required */
PRINTF ("XXXXXXXX\n");
PRINTF ("<invalid>\n");
}
} /* disassemble_instr() */
 
/common/abstract.h
148,7 → 148,9
extern void disassemble_memory (oraddr_t from,
oraddr_t to,
int nl);
extern void disassemble_instr (oraddr_t addr);
extern void disassemble_instr (oraddr_t phyaddr,
oraddr_t virtaddr,
uint32_t insn);
extern uint32_t evalsim_mem32 (oraddr_t, oraddr_t);
extern uint16_t evalsim_mem16 (oraddr_t, oraddr_t);
extern uint8_t evalsim_mem8 (oraddr_t, oraddr_t);

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