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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

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  • This comparison shows the changes necessary to convert path
    /openrisc/trunk/or1ksim/cpu
    from Rev 472 to Rev 483
    Reverse comparison

Rev 472 → Rev 483

/or32/insnset.c
546,7 → 546,8
}
INSTRUCTION (l_nop) {
uint32_t k = PARAM0;
switch (k) {
switch (k)
{
case NOP_NOP:
break;
case NOP_EXIT:
568,6 → 569,13
sim_done();
}
break;
case NOP_REPORT:
PRINTF("report(0x%"PRIxREG");\n", evalsim_reg(3));
break;
case NOP_PUTC: /*JPB */
printf( "%c", (char)(evalsim_reg( 3 ) & 0xff));
fflush( stdout );
break;
case NOP_CNT_RESET:
PRINTF("****************** counters reset ******************\n");
PRINTF("cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
575,10 → 583,6
runtime.sim.reset_cycles = runtime.sim.cycles;
runtime.cpu.reset_instructions = runtime.cpu.instructions;
break;
case NOP_PUTC: /*JPB */
printf( "%c", (char)(evalsim_reg( 3 ) & 0xff));
fflush( stdout );
break;
case NOP_GET_TICKS:
cpu_state.reg[11] = runtime.sim.cycles & 0xffffffff;
cpu_state.reg[12] = runtime.sim.cycles >> 32;
592,12 → 596,13
case NOP_TRACE_OFF:
runtime.sim.hush = 1;
break;
case NOP_REPORT:
PRINTF("report(0x%"PRIxREG");\n", evalsim_reg(3));
case NOP_RANDOM:
cpu_state.reg[11] = (unsigned int) (random () & 0xffffffff);
break;
case NOP_OR1KSIM:
cpu_state.reg[11] = 1;
break;
default:
if (k >= NOP_REPORT_FIRST && k <= NOP_REPORT_LAST)
PRINTF("report %" PRIdREG " (0x%"PRIxREG");\n", k - NOP_REPORT_FIRST,
evalsim_reg(3));
break;
}
}
/or1k/spr-defs.h
625,7 → 625,7
#define NOP_GET_PS 0x0007 /* JPB: Get picosecs/cycle */
#define NOP_TRACE_ON 0x0008 /* Turn on tracing */
#define NOP_TRACE_OFF 0x0009 /* Turn off tracing */
#define NOP_REPORT_FIRST 0x0400 /* Report with number */
#define NOP_REPORT_LAST 0x03ff /* Report with number */
#define NOP_RANDOM 0x000a /* Return 4 random bytes */
#define NOP_OR1KSIM 0x000b /* Return non-zero if this is Or1ksim */
 
#endif /* SPR_DEFS__H */

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