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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

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    /openrisc/trunk/or1ksim
    from Rev 112 to Rev 114
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Rev 112 → Rev 114

/cpu/or32/or32.c
332,8 → 332,8
 
{"l.addi", "rD,rA,I", "10 0x7 DDDDD AAAAA IIII IIII IIII IIII",
EF (l_add), OR32_W_FLAG, it_arith},
{"l.addic", "rD,rA,I", "10 0x8 DDDDD AAAAA IIII IIII IIII IIII", EFI,
0, it_arith},
{"l.addic", "rD,rA,I", "10 0x8 DDDDD AAAAA IIII IIII IIII IIII",
EF (l_addc), OR32_W_FLAG, it_arith},
{"l.andi", "rD,rA,K", "10 0x9 DDDDD AAAAA KKKK KKKK KKKK KKKK",
EF (l_and), OR32_W_FLAG, it_arith},
{"l.ori", "rD,rA,K", "10 0xA DDDDD AAAAA KKKK KKKK KKKK KKKK",
/cpu/or32/insnset.c
79,25 → 79,60
INSTRUCTION (l_addc) {
orreg_t temp1, temp2, temp3;
int8_t temp4;
int carry_in = (cpu_state.sprs[SPR_SR] & SPR_SR_CY) == SPR_SR_CY;
 
temp2 = (orreg_t)PARAM2;
temp3 = (orreg_t)PARAM1;
temp1 = temp2 + temp3;
if(cpu_state.sprs[SPR_SR] & SPR_SR_CY)
temp1++;
 
if(carry_in)
{
temp1++; /* Add in the carry bit */
}
 
SET_PARAM0(temp1);
SET_OV_FLAG_FN (temp1);
if (ARITH_SET_FLAG) {
if(!temp1)
cpu_state.sprs[SPR_SR] |= SPR_SR_F;
else
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
}
if ((uorreg_t) temp1 < (uorreg_t) temp2)
cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
 
/* Set overflow if two negative values gave a positive sum, or if two
positive values gave a negative sum. Otherwise clear it. There are no
corner cases with the extra bit carried in (unlike the carry flag - see
below). */
if ((((long int) temp2 < 0) &&
((long int) temp3 < 0) &&
((long int) temp1 >= 0)) ||
(((long int) temp2 >= 0) &&
((long int) temp3 >= 0) &&
((long int) temp1 < 0)))
{
cpu_state.sprs[SPR_SR] |= SPR_SR_OV;
}
else
cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
{
cpu_state.sprs[SPR_SR] &= ~SPR_SR_OV;
}
 
/* Set the carry flag if (as unsigned values) the result is smaller than
either operand (if it smaller than one, it will be smaller than both, so
we need only test one). If there is a carry in, the test should be less
than or equal, to deal with the 0 + 0xffffffff + c = 0 case (which
generates a carry). */
if ((carry_in && ((uorreg_t) temp1 <= (uorreg_t) temp2)) ||
((uorreg_t) temp1 < (uorreg_t) temp2))
{
cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
}
else
{
cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
}
 
/* Trigger a range exception if the overflow flag is set and the SR[OVE] bit
is set. */
if (((cpu_state.sprs[SPR_SR] & SPR_SR_OVE) == SPR_SR_OVE) &&
((cpu_state.sprs[SPR_SR] & SPR_SR_OV) == SPR_SR_OV))
{
except_handle (EXCEPT_RANGE, cpu_state.pc);
}
 
temp4 = temp1;
if (temp4 == temp1)
or1k_mstats.byteadd++;
/NEWS
9,10 → 9,13
 
The following bugs are fixed.
* Bug 1770: l.div does not set carry or give correct exception.
* Bug 1771: l.add* do not correctly set the overflow flag.
* Bug 1776: l.addic is not implemented.
 
The following bugs are either cannot be reproduced or will not be fixed.
 
The following bugs are outstanding
* Bug 1758: Memory controller issues. Workaround in the user guide.
 
 
New in release 0.4.0rc1
/ChangeLog
1,7 → 1,15
2010-06-10 Jeremy Bennett <jeremy.bennett@embecosm.com>
* peripheral/Makefile.am: mc-defines.h added to sources.
* cpu/or32/insnset.c <l_addc>: Updated to handle overflow and
exceptions correctly.
* cpu/or32/or32.c <or32_opcodes>: l.addic enabled.
 
2010-06-09 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Version changed to current date. Removed
enable_ov_flag as option for configuration.
* cpu/or32/insnset.c <l_add>: Updated to handle overflow and
exceptions correctly.
* peripheral/Makefile.am: mc-defines.h added to sources.
 
2010-06-08 Jeremy Bennett <jeremy.bennett@embecosm.com>
/testsuite/test-code-or1k/inst-set-test/is-add-test.S
62,6 → 62,92
 
#include "inst-set-test.h"
 
/* ----------------------------------------------------------------------------
* A macro to carry out a test of addition in registers
*
*
* Arguments
* set_flags: Flags to set in the SR
* clr_flags: Flags to clear in the SR
* opc: The opcode
* op1: First operand value
* op2: Second operand value
* res: Expected result
* str: Output string
* cy: Expected carry flag
* ov: Expected overflow flag
* ------------------------------------------------------------------------- */
#define TEST_ADD(set_flags, clr_flags, opc, op1, op2, res, str, cy, ov) \
l.mfspr r3,r0,SPR_SR ;\
LOAD_CONST (r2, set_flags) /* Set flags */ ;\
l.or r3,r3,r2 ;\
LOAD_CONST (r2, ~clr_flags) /* Clear flags */ ;\
l.and r3,r3,r2 ;\
l.mtspr r0,r3,SPR_SR ;\
;\
LOAD_CONST (r5,op1) /* Load numbers to add */ ;\
LOAD_CONST (r6,op2) ;\
opc r4,r5,r6 ;\
l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\
PUSH (r2) ;\
CHECK_RES (str, r4, res) ;\
POP(r2) /* Retrieve SR */ ;\
PUSH(r2) ;\
LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
CHECK_FLAG ("- carry flag set: ", cy) ;\
;\
POP(r2) /* Retrieve SR */ ;\
PUSH(r2) ;\
LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
CHECK_FLAG ("- overflow flag set: ", ov)
 
/* ----------------------------------------------------------------------------
* A macro to carry out a test of addition with an immediate value
*
*
* Arguments
* set_flags: Flags to set in the SR
* clr_flags: Flags to clear in the SR
* opc: The opcode
* op1: First operand value
* op2: Second operand value (immediate)
* res: Expected result
* str: Output string
* cy: Expected carry flag
* ov: Expected overflow flag
* ------------------------------------------------------------------------- */
#define TEST_ADDI(set_flags, clr_flags, opc, op1, op2, res, str, cy, ov) \
l.mfspr r3,r0,SPR_SR ;\
LOAD_CONST (r2, set_flags) /* Set flags */ ;\
l.or r3,r3,r2 ;\
LOAD_CONST (r2, ~clr_flags) /* Clear flags */ ;\
l.and r3,r3,r2 ;\
l.mtspr r0,r3,SPR_SR ;\
;\
LOAD_CONST (r5,op1) /* Load first number to add */ ;\
opc r4,r5,op2 ;\
l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\
PUSH (r2) ;\
CHECK_RES (str, r4, res) ;\
POP(r2) /* Retrieve SR */ ;\
PUSH(r2) ;\
LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
CHECK_FLAG ("- carry flag set: ", cy) ;\
;\
POP(r2) /* Retrieve SR */ ;\
PUSH(r2) ;\
LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
CHECK_FLAG ("- overflow flag set: ", ov)
 
.section .text
.global _start
_start:
75,269 → 161,434
l.nop
 
/* Add two small positive numbers */
LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) /* Clear flags */
TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
l.add, 1, 2, 3,
"0x00000001 + 0x00000002 = 0x00000003: ",
FALSE, FALSE)
 
/* Check carry in is ignored. */
TEST_ADD (SPR_SR_CY, SPR_SR_OV,
l.add, 1, 2, 3,
"0x00000001 + 0x00000002 = 0x00000003: ",
FALSE, FALSE)
 
/* Add two small negative numbers. Sets the carry flag but not the
overflow flag. */
TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
l.add, 0xffffffff, 0xfffffffe, 0xfffffffd,
"0xffffffff + 0xfffffffe = 0xfffffffd: ",
TRUE, FALSE)
 
/* Add two quite large positive numbers. Should set neither the
overflow nor the carry flag. */
TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
l.add, 0x40000000, 0x3fffffff, 0x7fffffff,
"0x40000000 + 0x3fffffff = 0x7fffffff: ",
FALSE, FALSE)
 
/* Add two large positive numbers. Should set the overflow, but not
the carry flag. */
TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
l.add, 0x40000000, 0x40000000, 0x80000000,
"0x40000000 + 0x40000000 = 0x80000000: ",
FALSE, TRUE)
 
/* Add two quite large negative numbers. Should set the carry, but not
the overflow flag. */
TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
l.add, 0xc0000000, 0xc0000000, 0x80000000,
"0xc0000000 + 0xc0000000 = 0x80000000: ",
TRUE, FALSE)
 
/* Add two large negative numbers. Should set both the overflow and
carry flags. */
TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
l.add, 0xbfffffff, 0xbfffffff, 0x7ffffffe,
"0xbfffffff + 0xbfffffff = 0x7ffffffe: ",
TRUE, TRUE)
 
/* Check that range exceptions are triggered */
l.mfspr r3,r0,SPR_SR
l.and r3,r3,r2
LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */
l.or r3,r3,r2
l.mtspr r0,r3,SPR_SR
LOAD_STR (r3, " ** OVE flag set **\n")
l.jal _puts
l.nop
 
LOAD_CONST (r5,1) /* Add two small positive numbers */
LOAD_CONST (r6,2)
l.add r4,r5,r6
l.mfspr r2,r0,SPR_SR /* So we can examine the carry flag */
PUSH (r2)
CHECK_RES ("0x00000001 + 0x00000002 = 0x00000003: ", r4, 0x00000003)
/* Check that an overflow alone causes a RANGE Exception. */
TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
l.add, 0x40000000, 0x40000000, 0x80000000,
"0x40000000 + 0x40000000 = 0x80000000: ",
FALSE, TRUE)
 
POP(r2) /* Retrieve SR */
PUSH(r2)
LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */
l.and r2,r2,r4
l.sfeq r2,r4
CHECK_FLAG ("- carry flag set: ", FALSE)
/* Check that a carry alone does not cause a RANGE Exception. */
TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
l.add, 0xffffffff, 0xfffffffe, 0xfffffffd,
"0xffffffff + 0xfffffffe = 0xfffffffd: ",
TRUE, FALSE)
 
POP(r2) /* Retrieve SR */
PUSH(r2)
LOAD_CONST (r4, SPR_SR_OV) /* The carry bit */
l.and r2,r2,r4
l.sfeq r2,r4
CHECK_FLAG ("- overflow flag set: ", FALSE)
/* Check that carry and overflow together cause an exception. */
TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
l.add, 0xbfffffff, 0xbfffffff, 0x7ffffffe,
"0xbfffffff + 0xbfffffff = 0x7ffffffe: ",
TRUE, TRUE)
 
/* Add two small negative numbers */
LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) /* Clear flags */
/* Finished checking range exceptions */
l.mfspr r3,r0,SPR_SR
LOAD_CONST (r2, ~SPR_SR_OVE) /* Clear OVE */
l.and r3,r3,r2
l.mtspr r0,r3,SPR_SR
LOAD_STR (r3, " ** OVE flag cleared **\n")
l.jal _puts
l.nop
 
LOAD_CONST (r5,0xffffffff) /* Add two small negative numbers */
LOAD_CONST (r6,0xfffffffe)
l.add r4,r5,r6
l.mfspr r2,r0,SPR_SR /* So we can examine the carry flag */
PUSH (r2)
CHECK_RES ("0xffffffff + 0xfffffffe = 0xfffffffd: ", r4, 0xfffffffd)
/* ----------------------------------------------------------------------------
* Test of add signed and carry, l.addc
* ------------------------------------------------------------------------- */
_addc:
LOAD_STR (r3, "l.addc\n")
l.jal _puts
l.nop
 
POP(r2) /* Retrieve SR */
PUSH(r2)
LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */
l.and r2,r2,r4
l.sfeq r2,r4
CHECK_FLAG ("- carry flag set: ", TRUE)
/* Add two small positive numbers */
TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
l.addc, 1, 2, 3,
"0x00000001 + 0x00000002 = 0x00000003: ",
FALSE, FALSE)
 
POP(r2) /* Retrieve SR */
PUSH(r2)
LOAD_CONST (r4, SPR_SR_OV) /* The carry bit */
l.and r2,r2,r4
l.sfeq r2,r4
CHECK_FLAG ("- overflow flag set: ", FALSE)
/* Add two small negative numbers. Sets the carry flag but not the
overflow flag. */
TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
l.addc, 0xffffffff, 0xfffffffe, 0xfffffffd,
"0xffffffff + 0xfffffffe = 0xfffffffd: ",
TRUE, FALSE)
 
/* Add two quite large positive numbers. Should set neither the
overflow nor the carry flag. */
LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) /* Clear flags */
l.mfspr r3,r0,SPR_SR
l.and r3,r3,r2
l.mtspr r0,r3,SPR_SR
TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
l.addc, 0x40000000, 0x3fffffff, 0x7fffffff,
"0x40000000 + 0x3fffffff = 0x7fffffff: ",
FALSE, FALSE)
 
LOAD_CONST (r5,0x40000000) /* Add two large positive numbers */
LOAD_CONST (r6,0x3fffffff)
l.add r4,r5,r6
l.mfspr r2,r0,SPR_SR /* So we can examine the carry flag */
PUSH (r2)
CHECK_RES ("0x40000000 + 0x3fffffff = 0x7fffffff: ", r4, 0x7fffffff)
/* Add two quite large positive numbers with a carry in. Should set
the overflow but not the carry flag. */
TEST_ADD (SPR_SR_CY, SPR_SR_OV,
l.addc, 0x40000000, 0x3fffffff, 0x80000000,
"0x40000000 + 0x3fffffff + c = 0x80000000: ",
FALSE, TRUE)
 
POP(r2) /* Retrieve SR */
PUSH(r2)
LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */
l.and r2,r2,r4
l.sfeq r2,r4
CHECK_FLAG ("- carry flag set: ", FALSE)
 
POP(r2) /* Retrieve SR */
PUSH(r2)
LOAD_CONST (r4, SPR_SR_OV) /* The carry bit */
l.and r2,r2,r4
l.sfeq r2,r4
CHECK_FLAG ("- overflow flag set: ", FALSE)
 
/* Add two large positive numbers. Should set the overflow, but not
the carry flag. */
LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) /* Clear flags */
l.mfspr r3,r0,SPR_SR
l.and r3,r3,r2
l.mtspr r0,r3,SPR_SR
TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
l.addc, 0x40000000, 0x40000000, 0x80000000,
"0x40000000 + 0x40000000 = 0x80000000: ",
FALSE, TRUE)
 
LOAD_CONST (r5,0x40000000) /* Add two large positive numbers */
LOAD_CONST (r6,0x40000000)
l.add r4,r5,r6
l.mfspr r2,r0,SPR_SR /* So we can examine the carry flag */
PUSH (r2)
CHECK_RES ("0x40000000 + 0x40000000 = 0x80000000: ", r4, 0x80000000)
/* Add the largest unsigned value to zero with a carry. This
potentially can break a simplistic test for carry that does not
consider the carry flag properly. Do it both ways around. */
TEST_ADD (SPR_SR_CY, SPR_SR_OV,
l.addc, 0xffffffff, 0x00000000, 0x00000000,
"0xffffffff + 0x00000000 + c = 0x00000000: ",
TRUE, FALSE)
 
POP(r2) /* Retrieve SR */
PUSH(r2)
LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */
l.and r2,r2,r4
l.sfeq r2,r4
CHECK_FLAG ("- carry flag set: ", FALSE)
TEST_ADD (SPR_SR_CY, SPR_SR_OV,
l.addc, 0x00000000, 0xffffffff, 0x00000000,
"0x00000000 + 0xffffffff + c = 0x00000000: ",
TRUE, FALSE)
 
POP(r2) /* Retrieve SR */
PUSH(r2)
LOAD_CONST (r4, SPR_SR_OV) /* The carry bit */
l.and r2,r2,r4
l.sfeq r2,r4
CHECK_FLAG ("- overflow flag set: ", TRUE)
 
/* Add two quite large negative numbers. Should set the carry, but not
the overflow flag. flag. */
LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) /* Clear flags */
TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
l.addc, 0xc0000000, 0xc0000000, 0x80000000,
"0xc0000000 + 0xc0000000 = 0x80000000: ",
TRUE, FALSE)
 
/* Add two quite large negative numbers that would overflow, with a
carry that just avoids the overflow. Should set the carry, but not
the overflow flag. flag. */
TEST_ADD (SPR_SR_CY, SPR_SR_OV,
l.addc, 0xc0000000, 0xbfffffff, 0x80000000,
"0xc0000000 + 0xbfffffff + c = 0x80000000: ",
TRUE, FALSE)
 
/* Add two large negative numbers. Should set both the overflow and
carry flags. */
TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
l.addc, 0xbfffffff, 0xbfffffff, 0x7ffffffe,
"0xbfffffff + 0xbfffffff = 0x7ffffffe: ",
TRUE, TRUE)
 
/* Check that range exceptions are triggered */
l.mfspr r3,r0,SPR_SR
l.and r3,r3,r2
LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */
l.or r3,r3,r2
l.mtspr r0,r3,SPR_SR
LOAD_STR (r3, " ** OVE flag set **\n")
l.jal _puts
l.nop
 
LOAD_CONST (r5,0xc0000000) /* Add two large positive numbers */
LOAD_CONST (r6,0xc0000000)
l.add r4,r5,r6
l.mfspr r2,r0,SPR_SR /* So we can examine the carry flag */
PUSH (r2)
CHECK_RES ("0xc0000000 + 0xc0000000 = 0x80000000: ", r4, 0x80000000)
/* Check that an overflow alone causes a RANGE Exception, even when it
is the carry that causes the overflow. */
TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
l.addc, 0x40000000, 0x40000000, 0x80000000,
"0x40000000 + 0x40000000 = 0x80000000: ",
FALSE, TRUE)
 
POP(r2) /* Retrieve SR */
PUSH(r2)
LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */
l.and r2,r2,r4
l.sfeq r2,r4
CHECK_FLAG ("- carry flag set: ", TRUE)
TEST_ADD (SPR_SR_CY, SPR_SR_OV,
l.addc, 0x40000000, 0x3fffffff, 0x80000000,
"0x40000000 + 0x3fffffff + c = 0x80000000: ",
FALSE, TRUE)
 
POP(r2) /* Retrieve SR */
PUSH(r2)
LOAD_CONST (r4, SPR_SR_OV) /* The carry bit */
l.and r2,r2,r4
l.sfeq r2,r4
CHECK_FLAG ("- overflow flag set: ", FALSE)
/* Check that a carry alone does not cause a RANGE Exception, even
when it is the carry that causes the overflow. */
TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
l.addc, 0xffffffff, 0xfffffffe, 0xfffffffd,
"0xffffffff + 0xfffffffe = 0xfffffffd: ",
TRUE, FALSE)
 
/* Add two large negative numbers. Should set both the overflow and
carry flags. */
LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) /* Clear flags */
TEST_ADD (SPR_SR_CY, SPR_SR_OV,
l.addc, 0x00000000, 0xffffffff, 0x00000000,
"0x00000000 + 0xffffffff + c = 0x00000000: ",
TRUE, FALSE)
 
/* Check that carry and overflow together cause an exception. */
TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
l.addc, 0xbfffffff, 0xbfffffff, 0x7ffffffe,
"0xbfffffff + 0xbfffffff = 0x7ffffffe: ",
TRUE, TRUE)
 
/* Finished checking range exceptions */
l.mfspr r3,r0,SPR_SR
LOAD_CONST (r2, ~SPR_SR_OVE) /* Clear OVE */
l.and r3,r3,r2
l.mtspr r0,r3,SPR_SR
LOAD_STR (r3, " ** OVE flag cleared **\n")
l.jal _puts
l.nop
 
LOAD_CONST (r5,0xbfffffff) /* Add two large negative numbers */
LOAD_CONST (r6,0xbfffffff)
l.add r4,r5,r6
l.mfspr r2,r0,SPR_SR /* So we can examine the carry flag */
PUSH (r2)
CHECK_RES ("0xbfffffff + 0xbfffffff = 0x7ffffffe: ", r4, 0x7ffffffe)
/* ----------------------------------------------------------------------------
* Test of add signed immediate, l.addi
* ------------------------------------------------------------------------- */
_addi:
LOAD_STR (r3, "l.addi\n")
l.jal _puts
l.nop
 
POP(r2) /* Retrieve SR */
PUSH(r2)
LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */
l.and r2,r2,r4
l.sfeq r2,r4
CHECK_FLAG ("- carry flag set: ", TRUE)
/* Add two small positive numbers */
TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
l.addi, 1, 2, 3,
"0x00000001 + 0x00000002 = 0x00000003: ",
FALSE, FALSE)
 
POP(r2) /* Retrieve SR */
PUSH(r2)
LOAD_CONST (r4, SPR_SR_OV) /* The carry bit */
l.and r2,r2,r4
l.sfeq r2,r4
CHECK_FLAG ("- overflow flag set: ", TRUE)
/* Check carry in is ignored. */
TEST_ADDI (SPR_SR_CY, SPR_SR_OV,
l.addi, 1, 2, 3,
"0x00000001 + 0x00000002 = 0x00000003: ",
FALSE, FALSE)
 
/* Add two small negative numbers. Sets the carry flag but not the
overflow flag. */
TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
l.addi, 0xffffffff, 0xfffe, 0xfffffffd,
"0xffffffff + 0xfffffffe = 0xfffffffd: ",
TRUE, FALSE)
 
/* Add two quite large positive numbers. Should set neither the
overflow nor the carry flag. */
TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
l.addi, 0x7fff8000, 0x7fff, 0x7fffffff,
"0x7fff8000 + 0x00007fff = 0x7fffffff: ",
FALSE, FALSE)
 
/* Add two large positive numbers. Should set the overflow, but not
the carry flag. */
TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
l.addi, 0x7fffc000, 0x4000, 0x80000000,
"0x7fffc000 + 0x00004000 = 0x80000000: ",
FALSE, TRUE)
 
/* Add two quite large negative numbers. Should set the carry, but not
the overflow flag. */
TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
l.addi, 0x80008000, 0x8000, 0x80000000,
"0x80008000 + 0xffff8000 = 0x80000000: ",
TRUE, FALSE)
 
/* Add two large negative numbers. Should set both the overflow and
carry flags. */
TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
l.addi, 0x80007fff, 0x8000, 0x7fffffff,
"0x80007fff + 0xffff8000 = 0x7fffffff: ",
TRUE, TRUE)
 
/* Check that range exceptions are triggered */
l.mfspr r3,r0,SPR_SR
LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */
l.mfspr r3,r0,SPR_SR
l.or r3,r3,r2
l.mtspr r0,r3,SPR_SR
LOAD_STR (r3, " OVE flag set\n")
LOAD_STR (r3, " ** OVE flag set **\n")
l.jal _puts
l.nop
 
/* Check that an overflow alone causes a RANGE Exception. */
LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) /* Clear flags */
TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
l.addi, 0x7fffc000, 0x4000, 0x80000000,
"0x7fffc000 + 0x00004000 = 0x80000000: ",
FALSE, TRUE)
 
/* Check that a carry alone does not cause a RANGE Exception. */
TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
l.addi, 0xffffffff, 0xfffe, 0xfffffffd,
"0xffffffff + 0xfffffffe = 0xfffffffd: ",
TRUE, FALSE)
 
/* Check that carry and overflow together cause an exception. */
TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
l.addi, 0x80007fff, 0x8000, 0x7fffffff,
"0x80007fff + 0xffff8000 = 0x7ffffffe: ",
TRUE, TRUE)
 
/* Finished checking range exceptions */
l.mfspr r3,r0,SPR_SR
LOAD_CONST (r2, ~SPR_SR_OVE) /* Clear OVE */
l.and r3,r3,r2
l.mtspr r0,r3,SPR_SR
LOAD_STR (r3, " ** OVE flag cleared **\n")
l.jal _puts
l.nop
 
LOAD_CONST (r5,0x40000000) /* Add two large positive numbers */
LOAD_CONST (r6,0x40000000)
l.add r4,r5,r6
l.mfspr r2,r0,SPR_SR /* So we can examine the carry flag */
PUSH (r2)
CHECK_RES ("0x40000000 + 0x40000000 = 0x80000000: ", r4, 0x80000000)
/* ----------------------------------------------------------------------------
* Test of add signed and carry, l.addic
* ------------------------------------------------------------------------- */
_addic:
LOAD_STR (r3, "l.addic\n")
l.jal _puts
l.nop
 
POP(r2) /* Retrieve SR */
PUSH(r2)
LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */
l.and r2,r2,r4
l.sfeq r2,r4
CHECK_FLAG ("- carry flag set: ", FALSE)
/* Add two small positive numbers */
TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
l.addic, 1, 2, 3,
"0x00000001 + 0x00000002 = 0x00000003: ",
FALSE, FALSE)
 
POP(r2) /* Retrieve SR */
PUSH(r2)
LOAD_CONST (r4, SPR_SR_OV) /* The carry bit */
l.and r2,r2,r4
l.sfeq r2,r4
CHECK_FLAG ("- overflow flag set: ", TRUE)
/* Add two small negative numbers. Sets the carry flag but not the
overflow flag. */
TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
l.addic, 0xffffffff, 0xfffe, 0xfffffffd,
"0xffffffff + 0xfffffffe = 0xfffffffd: ",
TRUE, FALSE)
 
/* Check that a carry alone does not cause a RANGE Exception. */
LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) /* Clear flags */
l.mfspr r3,r0,SPR_SR
l.and r3,r3,r2
l.mtspr r0,r3,SPR_SR
/* Add two quite large positive numbers. Should set neither the
overflow nor the carry flag. */
TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
l.addic, 0x7fff8000, 0x7fff, 0x7fffffff,
"0x7fff8000 + 0x00007fff = 0x7fffffff: ",
FALSE, FALSE)
 
LOAD_CONST (r5,0xffffffff) /* Add two small negative numbers */
LOAD_CONST (r6,0xfffffffe)
l.add r4,r5,r6
l.mfspr r2,r0,SPR_SR /* So we can examine the carry flag */
PUSH (r2)
CHECK_RES ("0xffffffff + 0xfffffffe = 0xfffffffd: ", r4, 0xfffffffd)
/* Add two quite large positive numbers with a carry in. Should set
the overflow but not the carry flag. */
TEST_ADDI (SPR_SR_CY, SPR_SR_OV,
l.addic, 0x7fff8000, 0x7fff, 0x80000000,
"0x7fff8000 + 0x00007fff + c = 0x80000000: ",
FALSE, TRUE)
 
POP(r2) /* Retrieve SR */
PUSH(r2)
LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */
l.and r2,r2,r4
l.sfeq r2,r4
CHECK_FLAG ("- carry flag set: ", TRUE)
/* Add two large positive numbers. Should set the overflow, but not
the carry flag. */
TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
l.addic, 0x7fffc000, 0x4000, 0x80000000,
"0x7fffc000 + 0x00004000 = 0x80000000: ",
FALSE, TRUE)
 
POP(r2) /* Retrieve SR */
PUSH(r2)
LOAD_CONST (r4, SPR_SR_OV) /* The carry bit */
l.and r2,r2,r4
l.sfeq r2,r4
CHECK_FLAG ("- overflow flag set: ", FALSE)
/* Add the largest unsigned value to zero with a carry. This
potentially can break a simplistic test for carry that does not
consider the carry flag properly. Do it both ways around. */
TEST_ADDI (SPR_SR_CY, SPR_SR_OV,
l.addic, 0xffffffff, 0x0000, 0x00000000,
"0xffffffff + 0x00000000 + c = 0x00000000: ",
TRUE, FALSE)
 
/* Check that carry and overflow together cause an exception. */
LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) /* Clear flags */
TEST_ADDI (SPR_SR_CY, SPR_SR_OV,
l.addic, 0x00000000, 0xffff, 0x00000000,
"0x00000000 + 0xffffffff + c = 0x00000000: ",
TRUE, FALSE)
 
/* Add two quite large negative numbers. Should set the carry, but not
the overflow flag. flag. */
TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
l.addic, 0x80008000, 0x8000, 0x80000000,
"0x80008000 + 0xffff8000 = 0x80000000: ",
TRUE, FALSE)
 
/* Add two quite large negative numbers that would overflow, with a
carry that just avoids the overflow. Should set the carry, but not
the overflow flag. flag. */
TEST_ADDI (SPR_SR_CY, SPR_SR_OV,
l.addic, 0x80007fff, 0x8000, 0x80000000,
"0x80007fff + 0xffff8000 + c = 0x80000000: ",
TRUE, FALSE)
 
/* Add two large negative numbers. Should set both the overflow and
carry flags. */
TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
l.addic, 0x80007fff, 0x8000, 0x7fffffff,
"0x80007fff + 0xffff8000 = 0x7fffffff: ",
TRUE, TRUE)
 
/* Check that range exceptions are triggered */
l.mfspr r3,r0,SPR_SR
l.and r3,r3,r2
LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */
l.or r3,r3,r2
l.mtspr r0,r3,SPR_SR
LOAD_STR (r3, " ** OVE flag set **\n")
l.jal _puts
l.nop
 
LOAD_CONST (r5,0xbfffffff) /* Add two large negative numbers */
LOAD_CONST (r6,0xbfffffff)
l.add r4,r5,r6
l.mfspr r2,r0,SPR_SR /* So we can examine the carry flag */
PUSH (r2)
CHECK_RES ("0xbfffffff + 0xbfffffff = 0x7ffffffe: ", r4, 0x7ffffffe)
/* Check that an overflow alone causes a RANGE Exception, even when it
is the carry that causes the overflow. */
TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
l.addic, 0x7fffc000, 0x4000, 0x80000000,
"0x7fffc000 + 0x00004000 = 0x80000000: ",
FALSE, TRUE)
 
POP(r2) /* Retrieve SR */
PUSH(r2)
LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */
l.and r2,r2,r4
l.sfeq r2,r4
CHECK_FLAG ("- carry flag set: ", TRUE)
TEST_ADDI (SPR_SR_CY, SPR_SR_OV,
l.addic, 0x7fffc000, 0x3fff, 0x80000000,
"0x7fffc000 + 0x00003fff + c = 0x80000000: ",
FALSE, TRUE)
 
POP(r2) /* Retrieve SR */
PUSH(r2)
LOAD_CONST (r4, SPR_SR_OV) /* The carry bit */
l.and r2,r2,r4
l.sfeq r2,r4
CHECK_FLAG ("- overflow flag set: ", TRUE)
/* Check that a carry alone does not cause a RANGE Exception, even
when it is the carry that causes the overflow. */
TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
l.addic, 0xffffffff, 0xfffe, 0xfffffffd,
"0xffffffff + 0xfffffffe = 0xfffffffd: ",
TRUE, FALSE)
 
TEST_ADDI (SPR_SR_CY, SPR_SR_OV,
l.addic, 0x00000000, 0xffff, 0x00000000,
"0x00000000 + 0xffffffff + c = 0x00000000: ",
TRUE, FALSE)
 
/* Check that carry and overflow together cause an exception. */
TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
l.addic, 0x80007fff, 0x8000, 0x7fffffff,
"0x80007fff + 0xffff8000 = 0x7ffffffe: ",
TRUE, TRUE)
 
/* Finished checking range exceptions */
l.mfspr r3,r0,SPR_SR
LOAD_CONST (r2, ~SPR_SR_OVE) /* Clear OVE */
l.mfspr r3,r0,SPR_SR
l.and r3,r3,r2
l.mtspr r0,r3,SPR_SR
LOAD_STR (r3, " OVE flag cleared\n")
LOAD_STR (r3, " ** OVE flag cleared **\n")
l.jal _puts
l.nop
 
/testsuite/test-code-or1k/ChangeLog
1,3 → 1,6
2010-06-10 Jeremy Bennett <jeremy.bennett@embecosm.com>
* inst-set-test/is-add-test.S: Added tests for l.addi and l.addic
 
2010-06-09 Jeremy Bennett <jeremy.bennett@embecosm.com>
* inst-set-test/is-add-test.S: Created.
* inst-set-test/Makefile.am: Updated for new tests
/testsuite/or1ksim.tests/inst-set-test.exp
63,44 → 63,200
"inst-set-test.cfg" "inst-set-test/is-div-test"
 
# Run the l.add, l.addc, l.addi and l.addic tests
run_or1ksim "lws-test" \
[list "!l.add" \
" 0x00000001 + 0x00000002 = 0x00000003: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" 0xffffffff + 0xfffffffe = 0xfffffffd: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" 0x40000000 + 0x3fffffff = 0x7fffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" 0x40000000 + 0x40000000 = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: TRUE" \
" 0xc0000000 + 0xc0000000 = 0x80000000: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" 0xbfffffff + 0xbfffffff = 0x7ffffffe: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: TRUE" \
"! OVE flag set" \
" RANGE exception" \
" - caused by: report(0xe0853000);" \
" - SR value: report(0x00009a01);" \
" 0x40000000 + 0x40000000 = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: TRUE" \
" 0xffffffff + 0xfffffffe = 0xfffffffd: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" RANGE exception" \
" - caused by: report(0xe0853000);" \
" - SR value: report(0x00009e01);" \
" 0xbfffffff + 0xbfffffff = 0x7ffffffe: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: TRUE" \
"! OVE flag cleared" \
"!Test completed" \
"!report(0xdeaddead);" \
"!exit(0)"] \
run_or1ksim "lws-test" \
[list "!l.add" \
" 0x00000001 + 0x00000002 = 0x00000003: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" 0x00000001 + 0x00000002 = 0x00000003: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" 0xffffffff + 0xfffffffe = 0xfffffffd: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" 0x40000000 + 0x3fffffff = 0x7fffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" 0x40000000 + 0x40000000 = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: TRUE" \
" 0xc0000000 + 0xc0000000 = 0x80000000: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" 0xbfffffff + 0xbfffffff = 0x7ffffffe: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: TRUE" \
"! ** OVE flag set **" \
" RANGE exception" \
" - caused by: report(0xe0853000);" \
" - SR value: report(0x00009a01);" \
" 0x40000000 + 0x40000000 = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: TRUE" \
" 0xffffffff + 0xfffffffe = 0xfffffffd: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" RANGE exception" \
" - caused by: report(0xe0853000);" \
" - SR value: report(0x00009e01);" \
" 0xbfffffff + 0xbfffffff = 0x7ffffffe: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: TRUE" \
"! ** OVE flag cleared **" \
"!l.addc" \
" 0x00000001 + 0x00000002 = 0x00000003: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" 0xffffffff + 0xfffffffe = 0xfffffffd: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" 0x40000000 + 0x3fffffff = 0x7fffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" 0x40000000 + 0x3fffffff + c = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: TRUE" \
" 0x40000000 + 0x40000000 = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: TRUE" \
" 0xffffffff + 0x00000000 + c = 0x00000000: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" 0x00000000 + 0xffffffff + c = 0x00000000: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" 0xc0000000 + 0xc0000000 = 0x80000000: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" 0xc0000000 + 0xbfffffff + c = 0x80000000: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" 0xbfffffff + 0xbfffffff = 0x7ffffffe: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: TRUE" \
"! ** OVE flag set **" \
" RANGE exception" \
" - caused by: report(0xe0853001);" \
" - SR value: report(0x00009a01);" \
" 0x40000000 + 0x40000000 = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: TRUE" \
" RANGE exception" \
" - caused by: report(0xe0853001);" \
" - SR value: report(0x00009a01);" \
" 0x40000000 + 0x3fffffff + c = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: TRUE" \
" 0xffffffff + 0xfffffffe = 0xfffffffd: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" 0x00000000 + 0xffffffff + c = 0x00000000: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" RANGE exception" \
" - caused by: report(0xe0853001);" \
" - SR value: report(0x00009e01);" \
" 0xbfffffff + 0xbfffffff = 0x7ffffffe: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: TRUE" \
"! ** OVE flag cleared **" \
"!l.addi" \
" 0x00000001 + 0x00000002 = 0x00000003: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" 0x00000001 + 0x00000002 = 0x00000003: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" 0xffffffff + 0xfffffffe = 0xfffffffd: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" 0x7fff8000 + 0x00007fff = 0x7fffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" 0x7fffc000 + 0x00004000 = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: TRUE" \
" 0x80008000 + 0xffff8000 = 0x80000000: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" 0x80007fff + 0xffff8000 = 0x7fffffff: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: TRUE" \
"! ** OVE flag set **" \
" RANGE exception" \
" - caused by: report(0x9c854000);" \
" - SR value: report(0x00009a01);" \
" 0x7fffc000 + 0x00004000 = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: TRUE" \
" 0xffffffff + 0xfffffffe = 0xfffffffd: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" RANGE exception" \
" - caused by: report(0x9c858000);" \
" - SR value: report(0x00009e01);" \
" 0x80007fff + 0xffff8000 = 0x7ffffffe: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: TRUE" \
"! ** OVE flag cleared **" \
"!l.addic" \
" 0x00000001 + 0x00000002 = 0x00000003: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" 0xffffffff + 0xfffffffe = 0xfffffffd: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" 0x7fff8000 + 0x00007fff = 0x7fffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" 0x7fff8000 + 0x00007fff + c = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: TRUE" \
" 0x7fffc000 + 0x00004000 = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: TRUE" \
" 0xffffffff + 0x00000000 + c = 0x00000000: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" 0x00000000 + 0xffffffff + c = 0x00000000: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" 0x80008000 + 0xffff8000 = 0x80000000: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" 0x80007fff + 0xffff8000 + c = 0x80000000: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" 0x80007fff + 0xffff8000 = 0x7fffffff: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: TRUE" \
"! ** OVE flag set **" \
" RANGE exception" \
" - caused by: report(0xa0854000);" \
" - SR value: report(0x00009a01);" \
" 0x7fffc000 + 0x00004000 = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: TRUE" \
" RANGE exception" \
" - caused by: report(0xa0853fff);" \
" - SR value: report(0x00009a01);" \
" 0x7fffc000 + 0x00003fff + c = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: TRUE" \
" 0xffffffff + 0xfffffffe = 0xfffffffd: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" 0x00000000 + 0xffffffff + c = 0x00000000: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" RANGE exception" \
" - caused by: report(0xa0858000);" \
" - SR value: report(0x00009e01);" \
" 0x80007fff + 0xffff8000 = 0x7ffffffe: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: TRUE" \
"! ** OVE flag cleared **" \
"!Test completed" \
"!report(0xdeaddead);" \
"!exit(0)"] \
"inst-set-test.cfg" "inst-set-test/is-add-test"
/testsuite/ChangeLog
1,3 → 1,6
2010-06-10 Jeremy Bennett <jeremy.bennett@embecosm.com>
* or1ksim.tests/inst-set-test.exp: Extended addition tests.
 
2010-06-09 Jeremy Bennett <jeremy.bennett@embecosm.com>
* or1ksim.tests/inst-set-test.exp: Added division and addition tests.
 
/testsuite/README
12,8 → 12,8
Tests are provided for the standalone simulator (or1ksim) and for the library
(libsim.a).
 
At the time of writing a total of 1,100 tests compile, run and pass. That
figure is broken down into 836 tests of the standalone simulator and 264 tests
At the time of writing a total of 1,247 tests compile, run and pass. That
figure is broken down into 983 tests of the standalone simulator and 264 tests
of the library
 
Configuration and make files are provided for further test programs. These
46,7 → 46,7
Working tests
=============
 
A total of 836 tests of standalone Or1ksim:
A total of 983 tests of standalone Or1ksim:
 
basic: 8 tests of a wide range of instructions and registers.
cache: 5 tests of the Or1ksim cache modeling
66,7 → 66,7
kbdtest: 26 tests of the PS2 keyboard interface.
local-global: 1 test of C local and global variables.
inst-set-test: A collection of tests of individual instructions
is-add-test 33 tests of the l.add* instructions (Bugs)
is-add-test 180 tests of the l.add* instructions (Bugs 1771, 1776)
is-div-test: 4 tests of the l.div and l.divu instruction (Bug 1770).
is-lws-test: 13 tests of the l.lws instruction (Bug 1767).
mem-test: 16 tests of simple memory access.

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