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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

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  • This comparison shows the changes necessary to convert path
    /openrisc/trunk/orpsocv2
    from Rev 807 to Rev 814
    Reverse comparison

Rev 807 → Rev 814

/rtl/verilog/or1200/or1200_cpu.v
90,6 → 90,7
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
parameter boot_adr = `OR1200_BOOT_ADR;
 
//
// I/O ports
413,7 → 414,7
//
// Instantiation of instruction fetch block
//
or1200_genpc or1200_genpc(
or1200_genpc #(.boot_adr(boot_adr)) or1200_genpc(
.clk(clk),
.rst(rst),
.icpu_adr_o(icpu_adr_o),
/rtl/verilog/or1200/or1200_genpc.v
109,11 → 109,11
input genpc_freeze;
input no_more_dslot;
 
parameter boot_adr = `OR1200_BOOT_ADR;
//
// Internal wires and regs
//
reg [31:2] pcreg_default;
wire [31:0] pcreg_boot;
reg pcreg_select;
reg [31:2] pcreg;
reg [31:0] pc;
258,7 → 258,7
always @(posedge clk or `OR1200_RST_EVENT rst)
// default value
if (rst == `OR1200_RST_VALUE) begin
pcreg_default <= `OR1200_BOOT_PCREG_DEFAULT; // jb
pcreg_default <= (boot_adr >>2) - 4;
pcreg_select <= 1'b1;// select async. value due to reset state
end
// selected value (different from default) is written into FF after
278,7 → 278,7
 
// select async. value for pcreg after reset - PC jumps to the address selected
// after boot.
assign pcreg_boot = `OR1200_BOOT_ADR; // changed JB
wire [31:0] pcreg_boot = boot_adr;
 
always @(pcreg_boot or pcreg_default or pcreg_select)
if (pcreg_select)
/rtl/verilog/or1200/or1200_top.v
616,7 → 616,9
//
// Instantiation of Instruction Cache
//
or1200_cpu or1200_cpu(
or1200_cpu
#(.boot_adr(boot_adr))
or1200_cpu(
.clk(clk_i),
.rst(rst_i),
 

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