URL
https://opencores.org/ocsvn/oscilloscope/oscilloscope/trunk
Subversion Repositories oscilloscope
Compare Revisions
- This comparison shows the changes necessary to convert path
/oscilloscope
- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/trunk/main.ucf
0,0 → 1,49
NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; |
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NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; |
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ; |
NET "SPI_MOSI" LOC = T4 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8; |
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NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; |
NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; |
NET "AMP_DOUT" LOC = "E18" | IOSTANDARD = LVCMOS33; |
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NET "DAC_CS" LOC = N8 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8; |
#NET "DAC_CLR" LOC = P8 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8; |
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NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "FPGA_INIT_B" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; |
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NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; |
NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; |
NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; |
NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; |
NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; |
NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; |
NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; |
NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; |
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# ==== Clock inputs (CLK) ==== |
NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ; |
# Define clock period for 50 MHz oscillator (40%/60% duty-cycle) |
NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%; |
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# ==== VGA Port (VGA) ==== |
NET "VGA_BLUE" LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; |
NET "VGA_GREEN" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; |
NET "VGA_HSYNC" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; |
NET "VGA_RED" LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; |
NET "VGA_VSYNC" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; |
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NET "CLK_50MHZ" CLOCK_DEDICATED_ROUTE = FALSE; |
PIN "div2/DCM_SP_inst.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; |
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NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ; |
NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ; |
#NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ; |
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NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ; |
NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ; |
NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ; |
NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ; |