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/trunk/rtl/sel_npc_logic.vhd
0,0 → 1,56
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:33:24 04/25/2012
-- Design Name:
-- Module Name: Concat - Sel_NPC_Logic
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity IFDecoder is
Port ( iSelNPC : in STD_LOGIC;
iBranchResult : in STD_LOGIC;
iAssertBranch : in STD_LOGIC;
oSelMuxNPC : out STD_LOGIC_VECTOR (1 downto 0));
end IFDecoder;
 
architecture Sel_NPC_Logic of IFDecoder is
 
begin
process (iSelNPC,iBranchResult,iAssertBranch)
variable mSel : std_logic_vector(2 downto 0);
begin
mSel := iSelNPC & iBranchResult & iAssertBranch;
oSelMuxNPC <= "00";
case(mSel) is
when "000" =>
oSelMuxNPC <= "00"; -- Not a jump, get PC+1
when "001" | "011" | "101" | "111" =>
oSelMuxNPC <= "11"; -- Jump misstaken
when "010" =>
oSelMuxNPC <= "01"; -- BTB in action: branch taken
when "100" | "110" =>
oSelMuxNPC <= "10"; -- Jump and Link, get RB
when others =>
oSelMuxNPC <= "00"; -- Nothing
end case;
end process;
 
end Sel_NPC_Logic;
 
 
 
 
/trunk/rtl/pc_adder.vhd
0,0 → 1,29
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity pc_adder is
generic (
DATA_WIDTH : integer := 16;
INC_PLUS : integer := 1
);
port (
pc : in std_logic_vector(DATA_WIDTH-1 downto 0);
pc_plus : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
 
end pc_adder;
 
architecture Behavioral of pc_adder is
 
begin
process(pc)
variable pc_aux : std_logic_vector(DATA_WIDTH-1 downto 0) := conv_std_logic_vector(0,DATA_WIDTH); -- verify if it is necessary
begin
pc_aux := pc + INC_PLUS;
pc_plus <= pc_aux;
end process;
end Behavioral;
/trunk/rtl/program_counter.vhd
0,0 → 1,35
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity program_counter is
generic(
DATA_WIDTH : integer := 16
);
port (
current_pc : in std_logic_vector(DATA_WIDTH-1 downto 0);
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
pc : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
 
end program_counter;
 
architecture Behavioral of program_counter is
begin
process(clk,enable)
variable counter : std_logic_vector (DATA_WIDTH-1 downto 0) := conv_std_logic_vector(0,DATA_WIDTH);
begin
pc <= counter;
if(clk='1' and clk'event) then
if(reset = '1') then
counter := conv_std_logic_vector(0,DATA_WIDTH);
else
if(enable = '1') then
counter := current_pc;
end if;
end if;
end if;
end process;
end Behavioral;
/trunk/rtl/common/adder.vhd
0,0 → 1,44
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:48:33 04/18/2012
-- Design Name:
-- Module Name: adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity adder is
Generic (
WIDTH : integer := 16 );
Port (
data_a : in std_logic_vector (WIDTH-1 downto 0);
data_b : in std_logic_vector (WIDTH-1 downto 0);
result : out std_logic_vector (WIDTH-1 downto 0) );
end adder;
 
architecture Macrofunction of adder is
begin
process(data_a, data_b)
variable mAux : std_logic_vector(WIDTH-1 downto 0) := conv_std_logic_vector(0,WIDTH);
begin
mAux := data_a + data_b;
result <= mAux;
end process;
 
end Macrofunction;
 
/trunk/rtl/common/dff.vhd
0,0 → 1,47
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:14:05 05/02/2012
-- Design Name:
-- Module Name: DFF - FlipFlop
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
 
entity dff is
Generic (WIDTH : integer := 16);
Port ( clk : in std_logic;
en : in std_logic;
rst_n : in std_logic;
D : in std_logic_vector (WIDTH-1 downto 0);
Q : out std_logic_vector (WIDTH-1 downto 0));
end dff;
 
architecture FlipFlop of dff is
 
begin
process (clock,reset)
begin
if(reset = '0') then
Q <= (others => '0');
elsif clock'event and clock = '1' then
if(enable = '1') then
Q <= D;
end if;
end if;
end process;
 
end FlipFlop;
 
/trunk/rtl/common/mux2x1.vhd
0,0 → 1,43
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:26:49 04/18/2012
-- Design Name:
-- Module Name: mux2x1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
 
entity mux2x1 is
Generic ( WIDTH : integer := 16 );
Port ( in_a : in std_logic_vector (WIDTH-1 downto 0);
in_b : in std_logic_vector (WIDTH-1 downto 0);
sel : in std_logic_vector (0 downto 0); -- FIXME
dataout : out std_logic_vector (WIDTH-1 downto 0));
end mux2x1;
 
architecture Primitive of mux2x1 is
begin
process(sel, in_a, in_b)
begin
case sel is
when "0" => dataout <= in_a;
when "1" => dataout <= in_b;
when others => dataout <= (others => '0');
end case;
end process;
end Primitive;
 
/trunk/rtl/common/mux3x1.vhd
0,0 → 1,45
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:02:04 04/19/2012
-- Design Name: Multiplexer 3 x 1
-- Module Name: mux3x1 - Multiplex
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
 
entity mux3x1 is
Generic ( WIDTH : integer := 16 );
Port ( in_a : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
in_b : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
in_c : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
dataout : out STD_LOGIC_VECTOR (WIDTH-1 downto 0));
end mux3x1;
 
architecture Multiplex of mux3x1 is
begin
process(sel, in_a, in_b, in_c)
begin
case sel is
when "00" => dataout <= in_a;
when "01" => dataout <= in_b;
when "10" => dataout <= in_c;
when others => dataout <= (others => '0');
end case;
end process;
 
end Multiplex;
 
/trunk/rtl/common/mux4x1.vhd
0,0 → 1,49
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:02:04 04/19/2012
-- Design Name: Multiplexer 3 x 1
-- Module Name: mux4x1 - Multiplex
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
 
entity mux4x1 is
generic (
WIDTH : integer := 16 );
port (
in_a : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
in_b : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
in_c : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
in_d : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
dataout : out STD_LOGIC_VECTOR (WIDTH-1 downto 0) );
end mux4x1;
 
architecture Multiplex of mux4x1 is
begin
process(sel, in_a, in_b, in_c)
begin
case sel is
when "00" => dataout <= in_a;
when "01" => dataout <= in_b;
when "10" => dataout <= in_c;
when "11" => dataout <= in_d;
when others => dataout <= (others => '0');
end case;
end process;
 
end Multiplex;
 
/trunk/rtl/fetch_dff.vhd
0,0 → 1,54
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:18:18 03/06/2012
-- Design Name:
-- Module Name: REG - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
 
entity fetch_dff is
generic (
DATA_WIDTH : integer := 16
);
port (
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
instruct_in : in STD_LOGIC_Vector (DATA_WIDTH-1 downto 0);
instruct_out : out std_logic_vector (DATA_WIDTH-1 downto 0);
mux_in : in STD_LOGIC_Vector (DATA_WIDTH-1 downto 0);
mux_out : out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end fetch_dff;
 
architecture Behavioral of fetch_dff is
begin
process(clk,reset)
begin
if(reset = '1') then
instruct_out <= (others => '0');
elsif (clk ='1' and clk'event) then
if(enable = '1') then
instruct_out <= instruct_in;
mux_out <= mux_in;
end if;
end if;
end process;
 
end Behavioral;
 
/trunk/rtl/instr_fetch.vhd
0,0 → 1,236
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
library work;
use work.ram_package.all;
 
entity instr_fetch is
generic(
DATA_WIDTH : integer := 16
);
port (
--inst_connect_from_host : in std_logic_vector(RAM_addr_width+RAM_data_width+1 downto 0);
--inst_connect_to_host : out std_logic_vector(RAM_data_width downto 0);
clk : IN std_logic;
reset : IN std_logic;
enable : IN std_logic;
enable_pc : IN std_logic;
--FLAG : IN std_logic;
--RESULTADO_ALU : IN std_logic_vector(DATA_WIDTH-1 downto 0);
iRb : IN std_logic_vector(DATA_WIDTH-1 downto 0);
iRdSelect : IN std_logic; -- Jump and link (Select R7)
-- Memory File read control
read_file : IN std_logic;
mux_out : OUT std_logic_vector(DATA_WIDTH-1 downto 0);
instruct_out : OUT std_logic_vector(DATA_WIDTH-1 downto 0);
-- @Pipeline
iJumpAddress : IN std_logic_vector(DATA_WIDTH-1 downto 0); -- Result from ID Adder
iBranchAssert : in std_logic_vector(1 downto 0); -- Branch verification in EXE
iBranchResult : in std_logic; -- From ID
-- Branch Recovering
iBranchAddress : in std_logic_vector(DATA_WIDTH-1 downto 0);
iNPCFromID : in std_logic_vector(DATA_WIDTH-1 downto 0)
-- @end Pipeline
);
end instr_fetch;
 
architecture TopLevel of instr_fetch is
component program_counter is
generic(
DATA_WIDTH : integer := 16
);
port (
current_pc : in std_logic_vector(DATA_WIDTH-1 downto 0);
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
pc : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component;
 
component pc_adder is
generic (
DATA_WIDTH : integer := 16;
INC_PLUS : integer := 1
);
port (
pc : in std_logic_vector(DATA_WIDTH-1 downto 0);
pc_plus : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component;
 
component next_pc_mux is
generic (
DATA_WIDTH : integer := 16
);
port (
pc_pus_one : in std_logic_vector(DATA_WIDTH-1 downto 0);
alu_output : in std_logic_vector(DATA_WIDTH-1 downto 0);
r7_result : in std_logic_vector(DATA_WIDTH-1 downto 0);
flush_npc : in std_logic_vector(DATA_WIDTH-1 downto 0);
select_signal : in std_logic_vector(1 downto 0); -- 0 - FLAG, 1 - iRdselect @ verify vector usage
enable : in std_logic;
next_pc : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component;
 
component fetch_dff is
generic (
DATA_WIDTH : integer := 16
);
port (
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
instruct_in : in STD_LOGIC_Vector (DATA_WIDTH-1 downto 0);
instruct_out : out std_logic_vector (DATA_WIDTH-1 downto 0);
mux_in : in STD_LOGIC_Vector (DATA_WIDTH-1 downto 0);
mux_out : out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end component;
 
--component ram is
-- port(
-- read_file : in std_logic;
-- write_file : in std_logic;
-- WE : in std_logic;
-- clk: in std_logic;
-- ADRESS : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- DATA : in std_logic_vector (DATA_WIDTH-1 downto 0);
-- Q : out std_logic_vector (DATA_WIDTH-1 downto 0)
-- );
--
--end component;
 
component inst_ram is
port (
--inst_connect_from_host : in std_logic_vector(RAM_addr_width+RAM_data_width+1 downto 0);
--inst_connect_to_host : out std_logic_vector(RAM_data_width downto 0);
clk : in std_logic;
rst : in std_logic;
we : in std_logic;
addr : in std_logic_vector(RAM_addr_width-1 downto 0);
datain : in std_logic_vector(RAM_data_width-1 downto 0);
dataout : out std_logic_vector(RAM_data_width-1 downto 0)
);
end component;
 
-- @Pipeline
component IFDecoder
Port ( iSelNPC : in std_logic;
iBranchResult : in std_logic;
iAssertBranch : in std_logic;
oSelMuxNPC : out std_logic_vector (1 downto 0));
end component;
component mux2x1
Generic (WIDTH : integer := 16);
Port ( iDataA : in std_logic_vector (WIDTH-1 downto 0);
iDataB : in std_logic_vector (WIDTH-1 downto 0);
iSelect : in std_logic_vector (0 downto 0);
oData : out std_logic_vector (WIDTH-1 downto 0));
end component;
 
signal PC, PC_1, mem_out, new_pc :std_logic_vector( DATA_WIDTH-1 downto 0);
--@Pipeline
signal sel_mux_npc : std_logic_vector(1 downto 0);
signal mFlushNPC : std_logic_vector(DATA_WIDTH-1 downto 0);
signal test : std_logic_vector(0 downto 0);
--Synthetise
signal maddress : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
inst_program_counter : program_counter
port map (
c urren t_pc => new_pc,
clk => clk,
reset => reset,
enable => enable_pc,
pc => PC
);
inst_pc_adder : pc_adder
port map (
pc_plus => PC_1,
pc => PC
);
inst_mux1 : mux1 port map(
PC_1 => PC_1,
--selectsignal => iRdselect & FLAG,
selectsignal => sel_mux_npc,
enable => enable_pc,
--RESULTADO_ALU => RESULTADO_ALU,
R7Result => iR,
SA IDA => new_pc,
--@Pipeline
--TODO: Generalizar este mux
RESULTADO_ALU => iJumpAddress,
iFlushNPC => mFlushNPC
);
maddress <= "000000" & PC(9 downto 0);
-- inst_ram : ram port map(
-- clk => clk,
-- WE => '0',
-- write_file => '0',
-- read_file => read_file,
-- DATA => "0000000000000000",
-- adress => maddress,
-- Q => mem_out
-- );
 
instr_mem : inst_ram
port map (
--inst_connect_from_host => inst_connect_from_host,
--inst_connect_to_host => inst_connect_to_host,
clk => clk,
rst => reset,
we => '0',
addr => PC(9 downto 0),
datain => (others => '0'),
dataout => mem_out
);
 
inst_fetch_dff : fetch_dff
port map (
clk => clk,
enable => enable,
instruct_out => instruct_out,
mux_out => mux_out,
instruct_in => mem_out,
mu x_in => new_pc,
--@Pipeline
reset => iBranchAssert(0)
);
 
--@Pipeline
MuxDecoder : IFDecoder
port map (
iSelNPC => iRdSelect,
iBranchResult => iBranchResult,
iAssertBranch => iBranchAssert(1),
oSelMuxNPC => sel_mux_npc
);
test <= conv_std_logic_vector(iBranchAssert(1),1);
MuxBranchRecover : mux2x1
generic map (WIDTH => 16)
port map (
iDataA => iNPCFromID,
iDataB => iBranchAddress,
iSelect => test,
oData => mFlushNPC
);
 
end TopLevel;
 
/trunk/rtl/next_pc_mux.vhd
0,0 → 1,41
library ieee;
use ieee.std_logic_1164.all;
 
entity next_pc_mux is
generic (
DATA_WIDTH : integer := 16
);
port (
pc_pus_one : in std_logic_vector(DATA_WIDTH-1 downto 0);
alu_output : in std_logic_vector(DATA_WIDTH-1 downto 0);
r7_result : in std_logic_vector(DATA_WIDTH-1 downto 0);
flush_npc : in std_logic_vector(DATA_WIDTH-1 downto 0);
select_signal : in std_logic_vector(1 downto 0); -- 0 - FLAG, 1 - iRdselect @ verify vector usage
enable : in std_logic;
next_pc : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
 
end next_pc_mux;
 
architecture Behavioral of next_pc_mux is
begin
 
process(enable,selectsignal,alu_output,pc_pus_one,flush_npc,r7_result)
begin
if(enable = '1') then
case select_signal is
when "00" =>
next_pc <= pc_pus_one;
when "01" =>
next_pc <= alu_output;
when "10" =>
next_pc <= r7_result;
when "11" =>
next_pc <= flush_npc;
when others =>
null;
end case;
end if;
end process;
end Behavioral;
/trunk/rtl/packages/flags.vhd
0,0 → 1,18
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
package Flags is
constant equals : std_logic_vector (3 downto 0) := "0001";
constant above : std_logic_vector (3 downto 0) := "0010";
constant overflow : std_logic_vector (3 downto 0) := "0100";
constant error : std_logic_vector (3 downto 0) := "1000";
end Flags;
/trunk/rtl/packages/opcodes.vhd
0,0 → 1,40
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
package Operations is
constant add: std_logic_vector (4 downto 0) := "00000";
constant addinc: std_logic_vector (4 downto 0) := "00001";
constant inca: std_logic_vector (4 downto 0) := "00011";
constant subdec: std_logic_vector (4 downto 0) := "00100";
constant sub: std_logic_vector (4 downto 0) := "00101";
constant deca: std_logic_vector (4 downto 0) := "00110";
constant lsl: std_logic_vector (4 downto 0) := "01000"; -- Left shift logic
constant asr: std_logic_vector (4 downto 0) := "01001"; -- Aritmetic shift right
constant zeros: std_logic_vector (4 downto 0) := "10000";
constant land: std_logic_vector (4 downto 0) := "10001"; -- Logic and
constant andnota: std_logic_vector (4 downto 0) := "10010";
constant passb: std_logic_vector (4 downto 0) := "10011";
constant andnotb: std_logic_vector (4 downto 0) := "10100";
constant passa: std_logic_vector (4 downto 0) := "10101";
constant lxor: std_logic_vector (4 downto 0) := "10110"; -- Logic XOR
constant lor: std_logic_vector (4 downto 0) := "10111"; -- Logic OR
constant lnor: std_logic_vector (4 downto 0) := "11000"; -- Logic NOR
constant lxnor: std_logic_vector (4 downto 0) := "11001"; -- Logic XOR
constant passnota: std_logic_vector (4 downto 0) := "11010";
constant ornota: std_logic_vector (4 downto 0) := "11011";
constant passnotb: std_logic_vector (4 downto 0) := "11100";
constant ornotb: std_logic_vector (4 downto 0) := "11101";
constant lnand: std_logic_vector (4 downto 0) := "11110"; -- Logic NAND
constant ones: std_logic_vector (4 downto 0) := "11111";
constant lcl: std_logic_vector (4 downto 0) := "00010"; -- Load constant low
constant lch: std_logic_vector (4 downto 0) := "00111"; -- Load constant high
end Operations;

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