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  • This comparison shows the changes necessary to convert path 
    /ourisc
    from Rev 10 to Rev 11
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Rev 10 → Rev 11

/trunk/rtl/common/adder.vhd
1,20 → 1,16
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:48:33 04/18/2012
-- Design Name:
-- Module Name: adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Engineer: Joao Carlos Nunes Bittencourt
----------------------------------------------------------------------------------
-- Create Date: 13:18:18 03/06/2012
----------------------------------------------------------------------------------
-- Design Name: Adder Macrofunction
-- Module Name: adder - behavioral
----------------------------------------------------------------------------------
-- Project Name: 16-bit uRISC Processor
----------------------------------------------------------------------------------
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 1.0 - File Created
-- 2.0 - Project refactoring
--
----------------------------------------------------------------------------------
library ieee;
26,19 → 22,19
Generic (
WIDTH : integer := 16 );
Port (
data_a : in std_logic_vector (WIDTH-1 downto 0);
data_b : in std_logic_vector (WIDTH-1 downto 0);
result : out std_logic_vector (WIDTH-1 downto 0) );
sink_a : in std_logic_vector (WIDTH-1 downto 0);
sink_b : in std_logic_vector (WIDTH-1 downto 0);
src_data : out std_logic_vector (WIDTH-1 downto 0) );
end adder;
 
architecture Macrofunction of adder is
architecture behavioral of adder is
begin
process(data_a, data_b)
variable mAux : std_logic_vector(WIDTH-1 downto 0) := conv_std_logic_vector(0,WIDTH);
process(sink_a, sink_b)
variable aux : std_logic_vector(WIDTH-1 downto 0) := conv_std_logic_vector(0,WIDTH);
begin
mAux := data_a + data_b;
result <= mAux;
aux := sink_a + sink_b;
src_data <= aux;
end process;
 
end Macrofunction;
end behavioral;
 
/trunk/rtl/common/dff.vhd
1,20 → 1,16
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:14:05 05/02/2012
-- Design Name:
-- Module Name: DFF - FlipFlop
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Engineer: Joao Carlos Nunes Bittencourt
----------------------------------------------------------------------------------
-- Create Date: 13:18:18 03/06/2012
----------------------------------------------------------------------------------
-- Design Name: D-Flip-flop
-- Module Name: dff - behavioral
----------------------------------------------------------------------------------
-- Project Name: 16-bit uRISC Processor
----------------------------------------------------------------------------------
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 1.0 - File Created
-- 2.0 - Project refactoring
--
----------------------------------------------------------------------------------
library ieee;
21,27 → 17,28
use ieee.std_logic_1164.all;
 
entity dff is
Generic (WIDTH : integer := 16);
Port ( clk : in std_logic;
en : in std_logic;
rst_n : in std_logic;
D : in std_logic_vector (WIDTH-1 downto 0);
Q : out std_logic_vector (WIDTH-1 downto 0));
generic( WIDTH : integer := 16 );
port ( clk : in std_logic;
enable : in std_logic;
rst_n : in std_logic;
sink_d : in std_logic_vector (WIDTH-1 downto 0);
src_q : out std_logic_vector (WIDTH-1 downto 0)
);
end dff;
 
architecture FlipFlop of dff is
architecture behavioral of dff is
 
begin
process (clock,reset)
begin
if(reset = '0') then
Q <= (others => '0');
src_q <= (others => '0');
elsif clock'event and clock = '1' then
if(enable = '1') then
Q <= D;
src_q <= sink_d;
end if;
end if;
end process;
 
end FlipFlop;
end behavioral;
 

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