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URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

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  • This comparison shows the changes necessary to convert path 
    /pcie_ds_dma
    from Rev 29 to Rev 30
    ↔ Reverse comparison
  •

Rev 29 → Rev 30

/trunk/soft/linux/application/wb_test/src/work/main.cpp
53,6 → 53,7
#include <unistd.h>
#include <stdlib.h>
#include <stdio.h>
#include <signal.h>
 
#include "cl_wbpex.h"
//#include "tf_test.h"
86,6 → 87,7
{
// анализ командной строки
setlocale( LC_ALL, "Russian" );
signal(SIGINT, signa_handler);
 
TF_Test *pTest=NULL;
TF_Test *pTest2=NULL;
/trunk/soft/linux/application/wb_test/src/work/wb_teststrm.cpp
1,4 → 1,5
 
#define __VERBOSE__
 
#include <stdio.h>
#include <fcntl.h>
68,10 → 69,10
 
rd0.trd=trdNo;
rd0.Strm=strmNo;
// pBrd->StreamInit( rd0.Strm, CntBuffer, SizeBuferOfBytes, rd0.trd, 1, isCycle, isSystem, isAgreeMode );
pBrd->StreamInit( rd0.Strm, CntBuffer, SizeBuferOfBytes, rd0.trd, 1, isCycle, isSystem, isAgreeMode );
 
bufIsvi = new U32[SizeBlockOfWords*2];
pBrd->StreamInit( rd0.Strm, CntBuffer, SizeBuferOfBytes, U32(0x3000),U32(1), 0, 1, U32(0) );
// pBrd->StreamInit( rd0.Strm, CntBuffer, SizeBuferOfBytes, U32(0x3000),U32(1), 0, 1, U32(0) );
}
 
void WB_TestStrm::Start( void )
134,10 → 135,13
//BRDC_fprintf( stderr, "%10s %10d %10d %10d %10d\n", "FIFO_0 :", tr0.BlockWr, rd0.BlockRd, rd0.BlockOk, rd0.BlockError );
//BRDC_fprintf( stderr, "%10s %10d %10d %10d %10d\n", "FIFO_1 :", tr1.BlockWr, rd1.BlockRd, rd1.BlockOk, rd1.BlockError );
 
U32 status = 0; //pBrd->RegPeekDir( rd0.trd, 0 ) & 0xFFFF;
rd0.BlockWr=pBrd->wb_block_read( 1, 0x11 );
U32 status = pBrd->wb_block_read( 1, 0x10 );
rd0.BlockWr = pBrd->wb_block_read( 1, 0x11 );
U32 sig = pBrd->wb_block_read( 1, 0x12 );
//pBrd->RegPeekDir( rd0.trd, 0 ) & 0xFFFF;
//rd0.BlockWr=pBrd->wb_block_read( 1, 0x11 );
 
BRDC_fprintf( stdout, "%6s %3d %10d %10d %10d %10d %9.1f %10.1f 0x%.4X %d %4d %4f\r", "TRD :", rd0.trd, rd0.BlockWr, rd0.BlockRd, rd0.BlockOk, rd0.BlockError, rd0.VelocityCurrent, rd0.VelocityAvarage, status, IsviStatus, IsviCnt, rd0.fftTime_us );
BRDC_fprintf( stdout, "%6s %3d %10d %10d %10d %10d %9.1f %10.1f 0x%.4X 0x%.8X %4d %4f\r", "TRD :", rd0.trd, rd0.BlockWr, rd0.BlockRd, rd0.BlockOk, rd0.BlockError, rd0.VelocityCurrent, rd0.VelocityAvarage, status, sig, IsviCnt, rd0.fftTime_us );
 
 
 
291,6 → 295,8
 
pBrd->RegPokeInd( 4, 0, 0x2038 );
*/
pBrd->wb_block_write( 1, 8, 1 );
 
pBrd->StreamStart( rd0.Strm );
 
U32 val;
303,7 → 309,8
val=pBrd->wb_block_read( 1, 8 );
BRDC_fprintf( stderr, "GEN_CTRL=0x%.4X \n", val );
 
pBrd->wb_block_write( 1, 9, 5 );
pBrd->wb_block_write( 1, 8, 0 );
pBrd->wb_block_write( 1, 9, 1 );
pBrd->wb_block_write( 1, 8, 0x6A0 );
 
val=pBrd->wb_block_read( 1, 8 );
/trunk/soft/linux/common/utils/cl_wbpex.cpp
77,7 → 77,7
if( strm>1 )
return 1;
 
DEBUG_PRINT("CL_AMBPEX::%s()\n", __FUNCTION__);
DEBUG_PRINT("CL_AMBPEX::%s( cycle=%d)\n", __FUNCTION__, cycle );
 
StreamParam *pStrm= m_streamParam+strm;
if( pStrm->status!=0 )
/trunk/soft/linux/driver/pexdrv/pexmodule.c
382,7 → 382,8
//err_msg(err_trace, "%s(%d)\n", __FUNCTION__, atomic_read(&pDevice->m_TotalIRQ));
 
flag = NextDmaTransfer(pDevice->m_DmaChannel[NumberOfChannel]);
if(!flag)
//if(!flag)
if( 0 )
{
DMA_CTRL_EXT CtrlExt;
CtrlExt.AsWhole = 0;
443,48 → 444,7
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
},
{
.vendor = INSYS_VENDOR_ID,
.device = AMBPEX8_DEVID,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
},
{
.vendor = INSYS_VENDOR_ID,
.device = ADP201X1AMB_DEVID,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
},
{
.vendor = INSYS_VENDOR_ID,
.device = ADP201X1DSP_DEVID,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
},
{
.vendor = INSYS_VENDOR_ID,
.device = AMBPEXARM_DEVID,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
},
{
.vendor = INSYS_VENDOR_ID,
.device = AMBFMC106P_DEVID,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
},
{
.vendor = INSYS_VENDOR_ID,
.device = AMBFMC114V_DEVID,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
},
{
.vendor = INSYS_VENDOR_ID,
.device = AMBKU_SSCOS_DEVID,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
},
 
{ },
};
 
/trunk/soft/linux/driver/pexdrv/hardware.c
16,6 → 16,8
#include "ambpexregs.h"
#include "memory.h"
 
 
int g_isAdm=0;
//--------------------------------------------------------------------
 
int set_device_name(struct pex_device *brd, u16 dev_id, int index)
25,13 → 27,7
 
switch(dev_id) {
case AMBPEX5_DEVID: snprintf(brd->m_name, 128, "%s%d", "AMBPEX5", index); break;
case AMBPEX8_DEVID: snprintf(brd->m_name, 128, "%s%d", "AMBPEX8", index); break;
case ADP201X1AMB_DEVID: snprintf(brd->m_name, 128, "%s%d", "ADP201X1AMB", index); break;
case ADP201X1DSP_DEVID: snprintf(brd->m_name, 128, "%s%d", "ADP201X1DSP", index); break;
case AMBPEXARM_DEVID: snprintf(brd->m_name, 128, "%s%d", "D2XT005", index); break;
case AMBFMC106P_DEVID: snprintf(brd->m_name, 128, "%s%d", "AMBFMC106P", index); break;
case AMBFMC114V_DEVID: snprintf(brd->m_name, 128, "%s%d", "AMBFMC114V", index); break;
case AMBKU_SSCOS_DEVID: snprintf(brd->m_name, 128, "%s%d", "AMBKU_SSCOS", index); break;
 
default:
snprintf(brd->m_name, sizeof(brd->m_name), "%s%d", "Unknown", index); break;
}
83,15 → 79,7
 
dbg_msg(dbg_trace, "%s(): DeviceID = 0x%X, DeviceRev = 0x%X.\n", __FUNCTION__, deviceID, deviceRev);
 
if((AMBPEX8_DEVID != deviceID) &&
(ADP201X1AMB_DEVID != deviceID) &&
(AMBPEX5_DEVID != deviceID) &&
(AMBPEXARM_DEVID != deviceID) &&
(AMBFMC114V_DEVID != deviceID)) {
 
dbg_msg(dbg_trace, "%s(): Unsupported device id: 0x%X.\n", __FUNCTION__, deviceID);
return -ENODEV;
}
 
temp = ReadOperationWordReg(brd, PEMAINadr_PLD_VER);
 
139,6 → 127,7
 
dbg_msg(dbg_trace, "%s(): m_DmaChanMask = 0x%X\n", __FUNCTION__, brd->m_DmaChanMask);
 
 
// подготовим к работе ПЛИС ADM
dbg_msg(dbg_trace, "%s(): Prepare ADM PLD.\n", __FUNCTION__);
WriteOperationWordReg(brd,PEMAINadr_BRD_MODE, 0);
457,11 → 446,11
int DmaEnable(struct pex_device *brd, u32 AdmNumber, u32 TetrNumber)
{
int Status = 0;
u32 Value = 0;
Status = ReadRegData(brd, AdmNumber, TetrNumber, 0, &Value);
if(Status != 0) return Status;
Value |= 0x8; // DRQ enable
Status = WriteRegData(brd, AdmNumber, TetrNumber, 0, Value);
//u32 Value = 0;
//Status = ReadRegData(brd, AdmNumber, TetrNumber, 0, &Value);
//if(Status != 0) return Status;
//Value |= 0x8; // DRQ enable
//Status = WriteRegData(brd, AdmNumber, TetrNumber, 0, Value);
//err_msg(err_trace, "%s: MODE0 = 0x%X.\n", __FUNCTION__, Value);
return Status;
}
471,11 → 460,11
int DmaDisable(struct pex_device *brd, u32 AdmNumber, u32 TetrNumber)
{
int Status = 0;
u32 Value = 0;
Status = ReadRegData(brd, AdmNumber, TetrNumber, 0, &Value);
if(Status != 0) return Status;
Value &= 0xfff7; // DRQ disable
Status = WriteRegData(brd, AdmNumber, TetrNumber, 0, Value);
//u32 Value = 0;
//Status = ReadRegData(brd, AdmNumber, TetrNumber, 0, &Value);
//if(Status != 0) return Status;
//Value &= 0xfff7; // DRQ disable
//Status = WriteRegData(brd, AdmNumber, TetrNumber, 0, Value);
return Status;
}
 
615,7 → 604,7
brd->m_DmaIrqEnbl = enbl;
 
tetr_num = GetTetrNum(brd->m_DmaChannel[NumberOfChannel]);
Status = DmaDisable(brd, 0, tetr_num);
//Status = DmaDisable(brd, 0, tetr_num);
CompleteDmaTransfer(brd->m_DmaChannel[NumberOfChannel]);
 
return Status;

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