OpenCores

branches/Virtex6/ML605/v6pcie.ise Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: branches/Virtex6/ML605/class_dlm.vhd =================================================================== --- branches/Virtex6/ML605/class_dlm.vhd (revision 9) +++ branches/Virtex6/ML605/class_dlm.vhd (nonexistent) @@ -1,199 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: ziti --- Engineer: wgao --- --- Create Date: 17:01:32 19 Jun 2009 --- Design Name: --- Module Name: class_dlm - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.abb64Package.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity class_dlm is --- Generic ( --- C_PRO_DAQ_WIDTH : integer := 16 ; --- C_PRO_DLM_WIDTH : integer := 4 ; --- C_PRO_CTL_WIDTH : integer := 16 --- ); - Port ( - - -- DLM Tx - dlm2send_va : OUT std_logic; - dlm2send_type : OUT std_logic_vector(4-1 downto 0); - - -- DLM Rx - dlm_rec_va : IN std_logic; - dlm_rec_type : IN std_logic_vector(4-1 downto 0); - - -- Link side: common signals - link_tx_clk : IN std_logic; - link_rx_clk : IN std_logic; - - -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - - -- Fabric side: DLM Rx - dlm_tv : IN std_logic; - dlm_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0); - - -- Fabric side: DLM Tx - dlm_rv : OUT std_logic; - dlm_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0); - - -- Interrupter trigger - DLM_irq : OUT std_logic; - - -- Fabric side: Common signals - trn_clk : IN std_logic; - protocol_rst : IN std_logic - - ); -end entity class_dlm; - - -architecture Behavioral of class_dlm is - - -- to synchronize the DLM messages across clock domains - component v6_afifo_8x8 - port ( - wr_clk : IN std_logic; - din : IN std_logic_VECTOR(8-1 downto 0); - wr_en : IN std_logic; - full : OUT std_logic; - - rd_clk : IN std_logic; - rd_en : IN std_logic; - dout : OUT std_logic_VECTOR(8-1 downto 0); - empty : OUT std_logic; - - rst : IN std_logic - ); - end component; - - -- Interrupter trigger - signal DLM_irq_i : std_logic; - - -- Fabric side: DLM Tx - signal dlm_rv_i : std_logic; - signal dlm_rd_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0); - - -- protocol side: DLM Send - signal dlm2send_va_i : std_logic; - signal dlm2send_type_i : std_logic_vector(4-1 downto 0); - - signal dlm_rx_din_padded : std_logic_vector(8-1 downto 0); - signal dlm_rx_dout : std_logic_vector(8-1 downto 0); - signal dlm_rx_empty : std_logic; - signal dlm_rx_empty_r1 : std_logic; - signal dlm_rx_full : std_logic; - - signal dlm_tx_din_padded : std_logic_vector(8-1 downto 0); - signal dlm_tx_dout : std_logic_vector(8-1 downto 0); - signal dlm_tx_empty : std_logic; - signal dlm_tx_empty_r1 : std_logic; - signal dlm_tx_full : std_logic; - - -begin - - -- Fabric side: DLM Tx - dlm_rv <= dlm_rv_i ; - dlm_rd <= dlm_rd_i ; - - -- protocol side: DLM Send - dlm2send_va <= dlm2send_va_i ; - dlm2send_type <= dlm2send_type_i ; - - DLM_irq <= DLM_irq_i ; - DLM_irq_i <= '0'; - - -- DLM direction: upstream - Transfer_DLM_upstream: - process (trn_clk, protocol_rst ) - begin - if protocol_rst = '1' then - dlm_rx_empty_r1 <= '1' ; - dlm_rv_i <= '0' ; - dlm_rd_i <= (OTHERS=>'0') ; - elsif trn_clk'event and trn_clk = '1' then - dlm_rx_empty_r1 <= dlm_rx_empty ; - dlm_rv_i <= not dlm_rx_empty_r1 ; - dlm_rd_i <= C_ALL_ZEROS(C_DBUS_WIDTH/2-1 downto 4) & dlm_rx_dout(4-1 downto 0) ; - end if; - end process; - - - -- DLM direction: downstream - Transfer_DLM_downstream: - process (link_tx_clk, protocol_rst ) - begin - if protocol_rst = '1' then - dlm_tx_empty_r1 <= '1' ; - dlm2send_va_i <= '0' ; - dlm2send_type_i <= (OTHERS=>'0') ; - elsif link_tx_clk'event and link_tx_clk = '1' then - dlm_tx_empty_r1 <= dlm_tx_empty ; - dlm2send_va_i <= not dlm_tx_empty_r1 ; - dlm2send_type_i <= dlm_tx_dout(4-1 downto 0); - end if; - end process; - - - dlm_rx_din_padded <= X"0" & dlm_rec_type(4-1 downto 0); - dlm_tx_din_padded <= X"0" & dlm_td(4-1 downto 0); - - - Sync_stage_from_ROC: - v6_afifo_8x8 - port map ( - wr_clk => link_tx_clk , -- IN std_logic; - wr_en => dlm_rec_va , -- IN std_logic; - din => dlm_rx_din_padded , -- IN std_logic_VECTOR(7 downto 0); - full => dlm_rx_full , -- OUT std_logic; - - rd_clk => trn_clk , -- IN std_logic; - rd_en => '1' , -- IN std_logic; - dout => dlm_rx_dout , -- OUT std_logic_VECTOR(7 downto 0); - empty => dlm_rx_empty , -- OUT std_logic; - - rst => protocol_rst -- IN std_logic - ); - - - Sync_stage_to_ROC: - v6_afifo_8x8 - port map ( - wr_clk => trn_clk , -- IN std_logic; - wr_en => dlm_tv , -- IN std_logic; - din => dlm_tx_din_padded , -- IN std_logic_VECTOR(7 downto 0); - full => dlm_tx_full , -- OUT std_logic; - - rd_clk => link_tx_clk , -- IN std_logic; - rd_en => '1' , -- IN std_logic; - dout => dlm_tx_dout , -- OUT std_logic_VECTOR(7 downto 0); - empty => dlm_tx_empty , -- OUT std_logic; - - rst => protocol_rst -- IN std_logic - ); - -end architecture Behavioral; Index: branches/Virtex6/ML605/v6pcie.gise =================================================================== --- branches/Virtex6/ML605/v6pcie.gise (revision 9) +++ branches/Virtex6/ML605/v6pcie.gise (nonexistent) @@ -1,51 +0,0 @@ - - - - - - - - - - - - - - - - - - - - 11.1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Index: branches/Virtex6/ML605/v6_pcie_v1_3/v6_pcie_readme.txt =================================================================== --- branches/Virtex6/ML605/v6_pcie_v1_3/v6_pcie_readme.txt (revision 9) +++ branches/Virtex6/ML605/v6_pcie_v1_3/v6_pcie_readme.txt (nonexistent) @@ -1,239 +0,0 @@ - - Core name: Xilinx Virtex-6 Integrated Block for PCI Express - Version: 1.3 - Release Date: September 16, 2009 - - -================================================================================ - -This document contains the following sections: - -1. Introduction -2. New Features -3. Resolved Issues -4. Known Issues -5. Technical Support -6. Other Information -7. Core Release History -8. Legal Disclaimer - -================================================================================ - -1. INTRODUCTION - -For the most recent updates to the IP installation instructions for this core, -please go to: - - http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm - - -For system requirements: - - http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm - - -This file contains release notes for the Xilinx LogiCORE(TM) IP Virtex-6 -Integrated Block for PCI Express v1.3 solution. For the latest core updates, -see the product page at: - - http://www.xilinx.com/products/ipcenter/V6_PCI_Express_Block.htm - - -2. NEW FEATURES - - - ISE 11.3 software support - - Virtex-6 Integrated Block for PCI Express Root Port support - - Implementation support for 512 Bytes MPS configuration for the 8-lane Gen2 - product. - - Implementation support for all part/packages for the 8-lane Gen2 product - - Added support for 6VHX380T-FF1155-1. - - -3. RESOLVED ISSUES - - - Error in generating core from ISE New source Wizard - o CR 517195 - - Issue resolved where ProjNav would error out with a Tcl scripting error when - attempting to generate the core from ISE New Source Wizard. - - - Incorrect UCF path in implement.bat file - o CR 523072 - - Issue resolved where the relative path to UCF in implement.bat is incorrect, - when design is generated and implemented on Windows operating systems. - - - BUFG driving MMCM clkin removed - o CR 511334 - - The BUFG driving the MMCM clkin was removed, to reduce the number of BUFGs - used in the design. - - - Root Port operation now supported in this release. - o CR 509679 - - Support added for Root Port operation of the PCIe Integrated Block. - - - FIFO_LIMIT setting could cause throttling on Transaction Transmit interface - for the 8-lane Gen2 operation only - o CR 524324 - - Issue resolved where the FIFO_LIMIT setting in the 8-lane Gen2 product - was not high enough and could cause throttling on the Transaction transmit - interface. - - - Incorrect cfg_trn_pending_n functionality - o CR 524835 - - Issue resolved where the cfg_trn_pending_n output of the core was inverted. - - - Implementation support for the 8-lane Gen2 product with 512 Bytes Max - Payload Size Configuration - o CR 522979 - - Implementation support is now available for the 8-lane Gen 2 product with - 512 Bytes Max Payload Size Configuration - - - Support for Non-default User Interface frequency when the Xilinx Development - Board selected is "ML 605" - o CR 522735 - - Implementation support is now available for non-default User Interface - frequency when the Xilinx Development Board selected is "ML 605". - - - Support for Programmed Power Management (PPM) state L1 for the 8-lane Gen2 - product - o CR 522902 - - Programmed Power Management (PPM) state L1 is now supported for the 8-lane - Gen2 product - - - trn_reof_n assertion without a trn_rsof_n assertion on Receive Transaction - Interface in the 8-lane Gen2 product, when receiving back-to-back - Transactions. - o CR 522593 - - Issue resolved where trn_reof_n might assert without trn_rsof_n assertion - if trn_rsrc_rdy_n were deasserted while a packet was being written into - the internal FIFO. - - - Requirement added for trn_tsrc_dsc_n assertion to be accompanied by - trn_teof_n assertion in the 8-lane Gen2 product - o CR 525136 - - The 8-lane Gen2 product now requires trn_tsrc_dsc_n assertion to be - accompanied by trn_teof_n assertion. - - - Transmit Transaction interface lock-up in the 8-lane Gen2 product. - o CR 525691 - - Issue resolved where the Transmit Transaction interface locks up on an - assertion of trn_teof_n, which is not qualified by trn_tsrc_rdy_n, in the - 8-lane Gen2 product. - -4. KNOWN ISSUES - - The following are known issues for v1.3 of this core at time of release: - - - Virtex-6 solutions are pending hardware validation. - - - trn_rnp_ok_n not supported in the 8-lane Gen2 Integrated Block - o CR 518631 - - Use of trn_rnp_ok_n is not supported in the 8-lane Gen 2 Integrated Block - for PCI Express product. - - Workaround : None - - - Gen2 operation only supported with 250 MHz Reference Clock. - o CR 522983 - - Gen 2 operation is only supported with 250 MHz Reference Clock. - - Workaround : Use an external PLL to convert 100 MHz clock to 250 MHz. - Contact Xilinx Support. - - - VHDL example design / testbench not supported. - o CR 510476 - - VHDL example design and testbench are not supported in the 11.2 release - - Workaround : None. Planned release in 11.4. - - The most recent information, including known issues, workarounds, and - resolutions for this version is provided in the IP Release Notes Guide located at - - http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf - -5. TECHNICAL SUPPORT - - To obtain technical support, create a WebCase at www.xilinx.com/support. - Questions are routed to a team with expertise using this product. - - Xilinx provides technical support for use of this product when used - according to the guidelines described in the core documentation, and - cannot guarantee timing, functionality, or support of this product for - designs that do not follow specified guidelines. - - -6. OTHER INFORMATION - - In this release, the only supported synthesis tool is XST. - Additionally, only Verilog simulation and example design files are provided. - -7. CORE RELEASE HISTORY - -Date By Version Description -================================================================================ -09/16/2009 Xilinx, Inc. 1.3 11.3 support -06/24/2009 Xilinx, Inc. 1.2 11.2 support -04/24/2009 Xilinx, Inc. 1.1 Initial release (BETA) -================================================================================ - -8. Legal Disclaimer - -(c) Copyright 2009 Xilinx, Inc. All rights reserved. - -This file contains confidential and proprietary information -of Xilinx, Inc. and is protected under U.S. and -international copyright and other intellectual property -laws. --- -DISCLAIMER -This disclaimer is not a license and does not grant any -rights to the materials distributed herewith. Except as -otherwise provided in a valid license issued to you by -Xilinx, and to the maximum extent permitted by applicable -law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -(2) Xilinx shall not be liable (whether in contract or tort, -including negligence, or under any other theory of -liability) for any loss or damage of any kind or nature -related to, arising under or in connection with these -materials, including for any direct, or any indirect, -special, incidental, or consequential loss or damage -(including loss of data, profits, goodwill, or any type of -loss or damage suffered as a result of any action brought -by a third party) even if such damage or loss was -reasonably foreseeable or Xilinx had been advised of the -possibility of the same. --- -CRITICAL APPLICATIONS -Xilinx products are not designed or intended to be fail- -safe, or for use in any application requiring fail-safe -performance, such as life-support or safety devices or -systems, Class III medical devices, nuclear facilities, -applications related to the deployment of airbags, or any -other applications that could lead to death, personal -injury, or severe property or environmental damage -individually and collectively, "Critical -Applications"). Customer assumes the sole risk and -liability of any use of Xilinx products in Critical -Applications, subject only to applicable laws and -regulations governing limitations on product liability. --- -THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -PART OF THIS FILE AT ALL TIMES. Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/v6_pcie_v1_3x8.v =================================================================== --- branches/Virtex6/ML605/v6_pcie_v1_3/source/v6_pcie_v1_3x8.v (revision 9) +++ branches/Virtex6/ML605/v6_pcie_v1_3/source/v6_pcie_v1_3x8.v (nonexistent) @@ -1,1191 +0,0 @@ -//----------------------------------------------------------------------------- -// -// (c) Copyright 2009 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information of Xilinx, Inc. -// and is protected under U.S. and international copyright and other -// intellectual property laws. -// -// DISCLAIMER -// -// This disclaimer is not a license and does not grant any rights to the -// materials distributed herewith. Except as otherwise provided in a valid -// license issued to you by Xilinx, and to the maximum extent permitted by -// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -// and (2) Xilinx shall not be liable (whether in contract or tort, including -// negligence, or under any other theory of liability) for any loss or damage -// of any kind or nature related to, arising under or in connection with these -// materials, including for any direct, or any indirect, special, incidental, -// or consequential loss or damage (including loss of data, profits, goodwill, -// or any type of loss or damage suffered as a result of any action brought by -// a third party) even if such damage or loss was reasonably foreseeable or -// Xilinx had been advised of the possibility of the same. -// -// CRITICAL APPLICATIONS -// -// Xilinx products are not designed or intended to be fail-safe, or for use in -// any application requiring fail-safe performance, such as life-support or -// safety devices or systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any other -// applications that could lead to death, personal injury, or severe property -// or environmental damage (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and liability of any use of -// Xilinx products in Critical Applications, subject only to applicable laws -// and regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -// AT ALL TIMES. -// -//----------------------------------------------------------------------------- -// Project : Virtex-6 Integrated Block for PCI Express -// File : v6_pcie_v1_3x8.v -//-- -//-- Description: Virtex6 solution wrapper : Endpoint for PCI Express -//-- -//-- -//-- -//-------------------------------------------------------------------------------- - -`timescale 1ns/1ns - -module v6_pcie_v1_3x8 # ( - parameter ALLOW_X8_GEN2 = "FALSE", - parameter BAR0 = 32'hFFFF0000, - parameter BAR1 = 32'hFFF00000, - parameter BAR2 = 32'hFFFFF000, - parameter BAR3 = 32'h00000000, - parameter BAR4 = 32'h00000000, - parameter BAR5 = 32'h00000000, - - parameter CARDBUS_CIS_POINTER = 32'h00000000, - parameter CLASS_CODE = 24'h050000, - parameter CMD_INTX_IMPLEMENTED = "TRUE", - parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE", - parameter CPL_TIMEOUT_RANGES_SUPPORTED = 4'h2, - - parameter DEV_CAP_ENDPOINT_L0S_LATENCY = 7, - parameter DEV_CAP_ENDPOINT_L1_LATENCY = 7, - parameter DEV_CAP_EXT_TAG_SUPPORTED = "FALSE", - parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2, - parameter DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0, - parameter DEVICE_ID = 16'h0153, - - parameter DISABLE_LANE_REVERSAL = "TRUE", - parameter DISABLE_SCRAMBLING = "FALSE", - parameter DSN_BASE_PTR = 12'h100, - parameter DSN_CAP_NEXTPTR = 12'h000, - parameter DSN_CAP_ON = "TRUE", - - parameter ENABLE_MSG_ROUTE = 11'h00000000000, - parameter ENABLE_RX_TD_ECRC_TRIM = "TRUE", - parameter EXPANSION_ROM = 32'h00000000, - parameter EXT_CFG_CAP_PTR = 6'h3F, - parameter EXT_CFG_XP_CAP_PTR = 10'h3FF, - parameter HEADER_TYPE = 8'h00, - parameter INTERRUPT_PIN = 8'h1, - - parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE", - parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE", - parameter LINK_CAP_MAX_LINK_SPEED = 4'h1, - parameter LINK_CAP_MAX_LINK_WIDTH = 6'h08, - parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE", - - parameter LINK_CTRL2_DEEMPHASIS = "FALSE", - parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE", - parameter LINK_CTRL2_TARGET_LINK_SPEED = 4'h0, - parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "FALSE", - - parameter LL_ACK_TIMEOUT = 15'h0000, - parameter LL_ACK_TIMEOUT_EN = "FALSE", - parameter LL_ACK_TIMEOUT_FUNC = 0, - parameter LL_REPLAY_TIMEOUT = 15'h0000, - parameter LL_REPLAY_TIMEOUT_EN = "FALSE", - parameter LL_REPLAY_TIMEOUT_FUNC = 0, - - parameter LTSSM_MAX_LINK_WIDTH = LINK_CAP_MAX_LINK_WIDTH, - parameter MSI_CAP_MULTIMSGCAP = 0, - parameter MSI_CAP_MULTIMSG_EXTENSION = 0, - parameter MSI_CAP_ON = "TRUE", - parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "FALSE", - parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE", - - parameter MSIX_CAP_ON = "FALSE", - parameter MSIX_CAP_PBA_BIR = 0, - parameter MSIX_CAP_PBA_OFFSET = 29'h0, - parameter MSIX_CAP_TABLE_BIR = 0, - parameter MSIX_CAP_TABLE_OFFSET = 29'h0, - parameter MSIX_CAP_TABLE_SIZE = 11'h000, - - parameter PCIE_CAP_DEVICE_PORT_TYPE = 4'b0000, - parameter PCIE_CAP_INT_MSG_NUM = 5'h1, - parameter PCIE_CAP_NEXTPTR = 8'h00, - parameter PCIE_DRP_ENABLE = "FALSE", - parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages - - parameter PM_CAP_DSI = "FALSE", - parameter PM_CAP_D1SUPPORT = "FALSE", - parameter PM_CAP_D2SUPPORT = "FALSE", - parameter PM_CAP_NEXTPTR = 8'h48, - parameter PM_CAP_PMESUPPORT = 5'h0F, - parameter PM_CSR_NOSOFTRST = "TRUE", - - parameter PM_DATA_SCALE0 = 2'h0, - parameter PM_DATA_SCALE1 = 2'h0, - parameter PM_DATA_SCALE2 = 2'h0, - parameter PM_DATA_SCALE3 = 2'h0, - parameter PM_DATA_SCALE4 = 2'h0, - parameter PM_DATA_SCALE5 = 2'h0, - parameter PM_DATA_SCALE6 = 2'h0, - parameter PM_DATA_SCALE7 = 2'h0, - - parameter PM_DATA0 = 8'h00, - parameter PM_DATA1 = 8'h00, - parameter PM_DATA2 = 8'h00, - parameter PM_DATA3 = 8'h00, - parameter PM_DATA4 = 8'h00, - parameter PM_DATA5 = 8'h00, - parameter PM_DATA6 = 8'h00, - parameter PM_DATA7 = 8'h00, - - parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz - parameter REVISION_ID = 8'h06, - parameter SUBSYSTEM_ID = 16'hABB3, - parameter SUBSYSTEM_VENDOR_ID = 16'h0084, - - parameter TL_RX_RAM_RADDR_LATENCY = 0, - parameter TL_RX_RAM_RDATA_LATENCY = 2, - parameter TL_RX_RAM_WRITE_LATENCY = 0, - parameter TL_TX_RAM_RADDR_LATENCY = 0, - parameter TL_TX_RAM_RDATA_LATENCY = 2, - parameter TL_TX_RAM_WRITE_LATENCY = 0, - - parameter UPCONFIG_CAPABLE = "TRUE", - parameter USER_CLK_FREQ = 3, - parameter VC_BASE_PTR = 12'h0, - parameter VC_CAP_NEXTPTR = 12'h000, - parameter VC_CAP_ON = "FALSE", - parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE", - - parameter VC0_CPL_INFINITE = "TRUE", - parameter VC0_RX_RAM_LIMIT = 13'h7FF, - parameter VC0_TOTAL_CREDITS_CD = 308, - parameter VC0_TOTAL_CREDITS_CH = 36, - parameter VC0_TOTAL_CREDITS_NPH = 12, - parameter VC0_TOTAL_CREDITS_PD = 308, - parameter VC0_TOTAL_CREDITS_PH = 32, - parameter VC0_TX_LASTPACKET = 29, - - parameter VENDOR_ID = 16'h10DC, - parameter VSEC_BASE_PTR = 12'h0, - parameter VSEC_CAP_NEXTPTR = 12'h000, - parameter VSEC_CAP_ON = "FALSE", - - parameter AER_BASE_PTR = 12'h128, - parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE", - parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE", - parameter AER_CAP_ID = 16'h0001, - parameter AER_CAP_INT_MSG_NUM_MSI = 5'h0a, - parameter AER_CAP_INT_MSG_NUM_MSIX = 5'h15, - parameter AER_CAP_NEXTPTR = 12'h160, - parameter AER_CAP_ON = "FALSE", - parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE", - parameter AER_CAP_VERSION = 4'h1, - - parameter CAPABILITIES_PTR = 8'h40, - parameter CRM_MODULE_RSTS = 7'h00, - parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE", - parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE", - parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE", - parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE", - parameter DEV_CAP_RSVD_14_12 = 0, - parameter DEV_CAP_RSVD_17_16 = 0, - parameter DEV_CAP_RSVD_31_29 = 0, - parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE", - - parameter DISABLE_ASPM_L1_TIMER = "FALSE", - parameter DISABLE_BAR_FILTERING = "FALSE", - parameter DISABLE_ID_CHECK = "FALSE", - parameter DISABLE_RX_TC_FILTER = "FALSE", - parameter DNSTREAM_LINK_NUM = 8'h00, - - parameter DSN_CAP_ID = 16'h0003, - parameter DSN_CAP_VERSION = 4'h1, - parameter ENTER_RVRY_EI_L0 = "TRUE", - parameter INFER_EI = 5'h0c, - parameter IS_SWITCH = "FALSE", - - parameter LAST_CONFIG_DWORD = 10'h3FF, - parameter LINK_CAP_ASPM_SUPPORT = 1, - parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE", - parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7, - parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7, - parameter LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7, - parameter LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7, - parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7, - parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7, - parameter LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7, - parameter LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7, - parameter LINK_CAP_RSVD_23_22 = 0, - parameter LINK_CONTROL_RCB = 0, - - parameter MSI_BASE_PTR = 8'h48, - parameter MSI_CAP_ID = 8'h05, - parameter MSI_CAP_NEXTPTR = 8'h60, - parameter MSIX_BASE_PTR = 8'h9c, - parameter MSIX_CAP_ID = 8'h11, - parameter MSIX_CAP_NEXTPTR = 8'h00, - parameter N_FTS_COMCLK_GEN1 = 255, - parameter N_FTS_COMCLK_GEN2 = 254, - parameter N_FTS_GEN1 = 255, - parameter N_FTS_GEN2 = 255, - - parameter PCIE_BASE_PTR = 8'h60, - parameter PCIE_CAP_CAPABILITY_ID = 8'h10, - parameter PCIE_CAP_CAPABILITY_VERSION = 4'h2, - parameter PCIE_CAP_ON = "TRUE", - parameter PCIE_CAP_RSVD_15_14 = 0, - parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE", - parameter PCIE_REVISION = 2, - parameter PGL0_LANE = 0, - parameter PGL1_LANE = 1, - parameter PGL2_LANE = 2, - parameter PGL3_LANE = 3, - parameter PGL4_LANE = 4, - parameter PGL5_LANE = 5, - parameter PGL6_LANE = 6, - parameter PGL7_LANE = 7, - parameter PL_AUTO_CONFIG = 0, - parameter PL_FAST_TRAIN = "FALSE", - - parameter PM_BASE_PTR = 8'h40, - parameter PM_CAP_AUXCURRENT = 0, - parameter PM_CAP_ID = 8'h01, - parameter PM_CAP_ON = "TRUE", - parameter PM_CAP_PME_CLOCK = "FALSE", - parameter PM_CAP_RSVD_04 = 0, - parameter PM_CAP_VERSION = 3, - parameter PM_CSR_BPCCEN = "FALSE", - parameter PM_CSR_B2B3 = "FALSE", - - parameter RECRC_CHK = 0, - parameter RECRC_CHK_TRIM = "FALSE", - parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE", - parameter SELECT_DLL_IF = "FALSE", - parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE", - parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE", - parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE", - parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE", - parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE", - parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE", - parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE", - parameter SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000, - parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE", - parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE", - parameter SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0, - parameter SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00, - parameter SPARE_BIT0 = 0, - parameter SPARE_BIT1 = 0, - parameter SPARE_BIT2 = 0, - parameter SPARE_BIT3 = 0, - parameter SPARE_BIT4 = 0, - parameter SPARE_BIT5 = 0, - parameter SPARE_BIT6 = 0, - parameter SPARE_BIT7 = 0, - parameter SPARE_BIT8 = 0, - parameter SPARE_BYTE0 = 8'h00, - parameter SPARE_BYTE1 = 8'h00, - parameter SPARE_BYTE2 = 8'h00, - parameter SPARE_BYTE3 = 8'h00, - parameter SPARE_WORD0 = 32'h00000000, - parameter SPARE_WORD1 = 32'h00000000, - parameter SPARE_WORD2 = 32'h00000000, - parameter SPARE_WORD3 = 32'h00000000, - - parameter TL_RBYPASS = "FALSE", - parameter TL_TFC_DISABLE = "FALSE", - parameter TL_TX_CHECKS_DISABLE = "FALSE", - parameter EXIT_LOOPBACK_ON_EI = "TRUE", - parameter UPSTREAM_FACING = "TRUE", - parameter UR_INV_REQ = "TRUE", - - parameter VC_CAP_ID = 16'h0002, - parameter VC_CAP_VERSION = 4'h1, - parameter VSEC_CAP_HDR_ID = 16'h1234, - parameter VSEC_CAP_HDR_LENGTH = 12'h018, - parameter VSEC_CAP_HDR_REVISION = 4'h1, - parameter VSEC_CAP_ID = 16'h000b, - parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE", - parameter VSEC_CAP_VERSION = 4'h1 -) -( - //------------------------------------------------------- - // 1. PCI Express (pci_exp) Interface - //------------------------------------------------------- - - // Tx - output [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_txp, - output [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_txn, - - // Rx - input [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_rxp, - input [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_rxn, - - //------------------------------------------------------- - // 2. Transaction (TRN) Interface - //------------------------------------------------------- - - // Common - output trn_clk, - output trn_reset_n, - output trn_lnk_up_n, - - // Tx - output [5:0] trn_tbuf_av, - output trn_tcfg_req_n, - output trn_terr_drop_n, - output trn_tdst_rdy_n, - input [63:0] trn_td, - input trn_trem_n, - input trn_tsof_n, - input trn_teof_n, - input trn_tsrc_rdy_n, - input trn_tsrc_dsc_n, - input trn_terrfwd_n, - input trn_tcfg_gnt_n, - input trn_tstr_n, - - // Rx - output [63:0] trn_rd, - output trn_rrem_n, - output trn_rsof_n, - output trn_reof_n, - output trn_rsrc_rdy_n, - output trn_rsrc_dsc_n, - output trn_rerrfwd_n, - output [6:0] trn_rbar_hit_n, - input trn_rdst_rdy_n, - input trn_rnp_ok_n, - - // Flow Control - output [11:0] trn_fc_cpld, - output [7:0] trn_fc_cplh, - output [11:0] trn_fc_npd, - output [7:0] trn_fc_nph, - output [11:0] trn_fc_pd, - output [7:0] trn_fc_ph, - input [2:0] trn_fc_sel, - - - //------------------------------------------------------- - // 3. Configuration (CFG) Interface - //------------------------------------------------------- - - output [31:0] cfg_do, - output cfg_rd_wr_done_n, - input [31:0] cfg_di, - input [3:0] cfg_byte_en_n, - input [9:0] cfg_dwaddr, - input cfg_wr_en_n, - input cfg_rd_en_n, - - input cfg_err_cor_n, - input cfg_err_ur_n, - input cfg_err_ecrc_n, - input cfg_err_cpl_timeout_n, - input cfg_err_cpl_abort_n, - input cfg_err_cpl_unexpect_n, - input cfg_err_posted_n, - input cfg_err_locked_n, - input [47:0] cfg_err_tlp_cpl_header, - output cfg_err_cpl_rdy_n, - input cfg_interrupt_n, - output cfg_interrupt_rdy_n, - input cfg_interrupt_assert_n, - input [7:0] cfg_interrupt_di, - output [7:0] cfg_interrupt_do, - output [2:0] cfg_interrupt_mmenable, - output cfg_interrupt_msienable, - output cfg_interrupt_msixenable, - output cfg_interrupt_msixfm, - input cfg_turnoff_ok_n, - output cfg_to_turnoff_n, - input cfg_trn_pending_n, - input cfg_pm_wake_n, - output [7:0] cfg_bus_number, - output [4:0] cfg_device_number, - output [2:0] cfg_function_number, - output [15:0] cfg_status, - output [15:0] cfg_command, - output [15:0] cfg_dstatus, - output [15:0] cfg_dcommand, - output [15:0] cfg_lstatus, - output [15:0] cfg_lcommand, - output [15:0] cfg_dcommand2, - output [2:0] cfg_pcie_link_state_n, - input [63:0] cfg_dsn, - output cfg_pmcsr_pme_en, - output cfg_pmcsr_pme_status, - output [1:0] cfg_pmcsr_powerstate, - output lnk_clk_en, - - //------------------------------------------------------- - // 4. Physical Layer Control and Status (PL) Interface - //------------------------------------------------------- - - output [2:0] pl_initial_link_width, - output [1:0] pl_lane_reversal_mode, - output pl_link_gen2_capable, - output pl_link_partner_gen2_supported, - output pl_link_upcfg_capable, - output [5:0] pl_ltssm_state, - output pl_received_hot_rst, - output pl_sel_link_rate, - output [1:0] pl_sel_link_width, - input pl_directed_link_auton, - input [1:0] pl_directed_link_change, - input pl_directed_link_speed, - input [1:0] pl_directed_link_width, - input pl_upstream_prefer_deemph, - - //------------------------------------------------------- - // 5. System (SYS) Interface - //------------------------------------------------------- - - input sys_clk, - input sys_reset_n - - -); - - - wire rx_func_level_reset_n; - wire cfg_msg_received; - wire cfg_msg_received_pme_to; - - wire cfg_cmd_bme; - wire cfg_cmd_intdis; - wire cfg_cmd_io_en; - wire cfg_cmd_mem_en; - wire cfg_cmd_serr_en; - wire cfg_dev_control_aux_power_en ; - wire cfg_dev_control_corr_err_reporting_en ; - wire cfg_dev_control_enable_relaxed_order ; - wire cfg_dev_control_ext_tag_en ; - wire cfg_dev_control_fatal_err_reporting_en ; - wire [2:0] cfg_dev_control_maxpayload ; - wire [2:0] cfg_dev_control_max_read_req ; - wire cfg_dev_control_non_fatal_reporting_en ; - wire cfg_dev_control_nosnoop_en ; - wire cfg_dev_control_phantom_en ; - wire cfg_dev_control_ur_err_reporting_en ; - wire cfg_dev_control2_cpltimeout_dis ; - wire [3:0] cfg_dev_control2_cpltimeout_val ; - wire cfg_dev_status_corr_err_detected ; - wire cfg_dev_status_fatal_err_detected ; - wire cfg_dev_status_nonfatal_err_detected ; - wire cfg_dev_status_ur_detected ; - wire cfg_link_control_auto_bandwidth_int_en ; - wire cfg_link_control_bandwidth_int_en ; - wire cfg_link_control_hw_auto_width_dis ; - wire cfg_link_control_clock_pm_en ; - wire cfg_link_control_extended_sync ; - wire cfg_link_control_common_clock ; - wire cfg_link_control_retrain_link ; - wire cfg_link_control_linkdisable ; - wire cfg_link_control_rcb ; - wire [1:0] cfg_link_control_aspm_control ; - wire cfg_link_status_autobandwidth_status ; - wire cfg_link_status_bandwidth_status ; - wire cfg_link_status_dll_active ; - wire cfg_link_status_link_training ; - wire [3:0] cfg_link_status_negotiated_link_width ; - wire [1:0] cfg_link_status_current_speed ; - wire [15:0] cfg_msg_data; - - wire sys_reset_n_d; - wire phy_rdy_n; - - wire trn_lnk_up_n_int; - wire trn_lnk_up_n_int1; - - wire trn_reset_n_int; - wire trn_reset_n_int1; - - reg [7:0] cfg_bus_number_d; - reg [4:0] cfg_device_number_d; - reg [2:0] cfg_function_number_d; - - // assigns to outputs - - assign cfg_to_turnoff_n = ~cfg_msg_received_pme_to; - - assign cfg_status = {16'b0}; - - assign cfg_command = {5'b0, - cfg_cmd_intdis, - 1'b0, - cfg_cmd_serr_en, - 5'b0, - cfg_cmd_bme, - cfg_cmd_mem_en, - cfg_cmd_io_en}; - - assign cfg_dstatus = {10'h0, - ~cfg_trn_pending_n, - 1'b0, - cfg_dev_status_ur_detected, - cfg_dev_status_fatal_err_detected, - cfg_dev_status_nonfatal_err_detected, - cfg_dev_status_corr_err_detected}; - - assign cfg_dcommand = {1'b0, - cfg_dev_control_max_read_req, - cfg_dev_control_nosnoop_en, - cfg_dev_control_aux_power_en, - cfg_dev_control_phantom_en, - cfg_dev_control_ext_tag_en, - cfg_dev_control_maxpayload, - cfg_dev_control_enable_relaxed_order, - cfg_dev_control_ur_err_reporting_en, - cfg_dev_control_fatal_err_reporting_en, - cfg_dev_control_non_fatal_reporting_en, - cfg_dev_control_corr_err_reporting_en }; - - assign cfg_lstatus = {cfg_link_status_autobandwidth_status, - cfg_link_status_bandwidth_status, - cfg_link_status_dll_active, - (LINK_STATUS_SLOT_CLOCK_CONFIG == "TRUE") ? 1'b1 : 1'b0, - cfg_link_status_link_training, - 1'b0, - {2'b00, cfg_link_status_negotiated_link_width}, - {2'b00, cfg_link_status_current_speed} }; - - assign cfg_lcommand = {cfg_link_control_auto_bandwidth_int_en, - cfg_link_control_bandwidth_int_en, - cfg_link_control_hw_auto_width_dis, - cfg_link_control_clock_pm_en, - cfg_link_control_extended_sync, - cfg_link_control_common_clock, - cfg_link_control_retrain_link, - cfg_link_control_linkdisable, - cfg_link_control_rcb, - 1'b0, - cfg_link_control_aspm_control}; - - assign cfg_bus_number = cfg_bus_number_d; - - assign cfg_device_number = cfg_device_number_d; - - assign cfg_function_number = cfg_function_number_d; - - assign cfg_dcommand2 = {11'b0, - cfg_dev_control2_cpltimeout_dis, - cfg_dev_control2_cpltimeout_val}; - - // Capture Bus/Device/Function number - - always @(posedge trn_clk) begin - if (trn_lnk_up_n) cfg_bus_number_d <= 8'b0; - else if (~cfg_msg_received) cfg_bus_number_d <= cfg_msg_data[15:8]; - end - - always @(posedge trn_clk) begin - if (trn_lnk_up_n) cfg_device_number_d <= 5'b0; - else if (~cfg_msg_received) cfg_device_number_d <= cfg_msg_data[7:3]; - end - - always @(posedge trn_clk) begin - if (trn_lnk_up_n) cfg_function_number_d <= 3'b0; - else if (~cfg_msg_received) cfg_function_number_d <= cfg_msg_data[2:0]; - end - - // Generate trn_lnk_up_n - -FDCP #( - - .INIT(1'b1) - -) trn_lnk_up_n_i ( - - .Q (trn_lnk_up_n), - .D (trn_lnk_up_n_int1), - .C (trn_clk), - .CLR (1'b0), - .PRE (1'b0) - -); - -FDCP #( - - .INIT(1'b1) - -) trn_lnk_up_n_int_i ( - - .Q (trn_lnk_up_n_int1), - .D (trn_lnk_up_n_int), - .C (trn_clk), - .CLR (1'b0), - .PRE (1'b0) - -); - - // Generate trn_reset_n - -FDCP #( - - .INIT(1'b0) - -) trn_reset_n_i ( - - .Q (trn_reset_n), - .D (trn_reset_n_int1 & ~phy_rdy_n), - .C (trn_clk), - .CLR (~sys_reset_n_d), - .PRE (1'b0) - -); - -FDCP #( - - .INIT(1'b0) - -) trn_reset_n_int_i ( - - .Q (trn_reset_n_int1 ), - .D (trn_reset_n_int & ~phy_rdy_n), - .C (trn_clk), - .CLR (~sys_reset_n_d), - .PRE (1'b0) - -); - - - -//------------------------------------------------------- -// PCI Express Reset Delay Module -//------------------------------------------------------- - -pcie_reset_delay_v6 #( - - .PL_FAST_TRAIN ( PL_FAST_TRAIN ), - .REF_CLK_FREQ ( REF_CLK_FREQ ) - -) -pcie_reset_delay_i ( - - .ref_clk ( sys_clk_bufg ), - .sys_reset_n ( sys_reset_n ), - .delayed_sys_reset_n ( sys_reset_n_d ) - -); - -//------------------------------------------------------- -// PCI Express Clocking Module -//------------------------------------------------------- - -pcie_clocking_v6 #( - - .CAP_LINK_WIDTH(LINK_CAP_MAX_LINK_WIDTH), - .CAP_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED), - .REF_CLK_FREQ(REF_CLK_FREQ), - .USER_CLK_FREQ(USER_CLK_FREQ) - -) -pcie_clocking_i ( - - .sys_clk ( sys_clk ), - .gt_pll_lock ( gt_pll_lock ), - .sel_lnk_rate ( pl_sel_link_rate ), - .sel_lnk_width ( pl_sel_link_width ), - - .sys_clk_bufg ( sys_clk_bufg ), - .pipe_clk ( pipe_clk ), - .user_clk ( user_clk ), - .block_clk ( block_clk ), - .clock_locked ( clock_locked ) - -); - -//------------------------------------------------------- -// Virtex6 PCI Express Block Module -//------------------------------------------------------- - -pcie_2_0_v6 #( - - .REF_CLK_FREQ ( REF_CLK_FREQ ), - .PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES ), - .AER_BASE_PTR ( AER_BASE_PTR ), - .AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ), - .AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ), - .AER_CAP_ID ( AER_CAP_ID ), - .AER_CAP_INT_MSG_NUM_MSI ( AER_CAP_INT_MSG_NUM_MSI ), - .AER_CAP_INT_MSG_NUM_MSIX ( AER_CAP_INT_MSG_NUM_MSIX ), - .AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ), - .AER_CAP_ON ( AER_CAP_ON ), - .AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ), - .AER_CAP_VERSION ( AER_CAP_VERSION ), - .ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ), - .BAR0 ( BAR0 ), - .BAR1 ( BAR1 ), - .BAR2 ( BAR2 ), - .BAR3 ( BAR3 ), - .BAR4 ( BAR4 ), - .BAR5 ( BAR5 ), - .CAPABILITIES_PTR ( CAPABILITIES_PTR ), - .CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ), - .CLASS_CODE ( CLASS_CODE ), - .CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ), - .CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ), - .CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ), - .CRM_MODULE_RSTS ( CRM_MODULE_RSTS ), - .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ), - .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ), - .DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ), - .DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ), - .DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ), - .DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ), - .DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ), - .DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ), - .DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ), - .DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ), - .DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ), - .DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ), - .DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ), - .DEVICE_ID ( DEVICE_ID ), - .DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ), - .DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ), - .DISABLE_ID_CHECK ( DISABLE_ID_CHECK ), - .DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ), - .DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ), - .DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ), - .DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ), - .DSN_BASE_PTR ( DSN_BASE_PTR ), - .DSN_CAP_ID ( DSN_CAP_ID ), - .DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ), - .DSN_CAP_ON ( DSN_CAP_ON ), - .DSN_CAP_VERSION ( DSN_CAP_VERSION ), - .ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ), - .ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ), - .ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ), - .EXPANSION_ROM ( EXPANSION_ROM ), - .EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ), - .EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ), - .HEADER_TYPE ( HEADER_TYPE ), - .INFER_EI ( INFER_EI ), - .INTERRUPT_PIN ( INTERRUPT_PIN ), - .IS_SWITCH ( IS_SWITCH ), - .LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ), - .LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ), - .LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ), - .LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ), - .LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ), - .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ), - .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ), - .LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ), - .LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ), - .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ), - .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ), - .LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ), - .LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ), - .LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ), - .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ), - .LINK_CAP_RSVD_23_22 ( LINK_CAP_RSVD_23_22 ), - .LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ), - .LINK_CONTROL_RCB ( LINK_CONTROL_RCB ), - .LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ), - .LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ), - .LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ), - .LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ), - .LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ), - .LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ), - .LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ), - .LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ), - .LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ), - .LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ), - .LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ), - .MSI_BASE_PTR ( MSI_BASE_PTR ), - .MSI_CAP_ID ( MSI_CAP_ID ), - .MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ), - .MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ), - .MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ), - .MSI_CAP_ON ( MSI_CAP_ON ), - .MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ), - .MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ), - .MSIX_BASE_PTR ( MSIX_BASE_PTR ), - .MSIX_CAP_ID ( MSIX_CAP_ID ), - .MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ), - .MSIX_CAP_ON ( MSIX_CAP_ON ), - .MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ), - .MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ), - .MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ), - .MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ), - .MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ), - .N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ), - .N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ), - .N_FTS_GEN1 ( N_FTS_GEN1 ), - .N_FTS_GEN2 ( N_FTS_GEN2 ), - .PCIE_BASE_PTR ( PCIE_BASE_PTR ), - .PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ), - .PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ), - .PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ), - .PCIE_CAP_INT_MSG_NUM ( PCIE_CAP_INT_MSG_NUM ), - .PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ), - .PCIE_CAP_ON ( PCIE_CAP_ON ), - .PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ), - .PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ), - .PCIE_REVISION ( PCIE_REVISION ), - .PGL0_LANE ( PGL0_LANE ), - .PGL1_LANE ( PGL1_LANE ), - .PGL2_LANE ( PGL2_LANE ), - .PGL3_LANE ( PGL3_LANE ), - .PGL4_LANE ( PGL4_LANE ), - .PGL5_LANE ( PGL5_LANE ), - .PGL6_LANE ( PGL6_LANE ), - .PGL7_LANE ( PGL7_LANE ), - .PL_AUTO_CONFIG ( PL_AUTO_CONFIG ), - .PL_FAST_TRAIN ( PL_FAST_TRAIN ), - .PM_BASE_PTR ( PM_BASE_PTR ), - .PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ), - .PM_CAP_DSI ( PM_CAP_DSI ), - .PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ), - .PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ), - .PM_CAP_ID ( PM_CAP_ID ), - .PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ), - .PM_CAP_ON ( PM_CAP_ON ), - .PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ), - .PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ), - .PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ), - .PM_CAP_VERSION ( PM_CAP_VERSION ), - .PM_CSR_BPCCEN ( PM_CSR_BPCCEN ), - .PM_CSR_B2B3 ( PM_CSR_B2B3 ), - .PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ), - .PM_DATA_SCALE0 ( PM_DATA_SCALE0 ), - .PM_DATA_SCALE1 ( PM_DATA_SCALE1 ), - .PM_DATA_SCALE2 ( PM_DATA_SCALE2 ), - .PM_DATA_SCALE3 ( PM_DATA_SCALE3 ), - .PM_DATA_SCALE4 ( PM_DATA_SCALE4 ), - .PM_DATA_SCALE5 ( PM_DATA_SCALE5 ), - .PM_DATA_SCALE6 ( PM_DATA_SCALE6 ), - .PM_DATA_SCALE7 ( PM_DATA_SCALE7 ), - .PM_DATA0 ( PM_DATA0 ), - .PM_DATA1 ( PM_DATA1 ), - .PM_DATA2 ( PM_DATA2 ), - .PM_DATA3 ( PM_DATA3 ), - .PM_DATA4 ( PM_DATA4 ), - .PM_DATA5 ( PM_DATA5 ), - .PM_DATA6 ( PM_DATA6 ), - .PM_DATA7 ( PM_DATA7 ), - .RECRC_CHK ( RECRC_CHK ), - .RECRC_CHK_TRIM ( RECRC_CHK_TRIM ), - .REVISION_ID ( REVISION_ID ), - .ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ), - .SELECT_DLL_IF ( SELECT_DLL_IF ), - .SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ), - .SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ), - .SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ), - .SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ), - .SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ), - .SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ), - .SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ), - .SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ), - .SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ), - .SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ), - .SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ), - .SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ), - .SPARE_BIT0 ( SPARE_BIT0 ), - .SPARE_BIT1 ( SPARE_BIT1 ), - .SPARE_BIT2 ( SPARE_BIT2 ), - .SPARE_BIT3 ( SPARE_BIT3 ), - .SPARE_BIT4 ( SPARE_BIT4 ), - .SPARE_BIT5 ( SPARE_BIT5 ), - .SPARE_BIT6 ( SPARE_BIT6 ), - .SPARE_BIT7 ( SPARE_BIT7 ), - .SPARE_BIT8 ( SPARE_BIT8 ), - .SPARE_BYTE0 ( SPARE_BYTE0 ), - .SPARE_BYTE1 ( SPARE_BYTE1 ), - .SPARE_BYTE2 ( SPARE_BYTE2 ), - .SPARE_BYTE3 ( SPARE_BYTE3 ), - .SPARE_WORD0 ( SPARE_WORD0 ), - .SPARE_WORD1 ( SPARE_WORD1 ), - .SPARE_WORD2 ( SPARE_WORD2 ), - .SPARE_WORD3 ( SPARE_WORD3 ), - .SUBSYSTEM_ID ( SUBSYSTEM_ID ), - .SUBSYSTEM_VENDOR_ID ( SUBSYSTEM_VENDOR_ID ), - .TL_RBYPASS ( TL_RBYPASS ), - .TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ), - .TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ), - .TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ), - .TL_TFC_DISABLE ( TL_TFC_DISABLE ), - .TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ), - .TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ), - .TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ), - .TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ), - .UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ), - .UPSTREAM_FACING ( UPSTREAM_FACING ), - .EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ), - .UR_INV_REQ ( UR_INV_REQ ), - .USER_CLK_FREQ ( USER_CLK_FREQ ), - .VC_BASE_PTR ( VC_BASE_PTR ), - .VC_CAP_ID ( VC_CAP_ID ), - .VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ), - .VC_CAP_ON ( VC_CAP_ON ), - .VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ), - .VC_CAP_VERSION ( VC_CAP_VERSION ), - .VC0_CPL_INFINITE ( VC0_CPL_INFINITE ), - .VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ), - .VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ), - .VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ), - .VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ), - .VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ), - .VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ), - .VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ), - .VENDOR_ID ( VENDOR_ID ), - .VSEC_BASE_PTR ( VSEC_BASE_PTR ), - .VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ), - .VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ), - .VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ), - .VSEC_CAP_ID ( VSEC_CAP_ID ), - .VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ), - .VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ), - .VSEC_CAP_ON ( VSEC_CAP_ON ), - .VSEC_CAP_VERSION ( VSEC_CAP_VERSION ) - -) -pcie_2_0_i ( - - .PCIEXPRXN( pci_exp_rxn ), - .PCIEXPRXP( pci_exp_rxp ), - .PCIEXPTXN( pci_exp_txn ), - .PCIEXPTXP( pci_exp_txp ), - - .SYSCLK( sys_clk ), - .TRNLNKUPN( trn_lnk_up_n_int ), - .TRNCLK( trn_clk ), - - .FUNDRSTN (sys_reset_n_d), - .PHYRDYN( phy_rdy_n ), - - .LNKCLKEN ( lnk_clk_en ), - .USERRSTN( trn_reset_n_int ), - .RECEIVEDFUNCLVLRSTN( rx_func_level_reset_n ), - .SYSRSTN( ~phy_rdy_n ), - .PLRSTN( 1'b1 ), - .DLRSTN( 1'b1 ), - .TLRSTN( 1'b1 ), - .FUNCLVLRSTN( 1'b1 ), - .CMRSTN( 1'b1 ), - .CMSTICKYRSTN( 1'b1 ), - - .TRNRBARHITN( trn_rbar_hit_n ), - .TRNRD( trn_rd ), - .TRNRECRCERRN( ), - .TRNREOFN( trn_reof_n ), - .TRNRERRFWDN( trn_rerrfwd_n ), - .TRNRREMN( trn_rrem_n ), - .TRNRSOFN( trn_rsof_n ), - .TRNRSRCDSCN( trn_rsrc_dsc_n ), - .TRNRSRCRDYN( trn_rsrc_rdy_n ), - .TRNRDSTRDYN( trn_rdst_rdy_n ), - .TRNRNPOKN( trn_rnp_ok_n ), - - .TRNTBUFAV( trn_tbuf_av ), - .TRNTCFGREQN( trn_tcfg_req_n ), - .TRNTDLLPDSTRDYN( ), - .TRNTDSTRDYN( trn_tdst_rdy_n ), - .TRNTERRDROPN( trn_terr_drop_n ), - .TRNTCFGGNTN( trn_tcfg_gnt_n ), - .TRNTD( trn_td ), - .TRNTDLLPDATA( 32'b0 ), - .TRNTDLLPSRCRDYN( 1'b1 ), - .TRNTECRCGENN( 1'b1 ), - .TRNTEOFN( trn_teof_n ), - .TRNTERRFWDN( trn_terrfwd_n ), - .TRNTREMN( trn_trem_n ), - .TRNTSOFN( trn_tsof_n ), - .TRNTSRCDSCN( trn_tsrc_dsc_n ), - .TRNTSRCRDYN( trn_tsrc_rdy_n ), - .TRNTSTRN( trn_tstr_n ), - - .TRNFCCPLD( trn_fc_cpld ), - .TRNFCCPLH( trn_fc_cplh ), - .TRNFCNPD( trn_fc_npd ), - .TRNFCNPH( trn_fc_nph ), - .TRNFCPD( trn_fc_pd ), - .TRNFCPH( trn_fc_ph ), - .TRNFCSEL( trn_fc_sel ), - - .CFGAERECRCCHECKEN(), - .CFGAERECRCGENEN(), - .CFGCOMMANDBUSMASTERENABLE( cfg_cmd_bme ), - .CFGCOMMANDINTERRUPTDISABLE( cfg_cmd_intdis ), - .CFGCOMMANDIOENABLE( cfg_cmd_io_en ), - .CFGCOMMANDMEMENABLE( cfg_cmd_mem_en ), - .CFGCOMMANDSERREN( cfg_cmd_serr_en ), - .CFGDEVCONTROLAUXPOWEREN( cfg_dev_control_aux_power_en ), - .CFGDEVCONTROLCORRERRREPORTINGEN( cfg_dev_control_corr_err_reporting_en ), - .CFGDEVCONTROLENABLERO( cfg_dev_control_enable_relaxed_order ), - .CFGDEVCONTROLEXTTAGEN( cfg_dev_control_ext_tag_en ), - .CFGDEVCONTROLFATALERRREPORTINGEN( cfg_dev_control_fatal_err_reporting_en ), - .CFGDEVCONTROLMAXPAYLOAD( cfg_dev_control_maxpayload ), - .CFGDEVCONTROLMAXREADREQ( cfg_dev_control_max_read_req ), - .CFGDEVCONTROLNONFATALREPORTINGEN( cfg_dev_control_non_fatal_reporting_en ), - .CFGDEVCONTROLNOSNOOPEN( cfg_dev_control_nosnoop_en ), - .CFGDEVCONTROLPHANTOMEN( cfg_dev_control_phantom_en ), - .CFGDEVCONTROLURERRREPORTINGEN( cfg_dev_control_ur_err_reporting_en ), - .CFGDEVCONTROL2CPLTIMEOUTDIS( cfg_dev_control2_cpltimeout_dis ), - .CFGDEVCONTROL2CPLTIMEOUTVAL( cfg_dev_control2_cpltimeout_val ), - .CFGDEVSTATUSCORRERRDETECTED( cfg_dev_status_corr_err_detected ), - .CFGDEVSTATUSFATALERRDETECTED( cfg_dev_status_fatal_err_detected ), - .CFGDEVSTATUSNONFATALERRDETECTED( cfg_dev_status_nonfatal_err_detected ), - .CFGDEVSTATUSURDETECTED( cfg_dev_status_ur_detected ), - .CFGDO( cfg_do ), - .CFGERRAERHEADERLOGSETN(), - .CFGERRCPLRDYN( cfg_err_cpl_rdy_n ), - .CFGINTERRUPTDO( cfg_interrupt_do ), - .CFGINTERRUPTMMENABLE( cfg_interrupt_mmenable ), - .CFGINTERRUPTMSIENABLE( cfg_interrupt_msienable ), - .CFGINTERRUPTMSIXENABLE( cfg_interrupt_msixenable ), - .CFGINTERRUPTMSIXFM( cfg_interrupt_msixfm ), - .CFGINTERRUPTRDYN( cfg_interrupt_rdy_n ), - .CFGLINKCONTROLRCB( cfg_link_control_rcb ), - .CFGLINKCONTROLASPMCONTROL( cfg_link_control_aspm_control ), - .CFGLINKCONTROLAUTOBANDWIDTHINTEN( cfg_link_control_auto_bandwidth_int_en ), - .CFGLINKCONTROLBANDWIDTHINTEN( cfg_link_control_bandwidth_int_en ), - .CFGLINKCONTROLCLOCKPMEN( cfg_link_control_clock_pm_en ), - .CFGLINKCONTROLCOMMONCLOCK( cfg_link_control_common_clock ), - .CFGLINKCONTROLEXTENDEDSYNC( cfg_link_control_extended_sync ), - .CFGLINKCONTROLHWAUTOWIDTHDIS( cfg_link_control_hw_auto_width_dis ), - .CFGLINKCONTROLLINKDISABLE( cfg_link_control_linkdisable ), - .CFGLINKCONTROLRETRAINLINK( cfg_link_control_retrain_link ), - .CFGLINKSTATUSAUTOBANDWIDTHSTATUS( cfg_link_status_autobandwidth_status ), - .CFGLINKSTATUSBANDWITHSTATUS( cfg_link_status_bandwidth_status ), - .CFGLINKSTATUSCURRENTSPEED( cfg_link_status_current_speed ), - .CFGLINKSTATUSDLLACTIVE( cfg_link_status_dll_active ), - .CFGLINKSTATUSLINKTRAINING( cfg_link_status_link_training ), - .CFGLINKSTATUSNEGOTIATEDWIDTH( cfg_link_status_negotiated_link_width ), - .CFGMSGDATA( cfg_msg_data ), - .CFGMSGRECEIVED( cfg_msg_received ), - .CFGMSGRECEIVEDASSERTINTA(), - .CFGMSGRECEIVEDASSERTINTB(), - .CFGMSGRECEIVEDASSERTINTC(), - .CFGMSGRECEIVEDASSERTINTD(), - .CFGMSGRECEIVEDDEASSERTINTA(), - .CFGMSGRECEIVEDDEASSERTINTB(), - .CFGMSGRECEIVEDDEASSERTINTC(), - .CFGMSGRECEIVEDDEASSERTINTD(), - .CFGMSGRECEIVEDERRCOR(), - .CFGMSGRECEIVEDERRFATAL(), - .CFGMSGRECEIVEDERRNONFATAL(), - .CFGMSGRECEIVEDPMASNAK(), - .CFGMSGRECEIVEDPMETO( cfg_msg_received_pme_to ), - .CFGMSGRECEIVEDPMETOACK(), - .CFGMSGRECEIVEDPMPME(), - .CFGMSGRECEIVEDSETSLOTPOWERLIMIT(), - .CFGMSGRECEIVEDUNLOCK(), - .CFGPCIELINKSTATE( cfg_pcie_link_state_n ), - .CFGPMCSRPMEEN ( cfg_pmcsr_pme_en ), - .CFGPMCSRPMESTATUS ( cfg_pmcsr_pme_status ), - .CFGPMCSRPOWERSTATE ( cfg_pmcsr_powerstate ), - .CFGPMRCVASREQL1N(), - .CFGPMRCVENTERL1N(), - .CFGPMRCVENTERL23N(), - .CFGPMRCVREQACKN(), - .CFGRDWRDONEN( cfg_rd_wr_done_n ), - .CFGSLOTCONTROLELECTROMECHILCTLPULSE(), - .CFGTRANSACTION(), - .CFGTRANSACTIONADDR(), - .CFGTRANSACTIONTYPE(), - .CFGVCTCVCMAP(), - .CFGBYTEENN( cfg_byte_en_n ), - .CFGDI( cfg_di ), - .CFGDSBUSNUMBER( 8'b0 ), - .CFGDSDEVICENUMBER( 5'b0 ), - .CFGDSFUNCTIONNUMBER( 3'b0 ), - .CFGDSN( cfg_dsn ), - .CFGDWADDR( cfg_dwaddr ), - .CFGERRACSN( 1'b1 ), - .CFGERRAERHEADERLOG( 128'h0 ), - .CFGERRCORN( cfg_err_cor_n ), - .CFGERRCPLABORTN( cfg_err_cpl_abort_n ), - .CFGERRCPLTIMEOUTN( cfg_err_cpl_timeout_n ), - .CFGERRCPLUNEXPECTN( cfg_err_cpl_unexpect_n ), - .CFGERRECRCN( cfg_err_ecrc_n ), - .CFGERRLOCKEDN( cfg_err_locked_n ), - .CFGERRPOSTEDN( cfg_err_posted_n ), - .CFGERRTLPCPLHEADER( cfg_err_tlp_cpl_header ), - .CFGERRURN( cfg_err_ur_n ), - .CFGINTERRUPTASSERTN( cfg_interrupt_assert_n ), - .CFGINTERRUPTDI( cfg_interrupt_di ), - .CFGINTERRUPTN( cfg_interrupt_n ), - .CFGPMDIRECTASPML1N( 1'b1 ), - .CFGPMSENDPMACKN( 1'b1 ), - .CFGPMSENDPMETON( 1'b1 ), - .CFGPMSENDPMNAKN( 1'b1 ), - .CFGPMTURNOFFOKN( cfg_turnoff_ok_n ), - .CFGPMWAKEN( cfg_pm_wake_n ), - .CFGPORTNUMBER( 8'h0 ), - .CFGRDENN( cfg_rd_en_n ), - .CFGTRNPENDINGN( cfg_trn_pending_n ), - .CFGWRENN( cfg_wr_en_n ), - .CFGWRREADONLYN( 1'b1 ), - .CFGWRRW1CASRWN( 1'b1 ), - - .PLINITIALLINKWIDTH( pl_initial_link_width ), - .PLLANEREVERSALMODE( pl_lane_reversal_mode ), - .PLLINKGEN2CAP( pl_link_gen2_capable ), - .PLLINKPARTNERGEN2SUPPORTED( pl_link_partner_gen2_supported ), - .PLLINKUPCFGCAP( pl_link_upcfg_capable ), - .PLLTSSMSTATE( pl_ltssm_state ), - .PLPHYLNKUPN( ), // Debug - .PLRECEIVEDHOTRST( pl_received_hot_rst ), - .PLRXPMSTATE(), // Debug - .PLSELLNKRATE( pl_sel_link_rate ), - .PLSELLNKWIDTH( pl_sel_link_width ), - .PLTXPMSTATE(), // Debug - .PLDIRECTEDLINKAUTON( pl_directed_link_auton ), - .PLDIRECTEDLINKCHANGE( pl_directed_link_change ), - .PLDIRECTEDLINKSPEED( pl_directed_link_speed ), - .PLDIRECTEDLINKWIDTH( pl_directed_link_width ), - .PLDOWNSTREAMDEEMPHSOURCE( 1'b0 ), - .PLUPSTREAMPREFERDEEMPH( pl_upstream_prefer_deemph ), - .PLTRANSMITHOTRST( 1'b0 ), - - .DBGSCLRA(), - .DBGSCLRB(), - .DBGSCLRC(), - .DBGSCLRD(), - .DBGSCLRE(), - .DBGSCLRF(), - .DBGSCLRG(), - .DBGSCLRH(), - .DBGSCLRI(), - .DBGSCLRJ(), - .DBGSCLRK(), - .DBGVECA(), - .DBGVECB(), - .DBGVECC(), - .PLDBGVEC(), - .DBGMODE( 2'b0 ), - .DBGSUBMODE( 1'b0 ), - .PLDBGMODE( 3'b0 ), - - .DRPDO(), - .DRPDRDY(), - .DRPCLK(1'b0), - .DRPDADDR(9'b0), - .DRPDEN(1'b0), - .DRPDI(16'b0), - .DRPDWE(1'b0), - - .GTPLLLOCK( gt_pll_lock ), - .PIPECLK( pipe_clk ), - .USERCLK( user_clk ), - .CLOCKLOCKED( clock_locked ) - - -); - -endmodule Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_clocking_v6.v =================================================================== --- branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_clocking_v6.v (revision 9) +++ branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_clocking_v6.v (nonexistent) @@ -1,282 +0,0 @@ -//----------------------------------------------------------------------------- -// -// (c) Copyright 2009 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information of Xilinx, Inc. -// and is protected under U.S. and international copyright and other -// intellectual property laws. -// -// DISCLAIMER -// -// This disclaimer is not a license and does not grant any rights to the -// materials distributed herewith. Except as otherwise provided in a valid -// license issued to you by Xilinx, and to the maximum extent permitted by -// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -// and (2) Xilinx shall not be liable (whether in contract or tort, including -// negligence, or under any other theory of liability) for any loss or damage -// of any kind or nature related to, arising under or in connection with these -// materials, including for any direct, or any indirect, special, incidental, -// or consequential loss or damage (including loss of data, profits, goodwill, -// or any type of loss or damage suffered as a result of any action brought by -// a third party) even if such damage or loss was reasonably foreseeable or -// Xilinx had been advised of the possibility of the same. -// -// CRITICAL APPLICATIONS -// -// Xilinx products are not designed or intended to be fail-safe, or for use in -// any application requiring fail-safe performance, such as life-support or -// safety devices or systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any other -// applications that could lead to death, personal injury, or severe property -// or environmental damage (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and liability of any use of -// Xilinx products in Critical Applications, subject only to applicable laws -// and regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -// AT ALL TIMES. -// -//----------------------------------------------------------------------------- -// Project : Virtex-6 Integrated Block for PCI Express -// File : pcie_clocking_v6.v -//-- Description: Clocking module for Virtex6 PCIe Block -//-- -//-- -//-- -//-------------------------------------------------------------------------------- - -`timescale 1ns/1ns - -module pcie_clocking_v6 # ( - - parameter CAP_LINK_WIDTH = 8, // 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8 - parameter CAP_LINK_SPEED = 4'h1, // 1 - Gen1 , 2 - Gen2 - parameter REF_CLK_FREQ = 0, // 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz - parameter USER_CLK_FREQ = 3 // 0 - 31.25 MHz , 1 - 62.5 MHz , 2 - 125 MHz , 3 - 250 MHz , 4 - 500Mhz - -) -( - - input wire sys_clk, - input wire gt_pll_lock, - input wire sel_lnk_rate, - input wire [1:0] sel_lnk_width, - - output wire sys_clk_bufg, - output wire pipe_clk, - output wire user_clk, - output wire block_clk, - output wire clock_locked - -); - - - wire mmcm_locked; - wire mmcm_clkfbin; - wire mmcm_clkfbout; - wire clk_500; - wire clk_250; - wire clk_125; - wire user_clk_prebuf; - wire sel_lnk_rate_d; - - assign clock_locked = mmcm_locked; - - // MMCM Configuration - - - localparam mmcm_clockin_period = (REF_CLK_FREQ == 0) ? 10 : - (REF_CLK_FREQ == 1) ? 8 : - (REF_CLK_FREQ == 2) ? 4 : 0; - - localparam mmcm_clockfb_mult = (REF_CLK_FREQ == 0) ? 10 : - (REF_CLK_FREQ == 1) ? 8 : - (REF_CLK_FREQ == 2) ? 8 : 0; - - - localparam mmcm_divclk_divide = (REF_CLK_FREQ == 0) ? 1 : - (REF_CLK_FREQ == 1) ? 1 : - (REF_CLK_FREQ == 2) ? 2 : 0; - - localparam mmcm_clock0_div = 4; - localparam mmcm_clock1_div = 8; - localparam mmcm_clock2_div = ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 0)) ? 32 : - ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 1)) ? 16 : - ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 1)) ? 16 : - ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 1)) ? 16 : 2; - localparam mmcm_clock3_div = 2; - generate - - // PIPE Clock BUFG. - - if (CAP_LINK_SPEED == 4'h1) begin : GEN1_LINK - - BUFG pipe_clk_bufg (.O(pipe_clk),.I(clk_125)); - - end else if (CAP_LINK_SPEED == 4'h2) begin : GEN2_LINK - - SRL16E #(.INIT(0)) sel_lnk_rate_delay (.Q(sel_lnk_rate_d), - .D(sel_lnk_rate), .CLK(pipe_clk),.CE(mmcm_locked), .A3(1'b1),.A2(1'b1),.A1(1'b1),.A0(1'b1)); - - BUFGMUX pipe_clk_bufgmux (.O(pipe_clk), .I0(clk_125),.I1(clk_250),.S(sel_lnk_rate_d)); - - end else begin : ILLEGAL_LINK_SPEED - - //$display("Confiuration Error : CAP_LINK_SPEED = %d, must be either 1 or 2.", CAP_LINK_SPEED); - //$finish; - - end - - // User Clock BUFG. - - if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 0)) begin : x1_GEN1_31_25 - - BUFG user_clk_bufg (.O(user_clk),.I(user_clk_prebuf)); - - end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 1)) begin : x1_GEN1_62_50 - - BUFG user_clk_bufg (.O(user_clk),.I(user_clk_prebuf)); - - end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 2)) begin : x1_GEN1_125_00 - - BUFG user_clk_bufg (.O(user_clk),.I(clk_125)); - - end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 3)) begin : x1_GEN1_250_00 - - BUFG user_clk_bufg (.O(user_clk),.I(clk_250)); - - end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 1)) begin : x1_GEN2_62_50 - - BUFG user_clk_bufg (.O(user_clk),.I(user_clk_prebuf)); - - end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 2)) begin : x1_GEN2_125_00 - - BUFG user_clk_bufg (.O(user_clk),.I(clk_125)); - - end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 3)) begin : x1_GEN2_250_00 - - BUFG user_clk_bufg (.O(user_clk),.I(clk_250)); - - end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 1)) begin : x2_GEN1_62_50 - - BUFG user_clk_bufg (.O(user_clk),.I(user_clk_prebuf)); - - end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 2)) begin : x2_GEN1_125_00 - - BUFG user_clk_bufg (.O(user_clk),.I(clk_125)); - - end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 3)) begin : x2_GEN1_250_00 - - BUFG user_clk_bufg (.O(user_clk),.I(clk_250)); - - end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 2)) begin : x2_GEN2_125_00 - - BUFG user_clk_bufg (.O(user_clk),.I(clk_125)); - - end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 3)) begin : x2_GEN2_250_00 - - BUFG user_clk_bufg (.O(user_clk),.I(clk_250)); - - end else if ((CAP_LINK_WIDTH == 6'h04) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 2)) begin : x4_GEN1_125_00 - - BUFG user_clk_bufg (.O(user_clk),.I(clk_125)); - - end else if ((CAP_LINK_WIDTH == 6'h04) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 3)) begin : x4_GEN1_250_00 - - BUFG user_clk_bufg (.O(user_clk),.I(clk_250)); - - end else if ((CAP_LINK_WIDTH == 6'h04) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 3)) begin : x4_GEN2_250_00 - - BUFG user_clk_bufg (.O(user_clk),.I(clk_250)); - - end else if ((CAP_LINK_WIDTH == 6'h08) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 3)) begin : x8_GEN1_250_00 - - BUFG user_clk_bufg (.O(user_clk),.I(clk_250)); - - end else if ((CAP_LINK_WIDTH == 6'h08) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 4)) begin : x8_GEN2_250_00 - - BUFG user_clk_bufg (.O(user_clk),.I(clk_250)); - BUFG block_clk_bufg (.O(block_clk),.I(clk_500)); - - end else begin : ILLEGAL_CONFIGURATION - - //$display("Confiuration Error : Unsupported Link Width, Link Speed and User Clock Frequency Combination"); - //$finish; - - end - - endgenerate - - // Feedback BUFG. Required for Temp Compensation - BUFG clkfbin_bufg_i (.O(mmcm_clkfbin), .I(mmcm_clkfbout)); - - // sys_clk BUFG. Required for routability from IBUFDS_GTXE1 - BUFG sys_clk_bufg_i (.O(sys_clk_bufg), .I(sys_clk)); - - MMCM_ADV # ( - - // 5 for 100 MHz , 4 for 125 MHz , 2 for 250 MHz - .CLKFBOUT_MULT_F (mmcm_clockfb_mult), - .DIVCLK_DIVIDE (mmcm_divclk_divide), - .CLKFBOUT_PHASE(0), - - // 10 for 100 MHz, 4 for 250 MHz - .CLKIN1_PERIOD (mmcm_clockin_period), - .CLKIN2_PERIOD (mmcm_clockin_period), - - // 500 MHz / mmcm_clockx_div - .CLKOUT0_DIVIDE_F (mmcm_clock0_div), - .CLKOUT0_PHASE (0), - - .CLKOUT1_DIVIDE (mmcm_clock1_div), - .CLKOUT1_PHASE (0), - - .CLKOUT2_DIVIDE (mmcm_clock2_div), - .CLKOUT2_PHASE (0), - - .CLKOUT3_DIVIDE (mmcm_clock3_div), - .CLKOUT3_PHASE (0) - - ) mmcm_adv_i ( - - .CLKFBOUT (mmcm_clkfbout), - .CLKOUT0 (clk_250), // 250 MHz for pipe_clk - .CLKOUT1 (clk_125), // 125 MHz for pipe_clk - .CLKOUT2 (user_clk_prebuf), // user clk - .CLKOUT3 (clk_500), - .CLKOUT4 (), - .CLKOUT5 (), - .CLKOUT6 (), - .DO (), - .DRDY (), - .CLKFBOUTB (), - .CLKFBSTOPPED (), - .CLKINSTOPPED (), - .CLKOUT0B (), - .CLKOUT1B (), - .CLKOUT2B (), - .CLKOUT3B (), - .PSDONE (), - .LOCKED (mmcm_locked), - .CLKFBIN (mmcm_clkfbin), - .CLKIN1 (sys_clk), - .CLKIN2 (1'b0), - .CLKINSEL (1'b1), - .DADDR (7'b0), - .DCLK (1'b0), - .DEN (1'b0), - .DI (16'b0), - .DWE (1'b0), - .PSEN (1'b0), - .PSINCDEC (1'b0), - .PWRDWN (1'b0), - .PSCLK (1'b0), - .RST (~gt_pll_lock) - ); - - -endmodule - Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_pipe_lane_v6.v =================================================================== --- branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_pipe_lane_v6.v (revision 9) +++ branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_pipe_lane_v6.v (nonexistent) @@ -1,294 +0,0 @@ -//----------------------------------------------------------------------------- -// -// (c) Copyright 2009 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information of Xilinx, Inc. -// and is protected under U.S. and international copyright and other -// intellectual property laws. -// -// DISCLAIMER -// -// This disclaimer is not a license and does not grant any rights to the -// materials distributed herewith. Except as otherwise provided in a valid -// license issued to you by Xilinx, and to the maximum extent permitted by -// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -// and (2) Xilinx shall not be liable (whether in contract or tort, including -// negligence, or under any other theory of liability) for any loss or damage -// of any kind or nature related to, arising under or in connection with these -// materials, including for any direct, or any indirect, special, incidental, -// or consequential loss or damage (including loss of data, profits, goodwill, -// or any type of loss or damage suffered as a result of any action brought by -// a third party) even if such damage or loss was reasonably foreseeable or -// Xilinx had been advised of the possibility of the same. -// -// CRITICAL APPLICATIONS -// -// Xilinx products are not designed or intended to be fail-safe, or for use in -// any application requiring fail-safe performance, such as life-support or -// safety devices or systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any other -// applications that could lead to death, personal injury, or severe property -// or environmental damage (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and liability of any use of -// Xilinx products in Critical Applications, subject only to applicable laws -// and regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -// AT ALL TIMES. -// -//----------------------------------------------------------------------------- -// Project : Virtex-6 Integrated Block for PCI Express -// File : pcie_pipe_lane_v6.v -//-- -//-- Description: PIPE per lane module for Virtex6 PCIe Block -//-- -//-- -//-- -//-------------------------------------------------------------------------------- - -`timescale 1ns/1ns - -module pcie_pipe_lane_v6 # -( - parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages -) -( - output wire [ 1:0] pipe_rx_char_is_k_o , - output wire [15:0] pipe_rx_data_o , - output wire pipe_rx_valid_o , - output wire pipe_rx_chanisaligned_o , - output wire [ 2:0] pipe_rx_status_o , - output wire pipe_rx_phy_status_o , - output wire pipe_rx_elec_idle_o , - input wire pipe_rx_polarity_i , - input wire pipe_tx_compliance_i , - input wire [ 1:0] pipe_tx_char_is_k_i , - input wire [15:0] pipe_tx_data_i , - input wire pipe_tx_elec_idle_i , - input wire [ 1:0] pipe_tx_powerdown_i , - - input wire [ 1:0] pipe_rx_char_is_k_i , - input wire [15:0] pipe_rx_data_i , - input wire pipe_rx_valid_i , - input wire pipe_rx_chanisaligned_i , - input wire [ 2:0] pipe_rx_status_i , - input wire pipe_rx_phy_status_i , - input wire pipe_rx_elec_idle_i , - output wire pipe_rx_polarity_o , - output wire pipe_tx_compliance_o , - output wire [ 1:0] pipe_tx_char_is_k_o , - output wire [15:0] pipe_tx_data_o , - output wire pipe_tx_elec_idle_o , - output wire [ 1:0] pipe_tx_powerdown_o , - - input wire pipe_clk , - input wire rst_n -); - -//******************************************************************// -// Reality check. // -//******************************************************************// - - parameter TCQ = 1; // clock to out delay model - - reg [ 1:0] pipe_rx_char_is_k_q ; - reg [15:0] pipe_rx_data_q ; - reg pipe_rx_valid_q ; - reg pipe_rx_chanisaligned_q ; - reg [ 2:0] pipe_rx_status_q ; - reg pipe_rx_phy_status_q ; - reg pipe_rx_elec_idle_q ; - - reg pipe_rx_polarity_q ; - reg pipe_tx_compliance_q ; - reg [ 1:0] pipe_tx_char_is_k_q ; - reg [15:0] pipe_tx_data_q ; - reg pipe_tx_elec_idle_q ; - reg [ 1:0] pipe_tx_powerdown_q ; - - reg [ 1:0] pipe_rx_char_is_k_qq ; - reg [15:0] pipe_rx_data_qq ; - reg pipe_rx_valid_qq ; - reg pipe_rx_chanisaligned_qq; - reg [ 2:0] pipe_rx_status_qq ; - reg pipe_rx_phy_status_qq ; - reg pipe_rx_elec_idle_qq ; - - reg pipe_rx_polarity_qq ; - reg pipe_tx_compliance_qq ; - reg [ 1:0] pipe_tx_char_is_k_qq ; - reg [15:0] pipe_tx_data_qq ; - reg pipe_tx_elec_idle_qq ; - reg [ 1:0] pipe_tx_powerdown_qq ; - - generate - - if (PIPE_PIPELINE_STAGES == 0) begin - - assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_i; - assign pipe_rx_data_o = pipe_rx_data_i; - assign pipe_rx_valid_o = pipe_rx_valid_i; - assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_i; - assign pipe_rx_status_o = pipe_rx_status_i; - assign pipe_rx_phy_status_o = pipe_rx_phy_status_i; - assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_i; - - assign pipe_rx_polarity_o = pipe_rx_polarity_i; - assign pipe_tx_compliance_o = pipe_tx_compliance_i; - assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_i; - assign pipe_tx_data_o = pipe_tx_data_i; - assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_i; - assign pipe_tx_powerdown_o = pipe_tx_powerdown_i; - - end else if (PIPE_PIPELINE_STAGES == 1) begin - - always @(posedge pipe_clk) begin - - if (rst_n) begin - - pipe_rx_char_is_k_q <= #TCQ 0; - pipe_rx_data_q <= #TCQ 0; - pipe_rx_valid_q <= #TCQ 0; - pipe_rx_chanisaligned_q <= #TCQ 0; - pipe_rx_status_q <= #TCQ 0; - pipe_rx_phy_status_q <= #TCQ 0; - pipe_rx_elec_idle_q <= #TCQ 0; - - pipe_rx_polarity_q <= #TCQ 0; - pipe_tx_compliance_q <= #TCQ 0; - pipe_tx_char_is_k_q <= #TCQ 0; - pipe_tx_data_q <= #TCQ 0; - pipe_tx_elec_idle_q <= #TCQ 1'b1; - pipe_tx_powerdown_q <= #TCQ 2'b10; - - end else begin - - pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i; - pipe_rx_data_q <= #TCQ pipe_rx_data_i; - pipe_rx_valid_q <= #TCQ pipe_rx_valid_i; - pipe_rx_chanisaligned_q <= #TCQ pipe_rx_chanisaligned_i; - pipe_rx_status_q <= #TCQ pipe_rx_status_i; - pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i; - pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i; - - pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i; - pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i; - pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i; - pipe_tx_data_q <= #TCQ pipe_tx_data_i; - pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i; - pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i; - - end - - end - - assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_q; - assign pipe_rx_data_o = pipe_rx_data_q; - assign pipe_rx_valid_o = pipe_rx_valid_q; - assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_q; - assign pipe_rx_status_o = pipe_rx_status_q; - assign pipe_rx_phy_status_o = pipe_rx_phy_status_q; - assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_q; - - assign pipe_rx_polarity_o = pipe_rx_polarity_q; - assign pipe_tx_compliance_o = pipe_tx_compliance_q; - assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_q; - assign pipe_tx_data_o = pipe_tx_data_q; - assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_q; - assign pipe_tx_powerdown_o = pipe_tx_powerdown_q; - - end else if (PIPE_PIPELINE_STAGES == 2) begin - - always @(posedge pipe_clk) begin - - if (rst_n) begin - - pipe_rx_char_is_k_q <= #TCQ 0; - pipe_rx_data_q <= #TCQ 0; - pipe_rx_valid_q <= #TCQ 0; - pipe_rx_chanisaligned_q <= #TCQ 0; - pipe_rx_status_q <= #TCQ 0; - pipe_rx_phy_status_q <= #TCQ 0; - pipe_rx_elec_idle_q <= #TCQ 0; - - pipe_rx_polarity_q <= #TCQ 0; - pipe_tx_compliance_q <= #TCQ 0; - pipe_tx_char_is_k_q <= #TCQ 0; - pipe_tx_data_q <= #TCQ 0; - pipe_tx_elec_idle_q <= #TCQ 1'b1; - pipe_tx_powerdown_q <= #TCQ 2'b10; - - pipe_rx_char_is_k_qq <= #TCQ 0; - pipe_rx_data_qq <= #TCQ 0; - pipe_rx_valid_qq <= #TCQ 0; - pipe_rx_chanisaligned_qq <= #TCQ 0; - pipe_rx_status_qq <= #TCQ 0; - pipe_rx_phy_status_qq <= #TCQ 0; - pipe_rx_elec_idle_qq <= #TCQ 0; - - pipe_rx_polarity_qq <= #TCQ 0; - pipe_tx_compliance_qq <= #TCQ 0; - pipe_tx_char_is_k_qq <= #TCQ 0; - pipe_tx_data_qq <= #TCQ 0; - pipe_tx_elec_idle_qq <= #TCQ 1'b1; - pipe_tx_powerdown_qq <= #TCQ 2'b10; - - end else begin - - pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i; - pipe_rx_data_q <= #TCQ pipe_rx_data_i; - pipe_rx_valid_q <= #TCQ pipe_rx_valid_i; - pipe_rx_chanisaligned_q <= #TCQ pipe_rx_chanisaligned_i; - pipe_rx_status_q <= #TCQ pipe_rx_status_i; - pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i; - pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i; - - pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i; - pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i; - pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i; - pipe_tx_data_q <= #TCQ pipe_tx_data_i; - pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i; - pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i; - - pipe_rx_char_is_k_qq <= #TCQ pipe_rx_char_is_k_q; - pipe_rx_data_qq <= #TCQ pipe_rx_data_q; - pipe_rx_valid_qq <= #TCQ pipe_rx_valid_q; - pipe_rx_chanisaligned_qq <= #TCQ pipe_rx_chanisaligned_q; - pipe_rx_status_qq <= #TCQ pipe_rx_status_q; - pipe_rx_phy_status_qq <= #TCQ pipe_rx_phy_status_q; - pipe_rx_elec_idle_qq <= #TCQ pipe_rx_elec_idle_q; - - pipe_rx_polarity_qq <= #TCQ pipe_rx_polarity_q; - pipe_tx_compliance_qq <= #TCQ pipe_tx_compliance_q; - pipe_tx_char_is_k_qq <= #TCQ pipe_tx_char_is_k_q; - pipe_tx_data_qq <= #TCQ pipe_tx_data_q; - pipe_tx_elec_idle_qq <= #TCQ pipe_tx_elec_idle_q; - pipe_tx_powerdown_qq <= #TCQ pipe_tx_powerdown_q; - - end - - end - - assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_qq; - assign pipe_rx_data_o = pipe_rx_data_qq; - assign pipe_rx_valid_o = pipe_rx_valid_qq; - assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_qq; - assign pipe_rx_status_o = pipe_rx_status_qq; - assign pipe_rx_phy_status_o = pipe_rx_phy_status_qq; - assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_qq; - - assign pipe_rx_polarity_o = pipe_rx_polarity_qq; - assign pipe_tx_compliance_o = pipe_tx_compliance_qq; - assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_qq; - assign pipe_tx_data_o = pipe_tx_data_qq; - assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_qq; - assign pipe_tx_powerdown_o = pipe_tx_powerdown_qq; - - end - - endgenerate - -endmodule Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_upconfig_fix_3451_v6.v =================================================================== --- branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_upconfig_fix_3451_v6.v (revision 9) +++ branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_upconfig_fix_3451_v6.v (nonexistent) @@ -1,142 +0,0 @@ -//----------------------------------------------------------------------------- -// -// (c) Copyright 2009 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information of Xilinx, Inc. -// and is protected under U.S. and international copyright and other -// intellectual property laws. -// -// DISCLAIMER -// -// This disclaimer is not a license and does not grant any rights to the -// materials distributed herewith. Except as otherwise provided in a valid -// license issued to you by Xilinx, and to the maximum extent permitted by -// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -// and (2) Xilinx shall not be liable (whether in contract or tort, including -// negligence, or under any other theory of liability) for any loss or damage -// of any kind or nature related to, arising under or in connection with these -// materials, including for any direct, or any indirect, special, incidental, -// or consequential loss or damage (including loss of data, profits, goodwill, -// or any type of loss or damage suffered as a result of any action brought by -// a third party) even if such damage or loss was reasonably foreseeable or -// Xilinx had been advised of the possibility of the same. -// -// CRITICAL APPLICATIONS -// -// Xilinx products are not designed or intended to be fail-safe, or for use in -// any application requiring fail-safe performance, such as life-support or -// safety devices or systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any other -// applications that could lead to death, personal injury, or severe property -// or environmental damage (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and liability of any use of -// Xilinx products in Critical Applications, subject only to applicable laws -// and regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -// AT ALL TIMES. -// -//----------------------------------------------------------------------------- -// Project : Virtex-6 Integrated Block for PCI Express -// File : pcie_upconfig_fix_3451_v6.v -//-- -//-- Description: Virtex6 Workaround for Root Port Upconfigurability Bug -//-- -//-- -//-------------------------------------------------------------------------------- - -`timescale 1ns/1ns - -module pcie_upconfig_fix_3451_v6 # ( - - parameter UPSTREAM_FACING = "TRUE", - parameter PL_FAST_TRAIN = "FALSE", - parameter LINK_CAP_MAX_LINK_WIDTH = 6'h08 - -) -( - - input pipe_clk, - input pl_phy_lnkup_n, - - input [5:0] pl_ltssm_state, - input pl_sel_lnk_rate, - input [1:0] pl_directed_link_change, - - input [3:0] cfg_link_status_negotiated_width, - - output filter_pipe - -); - - parameter TCQ = 1; - - reg reg_filter_pipe; - - reg [5:0] reg_prev_pl_ltssm_state; - wire [5:0] prev_pl_ltssm_state; - - reg [15:0] reg_tsx_counter; - wire [15:0] tsx_counter; - - wire [5:0] cap_link_width; - - // Corrupting all Tsx on all lanes as soon as we do R.RC->R.RI transition to allow time for - // the core to see the TS1s on all the lanes being configured at the same time - // R.RI has a 2ms timeout.Corrupting tsxs for ~1/4 of that time - // 225 pipe_clk cycles-sim_fast_train - // 60000 pipe_clk cycles-without sim_fast_train - // Not taking any action when PLDIRECTEDLINKCHANGE is set - - always @ (posedge pipe_clk) begin - - if (pl_phy_lnkup_n) begin - - reg_tsx_counter <= #TCQ 16'h0; - reg_filter_pipe <= #TCQ 1'b0; - - end else if ((pl_ltssm_state == 6'h20) && - (prev_pl_ltssm_state == 6'h1d) && - (cfg_link_status_negotiated_width != cap_link_width) && - (pl_directed_link_change[1:0] == 2'b00)) begin - - reg_tsx_counter <= #TCQ 16'h0; - reg_filter_pipe <= #TCQ 1'b1; - - end else if (filter_pipe == 1'b1) begin - - if (tsx_counter < ((PL_FAST_TRAIN == "TRUE") ? 16'd225: pl_sel_lnk_rate ? 16'd30000 : 16'd60000)) begin - - reg_tsx_counter <= #TCQ tsx_counter + 1'b1; - reg_filter_pipe <= #TCQ 1'b1; - - end else begin - - reg_tsx_counter <= #TCQ 16'h0; - reg_filter_pipe <= #TCQ 1'b0; - - end - - end - - end - - assign filter_pipe = (UPSTREAM_FACING == "TRUE") ? 1'b0 : reg_filter_pipe; - assign tsx_counter = reg_tsx_counter; - - always @(posedge pipe_clk) begin - - if (pl_phy_lnkup_n) - reg_prev_pl_ltssm_state <= #TCQ 6'h0; - else - reg_prev_pl_ltssm_state <= #TCQ pl_ltssm_state; - - end - assign prev_pl_ltssm_state = reg_prev_pl_ltssm_state; - - assign cap_link_width = LINK_CAP_MAX_LINK_WIDTH; - -endmodule Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_pipe_v6.v =================================================================== --- branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_pipe_v6.v (revision 9) +++ branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_pipe_v6.v (nonexistent) @@ -1,957 +0,0 @@ -//----------------------------------------------------------------------------- -// -// (c) Copyright 2009 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information of Xilinx, Inc. -// and is protected under U.S. and international copyright and other -// intellectual property laws. -// -// DISCLAIMER -// -// This disclaimer is not a license and does not grant any rights to the -// materials distributed herewith. Except as otherwise provided in a valid -// license issued to you by Xilinx, and to the maximum extent permitted by -// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -// and (2) Xilinx shall not be liable (whether in contract or tort, including -// negligence, or under any other theory of liability) for any loss or damage -// of any kind or nature related to, arising under or in connection with these -// materials, including for any direct, or any indirect, special, incidental, -// or consequential loss or damage (including loss of data, profits, goodwill, -// or any type of loss or damage suffered as a result of any action brought by -// a third party) even if such damage or loss was reasonably foreseeable or -// Xilinx had been advised of the possibility of the same. -// -// CRITICAL APPLICATIONS -// -// Xilinx products are not designed or intended to be fail-safe, or for use in -// any application requiring fail-safe performance, such as life-support or -// safety devices or systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any other -// applications that could lead to death, personal injury, or severe property -// or environmental damage (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and liability of any use of -// Xilinx products in Critical Applications, subject only to applicable laws -// and regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -// AT ALL TIMES. -// -//----------------------------------------------------------------------------- -// Project : Virtex-6 Integrated Block for PCI Express -// File : pcie_pipe_v6.v -//-- Description: PIPE module for Virtex6 PCIe Block -//-- -//-- -//-- -//-------------------------------------------------------------------------------- - -`timescale 1ns/1ns - -module pcie_pipe_v6 # -( - parameter NO_OF_LANES = 8, - parameter LINK_CAP_MAX_LINK_SPEED = 4'h1, - parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages -) -( - // Pipe Per-Link Signals - input wire pipe_tx_rcvr_det_i , - input wire pipe_tx_reset_i , - input wire pipe_tx_rate_i , - input wire pipe_tx_deemph_i , - input wire [2:0] pipe_tx_margin_i , - input wire pipe_tx_swing_i , - - output wire pipe_tx_rcvr_det_o , - output wire pipe_tx_reset_o , - output wire pipe_tx_rate_o , - output wire pipe_tx_deemph_o , - output wire [2:0] pipe_tx_margin_o , - output wire pipe_tx_swing_o , - - // Pipe Per-Lane Signals - Lane 0 - output wire [ 1:0] pipe_rx0_char_is_k_o , - output wire [15:0] pipe_rx0_data_o , - output wire pipe_rx0_valid_o , - output wire pipe_rx0_chanisaligned_o , - output wire [ 2:0] pipe_rx0_status_o , - output wire pipe_rx0_phy_status_o , - output wire pipe_rx0_elec_idle_o , - input wire pipe_rx0_polarity_i , - input wire pipe_tx0_compliance_i , - input wire [ 1:0] pipe_tx0_char_is_k_i , - input wire [15:0] pipe_tx0_data_i , - input wire pipe_tx0_elec_idle_i , - input wire [ 1:0] pipe_tx0_powerdown_i , - - input wire [ 1:0] pipe_rx0_char_is_k_i , - input wire [15:0] pipe_rx0_data_i , - input wire pipe_rx0_valid_i , - input wire pipe_rx0_chanisaligned_i , - input wire [ 2:0] pipe_rx0_status_i , - input wire pipe_rx0_phy_status_i , - input wire pipe_rx0_elec_idle_i , - output wire pipe_rx0_polarity_o , - output wire pipe_tx0_compliance_o , - output wire [ 1:0] pipe_tx0_char_is_k_o , - output wire [15:0] pipe_tx0_data_o , - output wire pipe_tx0_elec_idle_o , - output wire [ 1:0] pipe_tx0_powerdown_o , - - // Pipe Per-Lane Signals - Lane 1 - output wire [ 1:0] pipe_rx1_char_is_k_o , - output wire [15:0] pipe_rx1_data_o , - output wire pipe_rx1_valid_o , - output wire pipe_rx1_chanisaligned_o , - output wire [ 2:0] pipe_rx1_status_o , - output wire pipe_rx1_phy_status_o , - output wire pipe_rx1_elec_idle_o , - input wire pipe_rx1_polarity_i , - input wire pipe_tx1_compliance_i , - input wire [ 1:0] pipe_tx1_char_is_k_i , - input wire [15:0] pipe_tx1_data_i , - input wire pipe_tx1_elec_idle_i , - input wire [ 1:0] pipe_tx1_powerdown_i , - - input wire [ 1:0] pipe_rx1_char_is_k_i , - input wire [15:0] pipe_rx1_data_i , - input wire pipe_rx1_valid_i , - input wire pipe_rx1_chanisaligned_i , - input wire [ 2:0] pipe_rx1_status_i , - input wire pipe_rx1_phy_status_i , - input wire pipe_rx1_elec_idle_i , - output wire pipe_rx1_polarity_o , - output wire pipe_tx1_compliance_o , - output wire [ 1:0] pipe_tx1_char_is_k_o , - output wire [15:0] pipe_tx1_data_o , - output wire pipe_tx1_elec_idle_o , - output wire [ 1:0] pipe_tx1_powerdown_o , - - // Pipe Per-Lane Signals - Lane 2 - output wire [ 1:0] pipe_rx2_char_is_k_o , - output wire [15:0] pipe_rx2_data_o , - output wire pipe_rx2_valid_o , - output wire pipe_rx2_chanisaligned_o , - output wire [ 2:0] pipe_rx2_status_o , - output wire pipe_rx2_phy_status_o , - output wire pipe_rx2_elec_idle_o , - input wire pipe_rx2_polarity_i , - input wire pipe_tx2_compliance_i , - input wire [ 1:0] pipe_tx2_char_is_k_i , - input wire [15:0] pipe_tx2_data_i , - input wire pipe_tx2_elec_idle_i , - input wire [ 1:0] pipe_tx2_powerdown_i , - - input wire [ 1:0] pipe_rx2_char_is_k_i , - input wire [15:0] pipe_rx2_data_i , - input wire pipe_rx2_valid_i , - input wire pipe_rx2_chanisaligned_i , - input wire [ 2:0] pipe_rx2_status_i , - input wire pipe_rx2_phy_status_i , - input wire pipe_rx2_elec_idle_i , - output wire pipe_rx2_polarity_o , - output wire pipe_tx2_compliance_o , - output wire [ 1:0] pipe_tx2_char_is_k_o , - output wire [15:0] pipe_tx2_data_o , - output wire pipe_tx2_elec_idle_o , - output wire [ 1:0] pipe_tx2_powerdown_o , - - // Pipe Per-Lane Signals - Lane 3 - output wire [ 1:0] pipe_rx3_char_is_k_o , - output wire [15:0] pipe_rx3_data_o , - output wire pipe_rx3_valid_o , - output wire pipe_rx3_chanisaligned_o , - output wire [ 2:0] pipe_rx3_status_o , - output wire pipe_rx3_phy_status_o , - output wire pipe_rx3_elec_idle_o , - input wire pipe_rx3_polarity_i , - input wire pipe_tx3_compliance_i , - input wire [ 1:0] pipe_tx3_char_is_k_i , - input wire [15:0] pipe_tx3_data_i , - input wire pipe_tx3_elec_idle_i , - input wire [ 1:0] pipe_tx3_powerdown_i , - - input wire [ 1:0] pipe_rx3_char_is_k_i , - input wire [15:0] pipe_rx3_data_i , - input wire pipe_rx3_valid_i , - input wire pipe_rx3_chanisaligned_i , - input wire [ 2:0] pipe_rx3_status_i , - input wire pipe_rx3_phy_status_i , - input wire pipe_rx3_elec_idle_i , - output wire pipe_rx3_polarity_o , - output wire pipe_tx3_compliance_o , - output wire [ 1:0] pipe_tx3_char_is_k_o , - output wire [15:0] pipe_tx3_data_o , - output wire pipe_tx3_elec_idle_o , - output wire [ 1:0] pipe_tx3_powerdown_o , - - // Pipe Per-Lane Signals - Lane 4 - output wire [ 1:0] pipe_rx4_char_is_k_o , - output wire [15:0] pipe_rx4_data_o , - output wire pipe_rx4_valid_o , - output wire pipe_rx4_chanisaligned_o , - output wire [ 2:0] pipe_rx4_status_o , - output wire pipe_rx4_phy_status_o , - output wire pipe_rx4_elec_idle_o , - input wire pipe_rx4_polarity_i , - input wire pipe_tx4_compliance_i , - input wire [ 1:0] pipe_tx4_char_is_k_i , - input wire [15:0] pipe_tx4_data_i , - input wire pipe_tx4_elec_idle_i , - input wire [ 1:0] pipe_tx4_powerdown_i , - - input wire [ 1:0] pipe_rx4_char_is_k_i , - input wire [15:0] pipe_rx4_data_i , - input wire pipe_rx4_valid_i , - input wire pipe_rx4_chanisaligned_i , - input wire [ 2:0] pipe_rx4_status_i , - input wire pipe_rx4_phy_status_i , - input wire pipe_rx4_elec_idle_i , - output wire pipe_rx4_polarity_o , - output wire pipe_tx4_compliance_o , - output wire [ 1:0] pipe_tx4_char_is_k_o , - output wire [15:0] pipe_tx4_data_o , - output wire pipe_tx4_elec_idle_o , - output wire [ 1:0] pipe_tx4_powerdown_o , - - // Pipe Per-Lane Signals - Lane 5 - output wire [ 1:0] pipe_rx5_char_is_k_o , - output wire [15:0] pipe_rx5_data_o , - output wire pipe_rx5_valid_o , - output wire pipe_rx5_chanisaligned_o , - output wire [ 2:0] pipe_rx5_status_o , - output wire pipe_rx5_phy_status_o , - output wire pipe_rx5_elec_idle_o , - input wire pipe_rx5_polarity_i , - input wire pipe_tx5_compliance_i , - input wire [ 1:0] pipe_tx5_char_is_k_i , - input wire [15:0] pipe_tx5_data_i , - input wire pipe_tx5_elec_idle_i , - input wire [ 1:0] pipe_tx5_powerdown_i , - - input wire [ 1:0] pipe_rx5_char_is_k_i , - input wire [15:0] pipe_rx5_data_i , - input wire pipe_rx5_valid_i , - input wire pipe_rx5_chanisaligned_i , - input wire [ 2:0] pipe_rx5_status_i , - input wire pipe_rx5_phy_status_i , - input wire pipe_rx5_elec_idle_i , - output wire pipe_rx5_polarity_o , - output wire pipe_tx5_compliance_o , - output wire [ 1:0] pipe_tx5_char_is_k_o , - output wire [15:0] pipe_tx5_data_o , - output wire pipe_tx5_elec_idle_o , - output wire [ 1:0] pipe_tx5_powerdown_o , - - // Pipe Per-Lane Signals - Lane 6 - output wire [ 1:0] pipe_rx6_char_is_k_o , - output wire [15:0] pipe_rx6_data_o , - output wire pipe_rx6_valid_o , - output wire pipe_rx6_chanisaligned_o , - output wire [ 2:0] pipe_rx6_status_o , - output wire pipe_rx6_phy_status_o , - output wire pipe_rx6_elec_idle_o , - input wire pipe_rx6_polarity_i , - input wire pipe_tx6_compliance_i , - input wire [ 1:0] pipe_tx6_char_is_k_i , - input wire [15:0] pipe_tx6_data_i , - input wire pipe_tx6_elec_idle_i , - input wire [ 1:0] pipe_tx6_powerdown_i , - - input wire [ 1:0] pipe_rx6_char_is_k_i , - input wire [15:0] pipe_rx6_data_i , - input wire pipe_rx6_valid_i , - input wire pipe_rx6_chanisaligned_i , - input wire [ 2:0] pipe_rx6_status_i , - input wire pipe_rx6_phy_status_i , - input wire pipe_rx6_elec_idle_i , - output wire pipe_rx6_polarity_o , - output wire pipe_tx6_compliance_o , - output wire [ 1:0] pipe_tx6_char_is_k_o , - output wire [15:0] pipe_tx6_data_o , - output wire pipe_tx6_elec_idle_o , - output wire [ 1:0] pipe_tx6_powerdown_o , - - // Pipe Per-Lane Signals - Lane 7 - output wire [ 1:0] pipe_rx7_char_is_k_o , - output wire [15:0] pipe_rx7_data_o , - output wire pipe_rx7_valid_o , - output wire pipe_rx7_chanisaligned_o , - output wire [ 2:0] pipe_rx7_status_o , - output wire pipe_rx7_phy_status_o , - output wire pipe_rx7_elec_idle_o , - input wire pipe_rx7_polarity_i , - input wire pipe_tx7_compliance_i , - input wire [ 1:0] pipe_tx7_char_is_k_i , - input wire [15:0] pipe_tx7_data_i , - input wire pipe_tx7_elec_idle_i , - input wire [ 1:0] pipe_tx7_powerdown_i , - - input wire [ 1:0] pipe_rx7_char_is_k_i , - input wire [15:0] pipe_rx7_data_i , - input wire pipe_rx7_valid_i , - input wire pipe_rx7_chanisaligned_i , - input wire [ 2:0] pipe_rx7_status_i , - input wire pipe_rx7_phy_status_i , - input wire pipe_rx7_elec_idle_i , - output wire pipe_rx7_polarity_o , - output wire pipe_tx7_compliance_o , - output wire [ 1:0] pipe_tx7_char_is_k_o , - output wire [15:0] pipe_tx7_data_o , - output wire pipe_tx7_elec_idle_o , - output wire [ 1:0] pipe_tx7_powerdown_o , - - // Non PIPE signals - input wire [ 5:0] pl_ltssm_state , - input wire pipe_clk , - input wire rst_n -); - -//******************************************************************// -// Reality check. // -//******************************************************************// - - parameter Tc2o = 1; // clock to out delay model - - - wire [ 1:0] pipe_rx0_char_is_k_q ; - wire [15:0] pipe_rx0_data_q ; - wire [ 1:0] pipe_rx1_char_is_k_q ; - wire [15:0] pipe_rx1_data_q ; - wire [ 1:0] pipe_rx2_char_is_k_q ; - wire [15:0] pipe_rx2_data_q ; - wire [ 1:0] pipe_rx3_char_is_k_q ; - wire [15:0] pipe_rx3_data_q ; - wire [ 1:0] pipe_rx4_char_is_k_q ; - wire [15:0] pipe_rx4_data_q ; - wire [ 1:0] pipe_rx5_char_is_k_q ; - wire [15:0] pipe_rx5_data_q ; - wire [ 1:0] pipe_rx6_char_is_k_q ; - wire [15:0] pipe_rx6_data_q ; - wire [ 1:0] pipe_rx7_char_is_k_q ; - wire [15:0] pipe_rx7_data_q ; - -//synthesis translate_off -// initial begin -// $display("[%t] %m NO_OF_LANES %0d PIPE_PIPELINE_STAGES %0d", $time, NO_OF_LANES, PIPE_PIPELINE_STAGES); -// end -//synthesis translate_on - - generate - - pcie_pipe_misc_v6 # ( - - .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) - - ) - pipe_misc_i ( - - .pipe_tx_rcvr_det_i(pipe_tx_rcvr_det_i), - .pipe_tx_reset_i(pipe_tx_reset_i), - .pipe_tx_rate_i(pipe_tx_rate_i), - .pipe_tx_deemph_i(pipe_tx_deemph_i), - .pipe_tx_margin_i(pipe_tx_margin_i), - .pipe_tx_swing_i(pipe_tx_swing_i), - - .pipe_tx_rcvr_det_o(pipe_tx_rcvr_det_o), - .pipe_tx_reset_o(pipe_tx_reset_o), - .pipe_tx_rate_o(pipe_tx_rate_o), - .pipe_tx_deemph_o(pipe_tx_deemph_o), - .pipe_tx_margin_o(pipe_tx_margin_o), - .pipe_tx_swing_o(pipe_tx_swing_o) , - - .pipe_clk(pipe_clk), - .rst_n(rst_n) - ); - - - pcie_pipe_lane_v6 # ( - - .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) - - ) - pipe_lane_0_i ( - - .pipe_rx_char_is_k_o(pipe_rx0_char_is_k_q), - .pipe_rx_data_o(pipe_rx0_data_q), - .pipe_rx_valid_o(pipe_rx0_valid_o), - .pipe_rx_chanisaligned_o(pipe_rx0_chanisaligned_o), - .pipe_rx_status_o(pipe_rx0_status_o), - .pipe_rx_phy_status_o(pipe_rx0_phy_status_o), - .pipe_rx_elec_idle_o(pipe_rx0_elec_idle_o), - .pipe_rx_polarity_i(pipe_rx0_polarity_i), - .pipe_tx_compliance_i(pipe_tx0_compliance_i), - .pipe_tx_char_is_k_i(pipe_tx0_char_is_k_i), - .pipe_tx_data_i(pipe_tx0_data_i), - .pipe_tx_elec_idle_i(pipe_tx0_elec_idle_i), - .pipe_tx_powerdown_i(pipe_tx0_powerdown_i), - - .pipe_rx_char_is_k_i(pipe_rx0_char_is_k_i), - .pipe_rx_data_i(pipe_rx0_data_i), - .pipe_rx_valid_i(pipe_rx0_valid_i), - .pipe_rx_chanisaligned_i(pipe_rx0_chanisaligned_i), - .pipe_rx_status_i(pipe_rx0_status_i), - .pipe_rx_phy_status_i(pipe_rx0_phy_status_i), - .pipe_rx_elec_idle_i(pipe_rx0_elec_idle_i), - .pipe_rx_polarity_o(pipe_rx0_polarity_o), - .pipe_tx_compliance_o(pipe_tx0_compliance_o), - .pipe_tx_char_is_k_o(pipe_tx0_char_is_k_o), - .pipe_tx_data_o(pipe_tx0_data_o), - .pipe_tx_elec_idle_o(pipe_tx0_elec_idle_o), - .pipe_tx_powerdown_o(pipe_tx0_powerdown_o), - - .pipe_clk(pipe_clk), - .rst_n(rst_n) - - ); - - if (NO_OF_LANES >= 2) begin - - pcie_pipe_lane_v6 # ( - - .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) - - ) - pipe_lane_1_i ( - - .pipe_rx_char_is_k_o(pipe_rx1_char_is_k_q), - .pipe_rx_data_o(pipe_rx1_data_q), - .pipe_rx_valid_o(pipe_rx1_valid_o), - .pipe_rx_chanisaligned_o(pipe_rx1_chanisaligned_o), - .pipe_rx_status_o(pipe_rx1_status_o), - .pipe_rx_phy_status_o(pipe_rx1_phy_status_o), - .pipe_rx_elec_idle_o(pipe_rx1_elec_idle_o), - .pipe_rx_polarity_i(pipe_rx1_polarity_i), - .pipe_tx_compliance_i(pipe_tx1_compliance_i), - .pipe_tx_char_is_k_i(pipe_tx1_char_is_k_i), - .pipe_tx_data_i(pipe_tx1_data_i), - .pipe_tx_elec_idle_i(pipe_tx1_elec_idle_i), - .pipe_tx_powerdown_i(pipe_tx1_powerdown_i), - - .pipe_rx_char_is_k_i(pipe_rx1_char_is_k_i), - .pipe_rx_data_i(pipe_rx1_data_i), - .pipe_rx_valid_i(pipe_rx1_valid_i), - .pipe_rx_chanisaligned_i(pipe_rx1_chanisaligned_i), - .pipe_rx_status_i(pipe_rx1_status_i), - .pipe_rx_phy_status_i(pipe_rx1_phy_status_i), - .pipe_rx_elec_idle_i(pipe_rx1_elec_idle_i), - .pipe_rx_polarity_o(pipe_rx1_polarity_o), - .pipe_tx_compliance_o(pipe_tx1_compliance_o), - .pipe_tx_char_is_k_o(pipe_tx1_char_is_k_o), - .pipe_tx_data_o(pipe_tx1_data_o), - .pipe_tx_elec_idle_o(pipe_tx1_elec_idle_o), - .pipe_tx_powerdown_o(pipe_tx1_powerdown_o), - - .pipe_clk(pipe_clk), - .rst_n(rst_n) - - ); - - end - else begin -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< -// start remove before release -`ifndef PIPE_RX_ERR_INJ -// end remove before release -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< - assign pipe_rx1_char_is_k_o = 2'b00; - assign pipe_rx1_data_o = 16'h0000; - assign pipe_rx1_valid_o = 1'b0; - assign pipe_rx1_chanisaligned_o = 1'b0; - assign pipe_rx1_status_o = 3'b000; - assign pipe_rx1_phy_status_o = 1'b0; - assign pipe_rx1_elec_idle_o = 1'b1; - assign pipe_rx1_polarity_o = 1'b0; - assign pipe_tx1_compliance_o = 1'b0; - assign pipe_tx1_char_is_k_o = 2'b00; - assign pipe_tx1_data_o = 16'h0000; - assign pipe_tx1_elec_idle_o = 1'b1; - assign pipe_tx1_powerdown_o = 2'b00; -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< -// start remove before release -`endif // PIPE_RX_ERR_INJ -// end remove before release -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< - end - - if (NO_OF_LANES >= 4) begin - - pcie_pipe_lane_v6 # ( - - .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) - ) - pipe_lane_2_i ( - - .pipe_rx_char_is_k_o(pipe_rx2_char_is_k_q), - .pipe_rx_data_o(pipe_rx2_data_q), - .pipe_rx_valid_o(pipe_rx2_valid_o), - .pipe_rx_chanisaligned_o(pipe_rx2_chanisaligned_o), - .pipe_rx_status_o(pipe_rx2_status_o), - .pipe_rx_phy_status_o(pipe_rx2_phy_status_o), - .pipe_rx_elec_idle_o(pipe_rx2_elec_idle_o), - .pipe_rx_polarity_i(pipe_rx2_polarity_i), - .pipe_tx_compliance_i(pipe_tx2_compliance_i), - .pipe_tx_char_is_k_i(pipe_tx2_char_is_k_i), - .pipe_tx_data_i(pipe_tx2_data_i), - .pipe_tx_elec_idle_i(pipe_tx2_elec_idle_i), - .pipe_tx_powerdown_i(pipe_tx2_powerdown_i), - - .pipe_rx_char_is_k_i(pipe_rx2_char_is_k_i), - .pipe_rx_data_i(pipe_rx2_data_i), - .pipe_rx_valid_i(pipe_rx2_valid_i), - .pipe_rx_chanisaligned_i(pipe_rx2_chanisaligned_i), - .pipe_rx_status_i(pipe_rx2_status_i), - .pipe_rx_phy_status_i(pipe_rx2_phy_status_i), - .pipe_rx_elec_idle_i(pipe_rx2_elec_idle_i), - .pipe_rx_polarity_o(pipe_rx2_polarity_o), - .pipe_tx_compliance_o(pipe_tx2_compliance_o), - .pipe_tx_char_is_k_o(pipe_tx2_char_is_k_o), - .pipe_tx_data_o(pipe_tx2_data_o), - .pipe_tx_elec_idle_o(pipe_tx2_elec_idle_o), - .pipe_tx_powerdown_o(pipe_tx2_powerdown_o), - - .pipe_clk(pipe_clk), - .rst_n(rst_n) - - ); - - pcie_pipe_lane_v6 # ( - - .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) - - ) - pipe_lane_3_i ( - - .pipe_rx_char_is_k_o(pipe_rx3_char_is_k_q), - .pipe_rx_data_o(pipe_rx3_data_q), - .pipe_rx_valid_o(pipe_rx3_valid_o), - .pipe_rx_chanisaligned_o(pipe_rx3_chanisaligned_o), - .pipe_rx_status_o(pipe_rx3_status_o), - .pipe_rx_phy_status_o(pipe_rx3_phy_status_o), - .pipe_rx_elec_idle_o(pipe_rx3_elec_idle_o), - .pipe_rx_polarity_i(pipe_rx3_polarity_i), - .pipe_tx_compliance_i(pipe_tx3_compliance_i), - .pipe_tx_char_is_k_i(pipe_tx3_char_is_k_i), - .pipe_tx_data_i(pipe_tx3_data_i), - .pipe_tx_elec_idle_i(pipe_tx3_elec_idle_i), - .pipe_tx_powerdown_i(pipe_tx3_powerdown_i), - - .pipe_rx_char_is_k_i(pipe_rx3_char_is_k_i), - .pipe_rx_data_i(pipe_rx3_data_i), - .pipe_rx_valid_i(pipe_rx3_valid_i), - .pipe_rx_chanisaligned_i(pipe_rx3_chanisaligned_i), - .pipe_rx_status_i(pipe_rx3_status_i), - .pipe_rx_phy_status_i(pipe_rx3_phy_status_i), - .pipe_rx_elec_idle_i(pipe_rx3_elec_idle_i), - .pipe_rx_polarity_o(pipe_rx3_polarity_o), - .pipe_tx_compliance_o(pipe_tx3_compliance_o), - .pipe_tx_char_is_k_o(pipe_tx3_char_is_k_o), - .pipe_tx_data_o(pipe_tx3_data_o), - .pipe_tx_elec_idle_o(pipe_tx3_elec_idle_o), - .pipe_tx_powerdown_o(pipe_tx3_powerdown_o), - - .pipe_clk(pipe_clk), - .rst_n(rst_n) - - ); - - end - else begin -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< -// start remove before release -`ifndef PIPE_RX_ERR_INJ -// end remove before release -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< - assign pipe_rx2_char_is_k_o = 2'b00; - assign pipe_rx2_data_o = 16'h0000; - assign pipe_rx2_valid_o = 1'b0; - assign pipe_rx2_chanisaligned_o = 1'b0; - assign pipe_rx2_status_o = 3'b000; - assign pipe_rx2_phy_status_o = 1'b0; - assign pipe_rx2_elec_idle_o = 1'b1; - assign pipe_rx2_polarity_o = 1'b0; - assign pipe_tx2_compliance_o = 1'b0; - assign pipe_tx2_char_is_k_o = 2'b00; - assign pipe_tx2_data_o = 16'h0000; - assign pipe_tx2_elec_idle_o = 1'b1; - assign pipe_tx2_powerdown_o = 2'b00; - - assign pipe_rx3_char_is_k_o = 2'b00; - assign pipe_rx3_data_o = 16'h0000; - assign pipe_rx3_valid_o = 1'b0; - assign pipe_rx3_chanisaligned_o = 1'b0; - assign pipe_rx3_status_o = 3'b000; - assign pipe_rx3_phy_status_o = 1'b0; - assign pipe_rx3_elec_idle_o = 1'b1; - assign pipe_rx3_polarity_o = 1'b0; - assign pipe_tx3_compliance_o = 1'b0; - assign pipe_tx3_char_is_k_o = 2'b00; - assign pipe_tx3_data_o = 16'h0000; - assign pipe_tx3_elec_idle_o = 1'b1; - assign pipe_tx3_powerdown_o = 2'b00; -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< -// start remove before release -`endif // PIPE_RX_ERR_INJ -// end remove before release -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< - end - - if (NO_OF_LANES >= 8) begin - - pcie_pipe_lane_v6 # ( - - .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) - - ) - pipe_lane_4_i ( - - .pipe_rx_char_is_k_o(pipe_rx4_char_is_k_q), - .pipe_rx_data_o(pipe_rx4_data_q), - .pipe_rx_valid_o(pipe_rx4_valid_o), - .pipe_rx_chanisaligned_o(pipe_rx4_chanisaligned_o), - .pipe_rx_status_o(pipe_rx4_status_o), - .pipe_rx_phy_status_o(pipe_rx4_phy_status_o), - .pipe_rx_elec_idle_o(pipe_rx4_elec_idle_o), - .pipe_rx_polarity_i(pipe_rx4_polarity_i), - .pipe_tx_compliance_i(pipe_tx4_compliance_i), - .pipe_tx_char_is_k_i(pipe_tx4_char_is_k_i), - .pipe_tx_data_i(pipe_tx4_data_i), - .pipe_tx_elec_idle_i(pipe_tx4_elec_idle_i), - .pipe_tx_powerdown_i(pipe_tx4_powerdown_i), - - .pipe_rx_char_is_k_i(pipe_rx4_char_is_k_i), - .pipe_rx_data_i(pipe_rx4_data_i), - .pipe_rx_valid_i(pipe_rx4_valid_i), - .pipe_rx_chanisaligned_i(pipe_rx4_chanisaligned_i), - .pipe_rx_status_i(pipe_rx4_status_i), - .pipe_rx_phy_status_i(pipe_rx4_phy_status_i), - .pipe_rx_elec_idle_i(pipe_rx4_elec_idle_i), - .pipe_rx_polarity_o(pipe_rx4_polarity_o), - .pipe_tx_compliance_o(pipe_tx4_compliance_o), - .pipe_tx_char_is_k_o(pipe_tx4_char_is_k_o), - .pipe_tx_data_o(pipe_tx4_data_o), - .pipe_tx_elec_idle_o(pipe_tx4_elec_idle_o), - .pipe_tx_powerdown_o(pipe_tx4_powerdown_o), - - .pipe_clk(pipe_clk), - .rst_n(rst_n) - - ); - - pcie_pipe_lane_v6 # ( - - .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) - - ) - pipe_lane_5_i ( - - .pipe_rx_char_is_k_o(pipe_rx5_char_is_k_q), - .pipe_rx_data_o(pipe_rx5_data_q), - .pipe_rx_valid_o(pipe_rx5_valid_o), - .pipe_rx_chanisaligned_o(pipe_rx5_chanisaligned_o), - .pipe_rx_status_o(pipe_rx5_status_o), - .pipe_rx_phy_status_o(pipe_rx5_phy_status_o), - .pipe_rx_elec_idle_o(pipe_rx5_elec_idle_o), - .pipe_rx_polarity_i(pipe_rx5_polarity_i), - .pipe_tx_compliance_i(pipe_tx5_compliance_i), - .pipe_tx_char_is_k_i(pipe_tx5_char_is_k_i), - .pipe_tx_data_i(pipe_tx5_data_i), - .pipe_tx_elec_idle_i(pipe_tx5_elec_idle_i), - .pipe_tx_powerdown_i(pipe_tx5_powerdown_i), - - .pipe_rx_char_is_k_i(pipe_rx5_char_is_k_i), - .pipe_rx_data_i(pipe_rx5_data_i), - .pipe_rx_valid_i(pipe_rx5_valid_i), - .pipe_rx_chanisaligned_i(pipe_rx5_chanisaligned_i), - .pipe_rx_status_i(pipe_rx5_status_i), - .pipe_rx_phy_status_i(pipe_rx4_phy_status_i), - .pipe_rx_elec_idle_i(pipe_rx4_elec_idle_i), - .pipe_rx_polarity_o(pipe_rx5_polarity_o), - .pipe_tx_compliance_o(pipe_tx5_compliance_o), - .pipe_tx_char_is_k_o(pipe_tx5_char_is_k_o), - .pipe_tx_data_o(pipe_tx5_data_o), - .pipe_tx_elec_idle_o(pipe_tx5_elec_idle_o), - .pipe_tx_powerdown_o(pipe_tx5_powerdown_o), - - .pipe_clk(pipe_clk), - .rst_n(rst_n) - - ); - - pcie_pipe_lane_v6 # ( - - .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) - - ) - pipe_lane_6_i ( - - .pipe_rx_char_is_k_o(pipe_rx6_char_is_k_q), - .pipe_rx_data_o(pipe_rx6_data_q), - .pipe_rx_valid_o(pipe_rx6_valid_o), - .pipe_rx_chanisaligned_o(pipe_rx6_chanisaligned_o), - .pipe_rx_status_o(pipe_rx6_status_o), - .pipe_rx_phy_status_o(pipe_rx6_phy_status_o), - .pipe_rx_elec_idle_o(pipe_rx6_elec_idle_o), - .pipe_rx_polarity_i(pipe_rx6_polarity_i), - .pipe_tx_compliance_i(pipe_tx6_compliance_i), - .pipe_tx_char_is_k_i(pipe_tx6_char_is_k_i), - .pipe_tx_data_i(pipe_tx6_data_i), - .pipe_tx_elec_idle_i(pipe_tx6_elec_idle_i), - .pipe_tx_powerdown_i(pipe_tx6_powerdown_i), - - .pipe_rx_char_is_k_i(pipe_rx6_char_is_k_i), - .pipe_rx_data_i(pipe_rx6_data_i), - .pipe_rx_valid_i(pipe_rx6_valid_i), - .pipe_rx_chanisaligned_i(pipe_rx6_chanisaligned_i), - .pipe_rx_status_i(pipe_rx6_status_i), - .pipe_rx_phy_status_i(pipe_rx4_phy_status_i), - .pipe_rx_elec_idle_i(pipe_rx6_elec_idle_i), - .pipe_rx_polarity_o(pipe_rx6_polarity_o), - .pipe_tx_compliance_o(pipe_tx6_compliance_o), - .pipe_tx_char_is_k_o(pipe_tx6_char_is_k_o), - .pipe_tx_data_o(pipe_tx6_data_o), - .pipe_tx_elec_idle_o(pipe_tx6_elec_idle_o), - .pipe_tx_powerdown_o(pipe_tx6_powerdown_o), - - .pipe_clk(pipe_clk), - .rst_n(rst_n) - - ); - - pcie_pipe_lane_v6 # ( - - .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) - - ) - pipe_lane_7_i ( - - .pipe_rx_char_is_k_o(pipe_rx7_char_is_k_q), - .pipe_rx_data_o(pipe_rx7_data_q), - .pipe_rx_valid_o(pipe_rx7_valid_o), - .pipe_rx_chanisaligned_o(pipe_rx7_chanisaligned_o), - .pipe_rx_status_o(pipe_rx7_status_o), - .pipe_rx_phy_status_o(pipe_rx7_phy_status_o), - .pipe_rx_elec_idle_o(pipe_rx7_elec_idle_o), - .pipe_rx_polarity_i(pipe_rx7_polarity_i), - .pipe_tx_compliance_i(pipe_tx7_compliance_i), - .pipe_tx_char_is_k_i(pipe_tx7_char_is_k_i), - .pipe_tx_data_i(pipe_tx7_data_i), - .pipe_tx_elec_idle_i(pipe_tx7_elec_idle_i), - .pipe_tx_powerdown_i(pipe_tx7_powerdown_i), - - .pipe_rx_char_is_k_i(pipe_rx7_char_is_k_i), - .pipe_rx_data_i(pipe_rx7_data_i), - .pipe_rx_valid_i(pipe_rx7_valid_i), - .pipe_rx_chanisaligned_i(pipe_rx7_chanisaligned_i), - .pipe_rx_status_i(pipe_rx7_status_i), - .pipe_rx_phy_status_i(pipe_rx4_phy_status_i), - .pipe_rx_elec_idle_i(pipe_rx7_elec_idle_i), - .pipe_rx_polarity_o(pipe_rx7_polarity_o), - .pipe_tx_compliance_o(pipe_tx7_compliance_o), - .pipe_tx_char_is_k_o(pipe_tx7_char_is_k_o), - .pipe_tx_data_o(pipe_tx7_data_o), - .pipe_tx_elec_idle_o(pipe_tx7_elec_idle_o), - .pipe_tx_powerdown_o(pipe_tx7_powerdown_o), - - .pipe_clk(pipe_clk), - .rst_n(rst_n) - - ); - - end - else begin -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< -// start remove before release -`ifndef PIPE_RX_ERR_INJ -// end remove before release -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< - assign pipe_rx4_char_is_k_o = 2'b00; - assign pipe_rx4_data_o = 16'h0000; - assign pipe_rx4_valid_o = 1'b0; - assign pipe_rx4_chanisaligned_o = 1'b0; - assign pipe_rx4_status_o = 3'b000; - assign pipe_rx4_phy_status_o = 1'b0; - assign pipe_rx4_elec_idle_o = 1'b1; - assign pipe_rx4_polarity_o = 1'b0; - assign pipe_tx4_compliance_o = 1'b0; - assign pipe_tx4_char_is_k_o = 2'b00; - assign pipe_tx4_data_o = 16'h0000; - assign pipe_tx4_elec_idle_o = 1'b1; - assign pipe_tx4_powerdown_o = 2'b00; - - assign pipe_rx5_char_is_k_o = 2'b00; - assign pipe_rx5_data_o = 16'h0000; - assign pipe_rx5_valid_o = 1'b0; - assign pipe_rx5_chanisaligned_o = 1'b0; - assign pipe_rx5_status_o = 3'b000; - assign pipe_rx5_phy_status_o = 1'b0; - assign pipe_rx5_elec_idle_o = 1'b1; - assign pipe_rx5_polarity_o = 1'b0; - assign pipe_tx5_compliance_o = 1'b0; - assign pipe_tx5_char_is_k_o = 2'b00; - assign pipe_tx5_data_o = 16'h0000; - assign pipe_tx5_elec_idle_o = 1'b1; - assign pipe_tx5_powerdown_o = 2'b00; - - assign pipe_rx6_char_is_k_o = 2'b00; - assign pipe_rx6_data_o = 16'h0000; - assign pipe_rx6_valid_o = 1'b0; - assign pipe_rx6_chanisaligned_o = 1'b0; - assign pipe_rx6_status_o = 3'b000; - assign pipe_rx6_phy_status_o = 1'b0; - assign pipe_rx6_elec_idle_o = 1'b1; - assign pipe_rx6_polarity_o = 1'b0; - assign pipe_tx6_compliance_o = 1'b0; - assign pipe_tx6_char_is_k_o = 2'b00; - assign pipe_tx6_data_o = 16'h0000; - assign pipe_tx6_elec_idle_o = 1'b1; - assign pipe_tx6_powerdown_o = 2'b00; - - assign pipe_rx7_char_is_k_o = 2'b00; - assign pipe_rx7_data_o = 16'h0000; - assign pipe_rx7_valid_o = 1'b0; - assign pipe_rx7_chanisaligned_o = 1'b0; - assign pipe_rx7_status_o = 3'b000; - assign pipe_rx7_phy_status_o = 1'b0; - assign pipe_rx7_elec_idle_o = 1'b1; - assign pipe_rx7_polarity_o = 1'b0; - assign pipe_tx7_compliance_o = 1'b0; - assign pipe_tx7_char_is_k_o = 2'b00; - assign pipe_tx7_data_o = 16'h0000; - assign pipe_tx7_elec_idle_o = 1'b1; - assign pipe_tx7_powerdown_o = 2'b00; -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< -// start remove before release -`endif // PIPE_RX_ERR_INJ -// end remove before release -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< - end - - endgenerate - -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< -// start remove before release -`ifdef PIPE_RX_ERR_INJ - -generate - -if (LINK_CAP_MAX_LINK_SPEED == 4'h2) begin - -reg [5:0] pl_ltssm_state_q; - -always @(posedge pipe_clk) begin - - if (rst_n) - pl_ltssm_state_q <= 0; - else - pl_ltssm_state_q <= pl_ltssm_state; - -end - -wire plm_in_l0 = (pl_ltssm_state_q == 6'h16); - - -pcie_pipe_err_inject # ( - .NO_OF_LANES(NO_OF_LANES) -) -rx_err_inj( - - .enable(plm_in_l0), - .pipe_clk(pipe_clk), - .pipe_rst(!rst_n), - - .o_ln0_cisk(pipe_rx0_char_is_k_o), - .o_ln0_data(pipe_rx0_data_o), - .i_ln0_cisk(pipe_rx0_char_is_k_q), - .i_ln0_data(pipe_rx0_data_q), - .o_ln1_cisk(pipe_rx1_char_is_k_o), - .o_ln1_data(pipe_rx1_data_o), - .i_ln1_cisk((NO_OF_LANES >= 2 ) ? pipe_rx1_char_is_k_q : 2'b0), - .i_ln1_data((NO_OF_LANES >= 2 ) ? pipe_rx1_data_q : 16'h0), - .o_ln2_cisk(pipe_rx2_char_is_k_o), - .o_ln2_data(pipe_rx2_data_o), - .i_ln2_cisk((NO_OF_LANES >= 4 ) ? pipe_rx2_char_is_k_q : 2'b0), - .i_ln2_data((NO_OF_LANES >= 4 ) ? pipe_rx2_data_q : 16'h0), - .o_ln3_cisk(pipe_rx3_char_is_k_o), - .o_ln3_data(pipe_rx3_data_o), - .i_ln3_cisk((NO_OF_LANES >= 4 ) ? pipe_rx3_char_is_k_q : 2'b0), - .i_ln3_data((NO_OF_LANES >= 4 ) ? pipe_rx3_data_q : 16'h0), - .o_ln4_cisk(pipe_rx4_char_is_k_o), - .o_ln4_data(pipe_rx4_data_o), - .i_ln4_cisk((NO_OF_LANES >= 8 ) ? pipe_rx4_char_is_k_q : 2'b0), - .i_ln4_data((NO_OF_LANES >= 8 ) ? pipe_rx4_data_q : 16'h0), - .o_ln5_cisk(pipe_rx5_char_is_k_o), - .o_ln5_data(pipe_rx5_data_o), - .i_ln5_cisk((NO_OF_LANES >= 8 ) ? pipe_rx5_char_is_k_q : 2'b0), - .i_ln5_data((NO_OF_LANES >= 8 ) ? pipe_rx5_data_q : 16'h0), - .o_ln6_cisk(pipe_rx6_char_is_k_o), - .o_ln6_data(pipe_rx6_data_o), - .i_ln6_cisk((NO_OF_LANES >= 8 ) ? pipe_rx6_char_is_k_q : 2'b0), - .i_ln6_data((NO_OF_LANES >= 8 ) ? pipe_rx6_data_q : 16'h0), - .o_ln7_cisk(pipe_rx7_char_is_k_o), - .o_ln7_data(pipe_rx7_data_o), - .i_ln7_cisk((NO_OF_LANES >= 8 ) ? pipe_rx7_char_is_k_q : 2'b0), - .i_ln7_data((NO_OF_LANES >= 8 ) ? pipe_rx7_data_q : 16'h0) -); - -end else begin - -assign pipe_rx0_char_is_k_o = pipe_rx0_char_is_k_q; -assign pipe_rx0_data_o = pipe_rx0_data_q; -assign pipe_rx1_char_is_k_o = pipe_rx1_char_is_k_q; -assign pipe_rx1_data_o = pipe_rx1_data_q; -assign pipe_rx2_char_is_k_o = pipe_rx2_char_is_k_q; -assign pipe_rx2_data_o = pipe_rx2_data_q; -assign pipe_rx3_char_is_k_o = pipe_rx3_char_is_k_q; -assign pipe_rx3_data_o = pipe_rx3_data_q; -assign pipe_rx4_char_is_k_o = pipe_rx4_char_is_k_q; -assign pipe_rx4_data_o = pipe_rx4_data_q; -assign pipe_rx5_char_is_k_o = pipe_rx5_char_is_k_q; -assign pipe_rx5_data_o = pipe_rx5_data_q; -assign pipe_rx6_char_is_k_o = pipe_rx6_char_is_k_q; -assign pipe_rx6_data_o = pipe_rx6_data_q; -assign pipe_rx7_char_is_k_o = pipe_rx7_char_is_k_q; -assign pipe_rx7_data_o = pipe_rx7_data_q; - -end - -endgenerate - - -`endif // PIPE_RX_ERR_INJ -// end remove before release -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< - -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< -// start remove before release -`ifndef PIPE_RX_ERR_INJ -// end remove before release -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< - - assign pipe_rx0_char_is_k_o = pipe_rx0_char_is_k_q; - assign pipe_rx0_data_o = pipe_rx0_data_q; - assign pipe_rx1_char_is_k_o = pipe_rx1_char_is_k_q; - assign pipe_rx1_data_o = pipe_rx1_data_q; - assign pipe_rx2_char_is_k_o = pipe_rx2_char_is_k_q; - assign pipe_rx2_data_o = pipe_rx2_data_q; - assign pipe_rx3_char_is_k_o = pipe_rx3_char_is_k_q; - assign pipe_rx3_data_o = pipe_rx3_data_q; - assign pipe_rx4_char_is_k_o = pipe_rx4_char_is_k_q; - assign pipe_rx4_data_o = pipe_rx4_data_q; - assign pipe_rx5_char_is_k_o = pipe_rx5_char_is_k_q; - assign pipe_rx5_data_o = pipe_rx5_data_q; - assign pipe_rx6_char_is_k_o = pipe_rx6_char_is_k_q; - assign pipe_rx6_data_o = pipe_rx6_data_q; - assign pipe_rx7_char_is_k_o = pipe_rx7_char_is_k_q; - assign pipe_rx7_data_o = pipe_rx7_data_q; - -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< -// start remove before release -`endif // PIPE_RX_ERR_INJ -// end remove before release -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< - -endmodule Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/gtx_rx_valid_filter_v6.v =================================================================== --- branches/Virtex6/ML605/v6_pcie_v1_3/source/gtx_rx_valid_filter_v6.v (revision 9) +++ branches/Virtex6/ML605/v6_pcie_v1_3/source/gtx_rx_valid_filter_v6.v (nonexistent) @@ -1,320 +0,0 @@ - -//----------------------------------------------------------------------------- -// -// (c) Copyright 2009 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information of Xilinx, Inc. -// and is protected under U.S. and international copyright and other -// intellectual property laws. -// -// DISCLAIMER -// -// This disclaimer is not a license and does not grant any rights to the -// materials distributed herewith. Except as otherwise provided in a valid -// license issued to you by Xilinx, and to the maximum extent permitted by -// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -// and (2) Xilinx shall not be liable (whether in contract or tort, including -// negligence, or under any other theory of liability) for any loss or damage -// of any kind or nature related to, arising under or in connection with these -// materials, including for any direct, or any indirect, special, incidental, -// or consequential loss or damage (including loss of data, profits, goodwill, -// or any type of loss or damage suffered as a result of any action brought by -// a third party) even if such damage or loss was reasonably foreseeable or -// Xilinx had been advised of the possibility of the same. -// -// CRITICAL APPLICATIONS -// -// Xilinx products are not designed or intended to be fail-safe, or for use in -// any application requiring fail-safe performance, such as life-support or -// safety devices or systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any other -// applications that could lead to death, personal injury, or severe property -// or environmental damage (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and liability of any use of -// Xilinx products in Critical Applications, subject only to applicable laws -// and regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -// AT ALL TIMES. -// -//----------------------------------------------------------------------------- -// Project : Virtex-6 Integrated Block for PCI Express -// File : gtx_rx_valid_filter_v6.v - -`timescale 1ns / 1ns - -module GTX_RX_VALID_FILTER_V6 #( - - parameter CLK_COR_MIN_LAT = 28 - -) -( - output [1:0] USER_RXCHARISK, - output [15:0] USER_RXDATA, - output USER_RXVALID, - output USER_RXELECIDLE, - output [ 2:0] USER_RX_STATUS, - output USER_RX_PHY_STATUS, - - input [1:0] GT_RXCHARISK, - input [15:0] GT_RXDATA, - input GT_RXVALID, - input GT_RXELECIDLE, - input [ 2:0] GT_RX_STATUS, - input GT_RX_PHY_STATUS, - - - input USER_CLK, - input RESET - -); - - parameter TCQ = 1; - - parameter EIOS_DET_IDL = 5'b00001; - parameter EIOS_DET_NO_STR0 = 5'b00010; - parameter EIOS_DET_STR0 = 5'b00100; - parameter EIOS_DET_STR1 = 5'b01000; - parameter EIOS_DET_DONE = 5'b10000; - - parameter EIOS_COM = 8'hBC; - parameter EIOS_IDL = 8'h7C; - - reg [4:0] reg_state_eios_det; - wire [4:0] state_eios_det; - - reg reg_eios_detected; - wire eios_detected; - - reg reg_symbol_after_eios; - wire symbol_after_eios; - - parameter USER_RXVLD_IDL = 4'b0001; - parameter USER_RXVLD_EI = 4'b0010; - parameter USER_RXVLD_EI_DB0 = 4'b0100; - parameter USER_RXVLD_EI_DB1 = 4'b1000; - - reg [3:0] reg_state_rxvld_ei; - wire [3:0] state_rxvld_ei; - - reg [4:0] reg_rxvld_count; - wire [4:0] rxvld_count; - - reg [3:0] reg_rxvld_fallback; - wire [3:0] rxvld_fallback; - - reg [1:0] gt_rxcharisk_q; - reg [15:0] gt_rxdata_q; - reg gt_rxvalid_q; - reg gt_rxelecidle_q; - - reg [ 2:0] gt_rx_status_q; - reg gt_rx_phy_status_q; - - // EIOS detector - - always @(posedge USER_CLK) begin - - if (RESET) begin - - reg_eios_detected <= #TCQ 1'b0; - reg_state_eios_det <= #TCQ EIOS_DET_IDL; - reg_symbol_after_eios <= #TCQ 1'b0; - gt_rxcharisk_q <= #TCQ 2'b00; - gt_rxdata_q <= #TCQ 16'h0; - gt_rxvalid_q <= #TCQ 1'b0; - gt_rxelecidle_q <= #TCQ 1'b0; - gt_rx_status_q <= #TCQ 3'b000; - gt_rx_phy_status_q <= #TCQ 1'b0; - - end else begin - - reg_eios_detected <= #TCQ 1'b0; - reg_symbol_after_eios <= #TCQ 1'b0; - gt_rxcharisk_q <= #TCQ GT_RXCHARISK; - gt_rxdata_q <= #TCQ GT_RXDATA; - gt_rxvalid_q <= #TCQ GT_RXVALID; - gt_rxelecidle_q <= #TCQ GT_RXELECIDLE; - gt_rx_status_q <= #TCQ GT_RX_STATUS; - gt_rx_phy_status_q <= #TCQ GT_RX_PHY_STATUS; - - case ( state_eios_det ) - - EIOS_DET_IDL : begin - - if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_COM) && - (gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_IDL)) begin - - reg_state_eios_det <= #TCQ EIOS_DET_NO_STR0; - reg_eios_detected <= #TCQ 1'b1; - - end else if ((gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_COM)) - reg_state_eios_det <= #TCQ EIOS_DET_STR0; - else - reg_state_eios_det <= #TCQ EIOS_DET_IDL; - - end - - EIOS_DET_NO_STR0 : begin - - if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) && - (gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL))) - reg_state_eios_det <= #TCQ EIOS_DET_DONE; - else - reg_state_eios_det <= #TCQ EIOS_DET_IDL; - - end - - EIOS_DET_STR0 : begin - - if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) && - (gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL))) begin - - reg_state_eios_det <= #TCQ EIOS_DET_STR1; - reg_eios_detected <= #TCQ 1'b1; - reg_symbol_after_eios <= #TCQ 1'b1; - - end else - reg_state_eios_det <= #TCQ EIOS_DET_IDL; - - end - - EIOS_DET_STR1 : begin - - if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_IDL)) - reg_state_eios_det <= #TCQ EIOS_DET_DONE; - else - reg_state_eios_det <= #TCQ EIOS_DET_IDL; - - end - - EIOS_DET_DONE : begin - - reg_state_eios_det <= #TCQ EIOS_DET_IDL; - - end - - endcase - - end - - end - assign state_eios_det = reg_state_eios_det; - assign eios_detected = reg_eios_detected; - assign symbol_after_eios = reg_symbol_after_eios; - - // user_rxvalid generation - - always @(posedge USER_CLK) begin - - if (RESET) begin - - reg_state_rxvld_ei <= #TCQ USER_RXVLD_IDL; - - end else begin - - case ( state_rxvld_ei ) - - USER_RXVLD_IDL : begin - - if (eios_detected) - reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI; - else - reg_state_rxvld_ei <= #TCQ USER_RXVLD_IDL; - - end - - USER_RXVLD_EI : begin - - if (!gt_rxvalid_q) - reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI_DB0; - else if (rxvld_fallback == 4'b1111) - reg_state_rxvld_ei <= #TCQ USER_RXVLD_IDL; - else - reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI; - - end - - USER_RXVLD_EI_DB0 : begin - - if (gt_rxvalid_q) - reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI_DB1; - else - reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI_DB0; - - end - - USER_RXVLD_EI_DB1 : begin - - if (rxvld_count > CLK_COR_MIN_LAT) - reg_state_rxvld_ei <= #TCQ USER_RXVLD_IDL; - else - reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI_DB1; - - end - - endcase - - end - - end - assign state_rxvld_ei = reg_state_rxvld_ei; - - // RxValid counter - - always @(posedge USER_CLK) begin - - if (RESET) begin - - reg_rxvld_count <= #TCQ 5'b00000; - - end else begin - - if ((gt_rxvalid_q) && (state_rxvld_ei == USER_RXVLD_EI_DB1)) - reg_rxvld_count <= #TCQ reg_rxvld_count + 1'b1; - else - reg_rxvld_count <= #TCQ 5'b00000; - - end - - end - assign rxvld_count = reg_rxvld_count; - - // RxValid fallback - - always @(posedge USER_CLK) begin - - if (RESET) begin - - reg_rxvld_fallback <= #TCQ 4'b0000; - - end else begin - - if (state_rxvld_ei == USER_RXVLD_EI) - reg_rxvld_fallback <= #TCQ reg_rxvld_fallback + 1'b1; - else - reg_rxvld_fallback <= #TCQ 4'b0000; - - end - - end - assign rxvld_fallback = reg_rxvld_fallback; - - // Delay pipe_rx_elec_idle - - SRL16E #(.INIT(0)) rx_elec_idle_delay (.Q(USER_RXELECIDLE), - .D(gt_rxelecidle_q), - .CLK(USER_CLK), - .CE(1'b1), .A3(1'b1),.A2(1'b1),.A1(1'b1),.A0(1'b1)); - - assign USER_RXVALID = (state_rxvld_ei == USER_RXVLD_IDL) ? gt_rxvalid_q : 1'b0; - assign USER_RXCHARISK[0] = USER_RXVALID ? gt_rxcharisk_q[0] : 1'b0; - assign USER_RXCHARISK[1] = (USER_RXVALID && !symbol_after_eios) ? gt_rxcharisk_q[1] : 1'b0; - assign USER_RXDATA = gt_rxdata_q; - assign USER_RX_STATUS = (state_rxvld_ei == USER_RXVLD_IDL) ? gt_rx_status_q : 3'b000; - assign USER_RX_PHY_STATUS = gt_rx_phy_status_q; - -endmodule Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_reset_delay_v6.v =================================================================== --- branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_reset_delay_v6.v (revision 9) +++ branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_reset_delay_v6.v (nonexistent) @@ -1,104 +0,0 @@ -//----------------------------------------------------------------------------- -// -// (c) Copyright 2009 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information of Xilinx, Inc. -// and is protected under U.S. and international copyright and other -// intellectual property laws. -// -// DISCLAIMER -// -// This disclaimer is not a license and does not grant any rights to the -// materials distributed herewith. Except as otherwise provided in a valid -// license issued to you by Xilinx, and to the maximum extent permitted by -// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -// and (2) Xilinx shall not be liable (whether in contract or tort, including -// negligence, or under any other theory of liability) for any loss or damage -// of any kind or nature related to, arising under or in connection with these -// materials, including for any direct, or any indirect, special, incidental, -// or consequential loss or damage (including loss of data, profits, goodwill, -// or any type of loss or damage suffered as a result of any action brought by -// a third party) even if such damage or loss was reasonably foreseeable or -// Xilinx had been advised of the possibility of the same. -// -// CRITICAL APPLICATIONS -// -// Xilinx products are not designed or intended to be fail-safe, or for use in -// any application requiring fail-safe performance, such as life-support or -// safety devices or systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any other -// applications that could lead to death, personal injury, or severe property -// or environmental damage (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and liability of any use of -// Xilinx products in Critical Applications, subject only to applicable laws -// and regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -// AT ALL TIMES. -// -//----------------------------------------------------------------------------- -// Project : Virtex-6 Integrated Block for PCI Express -// File : pcie_reset_delay_v6.v -//-- -//-- Description: sys_reset_n delay (20ms) for Virtex6 PCIe Block -//-- -//-- -//-- -//-------------------------------------------------------------------------------- - -`timescale 1ns/1ns - -module pcie_reset_delay_v6 # ( - - parameter PL_FAST_TRAIN = "FALSE", - parameter REF_CLK_FREQ = 0 // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz - -) -( - - input wire ref_clk, - input wire sys_reset_n, - output delayed_sys_reset_n - -); - - parameter TCQ = 1; - - localparam TBIT = (PL_FAST_TRAIN == "FALSE") ? ((REF_CLK_FREQ == 1) ? 20: (REF_CLK_FREQ == 0) ? 20 : 21) : 2; - - reg [7:0] reg_count_7_0; - reg [7:0] reg_count_15_8; - reg [7:0] reg_count_23_16; - wire [23:0] concat_count; - - assign concat_count = {reg_count_23_16, reg_count_15_8, reg_count_7_0}; - - always @(posedge ref_clk or negedge sys_reset_n) begin - - if (!sys_reset_n) begin - - reg_count_7_0 <= #TCQ 8'h0; - reg_count_15_8 <= #TCQ 8'h0; - reg_count_23_16 <= #TCQ 8'h0; - - end else begin - - if (delayed_sys_reset_n != 1'b1) begin - - reg_count_7_0 <= #TCQ reg_count_7_0 + 1'b1; - reg_count_15_8 <= #TCQ (reg_count_7_0 == 8'hff)? reg_count_15_8 + 1'b1 : reg_count_15_8 ; - reg_count_23_16 <= #TCQ ((reg_count_15_8 == 8'hff) & (reg_count_7_0 == 8'hff)) ? reg_count_23_16 + 1'b1 : reg_count_23_16; - - end - - end - - end - - assign delayed_sys_reset_n = concat_count[TBIT]; - -endmodule - Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_gtx_v6.v =================================================================== --- branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_gtx_v6.v (revision 9) +++ branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_gtx_v6.v (nonexistent) @@ -1,477 +0,0 @@ -//----------------------------------------------------------------------------- -// -// (c) Copyright 2009 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information of Xilinx, Inc. -// and is protected under U.S. and international copyright and other -// intellectual property laws. -// -// DISCLAIMER -// -// This disclaimer is not a license and does not grant any rights to the -// materials distributed herewith. Except as otherwise provided in a valid -// license issued to you by Xilinx, and to the maximum extent permitted by -// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -// and (2) Xilinx shall not be liable (whether in contract or tort, including -// negligence, or under any other theory of liability) for any loss or damage -// of any kind or nature related to, arising under or in connection with these -// materials, including for any direct, or any indirect, special, incidental, -// or consequential loss or damage (including loss of data, profits, goodwill, -// or any type of loss or damage suffered as a result of any action brought by -// a third party) even if such damage or loss was reasonably foreseeable or -// Xilinx had been advised of the possibility of the same. -// -// CRITICAL APPLICATIONS -// -// Xilinx products are not designed or intended to be fail-safe, or for use in -// any application requiring fail-safe performance, such as life-support or -// safety devices or systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any other -// applications that could lead to death, personal injury, or severe property -// or environmental damage (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and liability of any use of -// Xilinx products in Critical Applications, subject only to applicable laws -// and regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -// AT ALL TIMES. -// -//----------------------------------------------------------------------------- -// Project : Virtex-6 Integrated Block for PCI Express -// File : pcie_gtx_v6.v -//-- Description: GTX module for Virtex6 PCIe Block -//-- -//-- -//-- -//-------------------------------------------------------------------------------- - -`timescale 1ns/1ns - -module pcie_gtx_v6 # -( - parameter NO_OF_LANES = 8, // 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8 - parameter LINK_CAP_MAX_LINK_SPEED = 4'h1, // 1 - Gen1, 2 - Gen2 - parameter REF_CLK_FREQ = 0, // 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz - parameter PL_FAST_TRAIN = "FALSE" -) -( - // Pipe Per-Link Signals - input wire pipe_tx_rcvr_det , - input wire pipe_tx_reset , - input wire pipe_tx_rate , - input wire pipe_tx_deemph , - input wire [2:0] pipe_tx_margin , - input wire pipe_tx_swing , - - // Pipe Per-Lane Signals - Lane 0 - output wire [ 1:0] pipe_rx0_char_is_k , - output wire [15:0] pipe_rx0_data , - output wire pipe_rx0_valid , - output wire pipe_rx0_chanisaligned , - output wire [ 2:0] pipe_rx0_status , - output wire pipe_rx0_phy_status , - output wire pipe_rx0_elec_idle , - input wire pipe_rx0_polarity , - input wire pipe_tx0_compliance , - input wire [ 1:0] pipe_tx0_char_is_k , - input wire [15:0] pipe_tx0_data , - input wire pipe_tx0_elec_idle , - input wire [ 1:0] pipe_tx0_powerdown , - - // Pipe Per-Lane Signals - Lane 1 - output wire [ 1:0] pipe_rx1_char_is_k , - output wire [15:0] pipe_rx1_data , - output wire pipe_rx1_valid , - output wire pipe_rx1_chanisaligned , - output wire [ 2:0] pipe_rx1_status , - output wire pipe_rx1_phy_status , - output wire pipe_rx1_elec_idle , - input wire pipe_rx1_polarity , - input wire pipe_tx1_compliance , - input wire [ 1:0] pipe_tx1_char_is_k , - input wire [15:0] pipe_tx1_data , - input wire pipe_tx1_elec_idle , - input wire [ 1:0] pipe_tx1_powerdown , - - // Pipe Per-Lane Signals - Lane 2 - output wire [ 1:0] pipe_rx2_char_is_k , - output wire [15:0] pipe_rx2_data , - output wire pipe_rx2_valid , - output wire pipe_rx2_chanisaligned , - output wire [ 2:0] pipe_rx2_status , - output wire pipe_rx2_phy_status , - output wire pipe_rx2_elec_idle , - input wire pipe_rx2_polarity , - input wire pipe_tx2_compliance , - input wire [ 1:0] pipe_tx2_char_is_k , - input wire [15:0] pipe_tx2_data , - input wire pipe_tx2_elec_idle , - input wire [ 1:0] pipe_tx2_powerdown , - - // Pipe Per-Lane Signals - Lane 3 - output wire [ 1:0] pipe_rx3_char_is_k , - output wire [15:0] pipe_rx3_data , - output wire pipe_rx3_valid , - output wire pipe_rx3_chanisaligned , - output wire [ 2:0] pipe_rx3_status , - output wire pipe_rx3_phy_status , - output wire pipe_rx3_elec_idle , - input wire pipe_rx3_polarity , - input wire pipe_tx3_compliance , - input wire [ 1:0] pipe_tx3_char_is_k , - input wire [15:0] pipe_tx3_data , - input wire pipe_tx3_elec_idle , - input wire [ 1:0] pipe_tx3_powerdown , - - // Pipe Per-Lane Signals - Lane 4 - output wire [ 1:0] pipe_rx4_char_is_k , - output wire [15:0] pipe_rx4_data , - output wire pipe_rx4_valid , - output wire pipe_rx4_chanisaligned , - output wire [ 2:0] pipe_rx4_status , - output wire pipe_rx4_phy_status , - output wire pipe_rx4_elec_idle , - input wire pipe_rx4_polarity , - input wire pipe_tx4_compliance , - input wire [ 1:0] pipe_tx4_char_is_k , - input wire [15:0] pipe_tx4_data , - input wire pipe_tx4_elec_idle , - input wire [ 1:0] pipe_tx4_powerdown , - - // Pipe Per-Lane Signals - Lane 5 - output wire [ 1:0] pipe_rx5_char_is_k , - output wire [15:0] pipe_rx5_data , - output wire pipe_rx5_valid , - output wire pipe_rx5_chanisaligned , - output wire [ 2:0] pipe_rx5_status , - output wire pipe_rx5_phy_status , - output wire pipe_rx5_elec_idle , - input wire pipe_rx5_polarity , - input wire pipe_tx5_compliance , - input wire [ 1:0] pipe_tx5_char_is_k , - input wire [15:0] pipe_tx5_data , - input wire pipe_tx5_elec_idle , - input wire [ 1:0] pipe_tx5_powerdown , - - // Pipe Per-Lane Signals - Lane 6 - output wire [ 1:0] pipe_rx6_char_is_k , - output wire [15:0] pipe_rx6_data , - output wire pipe_rx6_valid , - output wire pipe_rx6_chanisaligned , - output wire [ 2:0] pipe_rx6_status , - output wire pipe_rx6_phy_status , - output wire pipe_rx6_elec_idle , - input wire pipe_rx6_polarity , - input wire pipe_tx6_compliance , - input wire [ 1:0] pipe_tx6_char_is_k , - input wire [15:0] pipe_tx6_data , - input wire pipe_tx6_elec_idle , - input wire [ 1:0] pipe_tx6_powerdown , - - // Pipe Per-Lane Signals - Lane 7 - output wire [ 1:0] pipe_rx7_char_is_k , - output wire [15:0] pipe_rx7_data , - output wire pipe_rx7_valid , - output wire pipe_rx7_chanisaligned , - output wire [ 2:0] pipe_rx7_status , - output wire pipe_rx7_phy_status , - output wire pipe_rx7_elec_idle , - input wire pipe_rx7_polarity , - input wire pipe_tx7_compliance , - input wire [ 1:0] pipe_tx7_char_is_k , - input wire [15:0] pipe_tx7_data , - input wire pipe_tx7_elec_idle , - input wire [ 1:0] pipe_tx7_powerdown , - - // PCI Express signals - output wire [ (NO_OF_LANES-1):0] pci_exp_txn , - output wire [ (NO_OF_LANES-1):0] pci_exp_txp , - input wire [ (NO_OF_LANES-1):0] pci_exp_rxn , - input wire [ (NO_OF_LANES-1):0] pci_exp_rxp , - - // Non PIPE signals - input wire sys_clk , - input wire sys_rst_n , - input wire pipe_clk , - input wire clock_locked , - - output wire gt_pll_lock , - input wire [ 5:0] pl_ltssm_state , - output reg phy_rdy_n -); - - parameter TCQ = 1; // clock to out delay model - - wire [ 7:0] gt_rx_phy_status_wire ; - wire [ 7:0] gt_rxchanisaligned_wire ; - wire [127:0] gt_rx_data_k_wire ; - wire [127:0] gt_rx_data_wire ; - wire [ 7:0] gt_rx_elec_idle_wire ; - wire [ 23:0] gt_rx_status_wire ; - wire [ 7:0] gt_rx_valid_wire ; - wire [ 7:0] gt_rx_polarity ; - wire [ 15:0] gt_power_down ; - wire [ 7:0] gt_tx_char_disp_mode ; - wire [ 15:0] gt_tx_data_k ; - wire [127:0] gt_tx_data ; - wire gt_tx_detect_rx_loopback ; - wire [ 7:0] gt_tx_elec_idle ; - wire [ 7:0] gt_rx_elec_idle_reset ; - - wire [NO_OF_LANES-1:0] plllkdet; - wire RxResetDone; - wire plm_in_l0 = (pl_ltssm_state == 6'h16); - - reg local_pcs_reset; - reg local_pcs_reset_done; - reg [3:0] cnt_local_pcs_reset; - reg [4:0] phy_rdy_pre_cnt; - -gtx_wrapper_v6 #( - - .NO_OF_LANES(NO_OF_LANES), - .REF_CLK_FREQ(REF_CLK_FREQ), - .PL_FAST_TRAIN(PL_FAST_TRAIN) - -) -gtx_v6_i ( - - // TX - - .TX(pci_exp_txp[((NO_OF_LANES)-1):0]), - .TX_(pci_exp_txn[((NO_OF_LANES)-1):0]), - .TxData(gt_tx_data[((16*NO_OF_LANES)-1):0]), - .TxDataK(gt_tx_data_k[((2*NO_OF_LANES)-1):0]), - .TxElecIdle(gt_tx_elec_idle[((NO_OF_LANES)-1):0]), - .TxCompliance(gt_tx_char_disp_mode[((NO_OF_LANES)-1):0]), - - // RX - - .RX(pci_exp_rxp[((NO_OF_LANES)-1):0]), - .RX_(pci_exp_rxn[((NO_OF_LANES)-1):0]), - .RxData(gt_rx_data_wire[((16*NO_OF_LANES)-1):0]), - .RxDataK(gt_rx_data_k_wire[((2*NO_OF_LANES)-1):0]), - .RxPolarity(gt_rx_polarity[((NO_OF_LANES)-1):0]), - .RxValid(gt_rx_valid_wire[((NO_OF_LANES)-1):0]), - .RxElecIdle(gt_rx_elec_idle_wire[((NO_OF_LANES)-1):0]), - .RxStatus(gt_rx_status_wire[((3*NO_OF_LANES)-1):0]), - - // other - .GTRefClkout(), - .RxPLLLkDet(plllkdet), - .ChanIsAligned(gt_rxchanisaligned_wire[((NO_OF_LANES)-1):0]), - .TxDetectRx(gt_tx_detect_rx_loopback), - .PhyStatus(gt_rx_phy_status_wire[((NO_OF_LANES)-1):0]), - .TXPdownAsynch(~clock_locked), - .PowerDown(gt_power_down[((2*NO_OF_LANES)-1):0]), - .Rate(pipe_tx_rate), - .Reset_n(clock_locked), - .GTReset_n(sys_rst_n), - .PCLK(pipe_clk), - .REFCLK(sys_clk), - .TxDeemph(pipe_tx_deemph), - .TxMargin(pipe_tx_margin[2]), - .TxSwing(pipe_tx_swing), - .local_pcs_reset(local_pcs_reset), - .RxResetDone(RxResetDone), - .SyncDone(SyncDone) -); - -assign pipe_rx0_phy_status = gt_rx_phy_status_wire[0] ; -assign pipe_rx1_phy_status = (NO_OF_LANES >= 2 ) ? gt_rx_phy_status_wire[1] : 1'b0; -assign pipe_rx2_phy_status = (NO_OF_LANES >= 4 ) ? gt_rx_phy_status_wire[2] : 1'b0; -assign pipe_rx3_phy_status = (NO_OF_LANES >= 4 ) ? gt_rx_phy_status_wire[3] : 1'b0; -assign pipe_rx4_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[4] : 1'b0; -assign pipe_rx5_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[5] : 1'b0; -assign pipe_rx6_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[6] : 1'b0; -assign pipe_rx7_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[7] : 1'b0; - -assign pipe_rx0_chanisaligned = gt_rxchanisaligned_wire[0]; -assign pipe_rx1_chanisaligned = (NO_OF_LANES >= 2 ) ? gt_rxchanisaligned_wire[1] : 1'b0 ; -assign pipe_rx2_chanisaligned = (NO_OF_LANES >= 4 ) ? gt_rxchanisaligned_wire[2] : 1'b0 ; -assign pipe_rx3_chanisaligned = (NO_OF_LANES >= 4 ) ? gt_rxchanisaligned_wire[3] : 1'b0 ; -assign pipe_rx4_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[4] : 1'b0 ; -assign pipe_rx5_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[5] : 1'b0 ; -assign pipe_rx6_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[6] : 1'b0 ; -assign pipe_rx7_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[7] : 1'b0 ; - -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< - -assign pipe_rx0_char_is_k = {gt_rx_data_k_wire[1], gt_rx_data_k_wire[0]}; -assign pipe_rx1_char_is_k = (NO_OF_LANES >= 2 ) ? {gt_rx_data_k_wire[3], gt_rx_data_k_wire[2]} : 2'b0 ; -assign pipe_rx2_char_is_k = (NO_OF_LANES >= 4 ) ? {gt_rx_data_k_wire[5], gt_rx_data_k_wire[4]} : 2'b0 ; -assign pipe_rx3_char_is_k = (NO_OF_LANES >= 4 ) ? {gt_rx_data_k_wire[7], gt_rx_data_k_wire[6]} : 2'b0 ; -assign pipe_rx4_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[9], gt_rx_data_k_wire[8]} : 2'b0 ; -assign pipe_rx5_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[11], gt_rx_data_k_wire[10]} : 2'b0 ; -assign pipe_rx6_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[13], gt_rx_data_k_wire[12]} : 2'b0 ; -assign pipe_rx7_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[15], gt_rx_data_k_wire[14]} : 2'b0 ; - -assign pipe_rx0_data = {gt_rx_data_wire[ 15: 8], gt_rx_data_wire[ 7: 0]}; -assign pipe_rx1_data = (NO_OF_LANES >= 2 ) ? {gt_rx_data_wire[31:24], gt_rx_data_wire[23:16]} : 16'h0 ; -assign pipe_rx2_data = (NO_OF_LANES >= 4 ) ? {gt_rx_data_wire[47:40], gt_rx_data_wire[39:32]} : 16'h0 ; -assign pipe_rx3_data = (NO_OF_LANES >= 4 ) ? {gt_rx_data_wire[63:56], gt_rx_data_wire[55:48]} : 16'h0 ; -assign pipe_rx4_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[79:72], gt_rx_data_wire[71:64]} : 16'h0 ; -assign pipe_rx5_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[95:88], gt_rx_data_wire[87:80]} : 16'h0 ; -assign pipe_rx6_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[111:104], gt_rx_data_wire[103:96]} : 16'h0 ; -assign pipe_rx7_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[127:120], gt_rx_data_wire[119:112]} : 16'h0 ; - -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< - -assign pipe_rx0_elec_idle = gt_rx_elec_idle_wire[0]; -assign pipe_rx1_elec_idle = (NO_OF_LANES >= 2 ) ? gt_rx_elec_idle_wire[1] : 1'b1 ; -assign pipe_rx2_elec_idle = (NO_OF_LANES >= 4 ) ? gt_rx_elec_idle_wire[2] : 1'b1 ; -assign pipe_rx3_elec_idle = (NO_OF_LANES >= 4 ) ? gt_rx_elec_idle_wire[3] : 1'b1 ; -assign pipe_rx4_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[4] : 1'b1 ; -assign pipe_rx5_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[5] : 1'b1 ; -assign pipe_rx6_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[6] : 1'b1 ; -assign pipe_rx7_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[7] : 1'b1 ; - -assign pipe_rx0_status = gt_rx_status_wire[ 2: 0]; -assign pipe_rx1_status = (NO_OF_LANES >= 2 ) ? gt_rx_status_wire[ 5: 3] : 3'b0 ; -assign pipe_rx2_status = (NO_OF_LANES >= 4 ) ? gt_rx_status_wire[ 8: 6] : 3'b0 ; -assign pipe_rx3_status = (NO_OF_LANES >= 4 ) ? gt_rx_status_wire[11: 9] : 3'b0 ; -assign pipe_rx4_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[14:12] : 3'b0 ; -assign pipe_rx5_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[17:15] : 3'b0 ; -assign pipe_rx6_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[20:18] : 3'b0 ; -assign pipe_rx7_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[23:21] : 3'b0 ; - -assign pipe_rx0_valid = gt_rx_valid_wire[0]; -assign pipe_rx1_valid = (NO_OF_LANES >= 2 ) ? gt_rx_valid_wire[1] : 1'b0 ; -assign pipe_rx2_valid = (NO_OF_LANES >= 4 ) ? gt_rx_valid_wire[2] : 1'b0 ; -assign pipe_rx3_valid = (NO_OF_LANES >= 4 ) ? gt_rx_valid_wire[3] : 1'b0 ; -assign pipe_rx4_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[4] : 1'b0 ; -assign pipe_rx5_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[5] : 1'b0 ; -assign pipe_rx6_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[6] : 1'b0 ; -assign pipe_rx7_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[7] : 1'b0 ; - -assign gt_rx_polarity[0] = pipe_rx0_polarity; -assign gt_rx_polarity[1] = pipe_rx1_polarity; -assign gt_rx_polarity[2] = pipe_rx2_polarity; -assign gt_rx_polarity[3] = pipe_rx3_polarity; -assign gt_rx_polarity[4] = pipe_rx4_polarity; -assign gt_rx_polarity[5] = pipe_rx5_polarity; -assign gt_rx_polarity[6] = pipe_rx6_polarity; -assign gt_rx_polarity[7] = pipe_rx7_polarity; - -assign gt_power_down[ 1: 0] = pipe_tx0_powerdown; -assign gt_power_down[ 3: 2] = pipe_tx1_powerdown; -assign gt_power_down[ 5: 4] = pipe_tx2_powerdown; -assign gt_power_down[ 7: 6] = pipe_tx3_powerdown; -assign gt_power_down[ 9: 8] = pipe_tx4_powerdown; -assign gt_power_down[11:10] = pipe_tx5_powerdown; -assign gt_power_down[13:12] = pipe_tx6_powerdown; -assign gt_power_down[15:14] = pipe_tx7_powerdown; - -assign gt_tx_char_disp_mode = {pipe_tx7_compliance, - pipe_tx6_compliance, - pipe_tx5_compliance, - pipe_tx4_compliance, - pipe_tx3_compliance, - pipe_tx2_compliance, - pipe_tx1_compliance, - pipe_tx0_compliance}; - - -assign gt_tx_data_k = {pipe_tx7_char_is_k, - pipe_tx6_char_is_k, - pipe_tx5_char_is_k, - pipe_tx4_char_is_k, - pipe_tx3_char_is_k, - pipe_tx2_char_is_k, - pipe_tx1_char_is_k, - pipe_tx0_char_is_k}; - -assign gt_tx_data = {pipe_tx7_data, - pipe_tx6_data, - pipe_tx5_data, - pipe_tx4_data, - pipe_tx3_data, - pipe_tx2_data, - pipe_tx1_data, - pipe_tx0_data}; - -assign gt_tx_detect_rx_loopback = pipe_tx_rcvr_det; - -assign gt_tx_elec_idle = {pipe_tx7_elec_idle, - pipe_tx6_elec_idle, - pipe_tx5_elec_idle, - pipe_tx4_elec_idle, - pipe_tx3_elec_idle, - pipe_tx2_elec_idle, - pipe_tx1_elec_idle, - pipe_tx0_elec_idle}; - -assign gt_pll_lock = &plllkdet[NO_OF_LANES-1:0] | ~phy_rdy_pre_cnt[4]; - -// Asserted after all workarounds have completed. - -always @(posedge pipe_clk or negedge clock_locked) begin - - if (!clock_locked) begin - - phy_rdy_n <= #TCQ 1'b1; - - end else begin - - if (~&plllkdet[NO_OF_LANES-1:0]) - phy_rdy_n <= #TCQ 1'b1; - else if (local_pcs_reset_done && RxResetDone && phy_rdy_n && SyncDone) - phy_rdy_n <= #TCQ 1'b0; - - end - -end - -// Handle the warm reset case, where sys_rst_n is asseted when -// phy_rdy_n is asserted. phy_rdy_n is to be de-asserted -// before gt_pll_lock is de-asserted so that synnchronous -// logic see reset de-asset before clock is lost. - -always @(posedge pipe_clk or negedge clock_locked) begin - - if (!clock_locked) begin - - phy_rdy_pre_cnt <= #TCQ 5'b11111; - - end else begin - - if (gt_pll_lock && phy_rdy_n) - phy_rdy_pre_cnt <= #TCQ phy_rdy_pre_cnt + 1'b1; - - end - -end - -always @(posedge pipe_clk or negedge clock_locked) begin - - if (!clock_locked) begin - - cnt_local_pcs_reset <= #TCQ 4'hF; - local_pcs_reset <= #TCQ 1'b0; - local_pcs_reset_done <= #TCQ 1'b0; - - end else begin - - if ((local_pcs_reset == 1'b0) && (cnt_local_pcs_reset == 4'hF)) - local_pcs_reset <= #TCQ 1'b1; - else if ((local_pcs_reset == 1'b1) && (cnt_local_pcs_reset != 4'h0)) begin - local_pcs_reset <= #TCQ 1'b1; - cnt_local_pcs_reset <= #TCQ cnt_local_pcs_reset - 1'b1; - end else if ((local_pcs_reset == 1'b1) && (cnt_local_pcs_reset == 4'h0)) begin - local_pcs_reset <= #TCQ 1'b0; - local_pcs_reset_done <= #TCQ 1'b1; - end - - end - -end - -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< -//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< - -endmodule Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/gtx_wrapper_v6.v =================================================================== --- branches/Virtex6/ML605/v6_pcie_v1_3/source/gtx_wrapper_v6.v (revision 9) +++ branches/Virtex6/ML605/v6_pcie_v1_3/source/gtx_wrapper_v6.v (nonexistent) @@ -1,579 +0,0 @@ -//----------------------------------------------------------------------------- -// -// (c) Copyright 2009 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information of Xilinx, Inc. -// and is protected under U.S. and international copyright and other -// intellectual property laws. -// -// DISCLAIMER -// -// This disclaimer is not a license and does not grant any rights to the -// materials distributed herewith. Except as otherwise provided in a valid -// license issued to you by Xilinx, and to the maximum extent permitted by -// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -// and (2) Xilinx shall not be liable (whether in contract or tort, including -// negligence, or under any other theory of liability) for any loss or damage -// of any kind or nature related to, arising under or in connection with these -// materials, including for any direct, or any indirect, special, incidental, -// or consequential loss or damage (including loss of data, profits, goodwill, -// or any type of loss or damage suffered as a result of any action brought by -// a third party) even if such damage or loss was reasonably foreseeable or -// Xilinx had been advised of the possibility of the same. -// -// CRITICAL APPLICATIONS -// -// Xilinx products are not designed or intended to be fail-safe, or for use in -// any application requiring fail-safe performance, such as life-support or -// safety devices or systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any other -// applications that could lead to death, personal injury, or severe property -// or environmental damage (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and liability of any use of -// Xilinx products in Critical Applications, subject only to applicable laws -// and regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -// AT ALL TIMES. -// -//----------------------------------------------------------------------------- -// Project : Virtex-6 Integrated Block for PCI Express -// File : gtx_wrapper_v6.v -//-- Description: GTX module for Virtex6 PCIe Block -//-- -//-- -//-- -//-------------------------------------------------------------------------------- - -`timescale 1ns/1ns - -module gtx_wrapper_v6 ( - - // TX - TX, - TX_, - TxData, - TxDataK, - TxElecIdle, - TxCompliance, - - // RX - RX, - RX_, - RxData, - RxDataK, - RxPolarity, - RxValid, - RxElecIdle, - RxStatus, - - // other - GTRefClkout, - RxPLLLkDet, - TxDetectRx, - PhyStatus, - TXPdownAsynch, - PowerDown, - Rate, - Reset_n, - GTReset_n, - PCLK, - REFCLK, - TxDeemph, - TxMargin, - TxSwing, - ChanIsAligned, - local_pcs_reset, - RxResetDone, - SyncDone - - ); - - parameter NO_OF_LANES = 1; - parameter REF_CLK_FREQ = 0; - parameter PL_FAST_TRAIN = "FALSE"; - - localparam GTX_PLL_DIVSEL_FB = (REF_CLK_FREQ == 0) ? 5 : - (REF_CLK_FREQ == 1) ? 4 : - (REF_CLK_FREQ == 2) ? 2 : 0; - localparam SIMULATION = (PL_FAST_TRAIN == "TRUE") ? 1 : 0; - - localparam RXPLL_CP_CFG = (REF_CLK_FREQ == 0) ? 8'h09 : - (REF_CLK_FREQ == 1) ? 8'h09 : - (REF_CLK_FREQ == 2) ? 8'h0D : 8'h09; - - localparam TXPLL_CP_CFG = (REF_CLK_FREQ == 0) ? 8'h09 : - (REF_CLK_FREQ == 1) ? 8'h09 : - (REF_CLK_FREQ == 2) ? 8'h0D : 8'h09; - - localparam RX_CLK25_DIVIDER = (REF_CLK_FREQ == 0) ? 4 : - (REF_CLK_FREQ == 1) ? 5 : - (REF_CLK_FREQ == 2) ? 10 : 10 ; - - localparam TX_CLK25_DIVIDER = (REF_CLK_FREQ == 0) ? 4 : - (REF_CLK_FREQ == 1) ? 5 : - (REF_CLK_FREQ == 2) ? 10 : 10 ; - - // TX - output [NO_OF_LANES-1:0] TX; - output [NO_OF_LANES-1:0] TX_; - input [(NO_OF_LANES*16)-1:0] TxData; - input [(NO_OF_LANES*2)-1:0] TxDataK; - input [NO_OF_LANES-1:0] TxElecIdle; - input [NO_OF_LANES-1:0] TxCompliance; - - // RX - input [NO_OF_LANES-1:0] RX; - input [NO_OF_LANES-1:0] RX_; - output [(NO_OF_LANES*16)-1:0] RxData; - output [(NO_OF_LANES*2)-1:0] RxDataK; - input [NO_OF_LANES-1:0] RxPolarity; - output [NO_OF_LANES-1:0] RxValid; - output [NO_OF_LANES-1:0] RxElecIdle; - output [(NO_OF_LANES*3)-1:0] RxStatus; - - // other - output [NO_OF_LANES-1:0] GTRefClkout; - output [NO_OF_LANES-1:0] RxPLLLkDet; - input TxDetectRx; - output [NO_OF_LANES-1:0] PhyStatus; - input PCLK; - output [NO_OF_LANES-1:0] ChanIsAligned; - input TXPdownAsynch; - - input [(NO_OF_LANES*2)-1:0] PowerDown; - input Rate; - input Reset_n; - input GTReset_n; - input REFCLK; - input TxDeemph; - input TxMargin; - input TxSwing; - input local_pcs_reset; - output RxResetDone; - output SyncDone; - - genvar i; - - // dummy signals to avoid port mismatch with DUAL_GTX - wire [15:0] RxData_dummy; - wire [1:0] RxDataK_dummy; - wire [15:0] TxData_dummy; - wire [1:0] TxDataK_dummy; - - // inputs - wire [(NO_OF_LANES*16)-1:0] GTX_TxData = TxData; - wire [(NO_OF_LANES*2)-1:0] GTX_TxDataK = TxDataK; - wire [(NO_OF_LANES)-1:0] GTX_TxElecIdle = TxElecIdle; - wire [(NO_OF_LANES-1):0] GTX_TxCompliance = TxCompliance; - wire [(NO_OF_LANES)-1:0] GTX_RXP = RX[(NO_OF_LANES)-1:0]; - wire [(NO_OF_LANES)-1:0] GTX_RXN = RX_[(NO_OF_LANES)-1:0]; - - // outputs - wire [(NO_OF_LANES)-1:0] GTX_TXP; - wire [(NO_OF_LANES)-1:0] GTX_TXN; - wire [(NO_OF_LANES*16)-1:0] GTX_RxData; - wire [(NO_OF_LANES*2)-1:0] GTX_RxDataK; - wire [(NO_OF_LANES)-1:0] GTX_RxPolarity = RxPolarity ; - wire [(NO_OF_LANES)-1:0] GTX_RxValid; - wire [(NO_OF_LANES)-1:0] GTX_RxElecIdle; - wire [(NO_OF_LANES-1):0] GTX_RxResetDone; - wire [(NO_OF_LANES*3)-1:0] GTX_RxChbondLevel; - wire [(NO_OF_LANES*3)-1:0] GTX_RxStatus; - - - wire [3:0] RXCHBOND [NO_OF_LANES+1:0]; - wire [3:0] TXBYPASS8B10B = 4'b0000; - wire RXDEC8B10BUSE = 1'b1; - wire [NO_OF_LANES-1:0] GTX_PhyStatus; - wire RESETDONE [NO_OF_LANES-1:0]; - wire REFCLK; - wire GTXRESET = 1'b0; - - wire [NO_OF_LANES-1:0] SYNC_DONE; - wire [NO_OF_LANES-1:0] OUT_DIV_RESET; - wire [NO_OF_LANES-1:0] PCS_RESET; - wire [NO_OF_LANES-1:0] TXENPMAPHASEALIGN; - wire [NO_OF_LANES-1:0] TXPMASETPHASE; - wire [NO_OF_LANES-1:0] TXRESETDONE; - wire [NO_OF_LANES-1:0] TXRATEDONE; - wire [NO_OF_LANES-1:0] PHYSTATUS; - wire [NO_OF_LANES-1:0] RXVALID; - wire [NO_OF_LANES-1:0] RATE_CLK_SEL; - - - reg [(NO_OF_LANES-1):0] GTX_RxResetDone_q; - reg [(NO_OF_LANES-1):0] TXRESETDONE_q; - - wire [NO_OF_LANES-1:0] RxValid; - - assign RxResetDone = &(GTX_RxResetDone_q[(NO_OF_LANES)-1:0]); - assign TX[(NO_OF_LANES)-1:0] = GTX_TXP[(NO_OF_LANES)-1:0]; - assign TX_[(NO_OF_LANES)-1:0] = GTX_TXN[(NO_OF_LANES)-1:0]; - assign RXCHBOND[0] = 4'b0000; - assign TxData_dummy = 16'b0; - assign TxDataK_dummy = 2'b0; - assign SyncDone = &(SYNC_DONE[(NO_OF_LANES)-1:0]); - - // pipeline to improve timing - always @ (posedge PCLK) begin - - GTX_RxResetDone_q[(NO_OF_LANES)-1:0] <= GTX_RxResetDone[(NO_OF_LANES)-1:0]; - TXRESETDONE_q[(NO_OF_LANES)-1:0] <= TXRESETDONE[(NO_OF_LANES)-1:0]; - - end - - generate - - for (i=0; i < NO_OF_LANES; i=i+1) begin: GTXD - - assign GTX_RxChbondLevel[(3*i)+2:(3*i)] = (NO_OF_LANES-(i+1)); - - - GTX_RX_VALID_FILTER_V6 # ( - .CLK_COR_MIN_LAT(28) - ) - GTX_RX_VALID_FILTER ( - - .USER_RXCHARISK ( RxDataK[(2*i)+1:2*i] ), //O - .USER_RXDATA ( RxData[(16*i)+15:(16*i)+0] ), //O - .USER_RXVALID ( RxValid[i] ), //O - .USER_RXELECIDLE ( RxElecIdle[i] ), //O - .USER_RX_STATUS ( RxStatus[(3*i)+2:(3*i)] ), //O - .USER_RX_PHY_STATUS ( PhyStatus[i] ), //O - - - .GT_RXCHARISK ( GTX_RxDataK[(2*i)+1:2*i] ), //I - .GT_RXDATA ( GTX_RxData[(16*i)+15:(16*i)+0] ), //I - .GT_RXVALID ( GTX_RxValid[i] ), //I - .GT_RXELECIDLE ( GTX_RxElecIdle[i] ), //I - .GT_RX_STATUS ( GTX_RxStatus[(3*i)+2:(3*i)] ), //I - .GT_RX_PHY_STATUS ( PHYSTATUS[i] ), - - .USER_CLK ( PCLK ), //I - .RESET ( !Reset_n ) //I - - ); - - GTX_TX_SYNC_RATE_V6 # ( - .C_SIMULATION(SIMULATION) - ) - GTX_TX_SYNC ( - - .ENPMAPHASEALIGN ( TXENPMAPHASEALIGN[i] ), //O - .PMASETPHASE ( TXPMASETPHASE[i] ), //O - .SYNC_DONE ( SYNC_DONE[i] ), //O - .OUT_DIV_RESET ( OUT_DIV_RESET[i] ), //O - .PCS_RESET ( PCS_RESET[i] ), //O - .USER_PHYSTATUS ( PHYSTATUS[i] ), //O - .RATE_CLK_SEL ( RATE_CLK_SEL[i] ), //0 - - .USER_CLK ( PCLK ), //I - .RESET ( !Reset_n ), //I - .RATE ( Rate ), //I - .RATEDONE ( TXRATEDONE[i] ), //I - .GT_PHYSTATUS ( GTX_PhyStatus[i] ), //I - .RESETDONE ( TXRESETDONE_q[i] & GTX_RxResetDone_q[i] ), //I - - .DEBUG_STATUS ( ), // O - .ENPMA_STATE_MASK ( 3'b000 ), // I - .OUTDIV_STATE_MASK( 3'b010 ) // I - - ); - - GTXE1 # ( - - .TX_DRIVE_MODE("PIPE"), - .TX_CLK_SOURCE("RXPLL"), - .POWER_SAVE(10'b0000000100), - .CM_TRIM ( 2'b01 ), - .PMA_CDR_SCAN ( 27'h640404C ), - .PMA_CFG( 76'h0040000040000000003 ), - .RCV_TERM_GND ("TRUE"), - .RCV_TERM_VTTRX ("FALSE"), - .RX_DLYALIGN_EDGESET(5'b00010), - .RX_DLYALIGN_LPFINC(4'b0110), - .RX_DLYALIGN_OVRDSETTING(8'b10000000), - .TERMINATION_CTRL(5'b10101), - .TERMINATION_OVRD("TRUE"), - .TX_DLYALIGN_LPFINC(4'b0110), - .TX_DLYALIGN_OVRDSETTING(8'b10000000), - .TXPLL_CP_CFG( TXPLL_CP_CFG ), - .OOBDETECT_THRESHOLD( 3'b011 ), - .RXPLL_CP_CFG ( RXPLL_CP_CFG ), - //.TX_DETECT_RX_CFG( 14'h1832 ), - .TX_TDCC_CFG ( 2'b11 ), - .BIAS_CFG ( 17'h00014 ), - .AC_CAP_DIS ( "FALSE" ), - .DFE_CFG ( 8'b00011011 ), - .SIM_TX_ELEC_IDLE_LEVEL("1"), - .SIM_RECEIVER_DETECT_PASS("TRUE"), - .RX_EN_REALIGN_RESET_BUF("TRUE"), - .TX_IDLE_ASSERT_DELAY(3'b100), // TX-idle-set-to-idle (13 UI) - .TX_IDLE_DEASSERT_DELAY(3'b010), // TX-idle-to-diff (7 UI) - .CHAN_BOND_SEQ_2_CFG(5'b11111), // 5'b11111 for PCIE mode, 5'b00000 for other modes - .CHAN_BOND_KEEP_ALIGN("TRUE"), - .RX_IDLE_HI_CNT(4'b1000), - .RX_IDLE_LO_CNT(4'b0000), - .RX_EN_IDLE_RESET_BUF("TRUE"), - .TX_DATA_WIDTH(20), - .RX_DATA_WIDTH(20), - .ALIGN_COMMA_WORD(1), - .CHAN_BOND_1_MAX_SKEW(7), - .CHAN_BOND_2_MAX_SKEW(1), - .CHAN_BOND_SEQ_1_1(10'b0001000101), // D5.2 (end TS2) - .CHAN_BOND_SEQ_1_2(10'b0001000101), // D5.2 (end TS2) - .CHAN_BOND_SEQ_1_3(10'b0001000101), // D5.2 (end TS2) - .CHAN_BOND_SEQ_1_4(10'b0110111100), // K28.5 (COM) - .CHAN_BOND_SEQ_1_ENABLE(4'b1111), // order is 4321 - .CHAN_BOND_SEQ_2_1(10'b0100111100), // K28.1 (FTS) - .CHAN_BOND_SEQ_2_2(10'b0100111100), // K28.1 (FTS) - .CHAN_BOND_SEQ_2_3(10'b0110111100), // K28.5 (COM) - .CHAN_BOND_SEQ_2_4(10'b0100111100), // K28.1 (FTS) - .CHAN_BOND_SEQ_2_ENABLE(4'b1111), // order is 4321 - .CHAN_BOND_SEQ_2_USE("TRUE"), - .CHAN_BOND_SEQ_LEN(4), // 1..4 - .RX_CLK25_DIVIDER(RX_CLK25_DIVIDER), - .TX_CLK25_DIVIDER(TX_CLK25_DIVIDER), - .CLK_COR_ADJ_LEN(1), // 1..4 - .CLK_COR_DET_LEN(1), // 1..4 - .CLK_COR_INSERT_IDLE_FLAG("FALSE"), - .CLK_COR_KEEP_IDLE("FALSE"), - .CLK_COR_MAX_LAT(30), - .CLK_COR_MIN_LAT(28), - .CLK_COR_PRECEDENCE("TRUE"), - .CLK_CORRECT_USE("TRUE"), - .CLK_COR_REPEAT_WAIT(0), - .CLK_COR_SEQ_1_1(10'b0100011100), // K28.0 (SKP) - .CLK_COR_SEQ_1_2(10'b0000000000), - .CLK_COR_SEQ_1_3(10'b0000000000), - .CLK_COR_SEQ_1_4(10'b0000000000), - .CLK_COR_SEQ_1_ENABLE(4'b1111), - .CLK_COR_SEQ_2_1(10'b0000000000), - .CLK_COR_SEQ_2_2(10'b0000000000), - .CLK_COR_SEQ_2_3(10'b0000000000), - .CLK_COR_SEQ_2_4(10'b0000000000), - .CLK_COR_SEQ_2_ENABLE(4'b1111), - .CLK_COR_SEQ_2_USE("FALSE"), - .COMMA_10B_ENABLE(10'b1111111111), - .COMMA_DOUBLE("FALSE"), - .DEC_MCOMMA_DETECT("TRUE"), - .DEC_PCOMMA_DETECT("TRUE"), - .DEC_VALID_COMMA_ONLY("TRUE"), - .MCOMMA_10B_VALUE(10'b1010000011), - .MCOMMA_DETECT("TRUE"), - .PCI_EXPRESS_MODE("TRUE"), - .PCOMMA_10B_VALUE(10'b0101111100), - .PCOMMA_DETECT("TRUE"), - .RXPLL_DIVSEL_FB(GTX_PLL_DIVSEL_FB), // 1..5, 8, 10 - .TXPLL_DIVSEL_FB(GTX_PLL_DIVSEL_FB), // 1..5, 8, 10 - .RXPLL_DIVSEL_REF(1), // 1..6, 8, 10, 12, 16, 20 - .TXPLL_DIVSEL_REF(1), // 1..6, 8, 10, 12, 16, 20 - .RXPLL_DIVSEL_OUT(2), // 1, 2, 4 - .TXPLL_DIVSEL_OUT(2), // 1, 2, 4 - .RXPLL_DIVSEL45_FB(5), - .TXPLL_DIVSEL45_FB(5), - .RX_BUFFER_USE("TRUE"), - .RX_DECODE_SEQ_MATCH("TRUE"), - .RX_LOS_INVALID_INCR(8), // power of 2: 1..128 - .RX_LOSS_OF_SYNC_FSM("FALSE"), - .RX_LOS_THRESHOLD(128), // power of 2: 4..512 - .RX_SLIDE_MODE("AUTO"), // 00=OFF 01=AUTO 10=PCS 11=PMA - .RX_XCLK_SEL ("RXREC"), - .TX_BUFFER_USE("FALSE"), // Must be set to FALSE for use by PCIE - .TX_XCLK_SEL ("TXUSR"), // Must be set to TXUSR for use by PCIE - .TXPLL_LKDET_CFG (3'b101), - .RX_EYE_SCANMODE (2'b00), - .RX_EYE_OFFSET (8'h4C), - .PMA_RX_CFG ( 25'h05ce048 ), - .TRANS_TIME_NON_P2(8'h19), // Reduced simulation time - .TRANS_TIME_FROM_P2(12'h03c), // Reduced simulation time - .TRANS_TIME_TO_P2(10'h064), // Reduced simulation time - .TRANS_TIME_RATE(8'hD7), // Reduced simulation time - .SHOW_REALIGN_COMMA("FALSE"), - .TX_PMADATA_OPT(1'b0), // Lockup latch between PCS and PMA - .PMA_TX_CFG( 20'h00082 ) // Aligns posedge of USRCLK - - ) - GTX ( - - .COMFINISH (), - .COMINITDET (), - .COMSASDET (), - .COMWAKEDET (), - .DADDR (), - .DCLK (), - .DEN (), - .DFECLKDLYADJ (), - .DFECLKDLYADJMON (), - .DFEDLYOVRD ( 1'b1 ), - .DFEEYEDACMON (), - .DFESENSCAL (), - .DFETAP1 (), - .DFETAP1MONITOR (), - .DFETAP2 (), - .DFETAP2MONITOR (), - .DFETAP3 (), - .DFETAP3MONITOR (), - .DFETAP4 (), - .DFETAP4MONITOR (), - .DFETAPOVRD ( 1'b1 ), - .DI (), - .DRDY (), - .DRPDO (), - .DWE (), - .GATERXELECIDLE ( 1'b0 ), - .GREFCLKRX (), - .GREFCLKTX (), - .GTXRXRESET ( ~GTReset_n ), - .GTXTEST ( {11'b10000000000,OUT_DIV_RESET[i],1'b0} ), - .GTXTXRESET ( ~GTReset_n ), - .LOOPBACK ( 3'b000 ), - .MGTREFCLKFAB (), - .MGTREFCLKRX ( {1'b0,REFCLK} ), - .MGTREFCLKTX ( {1'b0,REFCLK} ), - .NORTHREFCLKRX (), - .NORTHREFCLKTX (), - .PHYSTATUS ( GTX_PhyStatus[i] ), - .PLLRXRESET ( 1'b0 ), - .PLLTXRESET ( 1'b0 ), - .PRBSCNTRESET ( 1'b0 ), - .RXBUFRESET ( 1'b0 ), - .RXBUFSTATUS (), - .RXBYTEISALIGNED (), - .RXBYTEREALIGN (), - .RXCDRRESET ( 1'b0 ), - .RXCHANBONDSEQ (), - .RXCHANISALIGNED ( ChanIsAligned[i] ), - .RXCHANREALIGN (), - .RXCHARISCOMMA (), - .RXCHARISK ( {RxDataK_dummy[1:0], GTX_RxDataK[(2*i)+1:2*i]} ), - .RXCHBONDI ( RXCHBOND[i] ), - .RXCHBONDLEVEL ( GTX_RxChbondLevel[(3*i)+2:(3*i)] ), - .RXCHBONDMASTER ( (i == 0) ), - .RXCHBONDO ( RXCHBOND[i+1] ), - .RXCHBONDSLAVE ( (i > 0) ), - .RXCLKCORCNT (), - .RXCOMMADET (), - .RXCOMMADETUSE ( 1'b1 ), - .RXDATA ( {RxData_dummy[15:0],GTX_RxData[(16*i)+15:(16*i)+0]} ), - .RXDATAVALID (), - .RXDEC8B10BUSE ( RXDEC8B10BUSE ), - .RXDISPERR (), - .RXDLYALIGNDISABLE ( 1'b1), - .RXELECIDLE ( GTX_RxElecIdle[i] ), - .RXENCHANSYNC ( 1'b1 ), - .RXENMCOMMAALIGN ( 1'b1 ), - .RXENPCOMMAALIGN ( 1'b1 ), - .RXENPMAPHASEALIGN ( 1'b0 ), - .RXENPRBSTST ( 3'b0 ), - .RXENSAMPLEALIGN ( 1'b0 ), - .RXEQMIX ( 10'b0110000110 ), - .RXGEARBOXSLIP ( 1'b0 ), - .RXHEADER (), - .RXHEADERVALID (), - .RXLOSSOFSYNC (), - .RXN ( GTX_RXN[i] ), - .RXNOTINTABLE (), - .RXOVERSAMPLEERR (), - .RXP ( GTX_RXP[i] ), - .RXPLLLKDET ( RxPLLLkDet[i] ), - .RXPLLLKDETEN ( 1'b1 ), - .RXPLLPOWERDOWN ( 1'b0 ), - .RXPLLREFSELDY ( 3'b000 ), - .RXPMASETPHASE ( 1'b0 ), - .RXPOLARITY ( GTX_RxPolarity[i] ), - .RXPOWERDOWN ( PowerDown[(2*i)+1:(2*i)] ), - .RXPRBSERR (), - .RXRATE ( {1'b1, Rate} ), - .RXRATEDONE ( ), - .RXRECCLK ( RXRECCLK ), - .RXRECCLKPCS ( ), - .RXRESET ( ~GTReset_n | local_pcs_reset | PCS_RESET[i] ), - .RXRESETDONE ( GTX_RxResetDone[i] ), - .RXRUNDISP (), - .RXSLIDE ( 1'b0 ), - .RXSTARTOFSEQ (), - .RXSTATUS ( GTX_RxStatus[(3*i)+2:(3*i)] ), - .RXUSRCLK ( PCLK ), - .RXUSRCLK2 ( PCLK ), - .RXVALID (GTX_RxValid[i]), - .SOUTHREFCLKRX (), - .SOUTHREFCLKTX (), - .TSTCLK0 ( 1'b0 ), - .TSTCLK1 ( 1'b0 ), - .TSTIN ( {20{1'b1}} ), - .TSTOUT (), - .TXBUFDIFFCTRL ( 3'b111 ), - .TXBUFSTATUS (), - .TXBYPASS8B10B ( TXBYPASS8B10B[3:0] ), - .TXCHARDISPMODE ( {3'b000, GTX_TxCompliance[i]} ), - .TXCHARDISPVAL ( 4'b0000 ), - .TXCHARISK ( {TxDataK_dummy[1:0], GTX_TxDataK[(2*i)+1:2*i]} ), - .TXCOMINIT ( 1'b0 ), - .TXCOMSAS ( 1'b0 ), - .TXCOMWAKE ( 1'b0 ), - .TXDATA ( {TxData_dummy[15:0], GTX_TxData[(16*i)+15:(16*i)+0]} ), - .TXDEEMPH ( TxDeemph ), - .TXDETECTRX ( TxDetectRx ), - .TXDIFFCTRL ( 4'b1111 ), - .TXDLYALIGNDISABLE ( 1'b1 ), - .TXELECIDLE ( GTX_TxElecIdle[i] ), - .TXENC8B10BUSE ( 1'b1 ), - .TXENPMAPHASEALIGN ( TXENPMAPHASEALIGN[i] ), - .TXENPRBSTST (), - .TXGEARBOXREADY (), - .TXHEADER (), - .TXINHIBIT ( 1'b0 ), - .TXKERR (), - .TXMARGIN ( {TxMargin, 2'b00} ), - .TXN ( GTX_TXN[i] ), - .TXOUTCLK (), - .TXOUTCLKPCS (), - .TXP ( GTX_TXP[i] ), - .TXPDOWNASYNCH ( TXPdownAsynch ), - .TXPLLLKDET ( ), - .TXPLLLKDETEN ( 1'b0 ), - .TXPLLPOWERDOWN ( 1'b0 ), - .TXPLLREFSELDY ( 3'b000 ), - .TXPMASETPHASE ( TXPMASETPHASE[i] ), - .TXPOLARITY ( 1'b0 ), - .TXPOSTEMPHASIS (), - .TXPOWERDOWN ( PowerDown[(2*i)+1:(2*i)] ), - .TXPRBSFORCEERR (), - .TXPREEMPHASIS (), - .TXRATE ( {1'b1, Rate} ), - .TXRESET ( ~GTReset_n | local_pcs_reset | PCS_RESET[i] ), - .TXRESETDONE ( TXRESETDONE[i] ), - .TXRUNDISP (), - .TXSEQUENCE (), - .TXSTARTSEQ (), - .TXSWING ( TxSwing ), - .TXUSRCLK ( PCLK ), - .TXUSRCLK2 ( PCLK ), - .USRCODEERR (), - .IGNORESIGDET (), - .PERFCLKRX (), - .PERFCLKTX (), - .RXDLYALIGNMONITOR (), - .RXDLYALIGNOVERRIDE ( 1'b0 ), - .RXDLYALIGNRESET (), - .RXDLYALIGNSWPPRECURB ( 1'b1 ), - .RXDLYALIGNUPDSW ( 1'b0 ), - .TXDLYALIGNMONITOR (), - .TXDLYALIGNOVERRIDE ( 1'b0 ), - .TXDLYALIGNRESET (), - .TXDLYALIGNUPDSW ( 1'b1 ), - .TXRATEDONE ( TXRATEDONE[i] ) - - - ); - end - - endgenerate - - -endmodule Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_bram_top_v6.v =================================================================== --- branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_bram_top_v6.v (revision 9) +++ branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_bram_top_v6.v (nonexistent) @@ -1,158 +0,0 @@ - -//----------------------------------------------------------------------------- -// -// (c) Copyright 2009 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information of Xilinx, Inc. -// and is protected under U.S. and international copyright and other -// intellectual property laws. -// -// DISCLAIMER -// -// This disclaimer is not a license and does not grant any rights to the -// materials distributed herewith. Except as otherwise provided in a valid -// license issued to you by Xilinx, and to the maximum extent permitted by -// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -// and (2) Xilinx shall not be liable (whether in contract or tort, including -// negligence, or under any other theory of liability) for any loss or damage -// of any kind or nature related to, arising under or in connection with these -// materials, including for any direct, or any indirect, special, incidental, -// or consequential loss or damage (including loss of data, profits, goodwill, -// or any type of loss or damage suffered as a result of any action brought by -// a third party) even if such damage or loss was reasonably foreseeable or -// Xilinx had been advised of the possibility of the same. -// -// CRITICAL APPLICATIONS -// -// Xilinx products are not designed or intended to be fail-safe, or for use in -// any application requiring fail-safe performance, such as life-support or -// safety devices or systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any other -// applications that could lead to death, personal injury, or severe property -// or environmental damage (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and liability of any use of -// Xilinx products in Critical Applications, subject only to applicable laws -// and regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -// AT ALL TIMES. -// -//----------------------------------------------------------------------------- -// Project : Virtex-6 Integrated Block for PCI Express -// File : pcie_bram_top_v6.v -//-- -//-- Description: BlockRAM top level module for Virtex6 PCIe Block -//-- -//-- -//-- -//-------------------------------------------------------------------------------- - -`timescale 1ns/1ns - -module pcie_bram_top_v6 -#( - parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 0, - - parameter VC0_TX_LASTPACKET = 31, - parameter TLM_TX_OVERHEAD = 24, - parameter TL_TX_RAM_RADDR_LATENCY = 1, - parameter TL_TX_RAM_RDATA_LATENCY = 2, - parameter TL_TX_RAM_WRITE_LATENCY = 1, - - parameter VC0_RX_LIMIT = 'h1FFF, - parameter TL_RX_RAM_RADDR_LATENCY = 1, - parameter TL_RX_RAM_RDATA_LATENCY = 2, - parameter TL_RX_RAM_WRITE_LATENCY = 1 -) - ( - input user_clk_i, - input reset_i, - - input mim_tx_wen, - input [12:0] mim_tx_waddr, - input [71:0] mim_tx_wdata, - input mim_tx_ren, - input mim_tx_rce, - input [12:0] mim_tx_raddr, - output [71:0] mim_tx_rdata, - - input mim_rx_wen, - input [12:0] mim_rx_waddr, - input [71:0] mim_rx_wdata, - input mim_rx_ren, - input mim_rx_rce, - input [12:0] mim_rx_raddr, - output [71:0] mim_rx_rdata - ); - - // TX calculations - localparam MPS_BYTES = ((DEV_CAP_MAX_PAYLOAD_SUPPORTED == 0) ? 128 : - (DEV_CAP_MAX_PAYLOAD_SUPPORTED == 1) ? 256 : - (DEV_CAP_MAX_PAYLOAD_SUPPORTED == 2) ? 512 : - 1024 ); - - localparam BYTES_TX = (VC0_TX_LASTPACKET + 1) * (MPS_BYTES + TLM_TX_OVERHEAD); - - localparam ROWS_TX = 1; - localparam COLS_TX = ((BYTES_TX <= 4096) ? 1 : - (BYTES_TX <= 8192) ? 2 : - (BYTES_TX <= 16384) ? 4 : - (BYTES_TX <= 32768) ? 8 : - 18 - ); - - // RX calculations - localparam ROWS_RX = 1; - - localparam COLS_RX = ((VC0_RX_LIMIT < 'h0200) ? 1 : - (VC0_RX_LIMIT < 'h0400) ? 2 : - (VC0_RX_LIMIT < 'h0800) ? 4 : - (VC0_RX_LIMIT < 'h1000) ? 8 : - 18 - ); - - initial begin - $display("[%t] %m ROWS_TX %0d COLS_TX %0d", $time, ROWS_TX, COLS_TX); - $display("[%t] %m ROWS_RX %0d COLS_RX %0d", $time, ROWS_RX, COLS_RX); - end - - pcie_brams_v6 #(.NUM_BRAMS (COLS_TX), - .RAM_RADDR_LATENCY(TL_TX_RAM_RADDR_LATENCY), - .RAM_RDATA_LATENCY(TL_TX_RAM_RDATA_LATENCY), - .RAM_WRITE_LATENCY(TL_TX_RAM_WRITE_LATENCY)) - pcie_brams_tx - ( - .user_clk_i(user_clk_i), - .reset_i(reset_i), - - .waddr(mim_tx_waddr), - .wen(mim_tx_wen), - .ren(mim_tx_ren), - .rce(mim_tx_rce), - .wdata(mim_tx_wdata), - .raddr(mim_tx_raddr), - .rdata(mim_tx_rdata) - ); - - pcie_brams_v6 #(.NUM_BRAMS (COLS_RX), - .RAM_RADDR_LATENCY(TL_RX_RAM_RADDR_LATENCY), - .RAM_RDATA_LATENCY(TL_RX_RAM_RDATA_LATENCY), - .RAM_WRITE_LATENCY(TL_RX_RAM_WRITE_LATENCY)) - pcie_brams_rx - ( - .user_clk_i(user_clk_i), - .reset_i(reset_i), - - .waddr(mim_rx_waddr), - .wen(mim_rx_wen), - .ren(mim_rx_ren), - .rce(mim_rx_rce), - .wdata(mim_rx_wdata), - .raddr(mim_rx_raddr), - .rdata(mim_rx_rdata) - ); - -endmodule // pcie_bram_top Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_brams_v6.v =================================================================== --- branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_brams_v6.v (revision 9) +++ branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_brams_v6.v (nonexistent) @@ -1,253 +0,0 @@ - -//----------------------------------------------------------------------------- -// -// (c) Copyright 2009 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information of Xilinx, Inc. -// and is protected under U.S. and international copyright and other -// intellectual property laws. -// -// DISCLAIMER -// -// This disclaimer is not a license and does not grant any rights to the -// materials distributed herewith. Except as otherwise provided in a valid -// license issued to you by Xilinx, and to the maximum extent permitted by -// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -// and (2) Xilinx shall not be liable (whether in contract or tort, including -// negligence, or under any other theory of liability) for any loss or damage -// of any kind or nature related to, arising under or in connection with these -// materials, including for any direct, or any indirect, special, incidental, -// or consequential loss or damage (including loss of data, profits, goodwill, -// or any type of loss or damage suffered as a result of any action brought by -// a third party) even if such damage or loss was reasonably foreseeable or -// Xilinx had been advised of the possibility of the same. -// -// CRITICAL APPLICATIONS -// -// Xilinx products are not designed or intended to be fail-safe, or for use in -// any application requiring fail-safe performance, such as life-support or -// safety devices or systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any other -// applications that could lead to death, personal injury, or severe property -// or environmental damage (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and liability of any use of -// Xilinx products in Critical Applications, subject only to applicable laws -// and regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -// AT ALL TIMES. -// -//----------------------------------------------------------------------------- -// Project : Virtex-6 Integrated Block for PCI Express -// File : pcie_brams_v6.v -//-- -//-- Description: BlockRAM module for Virtex6 PCIe Block -//-- -//-- -//-- -//-------------------------------------------------------------------------------- - -`timescale 1ns/1ns - -module pcie_brams_v6 -#( - // the number of BRAMs to use - // supported values are: - // 1,2,4,8,18 - parameter NUM_BRAMS = 0, - - // BRAM read address latency - // - // value meaning - // ==================================================== - // 0 BRAM read address port sample - // 1 BRAM read address port sample and a pipeline stage on the address port - parameter RAM_RADDR_LATENCY = 1, - - // BRAM read data latency - // - // value meaning - // ==================================================== - // 1 no BRAM OREG - // 2 use BRAM OREG - // 3 use BRAM OREG and a pipeline stage on the data port - parameter RAM_RDATA_LATENCY = 1, - - // BRAM write latency - // The BRAM write port is synchronous - // - // value meaning - // ==================================================== - // 0 BRAM write port sample - // 1 BRAM write port sample plus pipeline stage - parameter RAM_WRITE_LATENCY = 1 - ) - ( - input user_clk_i, - input reset_i, - - input wen, - input [12:0] waddr, - input [71:0] wdata, - input ren, - input rce, - input [12:0] raddr, - output [71:0] rdata - ); - - // turn on the bram output register - localparam DOB_REG = (RAM_RDATA_LATENCY > 1) ? 1 : 0; - - // calculate the data width of the individual brams - localparam [6:0] WIDTH = ((NUM_BRAMS == 1) ? 72 : - (NUM_BRAMS == 2) ? 36 : - (NUM_BRAMS == 4) ? 18 : - (NUM_BRAMS == 8) ? 9 : - 4 - ); - - parameter TCQ = 1; - - //synthesis translate_off - initial begin - $display("[%t] %m NUM_BRAMS %0d DOB_REG %0d WIDTH %0d RAM_WRITE_LATENCY %0d RAM_RADDR_LATENCY %0d RAM_RDATA_LATENCY %0d", - $time, NUM_BRAMS, DOB_REG, WIDTH, RAM_WRITE_LATENCY, RAM_RADDR_LATENCY, RAM_RDATA_LATENCY); - - case (NUM_BRAMS) - 1,2,4,8,18:; - default: - begin - $display("[%t] %m Error NUM_BRAMS %0d not supported", $time, NUM_BRAMS); - $finish; - end - endcase // case(NUM_BRAMS) - - case (RAM_RADDR_LATENCY) - 0,1:; - default: - begin - $display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RADDR_LATENCY); - $finish; - end - endcase // case (RAM_RADDR_LATENCY) - - case (RAM_RDATA_LATENCY) - 1,2,3:; - default: - begin - $display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RDATA_LATENCY); - $finish; - end - endcase // case (RAM_RDATA_LATENCY) - - case (RAM_WRITE_LATENCY) - 0,1:; - default: - begin - $display("[%t] %m Error RAM_WRITE_LATENCY %0d not supported", $time, RAM_WRITE_LATENCY); - $finish; - end - endcase // case(RAM_WRITE_LATENCY) - - end - //synthesis translate_on - - // model the delays for ram write latency - - wire wen_int; - wire [12:0] waddr_int; - wire [71:0] wdata_int; - - generate if (RAM_WRITE_LATENCY == 1) begin : wr_lat_2 - reg wen_dly; - reg [12:0] waddr_dly; - reg [71:0] wdata_dly; - - always @(posedge user_clk_i) begin - if (reset_i) begin - wen_dly <= #TCQ 1'b0; - waddr_dly <= #TCQ 13'b0; - wdata_dly <= #TCQ 72'b0; - end else begin - wen_dly <= #TCQ wen; - waddr_dly <= #TCQ waddr; - wdata_dly <= #TCQ wdata; - end - end - - assign wen_int = wen_dly; - assign waddr_int = waddr_dly; - assign wdata_int = wdata_dly; - end // if (RAM_WRITE_LATENCY == 1) - - else if (RAM_WRITE_LATENCY == 0) begin : wr_lat_1 - assign wen_int = wen; - assign waddr_int = waddr; - assign wdata_int = wdata; - end - endgenerate - - // model the delays for ram read latency - - wire ren_int; - wire [12:0] raddr_int; - wire [71:0] rdata_int; - - generate if (RAM_RADDR_LATENCY == 1) begin : raddr_lat_2 - reg ren_dly; - reg [12:0] raddr_dly; - - always @(posedge user_clk_i) begin - if (reset_i) begin - ren_dly <= #TCQ 1'b0; - raddr_dly <= #TCQ 13'b0; - end else begin - ren_dly <= #TCQ ren; - raddr_dly <= #TCQ raddr; - end // else: !if(reset_i) - end - - assign ren_int = ren_dly; - assign raddr_int = raddr_dly; - end // block: rd_lat_addr_2 - - else begin : raddr_lat_1 - assign ren_int = ren; - assign raddr_int = raddr; - end - endgenerate - - generate if (RAM_RDATA_LATENCY == 3) begin : rdata_lat_3 - reg [71:0] rdata_dly; - - always @(posedge user_clk_i) begin - if (reset_i) begin - rdata_dly <= #TCQ 72'b0; - end else begin - rdata_dly <= #TCQ rdata_int; - end // else: !if(reset_i) - end - - assign rdata = rdata_dly; - - end // block: rd_lat_data_3 - - else begin : rdata_lat_1_2 - assign #TCQ rdata = rdata_int; - end - endgenerate - - // instantiate the brams - generate - genvar i; - for (i = 0; i < NUM_BRAMS; i = i + 1) begin : brams - pcie_bram_v6 #(.DOB_REG(DOB_REG), .WIDTH(WIDTH)) - ram (.user_clk_i(user_clk_i), .reset_i(reset_i), - .wen_i(wen_int), .waddr_i(waddr_int), .wdata_i(wdata_int[(((i + 1) * WIDTH) - 1): (i * WIDTH)]), - .ren_i(ren_int), .raddr_i(raddr_int), .rdata_o(rdata_int[(((i + 1) * WIDTH) - 1): (i * WIDTH)]), .rce_i(rce)); - end - endgenerate -endmodule // pcie_brams_v6 Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_pipe_misc_v6.v =================================================================== --- branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_pipe_misc_v6.v (revision 9) +++ branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_pipe_misc_v6.v (nonexistent) @@ -1,194 +0,0 @@ -//----------------------------------------------------------------------------- -// -// (c) Copyright 2009 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information of Xilinx, Inc. -// and is protected under U.S. and international copyright and other -// intellectual property laws. -// -// DISCLAIMER -// -// This disclaimer is not a license and does not grant any rights to the -// materials distributed herewith. Except as otherwise provided in a valid -// license issued to you by Xilinx, and to the maximum extent permitted by -// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -// and (2) Xilinx shall not be liable (whether in contract or tort, including -// negligence, or under any other theory of liability) for any loss or damage -// of any kind or nature related to, arising under or in connection with these -// materials, including for any direct, or any indirect, special, incidental, -// or consequential loss or damage (including loss of data, profits, goodwill, -// or any type of loss or damage suffered as a result of any action brought by -// a third party) even if such damage or loss was reasonably foreseeable or -// Xilinx had been advised of the possibility of the same. -// -// CRITICAL APPLICATIONS -// -// Xilinx products are not designed or intended to be fail-safe, or for use in -// any application requiring fail-safe performance, such as life-support or -// safety devices or systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any other -// applications that could lead to death, personal injury, or severe property -// or environmental damage (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and liability of any use of -// Xilinx products in Critical Applications, subject only to applicable laws -// and regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -// AT ALL TIMES. -// -//----------------------------------------------------------------------------- -// Project : Virtex-6 Integrated Block for PCI Express -// File : pcie_pipe_misc_v6.v -//-- -//-- Description: Misc PIPE module for Virtex6 PCIe Block -//-- -//-- -//-- -//-------------------------------------------------------------------------------- - -`timescale 1ns/1ns - -module pcie_pipe_misc_v6 # -( - parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages -) -( - - input wire pipe_tx_rcvr_det_i , - input wire pipe_tx_reset_i , - input wire pipe_tx_rate_i , - input wire pipe_tx_deemph_i , - input wire [2:0] pipe_tx_margin_i , - input wire pipe_tx_swing_i , - - output wire pipe_tx_rcvr_det_o , - output wire pipe_tx_reset_o , - output wire pipe_tx_rate_o , - output wire pipe_tx_deemph_o , - output wire [2:0] pipe_tx_margin_o , - output wire pipe_tx_swing_o , - - input wire pipe_clk , - input wire rst_n -); - -//******************************************************************// -// Reality check. // -//******************************************************************// - - parameter TCQ = 1; // clock to out delay model - - reg pipe_tx_rcvr_det_q ; - reg pipe_tx_reset_q ; - reg pipe_tx_rate_q ; - reg pipe_tx_deemph_q ; - reg [2:0] pipe_tx_margin_q ; - reg pipe_tx_swing_q ; - - reg pipe_tx_rcvr_det_qq ; - reg pipe_tx_reset_qq ; - reg pipe_tx_rate_qq ; - reg pipe_tx_deemph_qq ; - reg [2:0] pipe_tx_margin_qq ; - reg pipe_tx_swing_qq ; - - generate - - if (PIPE_PIPELINE_STAGES == 0) begin - - - assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i; - assign pipe_tx_reset_o = pipe_tx_reset_i; - assign pipe_tx_rate_o = pipe_tx_rate_i; - assign pipe_tx_deemph_o = pipe_tx_deemph_i; - assign pipe_tx_margin_o = pipe_tx_margin_i; - assign pipe_tx_swing_o = pipe_tx_swing_i; - - end else if (PIPE_PIPELINE_STAGES == 1) begin - - always @(posedge pipe_clk) begin - - if (rst_n) begin - - pipe_tx_rcvr_det_q <= #TCQ 0; - pipe_tx_reset_q <= #TCQ 1'b1; - pipe_tx_rate_q <= #TCQ 0; - pipe_tx_deemph_q <= #TCQ 1'b1; - pipe_tx_margin_q <= #TCQ 0; - pipe_tx_swing_q <= #TCQ 0; - - end else begin - - pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i; - pipe_tx_reset_q <= #TCQ pipe_tx_reset_i; - pipe_tx_rate_q <= #TCQ pipe_tx_rate_i; - pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i; - pipe_tx_margin_q <= #TCQ pipe_tx_margin_i; - pipe_tx_swing_q <= #TCQ pipe_tx_swing_i; - - end - - end - - assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_q; - assign pipe_tx_reset_o = pipe_tx_reset_q; - assign pipe_tx_rate_o = pipe_tx_rate_q; - assign pipe_tx_deemph_o = pipe_tx_deemph_q; - assign pipe_tx_margin_o = pipe_tx_margin_q; - assign pipe_tx_swing_o = pipe_tx_swing_q; - - end else if (PIPE_PIPELINE_STAGES == 2) begin - - always @(posedge pipe_clk) begin - - if (rst_n) begin - - pipe_tx_rcvr_det_q <= #TCQ 0; - pipe_tx_reset_q <= #TCQ 1'b1; - pipe_tx_rate_q <= #TCQ 0; - pipe_tx_deemph_q <= #TCQ 1'b1; - pipe_tx_margin_q <= #TCQ 0; - pipe_tx_swing_q <= #TCQ 0; - - pipe_tx_rcvr_det_qq <= #TCQ 0; - pipe_tx_reset_qq <= #TCQ 1'b1; - pipe_tx_rate_qq <= #TCQ 0; - pipe_tx_deemph_qq <= #TCQ 1'b1; - pipe_tx_margin_qq <= #TCQ 0; - pipe_tx_swing_qq <= #TCQ 0; - - end else begin - - pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i; - pipe_tx_reset_q <= #TCQ pipe_tx_reset_i; - pipe_tx_rate_q <= #TCQ pipe_tx_rate_i; - pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i; - pipe_tx_margin_q <= #TCQ pipe_tx_margin_i; - pipe_tx_swing_q <= #TCQ pipe_tx_swing_i; - - pipe_tx_rcvr_det_qq <= #TCQ pipe_tx_rcvr_det_q; - pipe_tx_reset_qq <= #TCQ pipe_tx_reset_q; - pipe_tx_rate_qq <= #TCQ pipe_tx_rate_q; - pipe_tx_deemph_qq <= #TCQ pipe_tx_deemph_q; - pipe_tx_margin_qq <= #TCQ pipe_tx_margin_q; - pipe_tx_swing_qq <= #TCQ pipe_tx_swing_q; - - end - - end - - assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_qq; - assign pipe_tx_reset_o = pipe_tx_reset_qq; - assign pipe_tx_rate_o = pipe_tx_rate_qq; - assign pipe_tx_deemph_o = pipe_tx_deemph_qq; - assign pipe_tx_margin_o = pipe_tx_margin_qq; - assign pipe_tx_swing_o = pipe_tx_swing_qq; - - end - - endgenerate - -endmodule Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/v6_pcie_v1_3.v =================================================================== --- branches/Virtex6/ML605/v6_pcie_v1_3/source/v6_pcie_v1_3.v (revision 9) +++ branches/Virtex6/ML605/v6_pcie_v1_3/source/v6_pcie_v1_3.v (nonexistent) @@ -1,1191 +0,0 @@ -//----------------------------------------------------------------------------- -// -// (c) Copyright 2009 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information of Xilinx, Inc. -// and is protected under U.S. and international copyright and other -// intellectual property laws. -// -// DISCLAIMER -// -// This disclaimer is not a license and does not grant any rights to the -// materials distributed herewith. Except as otherwise provided in a valid -// license issued to you by Xilinx, and to the maximum extent permitted by -// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -// and (2) Xilinx shall not be liable (whether in contract or tort, including -// negligence, or under any other theory of liability) for any loss or damage -// of any kind or nature related to, arising under or in connection with these -// materials, including for any direct, or any indirect, special, incidental, -// or consequential loss or damage (including loss of data, profits, goodwill, -// or any type of loss or damage suffered as a result of any action brought by -// a third party) even if such damage or loss was reasonably foreseeable or -// Xilinx had been advised of the possibility of the same. -// -// CRITICAL APPLICATIONS -// -// Xilinx products are not designed or intended to be fail-safe, or for use in -// any application requiring fail-safe performance, such as life-support or -// safety devices or systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any other -// applications that could lead to death, personal injury, or severe property -// or environmental damage (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and liability of any use of -// Xilinx products in Critical Applications, subject only to applicable laws -// and regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -// AT ALL TIMES. -// -//----------------------------------------------------------------------------- -// Project : Virtex-6 Integrated Block for PCI Express -// File : v6_pcie_v1_3.v -//-- -//-- Description: Virtex6 solution wrapper : Endpoint for PCI Express -//-- -//-- -//-- -//-------------------------------------------------------------------------------- - -`timescale 1ns/1ns - -module v6_pcie_v1_3 # ( - parameter ALLOW_X8_GEN2 = "FALSE", - parameter BAR0 = 32'hFFFF0000, - parameter BAR1 = 32'hFFF00000, - parameter BAR2 = 32'hFFFFF000, - parameter BAR3 = 32'h00000000, - parameter BAR4 = 32'h00000000, - parameter BAR5 = 32'h00000000, - - parameter CARDBUS_CIS_POINTER = 32'h00000000, - parameter CLASS_CODE = 24'h050000, - parameter CMD_INTX_IMPLEMENTED = "TRUE", - parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE", - parameter CPL_TIMEOUT_RANGES_SUPPORTED = 4'h2, - - parameter DEV_CAP_ENDPOINT_L0S_LATENCY = 7, - parameter DEV_CAP_ENDPOINT_L1_LATENCY = 7, - parameter DEV_CAP_EXT_TAG_SUPPORTED = "FALSE", - parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2, - parameter DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0, - parameter DEVICE_ID = 16'h0153, - - parameter DISABLE_LANE_REVERSAL = "TRUE", - parameter DISABLE_SCRAMBLING = "FALSE", - parameter DSN_BASE_PTR = 12'h100, - parameter DSN_CAP_NEXTPTR = 12'h000, - parameter DSN_CAP_ON = "TRUE", - - parameter ENABLE_MSG_ROUTE = 11'h00000000000, - parameter ENABLE_RX_TD_ECRC_TRIM = "TRUE", - parameter EXPANSION_ROM = 32'h00000000, - parameter EXT_CFG_CAP_PTR = 6'h3F, - parameter EXT_CFG_XP_CAP_PTR = 10'h3FF, - parameter HEADER_TYPE = 8'h00, - parameter INTERRUPT_PIN = 8'h1, - - parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE", - parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE", - parameter LINK_CAP_MAX_LINK_SPEED = 4'h1, - parameter LINK_CAP_MAX_LINK_WIDTH = 6'h04, - parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE", - - parameter LINK_CTRL2_DEEMPHASIS = "FALSE", - parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE", - parameter LINK_CTRL2_TARGET_LINK_SPEED = 4'h0, - parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "FALSE", - - parameter LL_ACK_TIMEOUT = 15'h0000, - parameter LL_ACK_TIMEOUT_EN = "FALSE", - parameter LL_ACK_TIMEOUT_FUNC = 0, - parameter LL_REPLAY_TIMEOUT = 15'h0000, - parameter LL_REPLAY_TIMEOUT_EN = "FALSE", - parameter LL_REPLAY_TIMEOUT_FUNC = 0, - - parameter LTSSM_MAX_LINK_WIDTH = LINK_CAP_MAX_LINK_WIDTH, - parameter MSI_CAP_MULTIMSGCAP = 0, - parameter MSI_CAP_MULTIMSG_EXTENSION = 0, - parameter MSI_CAP_ON = "TRUE", - parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "FALSE", - parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE", - - parameter MSIX_CAP_ON = "FALSE", - parameter MSIX_CAP_PBA_BIR = 0, - parameter MSIX_CAP_PBA_OFFSET = 29'h0, - parameter MSIX_CAP_TABLE_BIR = 0, - parameter MSIX_CAP_TABLE_OFFSET = 29'h0, - parameter MSIX_CAP_TABLE_SIZE = 11'h000, - - parameter PCIE_CAP_DEVICE_PORT_TYPE = 4'b0000, - parameter PCIE_CAP_INT_MSG_NUM = 5'h1, - parameter PCIE_CAP_NEXTPTR = 8'h00, - parameter PCIE_DRP_ENABLE = "FALSE", - parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages - - parameter PM_CAP_DSI = "FALSE", - parameter PM_CAP_D1SUPPORT = "FALSE", - parameter PM_CAP_D2SUPPORT = "FALSE", - parameter PM_CAP_NEXTPTR = 8'h48, - parameter PM_CAP_PMESUPPORT = 5'h0F, - parameter PM_CSR_NOSOFTRST = "TRUE", - - parameter PM_DATA_SCALE0 = 2'h0, - parameter PM_DATA_SCALE1 = 2'h0, - parameter PM_DATA_SCALE2 = 2'h0, - parameter PM_DATA_SCALE3 = 2'h0, - parameter PM_DATA_SCALE4 = 2'h0, - parameter PM_DATA_SCALE5 = 2'h0, - parameter PM_DATA_SCALE6 = 2'h0, - parameter PM_DATA_SCALE7 = 2'h0, - - parameter PM_DATA0 = 8'h00, - parameter PM_DATA1 = 8'h00, - parameter PM_DATA2 = 8'h00, - parameter PM_DATA3 = 8'h00, - parameter PM_DATA4 = 8'h00, - parameter PM_DATA5 = 8'h00, - parameter PM_DATA6 = 8'h00, - parameter PM_DATA7 = 8'h00, - - parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz - parameter REVISION_ID = 8'h06, - parameter SUBSYSTEM_ID = 16'hABB3, - parameter SUBSYSTEM_VENDOR_ID = 16'h0084, - - parameter TL_RX_RAM_RADDR_LATENCY = 0, - parameter TL_RX_RAM_RDATA_LATENCY = 2, - parameter TL_RX_RAM_WRITE_LATENCY = 0, - parameter TL_TX_RAM_RADDR_LATENCY = 0, - parameter TL_TX_RAM_RDATA_LATENCY = 2, - parameter TL_TX_RAM_WRITE_LATENCY = 0, - - parameter UPCONFIG_CAPABLE = "TRUE", - parameter USER_CLK_FREQ = 2, - parameter VC_BASE_PTR = 12'h0, - parameter VC_CAP_NEXTPTR = 12'h000, - parameter VC_CAP_ON = "FALSE", - parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE", - - parameter VC0_CPL_INFINITE = "TRUE", - parameter VC0_RX_RAM_LIMIT = 13'h7FF, - parameter VC0_TOTAL_CREDITS_CD = 308, - parameter VC0_TOTAL_CREDITS_CH = 36, - parameter VC0_TOTAL_CREDITS_NPH = 12, - parameter VC0_TOTAL_CREDITS_PD = 308, - parameter VC0_TOTAL_CREDITS_PH = 32, - parameter VC0_TX_LASTPACKET = 29, - - parameter VENDOR_ID = 16'h10DC, - parameter VSEC_BASE_PTR = 12'h0, - parameter VSEC_CAP_NEXTPTR = 12'h000, - parameter VSEC_CAP_ON = "FALSE", - - parameter AER_BASE_PTR = 12'h128, - parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE", - parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE", - parameter AER_CAP_ID = 16'h0001, - parameter AER_CAP_INT_MSG_NUM_MSI = 5'h0a, - parameter AER_CAP_INT_MSG_NUM_MSIX = 5'h15, - parameter AER_CAP_NEXTPTR = 12'h160, - parameter AER_CAP_ON = "FALSE", - parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE", - parameter AER_CAP_VERSION = 4'h1, - - parameter CAPABILITIES_PTR = 8'h40, - parameter CRM_MODULE_RSTS = 7'h00, - parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE", - parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE", - parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE", - parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE", - parameter DEV_CAP_RSVD_14_12 = 0, - parameter DEV_CAP_RSVD_17_16 = 0, - parameter DEV_CAP_RSVD_31_29 = 0, - parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE", - - parameter DISABLE_ASPM_L1_TIMER = "FALSE", - parameter DISABLE_BAR_FILTERING = "FALSE", - parameter DISABLE_ID_CHECK = "FALSE", - parameter DISABLE_RX_TC_FILTER = "FALSE", - parameter DNSTREAM_LINK_NUM = 8'h00, - - parameter DSN_CAP_ID = 16'h0003, - parameter DSN_CAP_VERSION = 4'h1, - parameter ENTER_RVRY_EI_L0 = "TRUE", - parameter INFER_EI = 5'h0c, - parameter IS_SWITCH = "FALSE", - - parameter LAST_CONFIG_DWORD = 10'h3FF, - parameter LINK_CAP_ASPM_SUPPORT = 1, - parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE", - parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7, - parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7, - parameter LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7, - parameter LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7, - parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7, - parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7, - parameter LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7, - parameter LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7, - parameter LINK_CAP_RSVD_23_22 = 0, - parameter LINK_CONTROL_RCB = 0, - - parameter MSI_BASE_PTR = 8'h48, - parameter MSI_CAP_ID = 8'h05, - parameter MSI_CAP_NEXTPTR = 8'h60, - parameter MSIX_BASE_PTR = 8'h9c, - parameter MSIX_CAP_ID = 8'h11, - parameter MSIX_CAP_NEXTPTR = 8'h00, - parameter N_FTS_COMCLK_GEN1 = 255, - parameter N_FTS_COMCLK_GEN2 = 254, - parameter N_FTS_GEN1 = 255, - parameter N_FTS_GEN2 = 255, - - parameter PCIE_BASE_PTR = 8'h60, - parameter PCIE_CAP_CAPABILITY_ID = 8'h10, - parameter PCIE_CAP_CAPABILITY_VERSION = 4'h2, - parameter PCIE_CAP_ON = "TRUE", - parameter PCIE_CAP_RSVD_15_14 = 0, - parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE", - parameter PCIE_REVISION = 2, - parameter PGL0_LANE = 0, - parameter PGL1_LANE = 1, - parameter PGL2_LANE = 2, - parameter PGL3_LANE = 3, - parameter PGL4_LANE = 4, - parameter PGL5_LANE = 5, - parameter PGL6_LANE = 6, - parameter PGL7_LANE = 7, - parameter PL_AUTO_CONFIG = 0, - parameter PL_FAST_TRAIN = "FALSE", - - parameter PM_BASE_PTR = 8'h40, - parameter PM_CAP_AUXCURRENT = 0, - parameter PM_CAP_ID = 8'h01, - parameter PM_CAP_ON = "TRUE", - parameter PM_CAP_PME_CLOCK = "FALSE", - parameter PM_CAP_RSVD_04 = 0, - parameter PM_CAP_VERSION = 3, - parameter PM_CSR_BPCCEN = "FALSE", - parameter PM_CSR_B2B3 = "FALSE", - - parameter RECRC_CHK = 0, - parameter RECRC_CHK_TRIM = "FALSE", - parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE", - parameter SELECT_DLL_IF = "FALSE", - parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE", - parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE", - parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE", - parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE", - parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE", - parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE", - parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE", - parameter SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000, - parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE", - parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE", - parameter SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0, - parameter SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00, - parameter SPARE_BIT0 = 0, - parameter SPARE_BIT1 = 0, - parameter SPARE_BIT2 = 0, - parameter SPARE_BIT3 = 0, - parameter SPARE_BIT4 = 0, - parameter SPARE_BIT5 = 0, - parameter SPARE_BIT6 = 0, - parameter SPARE_BIT7 = 0, - parameter SPARE_BIT8 = 0, - parameter SPARE_BYTE0 = 8'h00, - parameter SPARE_BYTE1 = 8'h00, - parameter SPARE_BYTE2 = 8'h00, - parameter SPARE_BYTE3 = 8'h00, - parameter SPARE_WORD0 = 32'h00000000, - parameter SPARE_WORD1 = 32'h00000000, - parameter SPARE_WORD2 = 32'h00000000, - parameter SPARE_WORD3 = 32'h00000000, - - parameter TL_RBYPASS = "FALSE", - parameter TL_TFC_DISABLE = "FALSE", - parameter TL_TX_CHECKS_DISABLE = "FALSE", - parameter EXIT_LOOPBACK_ON_EI = "TRUE", - parameter UPSTREAM_FACING = "TRUE", - parameter UR_INV_REQ = "TRUE", - - parameter VC_CAP_ID = 16'h0002, - parameter VC_CAP_VERSION = 4'h1, - parameter VSEC_CAP_HDR_ID = 16'h1234, - parameter VSEC_CAP_HDR_LENGTH = 12'h018, - parameter VSEC_CAP_HDR_REVISION = 4'h1, - parameter VSEC_CAP_ID = 16'h000b, - parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE", - parameter VSEC_CAP_VERSION = 4'h1 -) -( - //------------------------------------------------------- - // 1. PCI Express (pci_exp) Interface - //------------------------------------------------------- - - // Tx - output [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_txp, - output [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_txn, - - // Rx - input [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_rxp, - input [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_rxn, - - //------------------------------------------------------- - // 2. Transaction (TRN) Interface - //------------------------------------------------------- - - // Common - output trn_clk, - output trn_reset_n, - output trn_lnk_up_n, - - // Tx - output [5:0] trn_tbuf_av, - output trn_tcfg_req_n, - output trn_terr_drop_n, - output trn_tdst_rdy_n, - input [63:0] trn_td, - input trn_trem_n, - input trn_tsof_n, - input trn_teof_n, - input trn_tsrc_rdy_n, - input trn_tsrc_dsc_n, - input trn_terrfwd_n, - input trn_tcfg_gnt_n, - input trn_tstr_n, - - // Rx - output [63:0] trn_rd, - output trn_rrem_n, - output trn_rsof_n, - output trn_reof_n, - output trn_rsrc_rdy_n, - output trn_rsrc_dsc_n, - output trn_rerrfwd_n, - output [6:0] trn_rbar_hit_n, - input trn_rdst_rdy_n, - input trn_rnp_ok_n, - - // Flow Control - output [11:0] trn_fc_cpld, - output [7:0] trn_fc_cplh, - output [11:0] trn_fc_npd, - output [7:0] trn_fc_nph, - output [11:0] trn_fc_pd, - output [7:0] trn_fc_ph, - input [2:0] trn_fc_sel, - - - //------------------------------------------------------- - // 3. Configuration (CFG) Interface - //------------------------------------------------------- - - output [31:0] cfg_do, - output cfg_rd_wr_done_n, - input [31:0] cfg_di, - input [3:0] cfg_byte_en_n, - input [9:0] cfg_dwaddr, - input cfg_wr_en_n, - input cfg_rd_en_n, - - input cfg_err_cor_n, - input cfg_err_ur_n, - input cfg_err_ecrc_n, - input cfg_err_cpl_timeout_n, - input cfg_err_cpl_abort_n, - input cfg_err_cpl_unexpect_n, - input cfg_err_posted_n, - input cfg_err_locked_n, - input [47:0] cfg_err_tlp_cpl_header, - output cfg_err_cpl_rdy_n, - input cfg_interrupt_n, - output cfg_interrupt_rdy_n, - input cfg_interrupt_assert_n, - input [7:0] cfg_interrupt_di, - output [7:0] cfg_interrupt_do, - output [2:0] cfg_interrupt_mmenable, - output cfg_interrupt_msienable, - output cfg_interrupt_msixenable, - output cfg_interrupt_msixfm, - input cfg_turnoff_ok_n, - output cfg_to_turnoff_n, - input cfg_trn_pending_n, - input cfg_pm_wake_n, - output [7:0] cfg_bus_number, - output [4:0] cfg_device_number, - output [2:0] cfg_function_number, - output [15:0] cfg_status, - output [15:0] cfg_command, - output [15:0] cfg_dstatus, - output [15:0] cfg_dcommand, - output [15:0] cfg_lstatus, - output [15:0] cfg_lcommand, - output [15:0] cfg_dcommand2, - output [2:0] cfg_pcie_link_state_n, - input [63:0] cfg_dsn, - output cfg_pmcsr_pme_en, - output cfg_pmcsr_pme_status, - output [1:0] cfg_pmcsr_powerstate, - output lnk_clk_en, - - //------------------------------------------------------- - // 4. Physical Layer Control and Status (PL) Interface - //------------------------------------------------------- - - output [2:0] pl_initial_link_width, - output [1:0] pl_lane_reversal_mode, - output pl_link_gen2_capable, - output pl_link_partner_gen2_supported, - output pl_link_upcfg_capable, - output [5:0] pl_ltssm_state, - output pl_received_hot_rst, - output pl_sel_link_rate, - output [1:0] pl_sel_link_width, - input pl_directed_link_auton, - input [1:0] pl_directed_link_change, - input pl_directed_link_speed, - input [1:0] pl_directed_link_width, - input pl_upstream_prefer_deemph, - - //------------------------------------------------------- - // 5. System (SYS) Interface - //------------------------------------------------------- - - input sys_clk, - input sys_reset_n - - -); - - - wire rx_func_level_reset_n; - wire cfg_msg_received; - wire cfg_msg_received_pme_to; - - wire cfg_cmd_bme; - wire cfg_cmd_intdis; - wire cfg_cmd_io_en; - wire cfg_cmd_mem_en; - wire cfg_cmd_serr_en; - wire cfg_dev_control_aux_power_en ; - wire cfg_dev_control_corr_err_reporting_en ; - wire cfg_dev_control_enable_relaxed_order ; - wire cfg_dev_control_ext_tag_en ; - wire cfg_dev_control_fatal_err_reporting_en ; - wire [2:0] cfg_dev_control_maxpayload ; - wire [2:0] cfg_dev_control_max_read_req ; - wire cfg_dev_control_non_fatal_reporting_en ; - wire cfg_dev_control_nosnoop_en ; - wire cfg_dev_control_phantom_en ; - wire cfg_dev_control_ur_err_reporting_en ; - wire cfg_dev_control2_cpltimeout_dis ; - wire [3:0] cfg_dev_control2_cpltimeout_val ; - wire cfg_dev_status_corr_err_detected ; - wire cfg_dev_status_fatal_err_detected ; - wire cfg_dev_status_nonfatal_err_detected ; - wire cfg_dev_status_ur_detected ; - wire cfg_link_control_auto_bandwidth_int_en ; - wire cfg_link_control_bandwidth_int_en ; - wire cfg_link_control_hw_auto_width_dis ; - wire cfg_link_control_clock_pm_en ; - wire cfg_link_control_extended_sync ; - wire cfg_link_control_common_clock ; - wire cfg_link_control_retrain_link ; - wire cfg_link_control_linkdisable ; - wire cfg_link_control_rcb ; - wire [1:0] cfg_link_control_aspm_control ; - wire cfg_link_status_autobandwidth_status ; - wire cfg_link_status_bandwidth_status ; - wire cfg_link_status_dll_active ; - wire cfg_link_status_link_training ; - wire [3:0] cfg_link_status_negotiated_link_width ; - wire [1:0] cfg_link_status_current_speed ; - wire [15:0] cfg_msg_data; - - wire sys_reset_n_d; - wire phy_rdy_n; - - wire trn_lnk_up_n_int; - wire trn_lnk_up_n_int1; - - wire trn_reset_n_int; - wire trn_reset_n_int1; - - reg [7:0] cfg_bus_number_d; - reg [4:0] cfg_device_number_d; - reg [2:0] cfg_function_number_d; - - // assigns to outputs - - assign cfg_to_turnoff_n = ~cfg_msg_received_pme_to; - - assign cfg_status = {16'b0}; - - assign cfg_command = {5'b0, - cfg_cmd_intdis, - 1'b0, - cfg_cmd_serr_en, - 5'b0, - cfg_cmd_bme, - cfg_cmd_mem_en, - cfg_cmd_io_en}; - - assign cfg_dstatus = {10'h0, - ~cfg_trn_pending_n, - 1'b0, - cfg_dev_status_ur_detected, - cfg_dev_status_fatal_err_detected, - cfg_dev_status_nonfatal_err_detected, - cfg_dev_status_corr_err_detected}; - - assign cfg_dcommand = {1'b0, - cfg_dev_control_max_read_req, - cfg_dev_control_nosnoop_en, - cfg_dev_control_aux_power_en, - cfg_dev_control_phantom_en, - cfg_dev_control_ext_tag_en, - cfg_dev_control_maxpayload, - cfg_dev_control_enable_relaxed_order, - cfg_dev_control_ur_err_reporting_en, - cfg_dev_control_fatal_err_reporting_en, - cfg_dev_control_non_fatal_reporting_en, - cfg_dev_control_corr_err_reporting_en }; - - assign cfg_lstatus = {cfg_link_status_autobandwidth_status, - cfg_link_status_bandwidth_status, - cfg_link_status_dll_active, - (LINK_STATUS_SLOT_CLOCK_CONFIG == "TRUE") ? 1'b1 : 1'b0, - cfg_link_status_link_training, - 1'b0, - {2'b00, cfg_link_status_negotiated_link_width}, - {2'b00, cfg_link_status_current_speed} }; - - assign cfg_lcommand = {cfg_link_control_auto_bandwidth_int_en, - cfg_link_control_bandwidth_int_en, - cfg_link_control_hw_auto_width_dis, - cfg_link_control_clock_pm_en, - cfg_link_control_extended_sync, - cfg_link_control_common_clock, - cfg_link_control_retrain_link, - cfg_link_control_linkdisable, - cfg_link_control_rcb, - 1'b0, - cfg_link_control_aspm_control}; - - assign cfg_bus_number = cfg_bus_number_d; - - assign cfg_device_number = cfg_device_number_d; - - assign cfg_function_number = cfg_function_number_d; - - assign cfg_dcommand2 = {11'b0, - cfg_dev_control2_cpltimeout_dis, - cfg_dev_control2_cpltimeout_val}; - - // Capture Bus/Device/Function number - - always @(posedge trn_clk) begin - if (trn_lnk_up_n) cfg_bus_number_d <= 8'b0; - else if (~cfg_msg_received) cfg_bus_number_d <= cfg_msg_data[15:8]; - end - - always @(posedge trn_clk) begin - if (trn_lnk_up_n) cfg_device_number_d <= 5'b0; - else if (~cfg_msg_received) cfg_device_number_d <= cfg_msg_data[7:3]; - end - - always @(posedge trn_clk) begin - if (trn_lnk_up_n) cfg_function_number_d <= 3'b0; - else if (~cfg_msg_received) cfg_function_number_d <= cfg_msg_data[2:0]; - end - - // Generate trn_lnk_up_n - -FDCP #( - - .INIT(1'b1) - -) trn_lnk_up_n_i ( - - .Q (trn_lnk_up_n), - .D (trn_lnk_up_n_int1), - .C (trn_clk), - .CLR (1'b0), - .PRE (1'b0) - -); - -FDCP #( - - .INIT(1'b1) - -) trn_lnk_up_n_int_i ( - - .Q (trn_lnk_up_n_int1), - .D (trn_lnk_up_n_int), - .C (trn_clk), - .CLR (1'b0), - .PRE (1'b0) - -); - - // Generate trn_reset_n - -FDCP #( - - .INIT(1'b0) - -) trn_reset_n_i ( - - .Q (trn_reset_n), - .D (trn_reset_n_int1 & ~phy_rdy_n), - .C (trn_clk), - .CLR (~sys_reset_n_d), - .PRE (1'b0) - -); - -FDCP #( - - .INIT(1'b0) - -) trn_reset_n_int_i ( - - .Q (trn_reset_n_int1 ), - .D (trn_reset_n_int & ~phy_rdy_n), - .C (trn_clk), - .CLR (~sys_reset_n_d), - .PRE (1'b0) - -); - - - -//------------------------------------------------------- -// PCI Express Reset Delay Module -//------------------------------------------------------- - -pcie_reset_delay_v6 #( - - .PL_FAST_TRAIN ( PL_FAST_TRAIN ), - .REF_CLK_FREQ ( REF_CLK_FREQ ) - -) -pcie_reset_delay_i ( - - .ref_clk ( sys_clk_bufg ), - .sys_reset_n ( sys_reset_n ), - .delayed_sys_reset_n ( sys_reset_n_d ) - -); - -//------------------------------------------------------- -// PCI Express Clocking Module -//------------------------------------------------------- - -pcie_clocking_v6 #( - - .CAP_LINK_WIDTH(LINK_CAP_MAX_LINK_WIDTH), - .CAP_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED), - .REF_CLK_FREQ(REF_CLK_FREQ), - .USER_CLK_FREQ(USER_CLK_FREQ) - -) -pcie_clocking_i ( - - .sys_clk ( sys_clk ), - .gt_pll_lock ( gt_pll_lock ), - .sel_lnk_rate ( pl_sel_link_rate ), - .sel_lnk_width ( pl_sel_link_width ), - - .sys_clk_bufg ( sys_clk_bufg ), - .pipe_clk ( pipe_clk ), - .user_clk ( user_clk ), - .block_clk ( block_clk ), - .clock_locked ( clock_locked ) - -); - -//------------------------------------------------------- -// Virtex6 PCI Express Block Module -//------------------------------------------------------- - -pcie_2_0_v6 #( - - .REF_CLK_FREQ ( REF_CLK_FREQ ), - .PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES ), - .AER_BASE_PTR ( AER_BASE_PTR ), - .AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ), - .AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ), - .AER_CAP_ID ( AER_CAP_ID ), - .AER_CAP_INT_MSG_NUM_MSI ( AER_CAP_INT_MSG_NUM_MSI ), - .AER_CAP_INT_MSG_NUM_MSIX ( AER_CAP_INT_MSG_NUM_MSIX ), - .AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ), - .AER_CAP_ON ( AER_CAP_ON ), - .AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ), - .AER_CAP_VERSION ( AER_CAP_VERSION ), - .ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ), - .BAR0 ( BAR0 ), - .BAR1 ( BAR1 ), - .BAR2 ( BAR2 ), - .BAR3 ( BAR3 ), - .BAR4 ( BAR4 ), - .BAR5 ( BAR5 ), - .CAPABILITIES_PTR ( CAPABILITIES_PTR ), - .CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ), - .CLASS_CODE ( CLASS_CODE ), - .CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ), - .CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ), - .CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ), - .CRM_MODULE_RSTS ( CRM_MODULE_RSTS ), - .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ), - .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ), - .DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ), - .DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ), - .DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ), - .DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ), - .DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ), - .DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ), - .DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ), - .DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ), - .DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ), - .DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ), - .DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ), - .DEVICE_ID ( DEVICE_ID ), - .DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ), - .DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ), - .DISABLE_ID_CHECK ( DISABLE_ID_CHECK ), - .DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ), - .DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ), - .DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ), - .DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ), - .DSN_BASE_PTR ( DSN_BASE_PTR ), - .DSN_CAP_ID ( DSN_CAP_ID ), - .DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ), - .DSN_CAP_ON ( DSN_CAP_ON ), - .DSN_CAP_VERSION ( DSN_CAP_VERSION ), - .ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ), - .ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ), - .ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ), - .EXPANSION_ROM ( EXPANSION_ROM ), - .EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ), - .EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ), - .HEADER_TYPE ( HEADER_TYPE ), - .INFER_EI ( INFER_EI ), - .INTERRUPT_PIN ( INTERRUPT_PIN ), - .IS_SWITCH ( IS_SWITCH ), - .LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ), - .LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ), - .LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ), - .LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ), - .LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ), - .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ), - .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ), - .LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ), - .LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ), - .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ), - .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ), - .LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ), - .LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ), - .LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ), - .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ), - .LINK_CAP_RSVD_23_22 ( LINK_CAP_RSVD_23_22 ), - .LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ), - .LINK_CONTROL_RCB ( LINK_CONTROL_RCB ), - .LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ), - .LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ), - .LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ), - .LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ), - .LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ), - .LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ), - .LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ), - .LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ), - .LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ), - .LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ), - .LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ), - .MSI_BASE_PTR ( MSI_BASE_PTR ), - .MSI_CAP_ID ( MSI_CAP_ID ), - .MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ), - .MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ), - .MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ), - .MSI_CAP_ON ( MSI_CAP_ON ), - .MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ), - .MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ), - .MSIX_BASE_PTR ( MSIX_BASE_PTR ), - .MSIX_CAP_ID ( MSIX_CAP_ID ), - .MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ), - .MSIX_CAP_ON ( MSIX_CAP_ON ), - .MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ), - .MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ), - .MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ), - .MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ), - .MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ), - .N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ), - .N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ), - .N_FTS_GEN1 ( N_FTS_GEN1 ), - .N_FTS_GEN2 ( N_FTS_GEN2 ), - .PCIE_BASE_PTR ( PCIE_BASE_PTR ), - .PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ), - .PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ), - .PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ), - .PCIE_CAP_INT_MSG_NUM ( PCIE_CAP_INT_MSG_NUM ), - .PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ), - .PCIE_CAP_ON ( PCIE_CAP_ON ), - .PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ), - .PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ), - .PCIE_REVISION ( PCIE_REVISION ), - .PGL0_LANE ( PGL0_LANE ), - .PGL1_LANE ( PGL1_LANE ), - .PGL2_LANE ( PGL2_LANE ), - .PGL3_LANE ( PGL3_LANE ), - .PGL4_LANE ( PGL4_LANE ), - .PGL5_LANE ( PGL5_LANE ), - .PGL6_LANE ( PGL6_LANE ), - .PGL7_LANE ( PGL7_LANE ), - .PL_AUTO_CONFIG ( PL_AUTO_CONFIG ), - .PL_FAST_TRAIN ( PL_FAST_TRAIN ), - .PM_BASE_PTR ( PM_BASE_PTR ), - .PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ), - .PM_CAP_DSI ( PM_CAP_DSI ), - .PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ), - .PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ), - .PM_CAP_ID ( PM_CAP_ID ), - .PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ), - .PM_CAP_ON ( PM_CAP_ON ), - .PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ), - .PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ), - .PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ), - .PM_CAP_VERSION ( PM_CAP_VERSION ), - .PM_CSR_BPCCEN ( PM_CSR_BPCCEN ), - .PM_CSR_B2B3 ( PM_CSR_B2B3 ), - .PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ), - .PM_DATA_SCALE0 ( PM_DATA_SCALE0 ), - .PM_DATA_SCALE1 ( PM_DATA_SCALE1 ), - .PM_DATA_SCALE2 ( PM_DATA_SCALE2 ), - .PM_DATA_SCALE3 ( PM_DATA_SCALE3 ), - .PM_DATA_SCALE4 ( PM_DATA_SCALE4 ), - .PM_DATA_SCALE5 ( PM_DATA_SCALE5 ), - .PM_DATA_SCALE6 ( PM_DATA_SCALE6 ), - .PM_DATA_SCALE7 ( PM_DATA_SCALE7 ), - .PM_DATA0 ( PM_DATA0 ), - .PM_DATA1 ( PM_DATA1 ), - .PM_DATA2 ( PM_DATA2 ), - .PM_DATA3 ( PM_DATA3 ), - .PM_DATA4 ( PM_DATA4 ), - .PM_DATA5 ( PM_DATA5 ), - .PM_DATA6 ( PM_DATA6 ), - .PM_DATA7 ( PM_DATA7 ), - .RECRC_CHK ( RECRC_CHK ), - .RECRC_CHK_TRIM ( RECRC_CHK_TRIM ), - .REVISION_ID ( REVISION_ID ), - .ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ), - .SELECT_DLL_IF ( SELECT_DLL_IF ), - .SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ), - .SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ), - .SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ), - .SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ), - .SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ), - .SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ), - .SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ), - .SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ), - .SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ), - .SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ), - .SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ), - .SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ), - .SPARE_BIT0 ( SPARE_BIT0 ), - .SPARE_BIT1 ( SPARE_BIT1 ), - .SPARE_BIT2 ( SPARE_BIT2 ), - .SPARE_BIT3 ( SPARE_BIT3 ), - .SPARE_BIT4 ( SPARE_BIT4 ), - .SPARE_BIT5 ( SPARE_BIT5 ), - .SPARE_BIT6 ( SPARE_BIT6 ), - .SPARE_BIT7 ( SPARE_BIT7 ), - .SPARE_BIT8 ( SPARE_BIT8 ), - .SPARE_BYTE0 ( SPARE_BYTE0 ), - .SPARE_BYTE1 ( SPARE_BYTE1 ), - .SPARE_BYTE2 ( SPARE_BYTE2 ), - .SPARE_BYTE3 ( SPARE_BYTE3 ), - .SPARE_WORD0 ( SPARE_WORD0 ), - .SPARE_WORD1 ( SPARE_WORD1 ), - .SPARE_WORD2 ( SPARE_WORD2 ), - .SPARE_WORD3 ( SPARE_WORD3 ), - .SUBSYSTEM_ID ( SUBSYSTEM_ID ), - .SUBSYSTEM_VENDOR_ID ( SUBSYSTEM_VENDOR_ID ), - .TL_RBYPASS ( TL_RBYPASS ), - .TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ), - .TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ), - .TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ), - .TL_TFC_DISABLE ( TL_TFC_DISABLE ), - .TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ), - .TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ), - .TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ), - .TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ), - .UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ), - .UPSTREAM_FACING ( UPSTREAM_FACING ), - .EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ), - .UR_INV_REQ ( UR_INV_REQ ), - .USER_CLK_FREQ ( USER_CLK_FREQ ), - .VC_BASE_PTR ( VC_BASE_PTR ), - .VC_CAP_ID ( VC_CAP_ID ), - .VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ), - .VC_CAP_ON ( VC_CAP_ON ), - .VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ), - .VC_CAP_VERSION ( VC_CAP_VERSION ), - .VC0_CPL_INFINITE ( VC0_CPL_INFINITE ), - .VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ), - .VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ), - .VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ), - .VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ), - .VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ), - .VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ), - .VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ), - .VENDOR_ID ( VENDOR_ID ), - .VSEC_BASE_PTR ( VSEC_BASE_PTR ), - .VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ), - .VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ), - .VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ), - .VSEC_CAP_ID ( VSEC_CAP_ID ), - .VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ), - .VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ), - .VSEC_CAP_ON ( VSEC_CAP_ON ), - .VSEC_CAP_VERSION ( VSEC_CAP_VERSION ) - -) -pcie_2_0_i ( - - .PCIEXPRXN( pci_exp_rxn ), - .PCIEXPRXP( pci_exp_rxp ), - .PCIEXPTXN( pci_exp_txn ), - .PCIEXPTXP( pci_exp_txp ), - - .SYSCLK( sys_clk ), - .TRNLNKUPN( trn_lnk_up_n_int ), - .TRNCLK( trn_clk ), - - .FUNDRSTN (sys_reset_n_d), - .PHYRDYN( phy_rdy_n ), - - .LNKCLKEN ( lnk_clk_en ), - .USERRSTN( trn_reset_n_int ), - .RECEIVEDFUNCLVLRSTN( rx_func_level_reset_n ), - .SYSRSTN( ~phy_rdy_n ), - .PLRSTN( 1'b1 ), - .DLRSTN( 1'b1 ), - .TLRSTN( 1'b1 ), - .FUNCLVLRSTN( 1'b1 ), - .CMRSTN( 1'b1 ), - .CMSTICKYRSTN( 1'b1 ), - - .TRNRBARHITN( trn_rbar_hit_n ), - .TRNRD( trn_rd ), - .TRNRECRCERRN( ), - .TRNREOFN( trn_reof_n ), - .TRNRERRFWDN( trn_rerrfwd_n ), - .TRNRREMN( trn_rrem_n ), - .TRNRSOFN( trn_rsof_n ), - .TRNRSRCDSCN( trn_rsrc_dsc_n ), - .TRNRSRCRDYN( trn_rsrc_rdy_n ), - .TRNRDSTRDYN( trn_rdst_rdy_n ), - .TRNRNPOKN( trn_rnp_ok_n ), - - .TRNTBUFAV( trn_tbuf_av ), - .TRNTCFGREQN( trn_tcfg_req_n ), - .TRNTDLLPDSTRDYN( ), - .TRNTDSTRDYN( trn_tdst_rdy_n ), - .TRNTERRDROPN( trn_terr_drop_n ), - .TRNTCFGGNTN( trn_tcfg_gnt_n ), - .TRNTD( trn_td ), - .TRNTDLLPDATA( 32'b0 ), - .TRNTDLLPSRCRDYN( 1'b1 ), - .TRNTECRCGENN( 1'b1 ), - .TRNTEOFN( trn_teof_n ), - .TRNTERRFWDN( trn_terrfwd_n ), - .TRNTREMN( trn_trem_n ), - .TRNTSOFN( trn_tsof_n ), - .TRNTSRCDSCN( trn_tsrc_dsc_n ), - .TRNTSRCRDYN( trn_tsrc_rdy_n ), - .TRNTSTRN( trn_tstr_n ), - - .TRNFCCPLD( trn_fc_cpld ), - .TRNFCCPLH( trn_fc_cplh ), - .TRNFCNPD( trn_fc_npd ), - .TRNFCNPH( trn_fc_nph ), - .TRNFCPD( trn_fc_pd ), - .TRNFCPH( trn_fc_ph ), - .TRNFCSEL( trn_fc_sel ), - - .CFGAERECRCCHECKEN(), - .CFGAERECRCGENEN(), - .CFGCOMMANDBUSMASTERENABLE( cfg_cmd_bme ), - .CFGCOMMANDINTERRUPTDISABLE( cfg_cmd_intdis ), - .CFGCOMMANDIOENABLE( cfg_cmd_io_en ), - .CFGCOMMANDMEMENABLE( cfg_cmd_mem_en ), - .CFGCOMMANDSERREN( cfg_cmd_serr_en ), - .CFGDEVCONTROLAUXPOWEREN( cfg_dev_control_aux_power_en ), - .CFGDEVCONTROLCORRERRREPORTINGEN( cfg_dev_control_corr_err_reporting_en ), - .CFGDEVCONTROLENABLERO( cfg_dev_control_enable_relaxed_order ), - .CFGDEVCONTROLEXTTAGEN( cfg_dev_control_ext_tag_en ), - .CFGDEVCONTROLFATALERRREPORTINGEN( cfg_dev_control_fatal_err_reporting_en ), - .CFGDEVCONTROLMAXPAYLOAD( cfg_dev_control_maxpayload ), - .CFGDEVCONTROLMAXREADREQ( cfg_dev_control_max_read_req ), - .CFGDEVCONTROLNONFATALREPORTINGEN( cfg_dev_control_non_fatal_reporting_en ), - .CFGDEVCONTROLNOSNOOPEN( cfg_dev_control_nosnoop_en ), - .CFGDEVCONTROLPHANTOMEN( cfg_dev_control_phantom_en ), - .CFGDEVCONTROLURERRREPORTINGEN( cfg_dev_control_ur_err_reporting_en ), - .CFGDEVCONTROL2CPLTIMEOUTDIS( cfg_dev_control2_cpltimeout_dis ), - .CFGDEVCONTROL2CPLTIMEOUTVAL( cfg_dev_control2_cpltimeout_val ), - .CFGDEVSTATUSCORRERRDETECTED( cfg_dev_status_corr_err_detected ), - .CFGDEVSTATUSFATALERRDETECTED( cfg_dev_status_fatal_err_detected ), - .CFGDEVSTATUSNONFATALERRDETECTED( cfg_dev_status_nonfatal_err_detected ), - .CFGDEVSTATUSURDETECTED( cfg_dev_status_ur_detected ), - .CFGDO( cfg_do ), - .CFGERRAERHEADERLOGSETN(), - .CFGERRCPLRDYN( cfg_err_cpl_rdy_n ), - .CFGINTERRUPTDO( cfg_interrupt_do ), - .CFGINTERRUPTMMENABLE( cfg_interrupt_mmenable ), - .CFGINTERRUPTMSIENABLE( cfg_interrupt_msienable ), - .CFGINTERRUPTMSIXENABLE( cfg_interrupt_msixenable ), - .CFGINTERRUPTMSIXFM( cfg_interrupt_msixfm ), - .CFGINTERRUPTRDYN( cfg_interrupt_rdy_n ), - .CFGLINKCONTROLRCB( cfg_link_control_rcb ), - .CFGLINKCONTROLASPMCONTROL( cfg_link_control_aspm_control ), - .CFGLINKCONTROLAUTOBANDWIDTHINTEN( cfg_link_control_auto_bandwidth_int_en ), - .CFGLINKCONTROLBANDWIDTHINTEN( cfg_link_control_bandwidth_int_en ), - .CFGLINKCONTROLCLOCKPMEN( cfg_link_control_clock_pm_en ), - .CFGLINKCONTROLCOMMONCLOCK( cfg_link_control_common_clock ), - .CFGLINKCONTROLEXTENDEDSYNC( cfg_link_control_extended_sync ), - .CFGLINKCONTROLHWAUTOWIDTHDIS( cfg_link_control_hw_auto_width_dis ), - .CFGLINKCONTROLLINKDISABLE( cfg_link_control_linkdisable ), - .CFGLINKCONTROLRETRAINLINK( cfg_link_control_retrain_link ), - .CFGLINKSTATUSAUTOBANDWIDTHSTATUS( cfg_link_status_autobandwidth_status ), - .CFGLINKSTATUSBANDWITHSTATUS( cfg_link_status_bandwidth_status ), - .CFGLINKSTATUSCURRENTSPEED( cfg_link_status_current_speed ), - .CFGLINKSTATUSDLLACTIVE( cfg_link_status_dll_active ), - .CFGLINKSTATUSLINKTRAINING( cfg_link_status_link_training ), - .CFGLINKSTATUSNEGOTIATEDWIDTH( cfg_link_status_negotiated_link_width ), - .CFGMSGDATA( cfg_msg_data ), - .CFGMSGRECEIVED( cfg_msg_received ), - .CFGMSGRECEIVEDASSERTINTA(), - .CFGMSGRECEIVEDASSERTINTB(), - .CFGMSGRECEIVEDASSERTINTC(), - .CFGMSGRECEIVEDASSERTINTD(), - .CFGMSGRECEIVEDDEASSERTINTA(), - .CFGMSGRECEIVEDDEASSERTINTB(), - .CFGMSGRECEIVEDDEASSERTINTC(), - .CFGMSGRECEIVEDDEASSERTINTD(), - .CFGMSGRECEIVEDERRCOR(), - .CFGMSGRECEIVEDERRFATAL(), - .CFGMSGRECEIVEDERRNONFATAL(), - .CFGMSGRECEIVEDPMASNAK(), - .CFGMSGRECEIVEDPMETO( cfg_msg_received_pme_to ), - .CFGMSGRECEIVEDPMETOACK(), - .CFGMSGRECEIVEDPMPME(), - .CFGMSGRECEIVEDSETSLOTPOWERLIMIT(), - .CFGMSGRECEIVEDUNLOCK(), - .CFGPCIELINKSTATE( cfg_pcie_link_state_n ), - .CFGPMCSRPMEEN ( cfg_pmcsr_pme_en ), - .CFGPMCSRPMESTATUS ( cfg_pmcsr_pme_status ), - .CFGPMCSRPOWERSTATE ( cfg_pmcsr_powerstate ), - .CFGPMRCVASREQL1N(), - .CFGPMRCVENTERL1N(), - .CFGPMRCVENTERL23N(), - .CFGPMRCVREQACKN(), - .CFGRDWRDONEN( cfg_rd_wr_done_n ), - .CFGSLOTCONTROLELECTROMECHILCTLPULSE(), - .CFGTRANSACTION(), - .CFGTRANSACTIONADDR(), - .CFGTRANSACTIONTYPE(), - .CFGVCTCVCMAP(), - .CFGBYTEENN( cfg_byte_en_n ), - .CFGDI( cfg_di ), - .CFGDSBUSNUMBER( 8'b0 ), - .CFGDSDEVICENUMBER( 5'b0 ), - .CFGDSFUNCTIONNUMBER( 3'b0 ), - .CFGDSN( cfg_dsn ), - .CFGDWADDR( cfg_dwaddr ), - .CFGERRACSN( 1'b1 ), - .CFGERRAERHEADERLOG( 128'h0 ), - .CFGERRCORN( cfg_err_cor_n ), - .CFGERRCPLABORTN( cfg_err_cpl_abort_n ), - .CFGERRCPLTIMEOUTN( cfg_err_cpl_timeout_n ), - .CFGERRCPLUNEXPECTN( cfg_err_cpl_unexpect_n ), - .CFGERRECRCN( cfg_err_ecrc_n ), - .CFGERRLOCKEDN( cfg_err_locked_n ), - .CFGERRPOSTEDN( cfg_err_posted_n ), - .CFGERRTLPCPLHEADER( cfg_err_tlp_cpl_header ), - .CFGERRURN( cfg_err_ur_n ), - .CFGINTERRUPTASSERTN( cfg_interrupt_assert_n ), - .CFGINTERRUPTDI( cfg_interrupt_di ), - .CFGINTERRUPTN( cfg_interrupt_n ), - .CFGPMDIRECTASPML1N( 1'b1 ), - .CFGPMSENDPMACKN( 1'b1 ), - .CFGPMSENDPMETON( 1'b1 ), - .CFGPMSENDPMNAKN( 1'b1 ), - .CFGPMTURNOFFOKN( cfg_turnoff_ok_n ), - .CFGPMWAKEN( cfg_pm_wake_n ), - .CFGPORTNUMBER( 8'h0 ), - .CFGRDENN( cfg_rd_en_n ), - .CFGTRNPENDINGN( cfg_trn_pending_n ), - .CFGWRENN( cfg_wr_en_n ), - .CFGWRREADONLYN( 1'b1 ), - .CFGWRRW1CASRWN( 1'b1 ), - - .PLINITIALLINKWIDTH( pl_initial_link_width ), - .PLLANEREVERSALMODE( pl_lane_reversal_mode ), - .PLLINKGEN2CAP( pl_link_gen2_capable ), - .PLLINKPARTNERGEN2SUPPORTED( pl_link_partner_gen2_supported ), - .PLLINKUPCFGCAP( pl_link_upcfg_capable ), - .PLLTSSMSTATE( pl_ltssm_state ), - .PLPHYLNKUPN( ), // Debug - .PLRECEIVEDHOTRST( pl_received_hot_rst ), - .PLRXPMSTATE(), // Debug - .PLSELLNKRATE( pl_sel_link_rate ), - .PLSELLNKWIDTH( pl_sel_link_width ), - .PLTXPMSTATE(), // Debug - .PLDIRECTEDLINKAUTON( pl_directed_link_auton ), - .PLDIRECTEDLINKCHANGE( pl_directed_link_change ), - .PLDIRECTEDLINKSPEED( pl_directed_link_speed ), - .PLDIRECTEDLINKWIDTH( pl_directed_link_width ), - .PLDOWNSTREAMDEEMPHSOURCE( 1'b0 ), - .PLUPSTREAMPREFERDEEMPH( pl_upstream_prefer_deemph ), - .PLTRANSMITHOTRST( 1'b0 ), - - .DBGSCLRA(), - .DBGSCLRB(), - .DBGSCLRC(), - .DBGSCLRD(), - .DBGSCLRE(), - .DBGSCLRF(), - .DBGSCLRG(), - .DBGSCLRH(), - .DBGSCLRI(), - .DBGSCLRJ(), - .DBGSCLRK(), - .DBGVECA(), - .DBGVECB(), - .DBGVECC(), - .PLDBGVEC(), - .DBGMODE( 2'b0 ), - .DBGSUBMODE( 1'b0 ), - .PLDBGMODE( 3'b0 ), - - .DRPDO(), - .DRPDRDY(), - .DRPCLK(1'b0), - .DRPDADDR(9'b0), - .DRPDEN(1'b0), - .DRPDI(16'b0), - .DRPDWE(1'b0), - - .GTPLLLOCK( gt_pll_lock ), - .PIPECLK( pipe_clk ), - .USERCLK( user_clk ), - .CLOCKLOCKED( clock_locked ) - - -); - -endmodule Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_2_0_v6.v =================================================================== --- branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_2_0_v6.v (revision 9) +++ branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_2_0_v6.v (nonexistent) @@ -1,1914 +0,0 @@ -//----------------------------------------------------------------------------- -// -// (c) Copyright 2009 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information of Xilinx, Inc. -// and is protected under U.S. and international copyright and other -// intellectual property laws. -// -// DISCLAIMER -// -// This disclaimer is not a license and does not grant any rights to the -// materials distributed herewith. Except as otherwise provided in a valid -// license issued to you by Xilinx, and to the maximum extent permitted by -// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -// and (2) Xilinx shall not be liable (whether in contract or tort, including -// negligence, or under any other theory of liability) for any loss or damage -// of any kind or nature related to, arising under or in connection with these -// materials, including for any direct, or any indirect, special, incidental, -// or consequential loss or damage (including loss of data, profits, goodwill, -// or any type of loss or damage suffered as a result of any action brought by -// a third party) even if such damage or loss was reasonably foreseeable or -// Xilinx had been advised of the possibility of the same. -// -// CRITICAL APPLICATIONS -// -// Xilinx products are not designed or intended to be fail-safe, or for use in -// any application requiring fail-safe performance, such as life-support or -// safety devices or systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any other -// applications that could lead to death, personal injury, or severe property -// or environmental damage (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and liability of any use of -// Xilinx products in Critical Applications, subject only to applicable laws -// and regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -// AT ALL TIMES. -// -//----------------------------------------------------------------------------- -// Project : Virtex-6 Integrated Block for PCI Express -// File : pcie_2_0_v6.v -//-- Description: Solution wrapper for Virtex6 Hard Block for PCI Express -//-- -//-- -//-- -//-------------------------------------------------------------------------------- -`timescale 1ps/1ps - -(* X_CORE_INFO = "v6_pcie_v1_3, Coregen 11.3" *) -module pcie_2_0_v6 #( - parameter TCQ = 1, - parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz - parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages - parameter AER_BASE_PTR = 12'h128, - parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE", - parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE", - parameter AER_CAP_ID = 16'h0001, - parameter AER_CAP_INT_MSG_NUM_MSI = 5'h0a, - parameter AER_CAP_INT_MSG_NUM_MSIX = 5'h15, - parameter AER_CAP_NEXTPTR = 12'h160, - parameter AER_CAP_ON = "FALSE", - parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE", - parameter AER_CAP_VERSION = 4'h1, - parameter ALLOW_X8_GEN2 = "TRUE", - parameter BAR0 = 32'hffffff00, - parameter BAR1 = 32'hffff0000, - parameter BAR2 = 32'hffff000c, - parameter BAR3 = 32'hffffffff, - parameter BAR4 = 32'h00000000, - parameter BAR5 = 32'h00000000, - parameter CAPABILITIES_PTR = 8'h40, - parameter CARDBUS_CIS_POINTER = 32'h00000000, - parameter CLASS_CODE = 24'h000000, - parameter CMD_INTX_IMPLEMENTED = "TRUE", - parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE", - parameter CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0, - parameter CRM_MODULE_RSTS = 7'h00, - parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE", - parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE", - parameter DEV_CAP_ENDPOINT_L0S_LATENCY = 0, - parameter DEV_CAP_ENDPOINT_L1_LATENCY = 0, - parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE", - parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE", - parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2, - parameter DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0, - parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE", - parameter DEV_CAP_RSVD_14_12 = 0, - parameter DEV_CAP_RSVD_17_16 = 0, - parameter DEV_CAP_RSVD_31_29 = 0, - parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE", - parameter DEVICE_ID = 16'h0007, - parameter DISABLE_ASPM_L1_TIMER = "FALSE", - parameter DISABLE_BAR_FILTERING = "FALSE", - parameter DISABLE_ID_CHECK = "FALSE", - parameter DISABLE_LANE_REVERSAL = "FALSE", - parameter DISABLE_RX_TC_FILTER = "FALSE", - parameter DISABLE_SCRAMBLING = "FALSE", - parameter DNSTREAM_LINK_NUM = 8'h00, - parameter DSN_BASE_PTR = 12'h100, - parameter DSN_CAP_ID = 16'h0003, - parameter DSN_CAP_NEXTPTR = 12'h000, - parameter DSN_CAP_ON = "TRUE", - parameter DSN_CAP_VERSION = 4'h1, - parameter ENABLE_MSG_ROUTE = 11'h000, - parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE", - parameter ENTER_RVRY_EI_L0 = "TRUE", - parameter EXPANSION_ROM = 32'hfffff001, - parameter EXT_CFG_CAP_PTR = 6'h3f, - parameter EXT_CFG_XP_CAP_PTR = 10'h3ff, - parameter HEADER_TYPE = 8'h00, - parameter INFER_EI = 5'h00, - parameter INTERRUPT_PIN = 8'h01, - parameter IS_SWITCH = "FALSE", - parameter LAST_CONFIG_DWORD = 10'h042, - parameter LINK_CAP_ASPM_SUPPORT = 1, - parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE", - parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE", - parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE", - parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7, - parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7, - parameter LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7, - parameter LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7, - parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7, - parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7, - parameter LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7, - parameter LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7, - parameter LINK_CAP_MAX_LINK_SPEED = 4'h1, - parameter LINK_CAP_MAX_LINK_WIDTH = 6'h08, - parameter LINK_CAP_RSVD_23_22 = 0, - parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE", - parameter LINK_CONTROL_RCB = 0, - parameter LINK_CTRL2_DEEMPHASIS = "FALSE", - parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE", - parameter LINK_CTRL2_TARGET_LINK_SPEED = 4'h0, - parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE", - parameter LL_ACK_TIMEOUT = 15'h0204, - parameter LL_ACK_TIMEOUT_EN = "FALSE", - parameter LL_ACK_TIMEOUT_FUNC = 0, - parameter LL_REPLAY_TIMEOUT = 15'h060d, - parameter LL_REPLAY_TIMEOUT_EN = "FALSE", - parameter LL_REPLAY_TIMEOUT_FUNC = 0, - parameter LTSSM_MAX_LINK_WIDTH = LINK_CAP_MAX_LINK_WIDTH, - parameter MSI_BASE_PTR = 8'h48, - parameter MSI_CAP_ID = 8'h05, - parameter MSI_CAP_MULTIMSGCAP = 0, - parameter MSI_CAP_MULTIMSG_EXTENSION = 0, - parameter MSI_CAP_NEXTPTR = 8'h60, - parameter MSI_CAP_ON = "FALSE", - parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE", - parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE", - parameter MSIX_BASE_PTR = 8'h9c, - parameter MSIX_CAP_ID = 8'h11, - parameter MSIX_CAP_NEXTPTR = 8'h00, - parameter MSIX_CAP_ON = "FALSE", - parameter MSIX_CAP_PBA_BIR = 0, - parameter MSIX_CAP_PBA_OFFSET = 29'h00000050, - parameter MSIX_CAP_TABLE_BIR = 0, - parameter MSIX_CAP_TABLE_OFFSET = 29'h00000040, - parameter MSIX_CAP_TABLE_SIZE = 11'h000, - parameter N_FTS_COMCLK_GEN1 = 255, - parameter N_FTS_COMCLK_GEN2 = 255, - parameter N_FTS_GEN1 = 255, - parameter N_FTS_GEN2 = 255, - parameter PCIE_BASE_PTR = 8'h60, - parameter PCIE_CAP_CAPABILITY_ID = 8'h10, - parameter PCIE_CAP_CAPABILITY_VERSION = 4'h2, - parameter PCIE_CAP_DEVICE_PORT_TYPE = 4'h0, - parameter PCIE_CAP_INT_MSG_NUM = 5'h00, - parameter PCIE_CAP_NEXTPTR = 8'h00, - parameter PCIE_CAP_ON = "TRUE", - parameter PCIE_CAP_RSVD_15_14 = 0, - parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE", - parameter PCIE_REVISION = 2, - parameter PGL0_LANE = 0, - parameter PGL1_LANE = 1, - parameter PGL2_LANE = 2, - parameter PGL3_LANE = 3, - parameter PGL4_LANE = 4, - parameter PGL5_LANE = 5, - parameter PGL6_LANE = 6, - parameter PGL7_LANE = 7, - parameter PL_AUTO_CONFIG = 0, - parameter PL_FAST_TRAIN = "FALSE", - parameter PM_BASE_PTR = 8'h40, - parameter PM_CAP_AUXCURRENT = 0, - parameter PM_CAP_DSI = "FALSE", - parameter PM_CAP_D1SUPPORT = "TRUE", - parameter PM_CAP_D2SUPPORT = "TRUE", - parameter PM_CAP_ID = 8'h01, - parameter PM_CAP_NEXTPTR = 8'h48, - parameter PM_CAP_ON = "TRUE", - parameter PM_CAP_PME_CLOCK = "FALSE", - parameter PM_CAP_PMESUPPORT = 5'h0f, - parameter PM_CAP_RSVD_04 = 0, - parameter PM_CAP_VERSION = 3, - parameter PM_CSR_BPCCEN = "FALSE", - parameter PM_CSR_B2B3 = "FALSE", - parameter PM_CSR_NOSOFTRST = "TRUE", - parameter PM_DATA_SCALE0 = 2'h1, - parameter PM_DATA_SCALE1 = 2'h1, - parameter PM_DATA_SCALE2 = 2'h1, - parameter PM_DATA_SCALE3 = 2'h1, - parameter PM_DATA_SCALE4 = 2'h1, - parameter PM_DATA_SCALE5 = 2'h1, - parameter PM_DATA_SCALE6 = 2'h1, - parameter PM_DATA_SCALE7 = 2'h1, - parameter PM_DATA0 = 8'h01, - parameter PM_DATA1 = 8'h01, - parameter PM_DATA2 = 8'h01, - parameter PM_DATA3 = 8'h01, - parameter PM_DATA4 = 8'h01, - parameter PM_DATA5 = 8'h01, - parameter PM_DATA6 = 8'h01, - parameter PM_DATA7 = 8'h01, - parameter RECRC_CHK = 0, - parameter RECRC_CHK_TRIM = "FALSE", - parameter REVISION_ID = 8'h00, - parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE", - parameter SELECT_DLL_IF = "FALSE", - parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE", - parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE", - parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE", - parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE", - parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE", - parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE", - parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE", - parameter SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000, - parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE", - parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE", - parameter SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0, - parameter SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00, - parameter SPARE_BIT0 = 0, - parameter SPARE_BIT1 = 0, - parameter SPARE_BIT2 = 0, - parameter SPARE_BIT3 = 0, - parameter SPARE_BIT4 = 0, - parameter SPARE_BIT5 = 0, - parameter SPARE_BIT6 = 0, - parameter SPARE_BIT7 = 0, - parameter SPARE_BIT8 = 0, - parameter SPARE_BYTE0 = 8'h00, - parameter SPARE_BYTE1 = 8'h00, - parameter SPARE_BYTE2 = 8'h00, - parameter SPARE_BYTE3 = 8'h00, - parameter SPARE_WORD0 = 32'h00000000, - parameter SPARE_WORD1 = 32'h00000000, - parameter SPARE_WORD2 = 32'h00000000, - parameter SPARE_WORD3 = 32'h00000000, - parameter SUBSYSTEM_ID = 16'h0007, - parameter SUBSYSTEM_VENDOR_ID = 16'h10ee, - parameter TL_RBYPASS = "FALSE", - parameter TL_RX_RAM_RADDR_LATENCY = 0, - parameter TL_RX_RAM_RDATA_LATENCY = 2, - parameter TL_RX_RAM_WRITE_LATENCY = 0, - parameter TL_TFC_DISABLE = "FALSE", - parameter TL_TX_CHECKS_DISABLE = "FALSE", - parameter TL_TX_RAM_RADDR_LATENCY = 0, - parameter TL_TX_RAM_RDATA_LATENCY = 2, - parameter TL_TX_RAM_WRITE_LATENCY = 0, - parameter UPCONFIG_CAPABLE = "TRUE", - parameter UPSTREAM_FACING = "TRUE", - parameter EXIT_LOOPBACK_ON_EI = "TRUE", - parameter UR_INV_REQ = "TRUE", - parameter USER_CLK_FREQ = 3, - parameter VC_BASE_PTR = 12'h10c, - parameter VC_CAP_ID = 16'h0002, - parameter VC_CAP_NEXTPTR = 12'h000, - parameter VC_CAP_ON = "FALSE", - parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE", - parameter VC_CAP_VERSION = 4'h1, - parameter VC0_CPL_INFINITE = "TRUE", - parameter VC0_RX_RAM_LIMIT = 13'h03ff, - parameter VC0_TOTAL_CREDITS_CD = 127, - parameter VC0_TOTAL_CREDITS_CH = 31, - parameter VC0_TOTAL_CREDITS_NPH = 12, - parameter VC0_TOTAL_CREDITS_PD = 288, - parameter VC0_TOTAL_CREDITS_PH = 32, - parameter VC0_TX_LASTPACKET = 31, - parameter VENDOR_ID = 16'h10ee, - parameter VSEC_BASE_PTR = 12'h160, - parameter VSEC_CAP_HDR_ID = 16'h1234, - parameter VSEC_CAP_HDR_LENGTH = 12'h018, - parameter VSEC_CAP_HDR_REVISION = 4'h1, - parameter VSEC_CAP_ID = 16'h000b, - parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE", - parameter VSEC_CAP_NEXTPTR = 12'h000, - parameter VSEC_CAP_ON = "FALSE", - parameter VSEC_CAP_VERSION = 4'h1 - -) -( - - input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PCIEXPRXN, - input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PCIEXPRXP, - output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PCIEXPTXN, - output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PCIEXPTXP, - - input SYSCLK, - input FUNDRSTN, - - output TRNLNKUPN, - output TRNCLK, - - output PHYRDYN, - output USERRSTN, - output RECEIVEDFUNCLVLRSTN, - output LNKCLKEN, - input SYSRSTN, - input PLRSTN, - input DLRSTN, - input TLRSTN, - input FUNCLVLRSTN, - input CMRSTN, - input CMSTICKYRSTN, - - output [6:0] TRNRBARHITN, - output [63:0] TRNRD, - output TRNRECRCERRN, - output TRNREOFN, - output TRNRERRFWDN, - output TRNRREMN, - output TRNRSOFN, - output TRNRSRCDSCN, - output TRNRSRCRDYN, - input TRNRDSTRDYN, - input TRNRNPOKN, - - output [5:0] TRNTBUFAV, - output TRNTCFGREQN, - - output TRNTDLLPDSTRDYN, - output TRNTDSTRDYN, - output TRNTERRDROPN, - - input TRNTCFGGNTN, - - input [63:0] TRNTD, - input [31:0] TRNTDLLPDATA, - input TRNTDLLPSRCRDYN, - input TRNTECRCGENN, - input TRNTEOFN, - input TRNTERRFWDN, - input TRNTREMN, - - - input TRNTSOFN, - input TRNTSRCDSCN, - input TRNTSRCRDYN, - input TRNTSTRN, - - output [11:0] TRNFCCPLD, - output [7:0] TRNFCCPLH, - output [11:0] TRNFCNPD, - output [7:0] TRNFCNPH, - output [11:0] TRNFCPD, - output [7:0] TRNFCPH, - input [2:0] TRNFCSEL, - - output CFGAERECRCCHECKEN, - output CFGAERECRCGENEN, - output CFGCOMMANDBUSMASTERENABLE, - output CFGCOMMANDINTERRUPTDISABLE, - output CFGCOMMANDIOENABLE, - output CFGCOMMANDMEMENABLE, - output CFGCOMMANDSERREN, - output CFGDEVCONTROLAUXPOWEREN, - output CFGDEVCONTROLCORRERRREPORTINGEN, - output CFGDEVCONTROLENABLERO, - output CFGDEVCONTROLEXTTAGEN, - output CFGDEVCONTROLFATALERRREPORTINGEN, - output [2:0] CFGDEVCONTROLMAXPAYLOAD, - output [2:0] CFGDEVCONTROLMAXREADREQ, - output CFGDEVCONTROLNONFATALREPORTINGEN, - output CFGDEVCONTROLNOSNOOPEN, - output CFGDEVCONTROLPHANTOMEN, - output CFGDEVCONTROLURERRREPORTINGEN, - output CFGDEVCONTROL2CPLTIMEOUTDIS, - output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL, - output CFGDEVSTATUSCORRERRDETECTED, - output CFGDEVSTATUSFATALERRDETECTED, - output CFGDEVSTATUSNONFATALERRDETECTED, - output CFGDEVSTATUSURDETECTED, - output [31:0] CFGDO, - output CFGERRAERHEADERLOGSETN, - output CFGERRCPLRDYN, - output [7:0] CFGINTERRUPTDO, - output [2:0] CFGINTERRUPTMMENABLE, - output CFGINTERRUPTMSIENABLE, - output CFGINTERRUPTMSIXENABLE, - output CFGINTERRUPTMSIXFM, - output CFGINTERRUPTRDYN, - output CFGLINKCONTROLRCB, - output [1:0] CFGLINKCONTROLASPMCONTROL, - output CFGLINKCONTROLAUTOBANDWIDTHINTEN, - output CFGLINKCONTROLBANDWIDTHINTEN, - output CFGLINKCONTROLCLOCKPMEN, - output CFGLINKCONTROLCOMMONCLOCK, - output CFGLINKCONTROLEXTENDEDSYNC, - output CFGLINKCONTROLHWAUTOWIDTHDIS, - output CFGLINKCONTROLLINKDISABLE, - output CFGLINKCONTROLRETRAINLINK, - output CFGLINKSTATUSAUTOBANDWIDTHSTATUS, - output CFGLINKSTATUSBANDWITHSTATUS, - output [1:0] CFGLINKSTATUSCURRENTSPEED, - output CFGLINKSTATUSDLLACTIVE, - output CFGLINKSTATUSLINKTRAINING, - output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH, - output [15:0] CFGMSGDATA, - output CFGMSGRECEIVED, - output CFGMSGRECEIVEDASSERTINTA, - output CFGMSGRECEIVEDASSERTINTB, - output CFGMSGRECEIVEDASSERTINTC, - output CFGMSGRECEIVEDASSERTINTD, - output CFGMSGRECEIVEDDEASSERTINTA, - output CFGMSGRECEIVEDDEASSERTINTB, - output CFGMSGRECEIVEDDEASSERTINTC, - output CFGMSGRECEIVEDDEASSERTINTD, - output CFGMSGRECEIVEDERRCOR, - output CFGMSGRECEIVEDERRFATAL, - output CFGMSGRECEIVEDERRNONFATAL, - output CFGMSGRECEIVEDPMASNAK, - output CFGMSGRECEIVEDPMETO, - output CFGMSGRECEIVEDPMETOACK, - output CFGMSGRECEIVEDPMPME, - output CFGMSGRECEIVEDSETSLOTPOWERLIMIT, - output CFGMSGRECEIVEDUNLOCK, - output [2:0] CFGPCIELINKSTATE, - output CFGPMCSRPMEEN, - output CFGPMCSRPMESTATUS, - output [1:0] CFGPMCSRPOWERSTATE, - output CFGPMRCVASREQL1N, - output CFGPMRCVENTERL1N, - output CFGPMRCVENTERL23N, - output CFGPMRCVREQACKN, - output CFGRDWRDONEN, - output CFGSLOTCONTROLELECTROMECHILCTLPULSE, - output CFGTRANSACTION, - output [6:0] CFGTRANSACTIONADDR, - output CFGTRANSACTIONTYPE, - output [6:0] CFGVCTCVCMAP, - input [3:0] CFGBYTEENN, - input [31:0] CFGDI, - input [7:0] CFGDSBUSNUMBER, - input [4:0] CFGDSDEVICENUMBER, - input [2:0] CFGDSFUNCTIONNUMBER, - input [63:0] CFGDSN, - input [9:0] CFGDWADDR, - input CFGERRACSN, - input [127:0] CFGERRAERHEADERLOG, - input CFGERRCORN, - input CFGERRCPLABORTN, - input CFGERRCPLTIMEOUTN, - input CFGERRCPLUNEXPECTN, - input CFGERRECRCN, - input CFGERRLOCKEDN, - input CFGERRPOSTEDN, - input [47:0] CFGERRTLPCPLHEADER, - input CFGERRURN, - input CFGINTERRUPTASSERTN, - input [7:0] CFGINTERRUPTDI, - input CFGINTERRUPTN, - input CFGPMDIRECTASPML1N, - input CFGPMSENDPMACKN, - input CFGPMSENDPMETON, - input CFGPMSENDPMNAKN, - input CFGPMTURNOFFOKN, - input CFGPMWAKEN, - input [7:0] CFGPORTNUMBER, - input CFGRDENN, - input CFGTRNPENDINGN, - input CFGWRENN, - input CFGWRREADONLYN, - input CFGWRRW1CASRWN, - - output [2:0] PLINITIALLINKWIDTH, - output [1:0] PLLANEREVERSALMODE, - output PLLINKGEN2CAP, - output PLLINKPARTNERGEN2SUPPORTED, - output PLLINKUPCFGCAP, - output [5:0] PLLTSSMSTATE, - output PLPHYLNKUPN, - output PLRECEIVEDHOTRST, - output [1:0] PLRXPMSTATE, - output PLSELLNKRATE, - output [1:0] PLSELLNKWIDTH, - output [2:0] PLTXPMSTATE, - input PLDIRECTEDLINKAUTON, - input [1:0] PLDIRECTEDLINKCHANGE, - input PLDIRECTEDLINKSPEED, - input [1:0] PLDIRECTEDLINKWIDTH, - input PLDOWNSTREAMDEEMPHSOURCE, - input PLUPSTREAMPREFERDEEMPH, - input PLTRANSMITHOTRST, - - output DBGSCLRA, - output DBGSCLRB, - output DBGSCLRC, - output DBGSCLRD, - output DBGSCLRE, - output DBGSCLRF, - output DBGSCLRG, - output DBGSCLRH, - output DBGSCLRI, - output DBGSCLRJ, - output DBGSCLRK, - output [63:0] DBGVECA, - output [63:0] DBGVECB, - output [11:0] DBGVECC, - output [11:0] PLDBGVEC, - input [1:0] DBGMODE, - input DBGSUBMODE, - input [2:0] PLDBGMODE, - output [15:0] DRPDO, - output DRPDRDY, - input DRPCLK, - input [8:0] DRPDADDR, - input DRPDEN, - input [15:0] DRPDI, - input DRPDWE, - - output GTPLLLOCK, - input PIPECLK, - input USERCLK, - input CLOCKLOCKED - - - ); - - // wire declarations - - wire LL2BADDLLPERRN; - wire LL2BADTLPERRN; - wire LL2PROTOCOLERRN; - wire LL2REPLAYROERRN; - wire LL2REPLAYTOERRN; - wire LL2SUSPENDOKN; - wire LL2TFCINIT1SEQN; - wire LL2TFCINIT2SEQN; - wire [12:0] MIMRXRADDR; - wire MIMRXRCE; - wire MIMRXREN; - wire [12:0] MIMRXWADDR; - wire [67:0] MIMRXWDATA; - wire MIMRXWEN; - wire [12:0] MIMTXRADDR; - wire MIMTXRCE; - wire MIMTXREN; - wire [12:0] MIMTXWADDR; - wire [68:0] MIMTXWDATA; - wire MIMTXWEN; - wire PIPERX0POLARITY; - wire PIPERX1POLARITY; - wire PIPERX2POLARITY; - wire PIPERX3POLARITY; - wire PIPERX4POLARITY; - wire PIPERX5POLARITY; - wire PIPERX6POLARITY; - wire PIPERX7POLARITY; - wire PIPETXDEEMPH; - wire [2:0] PIPETXMARGIN; - wire PIPETXRATE; - wire PIPETXRCVRDET; - wire PIPETXRESET; - wire [1:0] PIPETX0CHARISK; - wire PIPETX0COMPLIANCE; - wire [15:0] PIPETX0DATA; - wire PIPETX0ELECIDLE; - wire [1:0] PIPETX0POWERDOWN; - wire [1:0] PIPETX1CHARISK; - wire PIPETX1COMPLIANCE; - wire [15:0] PIPETX1DATA; - wire PIPETX1ELECIDLE; - wire [1:0] PIPETX1POWERDOWN; - wire [1:0] PIPETX2CHARISK; - wire PIPETX2COMPLIANCE; - wire [15:0] PIPETX2DATA; - wire PIPETX2ELECIDLE; - wire [1:0] PIPETX2POWERDOWN; - wire [1:0] PIPETX3CHARISK; - wire PIPETX3COMPLIANCE; - wire [15:0] PIPETX3DATA; - wire PIPETX3ELECIDLE; - wire [1:0] PIPETX3POWERDOWN; - wire [1:0] PIPETX4CHARISK; - wire PIPETX4COMPLIANCE; - wire [15:0] PIPETX4DATA; - wire PIPETX4ELECIDLE; - wire [1:0] PIPETX4POWERDOWN; - wire [1:0] PIPETX5CHARISK; - wire PIPETX5COMPLIANCE; - wire [15:0] PIPETX5DATA; - wire PIPETX5ELECIDLE; - wire [1:0] PIPETX5POWERDOWN; - wire [1:0] PIPETX6CHARISK; - wire PIPETX6COMPLIANCE; - wire [15:0] PIPETX6DATA; - wire PIPETX6ELECIDLE; - wire [1:0] PIPETX6POWERDOWN; - wire [1:0] PIPETX7CHARISK; - wire PIPETX7COMPLIANCE; - wire [15:0] PIPETX7DATA; - wire PIPETX7ELECIDLE; - wire [1:0] PIPETX7POWERDOWN; - wire PL2LINKUPN; - wire PL2RECEIVERERRN; - wire PL2RECOVERYN; - wire PL2RXELECIDLE; - wire PL2SUSPENDOK; - wire TL2ASPMSUSPENDCREDITCHECKOKN; - wire TL2ASPMSUSPENDREQN; - wire TL2PPMSUSPENDOKN; - wire LL2SENDASREQL1N = 1'b1; - wire LL2SENDENTERL1N = 1'b1; - wire LL2SENDENTERL23N = 1'b1; - wire LL2SUSPENDNOWN = 1'b1; - wire LL2TLPRCVN = 1'b1; - wire [67:0] MIMRXRDATA; - wire [68:0] MIMTXRDATA; - wire [4:0] PL2DIRECTEDLSTATE = 5'b0; - wire TL2ASPMSUSPENDCREDITCHECKN; - wire TL2PPMSUSPENDREQN; - wire PIPERX0CHANISALIGNED; - wire [1:0] PIPERX0CHARISK; - wire [15:0] PIPERX0DATA; - wire PIPERX0ELECIDLE; - wire PIPERX0PHYSTATUS; - wire [2:0] PIPERX0STATUS; - wire PIPERX0VALID; - wire PIPERX1CHANISALIGNED; - wire [1:0] PIPERX1CHARISK; - wire [15:0] PIPERX1DATA; - wire PIPERX1ELECIDLE; - wire PIPERX1PHYSTATUS; - wire [2:0] PIPERX1STATUS; - wire PIPERX1VALID; - wire PIPERX2CHANISALIGNED; - wire [1:0] PIPERX2CHARISK; - wire [15:0] PIPERX2DATA; - wire PIPERX2ELECIDLE; - wire PIPERX2PHYSTATUS; - wire [2:0] PIPERX2STATUS; - wire PIPERX2VALID; - wire PIPERX3CHANISALIGNED; - wire [1:0] PIPERX3CHARISK; - wire [15:0] PIPERX3DATA; - wire PIPERX3ELECIDLE; - wire PIPERX3PHYSTATUS; - wire [2:0] PIPERX3STATUS; - wire PIPERX3VALID; - wire PIPERX4CHANISALIGNED; - wire [1:0] PIPERX4CHARISK; - wire [15:0] PIPERX4DATA; - wire PIPERX4ELECIDLE; - wire PIPERX4PHYSTATUS; - wire [2:0] PIPERX4STATUS; - wire PIPERX4VALID; - wire PIPERX5CHANISALIGNED; - wire [1:0] PIPERX5CHARISK; - wire [15:0] PIPERX5DATA; - wire PIPERX5ELECIDLE; - wire PIPERX5PHYSTATUS; - wire [2:0] PIPERX5STATUS; - wire PIPERX5VALID; - wire PIPERX6CHANISALIGNED; - wire [1:0] PIPERX6CHARISK; - wire [15:0] PIPERX6DATA; - wire PIPERX6ELECIDLE; - wire PIPERX6PHYSTATUS; - wire [2:0] PIPERX6STATUS; - wire PIPERX6VALID; - wire PIPERX7CHANISALIGNED; - wire [1:0] PIPERX7CHARISK; - wire [15:0] PIPERX7DATA; - wire PIPERX7ELECIDLE; - wire PIPERX7PHYSTATUS; - wire [2:0] PIPERX7STATUS; - wire PIPERX7VALID; - - wire PIPERX0POLARITYGT; - wire PIPERX1POLARITYGT; - wire PIPERX2POLARITYGT; - wire PIPERX3POLARITYGT; - wire PIPERX4POLARITYGT; - wire PIPERX5POLARITYGT; - wire PIPERX6POLARITYGT; - wire PIPERX7POLARITYGT; - wire PIPETXDEEMPHGT; - wire [2:0] PIPETXMARGINGT; - wire PIPETXRATEGT; - wire PIPETXRCVRDETGT; - wire [1:0] PIPETX0CHARISKGT; - wire PIPETX0COMPLIANCEGT; - wire [15:0] PIPETX0DATAGT; - wire PIPETX0ELECIDLEGT; - wire [1:0] PIPETX0POWERDOWNGT; - wire [1:0] PIPETX1CHARISKGT; - wire PIPETX1COMPLIANCEGT; - wire [15:0] PIPETX1DATAGT; - wire PIPETX1ELECIDLEGT; - wire [1:0] PIPETX1POWERDOWNGT; - wire [1:0] PIPETX2CHARISKGT; - wire PIPETX2COMPLIANCEGT; - wire [15:0] PIPETX2DATAGT; - wire PIPETX2ELECIDLEGT; - wire [1:0] PIPETX2POWERDOWNGT; - wire [1:0] PIPETX3CHARISKGT; - wire PIPETX3COMPLIANCEGT; - wire [15:0] PIPETX3DATAGT; - wire PIPETX3ELECIDLEGT; - wire [1:0] PIPETX3POWERDOWNGT; - wire [1:0] PIPETX4CHARISKGT; - wire PIPETX4COMPLIANCEGT; - wire [15:0] PIPETX4DATAGT; - wire PIPETX4ELECIDLEGT; - wire [1:0] PIPETX4POWERDOWNGT; - wire [1:0] PIPETX5CHARISKGT; - wire PIPETX5COMPLIANCEGT; - wire [15:0] PIPETX5DATAGT; - wire PIPETX5ELECIDLEGT; - wire [1:0] PIPETX5POWERDOWNGT; - wire [1:0] PIPETX6CHARISKGT; - wire PIPETX6COMPLIANCEGT; - wire [15:0] PIPETX6DATAGT; - wire PIPETX6ELECIDLEGT; - wire [1:0] PIPETX6POWERDOWNGT; - wire [1:0] PIPETX7CHARISKGT; - wire PIPETX7COMPLIANCEGT; - wire [15:0] PIPETX7DATAGT; - wire PIPETX7ELECIDLEGT; - wire [1:0] PIPETX7POWERDOWNGT; - - wire PIPERX0CHANISALIGNEDGT; - wire [1:0] PIPERX0CHARISKGT; - wire [15:0] PIPERX0DATAGT; - wire PIPERX0ELECIDLEGT; - wire PIPERX0PHYSTATUSGT; - wire [2:0] PIPERX0STATUSGT; - wire PIPERX0VALIDGT; - wire PIPERX1CHANISALIGNEDGT; - wire [1:0] PIPERX1CHARISKGT; - wire [15:0] PIPERX1DATAGT; - wire PIPERX1ELECIDLEGT; - wire PIPERX1PHYSTATUSGT; - wire [2:0] PIPERX1STATUSGT; - wire PIPERX1VALIDGT; - wire PIPERX2CHANISALIGNEDGT; - wire [1:0] PIPERX2CHARISKGT; - wire [15:0] PIPERX2DATAGT; - wire PIPERX2ELECIDLEGT; - wire PIPERX2PHYSTATUSGT; - wire [2:0] PIPERX2STATUSGT; - wire PIPERX2VALIDGT; - wire PIPERX3CHANISALIGNEDGT; - wire [1:0] PIPERX3CHARISKGT; - wire [15:0] PIPERX3DATAGT; - wire PIPERX3ELECIDLEGT; - wire PIPERX3PHYSTATUSGT; - wire [2:0] PIPERX3STATUSGT; - wire PIPERX3VALIDGT; - wire PIPERX4CHANISALIGNEDGT; - wire [1:0] PIPERX4CHARISKGT; - wire [15:0] PIPERX4DATAGT; - wire PIPERX4ELECIDLEGT; - wire PIPERX4PHYSTATUSGT; - wire [2:0] PIPERX4STATUSGT; - wire PIPERX4VALIDGT; - wire PIPERX5CHANISALIGNEDGT; - wire [1:0] PIPERX5CHARISKGT; - wire [15:0] PIPERX5DATAGT; - wire PIPERX5ELECIDLEGT; - wire PIPERX5PHYSTATUSGT; - wire [2:0] PIPERX5STATUSGT; - wire PIPERX5VALIDGT; - wire PIPERX6CHANISALIGNEDGT; - wire [1:0] PIPERX6CHARISKGT; - wire [15:0] PIPERX6DATAGT; - wire PIPERX6ELECIDLEGT; - wire PIPERX6PHYSTATUSGT; - wire [2:0] PIPERX6STATUSGT; - wire PIPERX6VALIDGT; - wire PIPERX7CHANISALIGNEDGT; - wire [1:0] PIPERX7CHARISKGT; - wire [15:0] PIPERX7DATAGT; - wire PIPERX7ELECIDLEGT; - wire PIPERX7PHYSTATUSGT; - wire [2:0] PIPERX7STATUSGT; - wire PIPERX7VALIDGT; - - wire filter_pipe_upconfig_fix_3451; - - -// Assignments to outputs - - assign TRNCLK = USERCLK; - - - - -//------------------------------------------------------- -// Virtex6 PCI Express Block Module -//------------------------------------------------------- -PCIE_2_0 #( - - .AER_BASE_PTR ( AER_BASE_PTR ), - .AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ), - .AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ), - .AER_CAP_ID ( AER_CAP_ID ), - .AER_CAP_INT_MSG_NUM_MSI ( AER_CAP_INT_MSG_NUM_MSI ), - .AER_CAP_INT_MSG_NUM_MSIX ( AER_CAP_INT_MSG_NUM_MSIX ), - .AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ), - .AER_CAP_ON ( AER_CAP_ON ), - .AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ), - .AER_CAP_VERSION ( AER_CAP_VERSION ), - .ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ), - .BAR0 ( BAR0 ), - .BAR1 ( BAR1 ), - .BAR2 ( BAR2 ), - .BAR3 ( BAR3 ), - .BAR4 ( BAR4 ), - .BAR5 ( BAR5 ), - .CAPABILITIES_PTR ( CAPABILITIES_PTR ), - .CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ), - .CLASS_CODE ( CLASS_CODE ), - .CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ), - .CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ), - .CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ), - .CRM_MODULE_RSTS ( CRM_MODULE_RSTS ), - .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ), - .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ), - .DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ), - .DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ), - .DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ), - .DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ), - .DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ), - .DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ), - .DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ), - .DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ), - .DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ), - .DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ), - .DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ), - .DEVICE_ID ( DEVICE_ID ), - .DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ), - .DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ), - .DISABLE_ID_CHECK ( DISABLE_ID_CHECK ), - .DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ), - .DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ), - .DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ), - .DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ), - .DSN_BASE_PTR ( DSN_BASE_PTR ), - .DSN_CAP_ID ( DSN_CAP_ID ), - .DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ), - .DSN_CAP_ON ( DSN_CAP_ON ), - .DSN_CAP_VERSION ( DSN_CAP_VERSION ), - .ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ), - .ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ), - .ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ), - .EXPANSION_ROM ( EXPANSION_ROM ), - .EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ), - .EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ), - .HEADER_TYPE ( HEADER_TYPE ), - .INFER_EI ( INFER_EI ), - .INTERRUPT_PIN ( INTERRUPT_PIN ), - .IS_SWITCH ( IS_SWITCH ), - .LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ), - .LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ), - .LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ), - .LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ), - .LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ), - .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ), - .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ), - .LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ), - .LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ), - .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ), - .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ), - .LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ), - .LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ), - .LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ), - .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ), - .LINK_CAP_RSVD_23_22 ( LINK_CAP_RSVD_23_22 ), - .LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ), - .LINK_CONTROL_RCB ( LINK_CONTROL_RCB ), - .LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ), - .LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ), - .LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ), - .LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ), - .LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ), - .LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ), - .LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ), - .LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ), - .LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ), - .LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ), - .LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ), - .MSI_BASE_PTR ( MSI_BASE_PTR ), - .MSI_CAP_ID ( MSI_CAP_ID ), - .MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ), - .MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ), - .MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ), - .MSI_CAP_ON ( MSI_CAP_ON ), - .MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ), - .MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ), - .MSIX_BASE_PTR ( MSIX_BASE_PTR ), - .MSIX_CAP_ID ( MSIX_CAP_ID ), - .MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ), - .MSIX_CAP_ON ( MSIX_CAP_ON ), - .MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ), - .MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ), - .MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ), - .MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ), - .MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ), - .N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ), - .N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ), - .N_FTS_GEN1 ( N_FTS_GEN1 ), - .N_FTS_GEN2 ( N_FTS_GEN2 ), - .PCIE_BASE_PTR ( PCIE_BASE_PTR ), - .PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ), - .PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ), - .PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ), - .PCIE_CAP_INT_MSG_NUM ( PCIE_CAP_INT_MSG_NUM ), - .PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ), - .PCIE_CAP_ON ( PCIE_CAP_ON ), - .PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ), - .PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ), - .PCIE_REVISION ( PCIE_REVISION ), - .PGL0_LANE ( PGL0_LANE ), - .PGL1_LANE ( PGL1_LANE ), - .PGL2_LANE ( PGL2_LANE ), - .PGL3_LANE ( PGL3_LANE ), - .PGL4_LANE ( PGL4_LANE ), - .PGL5_LANE ( PGL5_LANE ), - .PGL6_LANE ( PGL6_LANE ), - .PGL7_LANE ( PGL7_LANE ), - .PL_AUTO_CONFIG ( PL_AUTO_CONFIG ), - .PL_FAST_TRAIN ( PL_FAST_TRAIN ), - .PM_BASE_PTR ( PM_BASE_PTR ), - .PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ), - .PM_CAP_DSI ( PM_CAP_DSI ), - .PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ), - .PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ), - .PM_CAP_ID ( PM_CAP_ID ), - .PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ), - .PM_CAP_ON ( PM_CAP_ON ), - .PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ), - .PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ), - .PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ), - .PM_CAP_VERSION ( PM_CAP_VERSION ), - .PM_CSR_BPCCEN ( PM_CSR_BPCCEN ), - .PM_CSR_B2B3 ( PM_CSR_B2B3 ), - .PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ), - .PM_DATA_SCALE0 ( PM_DATA_SCALE0 ), - .PM_DATA_SCALE1 ( PM_DATA_SCALE1 ), - .PM_DATA_SCALE2 ( PM_DATA_SCALE2 ), - .PM_DATA_SCALE3 ( PM_DATA_SCALE3 ), - .PM_DATA_SCALE4 ( PM_DATA_SCALE4 ), - .PM_DATA_SCALE5 ( PM_DATA_SCALE5 ), - .PM_DATA_SCALE6 ( PM_DATA_SCALE6 ), - .PM_DATA_SCALE7 ( PM_DATA_SCALE7 ), - .PM_DATA0 ( PM_DATA0 ), - .PM_DATA1 ( PM_DATA1 ), - .PM_DATA2 ( PM_DATA2 ), - .PM_DATA3 ( PM_DATA3 ), - .PM_DATA4 ( PM_DATA4 ), - .PM_DATA5 ( PM_DATA5 ), - .PM_DATA6 ( PM_DATA6 ), - .PM_DATA7 ( PM_DATA7 ), - .RECRC_CHK ( RECRC_CHK ), - .RECRC_CHK_TRIM ( RECRC_CHK_TRIM ), - .REVISION_ID ( REVISION_ID ), - .ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ), - .SELECT_DLL_IF ( SELECT_DLL_IF ), - .SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ), - .SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ), - .SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ), - .SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ), - .SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ), - .SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ), - .SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ), - .SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ), - .SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ), - .SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ), - .SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ), - .SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ), - .SPARE_BIT0 ( SPARE_BIT0 ), - .SPARE_BIT1 ( SPARE_BIT1 ), - .SPARE_BIT2 ( SPARE_BIT2 ), - .SPARE_BIT3 ( SPARE_BIT3 ), - .SPARE_BIT4 ( SPARE_BIT4 ), - .SPARE_BIT5 ( SPARE_BIT5 ), - .SPARE_BIT6 ( SPARE_BIT6 ), - .SPARE_BIT7 ( SPARE_BIT7 ), - .SPARE_BIT8 ( SPARE_BIT8 ), - .SPARE_BYTE0 ( SPARE_BYTE0 ), - .SPARE_BYTE1 ( SPARE_BYTE1 ), - .SPARE_BYTE2 ( SPARE_BYTE2 ), - .SPARE_BYTE3 ( SPARE_BYTE3 ), - .SPARE_WORD0 ( SPARE_WORD0 ), - .SPARE_WORD1 ( SPARE_WORD1 ), - .SPARE_WORD2 ( SPARE_WORD2 ), - .SPARE_WORD3 ( SPARE_WORD3 ), - .SUBSYSTEM_ID ( SUBSYSTEM_ID ), - .SUBSYSTEM_VENDOR_ID ( SUBSYSTEM_VENDOR_ID ), - .TL_RBYPASS ( TL_RBYPASS ), - .TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ), - .TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ), - .TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ), - .TL_TFC_DISABLE ( TL_TFC_DISABLE ), - .TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ), - .TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ), - .TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ), - .TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ), - .UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ), - .UPSTREAM_FACING ( UPSTREAM_FACING ), - .EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ), - .UR_INV_REQ ( UR_INV_REQ ), - .USER_CLK_FREQ ( USER_CLK_FREQ ), - .VC_BASE_PTR ( VC_BASE_PTR ), - .VC_CAP_ID ( VC_CAP_ID ), - .VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ), - .VC_CAP_ON ( VC_CAP_ON ), - .VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ), - .VC_CAP_VERSION ( VC_CAP_VERSION ), - .VC0_CPL_INFINITE ( VC0_CPL_INFINITE ), - .VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ), - .VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ), - .VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ), - .VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ), - .VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ), - .VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ), - .VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ), - .VENDOR_ID ( VENDOR_ID ), - .VSEC_BASE_PTR ( VSEC_BASE_PTR ), - .VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ), - .VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ), - .VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ), - .VSEC_CAP_ID ( VSEC_CAP_ID ), - .VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ), - .VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ), - .VSEC_CAP_ON ( VSEC_CAP_ON ), - .VSEC_CAP_VERSION ( VSEC_CAP_VERSION ) - -) -pcie_block_i ( - - .CFGAERECRCCHECKEN ( CFGAERECRCCHECKEN ), - .CFGAERECRCGENEN ( CFGAERECRCGENEN ), - .CFGCOMMANDBUSMASTERENABLE ( CFGCOMMANDBUSMASTERENABLE ), - .CFGCOMMANDINTERRUPTDISABLE ( CFGCOMMANDINTERRUPTDISABLE ), - .CFGCOMMANDIOENABLE ( CFGCOMMANDIOENABLE ), - .CFGCOMMANDMEMENABLE ( CFGCOMMANDMEMENABLE ), - .CFGCOMMANDSERREN ( CFGCOMMANDSERREN ), - .CFGDEVCONTROLAUXPOWEREN ( CFGDEVCONTROLAUXPOWEREN ), - .CFGDEVCONTROLCORRERRREPORTINGEN ( CFGDEVCONTROLCORRERRREPORTINGEN ), - .CFGDEVCONTROLENABLERO ( CFGDEVCONTROLENABLERO ), - .CFGDEVCONTROLEXTTAGEN ( CFGDEVCONTROLEXTTAGEN ), - .CFGDEVCONTROLFATALERRREPORTINGEN ( CFGDEVCONTROLFATALERRREPORTINGEN ), - .CFGDEVCONTROLMAXPAYLOAD ( CFGDEVCONTROLMAXPAYLOAD ), - .CFGDEVCONTROLMAXREADREQ ( CFGDEVCONTROLMAXREADREQ ), - .CFGDEVCONTROLNONFATALREPORTINGEN ( CFGDEVCONTROLNONFATALREPORTINGEN ), - .CFGDEVCONTROLNOSNOOPEN ( CFGDEVCONTROLNOSNOOPEN ), - .CFGDEVCONTROLPHANTOMEN ( CFGDEVCONTROLPHANTOMEN ), - .CFGDEVCONTROLURERRREPORTINGEN ( CFGDEVCONTROLURERRREPORTINGEN ), - .CFGDEVCONTROL2CPLTIMEOUTDIS ( CFGDEVCONTROL2CPLTIMEOUTDIS ), - .CFGDEVCONTROL2CPLTIMEOUTVAL ( CFGDEVCONTROL2CPLTIMEOUTVAL ), - .CFGDEVSTATUSCORRERRDETECTED ( CFGDEVSTATUSCORRERRDETECTED ), - .CFGDEVSTATUSFATALERRDETECTED ( CFGDEVSTATUSFATALERRDETECTED ), - .CFGDEVSTATUSNONFATALERRDETECTED ( CFGDEVSTATUSNONFATALERRDETECTED ), - .CFGDEVSTATUSURDETECTED ( CFGDEVSTATUSURDETECTED ), - .CFGDO ( CFGDO ), - .CFGERRAERHEADERLOGSETN ( CFGERRAERHEADERLOGSETN ), - - .CFGERRCPLRDYN ( CFGERRCPLRDYN ), - .CFGINTERRUPTDO ( CFGINTERRUPTDO ), - .CFGINTERRUPTMMENABLE ( CFGINTERRUPTMMENABLE ), - .CFGINTERRUPTMSIENABLE ( CFGINTERRUPTMSIENABLE ), - .CFGINTERRUPTMSIXENABLE ( CFGINTERRUPTMSIXENABLE ), - .CFGINTERRUPTMSIXFM ( CFGINTERRUPTMSIXFM ), - .CFGINTERRUPTRDYN ( CFGINTERRUPTRDYN ), - .CFGLINKCONTROLRCB ( CFGLINKCONTROLRCB ), - .CFGLINKCONTROLASPMCONTROL ( CFGLINKCONTROLASPMCONTROL ), - .CFGLINKCONTROLAUTOBANDWIDTHINTEN ( CFGLINKCONTROLAUTOBANDWIDTHINTEN ), - .CFGLINKCONTROLBANDWIDTHINTEN ( CFGLINKCONTROLBANDWIDTHINTEN ), - .CFGLINKCONTROLCLOCKPMEN ( CFGLINKCONTROLCLOCKPMEN ), - .CFGLINKCONTROLCOMMONCLOCK ( CFGLINKCONTROLCOMMONCLOCK ), - .CFGLINKCONTROLEXTENDEDSYNC ( CFGLINKCONTROLEXTENDEDSYNC ), - .CFGLINKCONTROLHWAUTOWIDTHDIS ( CFGLINKCONTROLHWAUTOWIDTHDIS ), - .CFGLINKCONTROLLINKDISABLE ( CFGLINKCONTROLLINKDISABLE ), - .CFGLINKCONTROLRETRAINLINK ( CFGLINKCONTROLRETRAINLINK ), - .CFGLINKSTATUSAUTOBANDWIDTHSTATUS ( CFGLINKSTATUSAUTOBANDWIDTHSTATUS ), - .CFGLINKSTATUSBANDWITHSTATUS ( CFGLINKSTATUSBANDWITHSTATUS ), - .CFGLINKSTATUSCURRENTSPEED ( CFGLINKSTATUSCURRENTSPEED ), - .CFGLINKSTATUSDLLACTIVE ( CFGLINKSTATUSDLLACTIVE ), - .CFGLINKSTATUSLINKTRAINING ( CFGLINKSTATUSLINKTRAINING ), - .CFGLINKSTATUSNEGOTIATEDWIDTH ( CFGLINKSTATUSNEGOTIATEDWIDTH ), - .CFGMSGDATA ( CFGMSGDATA ), - .CFGMSGRECEIVED ( CFGMSGRECEIVED ), - - .CFGMSGRECEIVEDASSERTINTA ( CFGMSGRECEIVEDASSERTINTA ), - .CFGMSGRECEIVEDASSERTINTB ( CFGMSGRECEIVEDASSERTINTB ), - .CFGMSGRECEIVEDASSERTINTC ( CFGMSGRECEIVEDASSERTINTC ), - .CFGMSGRECEIVEDASSERTINTD ( CFGMSGRECEIVEDASSERTINTD ), - .CFGMSGRECEIVEDDEASSERTINTA ( CFGMSGRECEIVEDDEASSERTINTA ), - .CFGMSGRECEIVEDDEASSERTINTB ( CFGMSGRECEIVEDDEASSERTINTB ), - .CFGMSGRECEIVEDDEASSERTINTC ( CFGMSGRECEIVEDDEASSERTINTC ), - .CFGMSGRECEIVEDDEASSERTINTD ( CFGMSGRECEIVEDDEASSERTINTD ), - .CFGMSGRECEIVEDERRCOR ( CFGMSGRECEIVEDERRCOR ), - .CFGMSGRECEIVEDERRFATAL ( CFGMSGRECEIVEDERRFATAL ), - .CFGMSGRECEIVEDERRNONFATAL ( CFGMSGRECEIVEDERRNONFATAL ), - - .CFGMSGRECEIVEDPMASNAK ( CFGMSGRECEIVEDPMASNAK ), - .CFGMSGRECEIVEDPMETO ( CFGMSGRECEIVEDPMETO ), - - - .CFGMSGRECEIVEDPMETOACK ( CFGMSGRECEIVEDPMETOACK ), - .CFGMSGRECEIVEDPMPME ( CFGMSGRECEIVEDPMPME ), - - - .CFGMSGRECEIVEDSETSLOTPOWERLIMIT ( CFGMSGRECEIVEDSETSLOTPOWERLIMIT ), - .CFGMSGRECEIVEDUNLOCK ( CFGMSGRECEIVEDUNLOCK ), - .CFGPCIELINKSTATE ( CFGPCIELINKSTATE ), - - - .CFGPMRCVASREQL1N ( CFGPMRCVASREQL1N ), - .CFGPMRCVENTERL1N ( CFGPMRCVENTERL1N ), - .CFGPMRCVENTERL23N ( CFGPMRCVENTERL23N ), - - .CFGPMRCVREQACKN ( CFGPMRCVREQACKN ), - .CFGPMCSRPMEEN( CFGPMCSRPMEEN ), - .CFGPMCSRPMESTATUS( CFGPMCSRPMESTATUS ), - .CFGPMCSRPOWERSTATE( CFGPMCSRPOWERSTATE ), - .CFGRDWRDONEN ( CFGRDWRDONEN ), - - .CFGSLOTCONTROLELECTROMECHILCTLPULSE ( CFGSLOTCONTROLELECTROMECHILCTLPULSE ), - - .CFGTRANSACTION ( CFGTRANSACTION ), - .CFGTRANSACTIONADDR ( CFGTRANSACTIONADDR ), - .CFGTRANSACTIONTYPE ( CFGTRANSACTIONTYPE ), - - .CFGVCTCVCMAP ( CFGVCTCVCMAP ), - .DBGSCLRA ( DBGSCLRA ), - .DBGSCLRB ( DBGSCLRB ), - .DBGSCLRC ( DBGSCLRC ), - .DBGSCLRD ( DBGSCLRD ), - .DBGSCLRE ( DBGSCLRE ), - .DBGSCLRF ( DBGSCLRF ), - .DBGSCLRG ( DBGSCLRG ), - .DBGSCLRH ( DBGSCLRH ), - .DBGSCLRI ( DBGSCLRI ), - .DBGSCLRJ ( DBGSCLRJ ), - .DBGSCLRK ( DBGSCLRK ), - .DBGVECA ( DBGVECA ), - .DBGVECB ( DBGVECB ), - .DBGVECC ( DBGVECC ), - .DRPDO ( DRPDO ), - .DRPDRDY ( DRPDRDY ), - .LL2BADDLLPERRN ( LL2BADDLLPERRN ), - .LL2BADTLPERRN ( LL2BADTLPERRN ), - .LL2PROTOCOLERRN ( LL2PROTOCOLERRN ), - .LL2REPLAYROERRN ( LL2REPLAYROERRN ), - .LL2REPLAYTOERRN ( LL2REPLAYTOERRN ), - .LL2SUSPENDOKN ( LL2SUSPENDOKN ), - .LL2TFCINIT1SEQN ( LL2TFCINIT1SEQN ), - .LL2TFCINIT2SEQN ( LL2TFCINIT2SEQN ), - .MIMRXRADDR ( MIMRXRADDR ), - .MIMRXRCE ( MIMRXRCE ), - .MIMRXREN ( MIMRXREN ), - .MIMRXWADDR ( MIMRXWADDR ), - .MIMRXWDATA ( MIMRXWDATA ), - .MIMRXWEN ( MIMRXWEN ), - .MIMTXRADDR ( MIMTXRADDR ), - .MIMTXRCE ( MIMTXRCE ), - .MIMTXREN ( MIMTXREN ), - .MIMTXWADDR ( MIMTXWADDR ), - .MIMTXWDATA ( MIMTXWDATA ), - .MIMTXWEN ( MIMTXWEN ), - .PIPERX0POLARITY ( PIPERX0POLARITY ), - .PIPERX1POLARITY ( PIPERX1POLARITY ), - .PIPERX2POLARITY ( PIPERX2POLARITY ), - .PIPERX3POLARITY ( PIPERX3POLARITY ), - .PIPERX4POLARITY ( PIPERX4POLARITY ), - .PIPERX5POLARITY ( PIPERX5POLARITY ), - .PIPERX6POLARITY ( PIPERX6POLARITY ), - .PIPERX7POLARITY ( PIPERX7POLARITY ), - .PIPETXDEEMPH ( PIPETXDEEMPH ), - .PIPETXMARGIN ( PIPETXMARGIN ), - .PIPETXRATE ( PIPETXRATE ), - .PIPETXRCVRDET ( PIPETXRCVRDET ), - .PIPETXRESET ( PIPETXRESET ), - .PIPETX0CHARISK ( PIPETX0CHARISK ), - .PIPETX0COMPLIANCE ( PIPETX0COMPLIANCE ), - .PIPETX0DATA ( PIPETX0DATA ), - .PIPETX0ELECIDLE ( PIPETX0ELECIDLE ), - .PIPETX0POWERDOWN ( PIPETX0POWERDOWN ), - .PIPETX1CHARISK ( PIPETX1CHARISK ), - .PIPETX1COMPLIANCE ( PIPETX1COMPLIANCE ), - .PIPETX1DATA ( PIPETX1DATA ), - .PIPETX1ELECIDLE ( PIPETX1ELECIDLE ), - .PIPETX1POWERDOWN ( PIPETX1POWERDOWN ), - .PIPETX2CHARISK ( PIPETX2CHARISK ), - .PIPETX2COMPLIANCE ( PIPETX2COMPLIANCE ), - .PIPETX2DATA ( PIPETX2DATA ), - .PIPETX2ELECIDLE ( PIPETX2ELECIDLE ), - .PIPETX2POWERDOWN ( PIPETX2POWERDOWN ), - .PIPETX3CHARISK ( PIPETX3CHARISK ), - .PIPETX3COMPLIANCE ( PIPETX3COMPLIANCE ), - .PIPETX3DATA ( PIPETX3DATA ), - .PIPETX3ELECIDLE ( PIPETX3ELECIDLE ), - .PIPETX3POWERDOWN ( PIPETX3POWERDOWN ), - .PIPETX4CHARISK ( PIPETX4CHARISK ), - .PIPETX4COMPLIANCE ( PIPETX4COMPLIANCE ), - .PIPETX4DATA ( PIPETX4DATA ), - .PIPETX4ELECIDLE ( PIPETX4ELECIDLE ), - .PIPETX4POWERDOWN ( PIPETX4POWERDOWN ), - .PIPETX5CHARISK ( PIPETX5CHARISK ), - .PIPETX5COMPLIANCE ( PIPETX5COMPLIANCE ), - .PIPETX5DATA ( PIPETX5DATA ), - .PIPETX5ELECIDLE ( PIPETX5ELECIDLE ), - .PIPETX5POWERDOWN ( PIPETX5POWERDOWN ), - .PIPETX6CHARISK ( PIPETX6CHARISK ), - .PIPETX6COMPLIANCE ( PIPETX6COMPLIANCE ), - .PIPETX6DATA ( PIPETX6DATA ), - .PIPETX6ELECIDLE ( PIPETX6ELECIDLE ), - .PIPETX6POWERDOWN ( PIPETX6POWERDOWN ), - .PIPETX7CHARISK ( PIPETX7CHARISK ), - .PIPETX7COMPLIANCE ( PIPETX7COMPLIANCE ), - .PIPETX7DATA ( PIPETX7DATA ), - .PIPETX7ELECIDLE ( PIPETX7ELECIDLE ), - .PIPETX7POWERDOWN ( PIPETX7POWERDOWN ), - .PLDBGVEC ( PLDBGVEC ), - .PLINITIALLINKWIDTH ( PLINITIALLINKWIDTH ), - .PLLANEREVERSALMODE ( PLLANEREVERSALMODE ), - .PLLINKGEN2CAP ( PLLINKGEN2CAP ), - .PLLINKPARTNERGEN2SUPPORTED ( PLLINKPARTNERGEN2SUPPORTED ), - .PLLINKUPCFGCAP ( PLLINKUPCFGCAP ), - .PLLTSSMSTATE ( PLLTSSMSTATE ), - .PLPHYLNKUPN ( PLPHYLNKUPN ), - .PLRECEIVEDHOTRST ( PLRECEIVEDHOTRST ), - .PLRXPMSTATE ( PLRXPMSTATE ), - .PLSELLNKRATE ( PLSELLNKRATE ), - .PLSELLNKWIDTH ( PLSELLNKWIDTH ), - .PLTXPMSTATE ( PLTXPMSTATE ), - .PL2LINKUPN ( PL2LINKUPN ), - .PL2RECEIVERERRN ( PL2RECEIVERERRN ), - .PL2RECOVERYN ( PL2RECOVERYN ), - .PL2RXELECIDLE ( PL2RXELECIDLE ), - .PL2SUSPENDOK ( PL2SUSPENDOK ), - .RECEIVEDFUNCLVLRSTN ( RECEIVEDFUNCLVLRSTN ), - .LNKCLKEN ( LNKCLKEN ), - .TL2ASPMSUSPENDCREDITCHECKOKN ( TL2ASPMSUSPENDCREDITCHECKOKN ), - .TL2ASPMSUSPENDREQN ( TL2ASPMSUSPENDREQN ), - .TL2PPMSUSPENDOKN ( TL2PPMSUSPENDOKN ), - .TRNFCCPLD ( TRNFCCPLD ), - .TRNFCCPLH ( TRNFCCPLH ), - .TRNFCNPD ( TRNFCNPD ), - .TRNFCNPH ( TRNFCNPH ), - .TRNFCPD ( TRNFCPD ), - .TRNFCPH ( TRNFCPH ), - .TRNLNKUPN ( TRNLNKUPN ), - .TRNRBARHITN ( TRNRBARHITN ), - .TRNRD ( TRNRD ), - - .TRNRDLLPDATA ( ), - .TRNRDLLPSRCRDYN ( TRNRDLLPSRCRDYN ), - .TRNRECRCERRN ( TRNRECRCERRN ), - .TRNREOFN ( TRNREOFN ), - .TRNRERRFWDN ( TRNRERRFWDN ), - .TRNRREMN ( TRNRREMN ), - .TRNRSOFN ( TRNRSOFN ), - .TRNRSRCDSCN ( TRNRSRCDSCN ), - .TRNRSRCRDYN ( TRNRSRCRDYN ), - .TRNTBUFAV ( TRNTBUFAV ), - .TRNTCFGREQN ( TRNTCFGREQN ), - .TRNTDLLPDSTRDYN ( TRNTDLLPDSTRDYN ), - .TRNTDSTRDYN ( TRNTDSTRDYN ), - .TRNTERRDROPN ( TRNTERRDROPN ), - .USERRSTN ( USERRSTN ), - .CFGBYTEENN ( CFGBYTEENN ), - .CFGDI ( CFGDI ), - .CFGDSBUSNUMBER ( CFGDSBUSNUMBER ), - .CFGDSDEVICENUMBER ( CFGDSDEVICENUMBER ), - .CFGDSFUNCTIONNUMBER ( CFGDSFUNCTIONNUMBER ), - .CFGDSN ( CFGDSN ), - .CFGDWADDR ( CFGDWADDR ), - .CFGERRACSN ( CFGERRACSN ), - .CFGERRAERHEADERLOG ( CFGERRAERHEADERLOG ), - .CFGERRCORN ( CFGERRCORN ), - .CFGERRCPLABORTN ( CFGERRCPLABORTN ), - .CFGERRCPLTIMEOUTN ( CFGERRCPLTIMEOUTN ), - .CFGERRCPLUNEXPECTN ( CFGERRCPLUNEXPECTN ), - .CFGERRECRCN ( CFGERRECRCN ), - .CFGERRLOCKEDN ( CFGERRLOCKEDN ), - .CFGERRPOSTEDN ( CFGERRPOSTEDN ), - .CFGERRTLPCPLHEADER ( CFGERRTLPCPLHEADER ), - .CFGERRURN ( CFGERRURN ), - .CFGINTERRUPTASSERTN ( CFGINTERRUPTASSERTN ), - .CFGINTERRUPTDI ( CFGINTERRUPTDI ), - .CFGINTERRUPTN ( CFGINTERRUPTN ), - .CFGPMDIRECTASPML1N ( CFGPMDIRECTASPML1N ), - .CFGPMSENDPMACKN ( CFGPMSENDPMACKN ), - .CFGPMSENDPMETON ( CFGPMSENDPMETON ), - .CFGPMSENDPMNAKN ( CFGPMSENDPMNAKN ), - .CFGPMTURNOFFOKN ( CFGPMTURNOFFOKN ), - .CFGPMWAKEN ( CFGPMWAKEN ), - .CFGPORTNUMBER ( CFGPORTNUMBER ), - .CFGRDENN ( CFGRDENN ), - .CFGTRNPENDINGN ( CFGTRNPENDINGN ), - .CFGWRENN ( CFGWRENN ), - .CFGWRREADONLYN ( CFGWRREADONLYN ), - .CFGWRRW1CASRWN ( CFGWRRW1CASRWN ), - .CMRSTN ( CMRSTN ), - .CMSTICKYRSTN ( CMSTICKYRSTN ), - .DBGMODE ( DBGMODE ), - .DBGSUBMODE ( DBGSUBMODE ), - .DLRSTN ( DLRSTN ), - .DRPCLK ( DRPCLK ), - .DRPDADDR ( DRPDADDR ), - .DRPDEN ( DRPDEN ), - .DRPDI ( DRPDI ), - .DRPDWE ( DRPDWE ), - .FUNCLVLRSTN ( FUNCLVLRSTN ), - .LL2SENDASREQL1N ( LL2SENDASREQL1N ), - .LL2SENDENTERL1N ( LL2SENDENTERL1N ), - .LL2SENDENTERL23N ( LL2SENDENTERL23N ), - .LL2SUSPENDNOWN ( LL2SUSPENDNOWN ), - .LL2TLPRCVN ( LL2TLPRCVN ), - .MIMRXRDATA ( MIMRXRDATA ), - .MIMTXRDATA ( MIMTXRDATA ), - .PIPECLK ( PIPECLK ), - .PIPERX0CHANISALIGNED ( PIPERX0CHANISALIGNED ), - .PIPERX0CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX0CHARISK ), - .PIPERX0DATA ( PIPERX0DATA ), - .PIPERX0ELECIDLE ( PIPERX0ELECIDLE ), - .PIPERX0PHYSTATUS ( PIPERX0PHYSTATUS ), - .PIPERX0STATUS ( PIPERX0STATUS ), - .PIPERX0VALID ( PIPERX0VALID ), - .PIPERX1CHANISALIGNED ( PIPERX1CHANISALIGNED ), - .PIPERX1CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX1CHARISK ), - .PIPERX1DATA ( PIPERX1DATA ), - .PIPERX1ELECIDLE ( PIPERX1ELECIDLE ), - .PIPERX1PHYSTATUS ( PIPERX1PHYSTATUS ), - .PIPERX1STATUS ( PIPERX1STATUS ), - .PIPERX1VALID ( PIPERX1VALID ), - .PIPERX2CHANISALIGNED ( PIPERX2CHANISALIGNED ), - .PIPERX2CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX2CHARISK ), - .PIPERX2DATA ( PIPERX2DATA ), - .PIPERX2ELECIDLE ( PIPERX2ELECIDLE ), - .PIPERX2PHYSTATUS ( PIPERX2PHYSTATUS ), - .PIPERX2STATUS ( PIPERX2STATUS ), - .PIPERX2VALID ( PIPERX2VALID ), - .PIPERX3CHANISALIGNED ( PIPERX3CHANISALIGNED ), - .PIPERX3CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX3CHARISK ), - .PIPERX3DATA ( PIPERX3DATA ), - .PIPERX3ELECIDLE ( PIPERX3ELECIDLE ), - .PIPERX3PHYSTATUS ( PIPERX3PHYSTATUS ), - .PIPERX3STATUS ( PIPERX3STATUS ), - .PIPERX3VALID ( PIPERX3VALID ), - .PIPERX4CHANISALIGNED ( PIPERX4CHANISALIGNED ), - .PIPERX4CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX4CHARISK ), - .PIPERX4DATA ( PIPERX4DATA ), - .PIPERX4ELECIDLE ( PIPERX4ELECIDLE ), - .PIPERX4PHYSTATUS ( PIPERX4PHYSTATUS ), - .PIPERX4STATUS ( PIPERX4STATUS ), - .PIPERX4VALID ( PIPERX4VALID ), - .PIPERX5CHANISALIGNED ( PIPERX5CHANISALIGNED ), - .PIPERX5CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX5CHARISK ), - .PIPERX5DATA ( PIPERX5DATA ), - .PIPERX5ELECIDLE ( PIPERX5ELECIDLE ), - .PIPERX5PHYSTATUS ( PIPERX5PHYSTATUS ), - .PIPERX5STATUS ( PIPERX5STATUS ), - .PIPERX5VALID ( PIPERX5VALID ), - .PIPERX6CHANISALIGNED ( PIPERX6CHANISALIGNED ), - .PIPERX6CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX6CHARISK ), - .PIPERX6DATA ( PIPERX6DATA ), - .PIPERX6ELECIDLE ( PIPERX6ELECIDLE ), - .PIPERX6PHYSTATUS ( PIPERX6PHYSTATUS ), - .PIPERX6STATUS ( PIPERX6STATUS ), - .PIPERX6VALID ( PIPERX6VALID ), - .PIPERX7CHANISALIGNED ( PIPERX7CHANISALIGNED ), - .PIPERX7CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX7CHARISK ), - .PIPERX7DATA ( PIPERX7DATA ), - .PIPERX7ELECIDLE ( PIPERX7ELECIDLE ), - .PIPERX7PHYSTATUS ( PIPERX7PHYSTATUS ), - .PIPERX7STATUS ( PIPERX7STATUS ), - .PIPERX7VALID ( PIPERX7VALID ), - .PLDBGMODE ( PLDBGMODE ), - .PLDIRECTEDLINKAUTON ( PLDIRECTEDLINKAUTON ), - .PLDIRECTEDLINKCHANGE ( PLDIRECTEDLINKCHANGE ), - .PLDIRECTEDLINKSPEED ( PLDIRECTEDLINKSPEED ), - .PLDIRECTEDLINKWIDTH ( PLDIRECTEDLINKWIDTH ), - .PLDOWNSTREAMDEEMPHSOURCE ( PLDOWNSTREAMDEEMPHSOURCE ), - .PLRSTN ( PLRSTN ), - .PLTRANSMITHOTRST ( PLTRANSMITHOTRST ), - .PLUPSTREAMPREFERDEEMPH ( PLUPSTREAMPREFERDEEMPH ), - .PL2DIRECTEDLSTATE ( PL2DIRECTEDLSTATE ), - .SYSRSTN ( SYSRSTN ), - .TLRSTN ( TLRSTN ), - .TL2ASPMSUSPENDCREDITCHECKN ( 1'b1), - .TL2PPMSUSPENDREQN ( 1'b1 ), - .TRNFCSEL ( TRNFCSEL ), - .TRNRDSTRDYN ( TRNRDSTRDYN ), - .TRNRNPOKN ( TRNRNPOKN ), - .TRNTCFGGNTN ( TRNTCFGGNTN ), - .TRNTD ( TRNTD ), - .TRNTDLLPDATA ( TRNTDLLPDATA ), - .TRNTDLLPSRCRDYN ( TRNTDLLPSRCRDYN ), - .TRNTECRCGENN ( TRNTECRCGENN ), - .TRNTEOFN ( TRNTEOFN ), - .TRNTERRFWDN ( TRNTERRFWDN ), - .TRNTREMN ( TRNTREMN ), - .TRNTSOFN ( TRNTSOFN ), - .TRNTSRCDSCN ( TRNTSRCDSCN ), - .TRNTSRCRDYN ( TRNTSRCRDYN ), - .TRNTSTRN ( TRNTSTRN ), - .USERCLK ( USERCLK ) - -); - -//------------------------------------------------------- -// Virtex6 PIPE Module -//------------------------------------------------------- - -pcie_pipe_v6 # ( - - .NO_OF_LANES(LINK_CAP_MAX_LINK_WIDTH), - .LINK_CAP_MAX_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED), - .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES) - -) -pcie_pipe_i ( - - // Pipe Per-Link Signals - .pipe_tx_rcvr_det_i (PIPETXRCVRDET), - .pipe_tx_reset_i (PIPETXRESET), - .pipe_tx_rate_i (PIPETXRATE), - .pipe_tx_deemph_i (PIPETXDEEMPH), - .pipe_tx_margin_i (PIPETXMARGIN), - .pipe_tx_swing_i (1'b0), - - .pipe_tx_rcvr_det_o (PIPETXRCVRDETGT), - .pipe_tx_reset_o ( ), - .pipe_tx_rate_o (PIPETXRATEGT), - .pipe_tx_deemph_o (PIPETXDEEMPHGT), - .pipe_tx_margin_o (PIPETXMARGINGT), - .pipe_tx_swing_o ( ), - - // Pipe Per-Lane Signals - Lane 0 - .pipe_rx0_char_is_k_o (PIPERX0CHARISK ), - .pipe_rx0_data_o (PIPERX0DATA ), - .pipe_rx0_valid_o (PIPERX0VALID ), - .pipe_rx0_chanisaligned_o (PIPERX0CHANISALIGNED ), - .pipe_rx0_status_o (PIPERX0STATUS ), - .pipe_rx0_phy_status_o (PIPERX0PHYSTATUS ), - .pipe_rx0_elec_idle_i (PIPERX0ELECIDLEGT ), - .pipe_rx0_polarity_i (PIPERX0POLARITY ), - .pipe_tx0_compliance_i (PIPETX0COMPLIANCE ), - .pipe_tx0_char_is_k_i (PIPETX0CHARISK ), - .pipe_tx0_data_i (PIPETX0DATA ), - .pipe_tx0_elec_idle_i (PIPETX0ELECIDLE ), - .pipe_tx0_powerdown_i (PIPETX0POWERDOWN ), - - .pipe_rx0_char_is_k_i (PIPERX0CHARISKGT ), - .pipe_rx0_data_i (PIPERX0DATAGT ), - .pipe_rx0_valid_i (PIPERX0VALIDGT ), - .pipe_rx0_chanisaligned_i (PIPERX0CHANISALIGNEDGT ), - .pipe_rx0_status_i (PIPERX0STATUSGT ), - .pipe_rx0_phy_status_i (PIPERX0PHYSTATUSGT ), - .pipe_rx0_elec_idle_o (PIPERX0ELECIDLE ), - .pipe_rx0_polarity_o (PIPERX0POLARITYGT ), - .pipe_tx0_compliance_o (PIPETX0COMPLIANCEGT ), - .pipe_tx0_char_is_k_o (PIPETX0CHARISKGT ), - .pipe_tx0_data_o (PIPETX0DATAGT ), - .pipe_tx0_elec_idle_o (PIPETX0ELECIDLEGT ), - .pipe_tx0_powerdown_o (PIPETX0POWERDOWNGT ), - - // Pipe Per-Lane Signals - Lane 1 - .pipe_rx1_char_is_k_o (PIPERX1CHARISK ), - .pipe_rx1_data_o (PIPERX1DATA ), - .pipe_rx1_valid_o (PIPERX1VALID ), - .pipe_rx1_chanisaligned_o (PIPERX1CHANISALIGNED ), - .pipe_rx1_status_o (PIPERX1STATUS ), - .pipe_rx1_phy_status_o (PIPERX1PHYSTATUS ), - .pipe_rx1_elec_idle_i (PIPERX1ELECIDLEGT ), - .pipe_rx1_polarity_i (PIPERX1POLARITY ), - .pipe_tx1_compliance_i (PIPETX1COMPLIANCE ), - .pipe_tx1_char_is_k_i (PIPETX1CHARISK ), - .pipe_tx1_data_i (PIPETX1DATA ), - .pipe_tx1_elec_idle_i (PIPETX1ELECIDLE ), - .pipe_tx1_powerdown_i (PIPETX1POWERDOWN ), - - .pipe_rx1_char_is_k_i (PIPERX1CHARISKGT ), - .pipe_rx1_data_i (PIPERX1DATAGT ), - .pipe_rx1_valid_i (PIPERX1VALIDGT ), - .pipe_rx1_chanisaligned_i (PIPERX1CHANISALIGNEDGT ), - .pipe_rx1_status_i (PIPERX1STATUSGT ), - .pipe_rx1_phy_status_i (PIPERX1PHYSTATUSGT ), - .pipe_rx1_elec_idle_o (PIPERX1ELECIDLE ), - .pipe_rx1_polarity_o (PIPERX1POLARITYGT ), - .pipe_tx1_compliance_o (PIPETX1COMPLIANCEGT ), - .pipe_tx1_char_is_k_o (PIPETX1CHARISKGT ), - .pipe_tx1_data_o (PIPETX1DATAGT ), - .pipe_tx1_elec_idle_o (PIPETX1ELECIDLEGT ), - .pipe_tx1_powerdown_o (PIPETX1POWERDOWNGT ), - - // Pipe Per-Lane Signals - Lane 2 - .pipe_rx2_char_is_k_o (PIPERX2CHARISK ), - .pipe_rx2_data_o (PIPERX2DATA ), - .pipe_rx2_valid_o (PIPERX2VALID ), - .pipe_rx2_chanisaligned_o (PIPERX2CHANISALIGNED ), - .pipe_rx2_status_o (PIPERX2STATUS ), - .pipe_rx2_phy_status_o (PIPERX2PHYSTATUS ), - .pipe_rx2_elec_idle_i (PIPERX2ELECIDLEGT ), - .pipe_rx2_polarity_i (PIPERX2POLARITY ), - .pipe_tx2_compliance_i (PIPETX2COMPLIANCE ), - .pipe_tx2_char_is_k_i (PIPETX2CHARISK ), - .pipe_tx2_data_i (PIPETX2DATA ), - .pipe_tx2_elec_idle_i (PIPETX2ELECIDLE ), - .pipe_tx2_powerdown_i (PIPETX2POWERDOWN ), - - .pipe_rx2_char_is_k_i (PIPERX2CHARISKGT ), - .pipe_rx2_data_i (PIPERX2DATAGT ), - .pipe_rx2_valid_i (PIPERX2VALIDGT ), - .pipe_rx2_chanisaligned_i (PIPERX2CHANISALIGNEDGT ), - .pipe_rx2_status_i (PIPERX2STATUSGT ), - .pipe_rx2_phy_status_i (PIPERX2PHYSTATUSGT ), - .pipe_rx2_elec_idle_o (PIPERX2ELECIDLE ), - .pipe_rx2_polarity_o (PIPERX2POLARITYGT ), - .pipe_tx2_compliance_o (PIPETX2COMPLIANCEGT ), - .pipe_tx2_char_is_k_o (PIPETX2CHARISKGT ), - .pipe_tx2_data_o (PIPETX2DATAGT ), - .pipe_tx2_elec_idle_o (PIPETX2ELECIDLEGT ), - .pipe_tx2_powerdown_o (PIPETX2POWERDOWNGT ), - - // Pipe Per-Lane Signals - Lane 3 - .pipe_rx3_char_is_k_o (PIPERX3CHARISK ), - .pipe_rx3_data_o (PIPERX3DATA ), - .pipe_rx3_valid_o (PIPERX3VALID ), - .pipe_rx3_chanisaligned_o (PIPERX3CHANISALIGNED ), - .pipe_rx3_status_o (PIPERX3STATUS ), - .pipe_rx3_phy_status_o (PIPERX3PHYSTATUS ), - .pipe_rx3_elec_idle_i (PIPERX3ELECIDLEGT ), - .pipe_rx3_polarity_i (PIPERX3POLARITY ), - .pipe_tx3_compliance_i (PIPETX3COMPLIANCE ), - .pipe_tx3_char_is_k_i (PIPETX3CHARISK ), - .pipe_tx3_data_i (PIPETX3DATA ), - .pipe_tx3_elec_idle_i (PIPETX3ELECIDLE ), - .pipe_tx3_powerdown_i (PIPETX3POWERDOWN ), - - .pipe_rx3_char_is_k_i (PIPERX3CHARISKGT ), - .pipe_rx3_data_i (PIPERX3DATAGT ), - .pipe_rx3_valid_i (PIPERX3VALIDGT ), - .pipe_rx3_chanisaligned_i (PIPERX3CHANISALIGNEDGT ), - .pipe_rx3_status_i (PIPERX3STATUSGT ), - .pipe_rx3_phy_status_i (PIPERX3PHYSTATUSGT ), - .pipe_rx3_elec_idle_o (PIPERX3ELECIDLE ), - .pipe_rx3_polarity_o (PIPERX3POLARITYGT ), - .pipe_tx3_compliance_o (PIPETX3COMPLIANCEGT ), - .pipe_tx3_char_is_k_o (PIPETX3CHARISKGT ), - .pipe_tx3_data_o (PIPETX3DATAGT ), - .pipe_tx3_elec_idle_o (PIPETX3ELECIDLEGT ), - .pipe_tx3_powerdown_o (PIPETX3POWERDOWNGT ), - - // Pipe Per-Lane Signals - Lane 4 - .pipe_rx4_char_is_k_o (PIPERX4CHARISK ), - .pipe_rx4_data_o (PIPERX4DATA ), - .pipe_rx4_valid_o (PIPERX4VALID ), - .pipe_rx4_chanisaligned_o (PIPERX4CHANISALIGNED ), - .pipe_rx4_status_o (PIPERX4STATUS ), - .pipe_rx4_phy_status_o (PIPERX4PHYSTATUS ), - .pipe_rx4_elec_idle_i (PIPERX4ELECIDLEGT ), - .pipe_rx4_polarity_i (PIPERX4POLARITY ), - .pipe_tx4_compliance_i (PIPETX4COMPLIANCE ), - .pipe_tx4_char_is_k_i (PIPETX4CHARISK ), - .pipe_tx4_data_i (PIPETX4DATA ), - .pipe_tx4_elec_idle_i (PIPETX4ELECIDLE ), - .pipe_tx4_powerdown_i (PIPETX4POWERDOWN ), - - .pipe_rx4_char_is_k_i (PIPERX4CHARISKGT ), - .pipe_rx4_data_i (PIPERX4DATAGT ), - .pipe_rx4_valid_i (PIPERX4VALIDGT ), - .pipe_rx4_chanisaligned_i (PIPERX4CHANISALIGNEDGT ), - .pipe_rx4_status_i (PIPERX4STATUSGT ), - .pipe_rx4_phy_status_i (PIPERX4PHYSTATUSGT ), - .pipe_rx4_elec_idle_o (PIPERX4ELECIDLE ), - .pipe_rx4_polarity_o (PIPERX4POLARITYGT ), - .pipe_tx4_compliance_o (PIPETX4COMPLIANCEGT ), - .pipe_tx4_char_is_k_o (PIPETX4CHARISKGT ), - .pipe_tx4_data_o (PIPETX4DATAGT ), - .pipe_tx4_elec_idle_o (PIPETX4ELECIDLEGT ), - .pipe_tx4_powerdown_o (PIPETX4POWERDOWNGT ), - - // Pipe Per-Lane Signals - Lane 5 - .pipe_rx5_char_is_k_o (PIPERX5CHARISK ), - .pipe_rx5_data_o (PIPERX5DATA ), - .pipe_rx5_valid_o (PIPERX5VALID ), - .pipe_rx5_chanisaligned_o (PIPERX5CHANISALIGNED ), - .pipe_rx5_status_o (PIPERX5STATUS ), - .pipe_rx5_phy_status_o (PIPERX5PHYSTATUS ), - .pipe_rx5_elec_idle_i (PIPERX5ELECIDLEGT ), - .pipe_rx5_polarity_i (PIPERX5POLARITY ), - .pipe_tx5_compliance_i (PIPETX5COMPLIANCE ), - .pipe_tx5_char_is_k_i (PIPETX5CHARISK ), - .pipe_tx5_data_i (PIPETX5DATA ), - .pipe_tx5_elec_idle_i (PIPETX5ELECIDLE ), - .pipe_tx5_powerdown_i (PIPETX5POWERDOWN ), - - .pipe_rx5_char_is_k_i (PIPERX5CHARISKGT ), - .pipe_rx5_data_i (PIPERX5DATAGT ), - .pipe_rx5_valid_i (PIPERX5VALIDGT ), - .pipe_rx5_chanisaligned_i (PIPERX5CHANISALIGNEDGT ), - .pipe_rx5_status_i (PIPERX5STATUSGT ), - .pipe_rx5_phy_status_i (PIPERX5PHYSTATUSGT ), - .pipe_rx5_elec_idle_o (PIPERX5ELECIDLE ), - .pipe_rx5_polarity_o (PIPERX5POLARITYGT ), - .pipe_tx5_compliance_o (PIPETX5COMPLIANCEGT ), - .pipe_tx5_char_is_k_o (PIPETX5CHARISKGT ), - .pipe_tx5_data_o (PIPETX5DATAGT ), - .pipe_tx5_elec_idle_o (PIPETX5ELECIDLEGT ), - .pipe_tx5_powerdown_o (PIPETX5POWERDOWNGT ), - - // Pipe Per-Lane Signals - Lane 6 - .pipe_rx6_char_is_k_o (PIPERX6CHARISK ), - .pipe_rx6_data_o (PIPERX6DATA ), - .pipe_rx6_valid_o (PIPERX6VALID ), - .pipe_rx6_chanisaligned_o (PIPERX6CHANISALIGNED ), - .pipe_rx6_status_o (PIPERX6STATUS ), - .pipe_rx6_phy_status_o (PIPERX6PHYSTATUS ), - .pipe_rx6_elec_idle_i (PIPERX6ELECIDLEGT ), - .pipe_rx6_polarity_i (PIPERX6POLARITY ), - .pipe_tx6_compliance_i (PIPETX6COMPLIANCE ), - .pipe_tx6_char_is_k_i (PIPETX6CHARISK ), - .pipe_tx6_data_i (PIPETX6DATA ), - .pipe_tx6_elec_idle_i (PIPETX6ELECIDLE ), - .pipe_tx6_powerdown_i (PIPETX6POWERDOWN ), - - .pipe_rx6_char_is_k_i (PIPERX6CHARISKGT ), - .pipe_rx6_data_i (PIPERX6DATAGT ), - .pipe_rx6_valid_i (PIPERX6VALIDGT ), - .pipe_rx6_chanisaligned_i (PIPERX6CHANISALIGNEDGT ), - .pipe_rx6_status_i (PIPERX6STATUSGT ), - .pipe_rx6_phy_status_i (PIPERX6PHYSTATUSGT ), - .pipe_rx6_elec_idle_o (PIPERX6ELECIDLE ), - .pipe_rx6_polarity_o (PIPERX6POLARITYGT ), - .pipe_tx6_compliance_o (PIPETX6COMPLIANCEGT ), - .pipe_tx6_char_is_k_o (PIPETX6CHARISKGT ), - .pipe_tx6_data_o (PIPETX6DATAGT ), - .pipe_tx6_elec_idle_o (PIPETX6ELECIDLEGT ), - .pipe_tx6_powerdown_o (PIPETX6POWERDOWNGT ), - - // Pipe Per-Lane Signals - Lane 7 - .pipe_rx7_char_is_k_o (PIPERX7CHARISK ), - .pipe_rx7_data_o (PIPERX7DATA ), - .pipe_rx7_valid_o (PIPERX7VALID ), - .pipe_rx7_chanisaligned_o (PIPERX7CHANISALIGNED ), - .pipe_rx7_status_o (PIPERX7STATUS ), - .pipe_rx7_phy_status_o (PIPERX7PHYSTATUS ), - .pipe_rx7_elec_idle_i (PIPERX7ELECIDLEGT ), - .pipe_rx7_polarity_i (PIPERX7POLARITY ), - .pipe_tx7_compliance_i (PIPETX7COMPLIANCE ), - .pipe_tx7_char_is_k_i (PIPETX7CHARISK ), - .pipe_tx7_data_i (PIPETX7DATA ), - .pipe_tx7_elec_idle_i (PIPETX7ELECIDLE ), - .pipe_tx7_powerdown_i (PIPETX7POWERDOWN ), - - .pipe_rx7_char_is_k_i (PIPERX7CHARISKGT ), - .pipe_rx7_data_i (PIPERX7DATAGT ), - .pipe_rx7_valid_i (PIPERX7VALIDGT ), - .pipe_rx7_chanisaligned_i (PIPERX7CHANISALIGNEDGT ), - .pipe_rx7_status_i (PIPERX7STATUSGT ), - .pipe_rx7_phy_status_i (PIPERX7PHYSTATUSGT ), - .pipe_rx7_elec_idle_o (PIPERX7ELECIDLE ), - .pipe_rx7_polarity_o (PIPERX7POLARITYGT ), - .pipe_tx7_compliance_o (PIPETX7COMPLIANCEGT ), - .pipe_tx7_char_is_k_o (PIPETX7CHARISKGT ), - .pipe_tx7_data_o (PIPETX7DATAGT ), - .pipe_tx7_elec_idle_o (PIPETX7ELECIDLEGT ), - .pipe_tx7_powerdown_o (PIPETX7POWERDOWNGT ), - - // Non PIPE signals - .pl_ltssm_state (PLLTSSMSTATE ), - .pipe_clk (PIPECLK ), - .rst_n (PHYRDYN ) -); - -//------------------------------------------------------- -// Virtex6 GTX Module -//------------------------------------------------------- - -pcie_gtx_v6 #( - - .NO_OF_LANES(LINK_CAP_MAX_LINK_WIDTH), - .LINK_CAP_MAX_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED), - .REF_CLK_FREQ(REF_CLK_FREQ), - .PL_FAST_TRAIN(PL_FAST_TRAIN) - -) -pcie_gt_i ( - - // Pipe Common Signals - .pipe_tx_rcvr_det (PIPETXRCVRDETGT ), - .pipe_tx_reset (1'b0 ), - .pipe_tx_rate (PIPETXRATEGT ), - .pipe_tx_deemph (PIPETXDEEMPHGT ), - .pipe_tx_margin (PIPETXMARGINGT ), - .pipe_tx_swing (1'b0), - - // Pipe Per-Lane Signals - Lane 0 - .pipe_rx0_char_is_k (PIPERX0CHARISKGT ), - .pipe_rx0_data (PIPERX0DATAGT ), - .pipe_rx0_valid (PIPERX0VALIDGT ), - .pipe_rx0_chanisaligned (PIPERX0CHANISALIGNEDGT ), - .pipe_rx0_status (PIPERX0STATUSGT ), - .pipe_rx0_phy_status (PIPERX0PHYSTATUSGT ), - .pipe_rx0_elec_idle (PIPERX0ELECIDLEGT ), - .pipe_rx0_polarity (PIPERX0POLARITYGT ), - .pipe_tx0_compliance (PIPETX0COMPLIANCEGT ), - .pipe_tx0_char_is_k (PIPETX0CHARISKGT ), - .pipe_tx0_data (PIPETX0DATAGT ), - .pipe_tx0_elec_idle (PIPETX0ELECIDLEGT ), - .pipe_tx0_powerdown (PIPETX0POWERDOWNGT ), - - // Pipe Per-Lane Signals - Lane 1 - .pipe_rx1_char_is_k (PIPERX1CHARISKGT ), - .pipe_rx1_data (PIPERX1DATAGT ), - .pipe_rx1_valid (PIPERX1VALIDGT ), - .pipe_rx1_chanisaligned (PIPERX1CHANISALIGNEDGT ), - .pipe_rx1_status (PIPERX1STATUSGT ), - .pipe_rx1_phy_status (PIPERX1PHYSTATUSGT ), - .pipe_rx1_elec_idle (PIPERX1ELECIDLEGT ), - .pipe_rx1_polarity (PIPERX1POLARITYGT ), - .pipe_tx1_compliance (PIPETX1COMPLIANCEGT ), - .pipe_tx1_char_is_k (PIPETX1CHARISKGT ), - .pipe_tx1_data (PIPETX1DATAGT ), - .pipe_tx1_elec_idle (PIPETX1ELECIDLEGT ), - .pipe_tx1_powerdown (PIPETX1POWERDOWNGT ), - - // Pipe Per-Lane Signals - Lane 2 - .pipe_rx2_char_is_k (PIPERX2CHARISKGT ), - .pipe_rx2_data (PIPERX2DATAGT ), - .pipe_rx2_valid (PIPERX2VALIDGT ), - .pipe_rx2_chanisaligned (PIPERX2CHANISALIGNEDGT ), - .pipe_rx2_status (PIPERX2STATUSGT ), - .pipe_rx2_phy_status (PIPERX2PHYSTATUSGT ), - .pipe_rx2_elec_idle (PIPERX2ELECIDLEGT ), - .pipe_rx2_polarity (PIPERX2POLARITYGT ), - .pipe_tx2_compliance (PIPETX2COMPLIANCEGT ), - .pipe_tx2_char_is_k (PIPETX2CHARISKGT ), - .pipe_tx2_data (PIPETX2DATAGT ), - .pipe_tx2_elec_idle (PIPETX2ELECIDLEGT ), - .pipe_tx2_powerdown (PIPETX2POWERDOWNGT ), - - // Pipe Per-Lane Signals - Lane 3 - .pipe_rx3_char_is_k (PIPERX3CHARISKGT ), - .pipe_rx3_data (PIPERX3DATAGT ), - .pipe_rx3_valid (PIPERX3VALIDGT ), - .pipe_rx3_chanisaligned (PIPERX3CHANISALIGNEDGT ), - .pipe_rx3_status (PIPERX3STATUSGT ), - .pipe_rx3_phy_status (PIPERX3PHYSTATUSGT ), - .pipe_rx3_elec_idle (PIPERX3ELECIDLEGT ), - .pipe_rx3_polarity (PIPERX3POLARITYGT ), - .pipe_tx3_compliance (PIPETX3COMPLIANCEGT ), - .pipe_tx3_char_is_k (PIPETX3CHARISKGT ), - .pipe_tx3_data (PIPETX3DATAGT ), - .pipe_tx3_elec_idle (PIPETX3ELECIDLEGT ), - .pipe_tx3_powerdown (PIPETX3POWERDOWNGT ), - - // Pipe Per-Lane Signals - Lane 4 - .pipe_rx4_char_is_k (PIPERX4CHARISKGT ), - .pipe_rx4_data (PIPERX4DATAGT ), - .pipe_rx4_valid (PIPERX4VALIDGT ), - .pipe_rx4_chanisaligned (PIPERX4CHANISALIGNEDGT ), - .pipe_rx4_status (PIPERX4STATUSGT ), - .pipe_rx4_phy_status (PIPERX4PHYSTATUSGT ), - .pipe_rx4_elec_idle (PIPERX4ELECIDLEGT ), - .pipe_rx4_polarity (PIPERX4POLARITYGT ), - .pipe_tx4_compliance (PIPETX4COMPLIANCEGT ), - .pipe_tx4_char_is_k (PIPETX4CHARISKGT ), - .pipe_tx4_data (PIPETX4DATAGT ), - .pipe_tx4_elec_idle (PIPETX4ELECIDLEGT ), - .pipe_tx4_powerdown (PIPETX4POWERDOWNGT ), - - // Pipe Per-Lane Signals - Lane 5 - .pipe_rx5_char_is_k (PIPERX5CHARISKGT ), - .pipe_rx5_data (PIPERX5DATAGT ), - .pipe_rx5_valid (PIPERX5VALIDGT ), - .pipe_rx5_chanisaligned (PIPERX5CHANISALIGNEDGT ), - .pipe_rx5_status (PIPERX5STATUSGT ), - .pipe_rx5_phy_status (PIPERX5PHYSTATUSGT ), - .pipe_rx5_elec_idle (PIPERX5ELECIDLEGT ), - .pipe_rx5_polarity (PIPERX5POLARITYGT ), - .pipe_tx5_compliance (PIPETX5COMPLIANCEGT ), - .pipe_tx5_char_is_k (PIPETX5CHARISKGT ), - .pipe_tx5_data (PIPETX5DATAGT ), - .pipe_tx5_elec_idle (PIPETX5ELECIDLEGT ), - .pipe_tx5_powerdown (PIPETX5POWERDOWNGT ), - - // Pipe Per-Lane Signals - Lane 6 - .pipe_rx6_char_is_k (PIPERX6CHARISKGT ), - .pipe_rx6_data (PIPERX6DATAGT ), - .pipe_rx6_valid (PIPERX6VALIDGT ), - .pipe_rx6_chanisaligned (PIPERX6CHANISALIGNEDGT ), - .pipe_rx6_status (PIPERX6STATUSGT ), - .pipe_rx6_phy_status (PIPERX6PHYSTATUSGT ), - .pipe_rx6_elec_idle (PIPERX6ELECIDLEGT ), - .pipe_rx6_polarity (PIPERX6POLARITYGT ), - .pipe_tx6_compliance (PIPETX6COMPLIANCEGT ), - .pipe_tx6_char_is_k (PIPETX6CHARISKGT ), - .pipe_tx6_data (PIPETX6DATAGT ), - .pipe_tx6_elec_idle (PIPETX6ELECIDLEGT ), - .pipe_tx6_powerdown (PIPETX6POWERDOWNGT ), - - // Pipe Per-Lane Signals - Lane 7 - .pipe_rx7_char_is_k (PIPERX7CHARISKGT ), - .pipe_rx7_data (PIPERX7DATAGT ), - .pipe_rx7_valid (PIPERX7VALIDGT ), - .pipe_rx7_chanisaligned (PIPERX7CHANISALIGNEDGT ), - .pipe_rx7_status (PIPERX7STATUSGT ), - .pipe_rx7_phy_status (PIPERX7PHYSTATUSGT ), - .pipe_rx7_elec_idle (PIPERX7ELECIDLEGT ), - .pipe_rx7_polarity (PIPERX7POLARITYGT ), - .pipe_tx7_compliance (PIPETX7COMPLIANCEGT ), - .pipe_tx7_char_is_k (PIPETX7CHARISKGT ), - .pipe_tx7_data (PIPETX7DATAGT ), - .pipe_tx7_elec_idle (PIPETX7ELECIDLEGT ), - .pipe_tx7_powerdown (PIPETX7POWERDOWNGT ), - - // PCI Express Signals - .pci_exp_txn (PCIEXPTXN ), - .pci_exp_txp (PCIEXPTXP ), - .pci_exp_rxn (PCIEXPRXN ), - .pci_exp_rxp (PCIEXPRXP ), - - // Non PIPE Signals - .sys_clk (SYSCLK ), - .sys_rst_n (FUNDRSTN ), - .pipe_clk (PIPECLK ), - .clock_locked (CLOCKLOCKED ), - .pl_ltssm_state (PLLTSSMSTATE ), - - .gt_pll_lock (GTPLLLOCK ), - .phy_rdy_n (PHYRDYN ) - -); - -//------------------------------------------------------- -// PCI Express BRAM Module -//------------------------------------------------------- - -pcie_bram_top_v6 #( - - .DEV_CAP_MAX_PAYLOAD_SUPPORTED(DEV_CAP_MAX_PAYLOAD_SUPPORTED), - - .VC0_TX_LASTPACKET(VC0_TX_LASTPACKET), - .TL_TX_RAM_RADDR_LATENCY(TL_TX_RAM_RADDR_LATENCY), - .TL_TX_RAM_RDATA_LATENCY(TL_TX_RAM_RDATA_LATENCY), - .TL_TX_RAM_WRITE_LATENCY(TL_TX_RAM_WRITE_LATENCY), - - .VC0_RX_LIMIT(VC0_RX_RAM_LIMIT), - .TL_RX_RAM_RADDR_LATENCY(TL_RX_RAM_RADDR_LATENCY), - .TL_RX_RAM_RDATA_LATENCY(TL_RX_RAM_RDATA_LATENCY), - .TL_RX_RAM_WRITE_LATENCY(TL_RX_RAM_WRITE_LATENCY) - -) -pcie_bram_i ( - - .user_clk_i( USERCLK ), - .reset_i( PHYRDYN ), - - .mim_tx_waddr( MIMTXWADDR ), - .mim_tx_wen( MIMTXWEN ), - .mim_tx_ren( MIMTXREN ), - .mim_tx_rce( MIMTXRCE ), - .mim_tx_wdata( MIMTXWDATA ), - .mim_tx_raddr( MIMTXRADDR ), - .mim_tx_rdata( MIMTXRDATA ), - - .mim_rx_waddr( MIMRXWADDR ), - .mim_rx_wen( MIMRXWEN ), - .mim_rx_ren( MIMRXREN ), - .mim_rx_rce( MIMRXRCE ), - .mim_rx_wdata( MIMRXWDATA ), - .mim_rx_raddr( MIMRXRADDR ), - .mim_rx_rdata( MIMRXRDATA ) - -); - - -//------------------------------------------------------- -// PCI Express Port Workarounds -//------------------------------------------------------- - -pcie_upconfig_fix_3451_v6 # ( - - .UPSTREAM_FACING ( UPSTREAM_FACING ), - .PL_FAST_TRAIN ( PL_FAST_TRAIN ), - .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ) - -) -pcie_upconfig_fix_3451_v6_i ( - - .pipe_clk(PIPECLK), - .pl_phy_lnkup_n(PLPHYLNKUPN), - - .pl_ltssm_state(PLLTSSMSTATE), - .pl_sel_lnk_rate(PLSELLNKRATE), - .pl_directed_link_change(PLDIRECTEDLINKCHANGE), - - .cfg_link_status_negotiated_width(CFGLINKSTATUSNEGOTIATEDWIDTH), - - .filter_pipe(filter_pipe_upconfig_fix_3451) - -); - -endmodule Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_bram_v6.v =================================================================== --- branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_bram_v6.v (revision 9) +++ branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_bram_v6.v (nonexistent) @@ -1,287 +0,0 @@ -//----------------------------------------------------------------------------- -// -// (c) Copyright 2009 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information of Xilinx, Inc. -// and is protected under U.S. and international copyright and other -// intellectual property laws. -// -// DISCLAIMER -// -// This disclaimer is not a license and does not grant any rights to the -// materials distributed herewith. Except as otherwise provided in a valid -// license issued to you by Xilinx, and to the maximum extent permitted by -// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -// and (2) Xilinx shall not be liable (whether in contract or tort, including -// negligence, or under any other theory of liability) for any loss or damage -// of any kind or nature related to, arising under or in connection with these -// materials, including for any direct, or any indirect, special, incidental, -// or consequential loss or damage (including loss of data, profits, goodwill, -// or any type of loss or damage suffered as a result of any action brought by -// a third party) even if such damage or loss was reasonably foreseeable or -// Xilinx had been advised of the possibility of the same. -// -// CRITICAL APPLICATIONS -// -// Xilinx products are not designed or intended to be fail-safe, or for use in -// any application requiring fail-safe performance, such as life-support or -// safety devices or systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any other -// applications that could lead to death, personal injury, or severe property -// or environmental damage (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and liability of any use of -// Xilinx products in Critical Applications, subject only to applicable laws -// and regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -// AT ALL TIMES. -// -//----------------------------------------------------------------------------- -// Project : Virtex-6 Integrated Block for PCI Express -// File : pcie_bram_v6.v -//-- -//-- Description: BlockRAM module for Virtex6 PCIe Block -//-- -//-- -//-- -//-------------------------------------------------------------------------------- - -`timescale 1ns/1ns - -module pcie_bram_v6 - #( - parameter DOB_REG = 0,// 1 use the output register 0 don't use the output register - parameter WIDTH = 0 // supported WIDTH's are: 4, 9, 18, 36 (uses RAMB36) and 72 (uses RAMB36SDP) - ) - ( - input user_clk_i,// user clock - input reset_i, // bram reset - - input wen_i, // write enable - input [12:0] waddr_i, // write address - input [WIDTH - 1:0] wdata_i, // write data - - input ren_i, // read enable - input rce_i, // output register clock enable - input [12:0] raddr_i, // read address - - output [WIDTH - 1:0] rdata_o // read data - ); - - // map the address bits - localparam ADDR_MSB = ((WIDTH == 4) ? 12 : - (WIDTH == 9) ? 11 : - (WIDTH == 18) ? 10 : - (WIDTH == 36) ? 9 : - 8 - ); - - // set the width of the tied off low address bits - localparam ADDR_LO_BITS = ((WIDTH == 4) ? 2 : - (WIDTH == 9) ? 3 : - (WIDTH == 18) ? 4 : - (WIDTH == 36) ? 5 : - 0 // for WIDTH 72 use RAMB36SDP - ); - - // map the data bits - localparam D_MSB = ((WIDTH == 4) ? 3 : - (WIDTH == 9) ? 7 : - (WIDTH == 18) ? 15 : - (WIDTH == 36) ? 31 : - 63 - ); - - // map the data parity bits - localparam DP_LSB = D_MSB + 1; - - localparam DP_MSB = ((WIDTH == 4) ? 4 : - (WIDTH == 9) ? 8 : - (WIDTH == 18) ? 17 : - (WIDTH == 36) ? 35 : - 71 - ); - - localparam DPW = DP_MSB - DP_LSB + 1; - - localparam WRITE_MODE = "NO_CHANGE"; - - //synthesis translate_off - initial begin - //$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d", - // $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB); - - case (WIDTH) - 4,9,18,36,72:; - default: - begin - $display("[%t] %m Error WIDTH %0d not supported", $time, WIDTH); - $finish; - end - endcase // case (WIDTH) - end - //synthesis translate_on - - generate - if (WIDTH == 72) begin : use_ramb36sdp - - // use RAMB36SDP if the width is 72 - RAMB36SDP #( - .DO_REG (DOB_REG) - ) - ramb36sdp( - .WRCLK (user_clk_i), - .SSR (1'b0), - .WRADDR (waddr_i[ADDR_MSB:0]), - .DI (wdata_i[D_MSB:0]), - .DIP (wdata_i[DP_MSB:DP_LSB]), - .WREN (wen_i), - .WE ({8{wen_i}}), - - .RDCLK (user_clk_i), - .RDADDR (raddr_i[ADDR_MSB:0]), - .DO (rdata_o[D_MSB:0]), - .DOP (rdata_o[DP_MSB:DP_LSB]), - .RDEN (ren_i), - .REGCE (rce_i) - ); - - // use RAMB36's if the width is 4, 9, 18, or 36 - end else if (WIDTH == 36) begin : use_ramb36 - - RAMB36 #( - .DOA_REG (0), - .DOB_REG (DOB_REG), - .READ_WIDTH_A (0), - .READ_WIDTH_B (WIDTH), - .WRITE_WIDTH_A (WIDTH), - .WRITE_WIDTH_B (0), - .WRITE_MODE_A (WRITE_MODE) - ) - ramb36( - .CLKA (user_clk_i), - .SSRA (1'b0), - .REGCEA (1'b0), - .CASCADEINLATA (1'b0), - .CASCADEINREGA (1'b0), - .CASCADEOUTLATA (), - .CASCADEOUTREGA (), - .DOA (), - .DOPA (), - .ADDRA ({1'b1, waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}), - .DIA (wdata_i[D_MSB:0]), - .DIPA (wdata_i[DP_MSB:DP_LSB]), - .ENA (wen_i), - .WEA ({4{wen_i}}), - - .CLKB (user_clk_i), - .SSRB (1'b0), - .WEB (4'b0), - .CASCADEINLATB (1'b0), - .CASCADEINREGB (1'b0), - .CASCADEOUTLATB (), - .CASCADEOUTREGB (), - .DIB (32'b0), - .DIPB ( 4'b0), - .ADDRB ({1'b1, raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}), - .DOB (rdata_o[D_MSB:0]), - .DOPB (rdata_o[DP_MSB:DP_LSB]), - .ENB (ren_i), - .REGCEB (rce_i) - ); - - end else if (WIDTH < 36 && WIDTH > 4) begin : use_ramb36 - - wire [31 - D_MSB - 1 : 0] dob_unused; - wire [ 4 - DPW - 1 : 0] dopb_unused; - - RAMB36 #( - .DOA_REG (0), - .DOB_REG (DOB_REG), - .READ_WIDTH_A (0), - .READ_WIDTH_B (WIDTH), - .WRITE_WIDTH_A (WIDTH), - .WRITE_WIDTH_B (0), - .WRITE_MODE_A (WRITE_MODE) - ) - ramb36( - .CLKA (user_clk_i), - .SSRA (1'b0), - .REGCEA (1'b0), - .CASCADEINLATA (1'b0), - .CASCADEINREGA (1'b0), - .CASCADEOUTLATA (), - .CASCADEOUTREGA (), - .DOA (), - .DOPA (), - .ADDRA ({1'b1, waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}), - .DIA ({{31 - D_MSB{1'b0}},wdata_i[D_MSB:0]}), - .DIPA ({{ 4 - DPW {1'b0}},wdata_i[DP_MSB:DP_LSB]}), - .ENA (wen_i), - .WEA ({4{wen_i}}), - - .CLKB (user_clk_i), - .SSRB (1'b0), - .WEB (4'b0), - .CASCADEINLATB (1'b0), - .CASCADEINREGB (1'b0), - .CASCADEOUTLATB (), - .CASCADEOUTREGB (), - .DIB (32'b0), - .DIPB ( 4'b0), - .ADDRB ({1'b1, raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}), - .DOB ({dob_unused, rdata_o[D_MSB:0]}), - .DOPB ({dopb_unused, rdata_o[DP_MSB:DP_LSB]}), - .ENB (ren_i), - .REGCEB (rce_i) - ); - - end else if (WIDTH == 4) begin : use_ramb36 - - wire [31 - D_MSB - 1 : 0] dob_unused; - - RAMB36 #( - .DOB_REG (DOB_REG), - .READ_WIDTH_A (0), - .READ_WIDTH_B (WIDTH), - .WRITE_WIDTH_A (WIDTH), - .WRITE_WIDTH_B (0), - .WRITE_MODE_A (WRITE_MODE) - ) - ramb36( - .CLKA (user_clk_i), - .SSRA (1'b0), - .REGCEA (1'b0), - .CASCADEINLATA (1'b0), - .CASCADEINREGA (1'b0), - .CASCADEOUTLATA (), - .CASCADEOUTREGA (), - .DOA (), - .DOPA (), - .ADDRA ({1'b1, waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}), - .DIA ({{31 - D_MSB{1'b0}},wdata_i[D_MSB:0]}), - //.DIPA (wdata_i[DP_MSB:DP_LSB]), - .ENA (wen_i), - .WEA ({4{wen_i}}), - - .CLKB (user_clk_i), - .SSRB (1'b0), - .WEB (4'b0), - .CASCADEINLATB (1'b0), - .CASCADEINREGB (1'b0), - .CASCADEOUTLATB (), - .CASCADEOUTREGB (), - .ADDRB ({1'b1, raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}), - .DOB ({dob_unused,rdata_o[D_MSB:0]}), - //.DOPB (rdata_o[DP_MSB:DP_LSB]), - .ENB (ren_i), - .REGCEB (rce_i) - ); - - end // block: use_ramb36 - endgenerate - -endmodule // pcie_bram_v6 Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/gtx_tx_sync_rate_v6.v =================================================================== --- branches/Virtex6/ML605/v6_pcie_v1_3/source/gtx_tx_sync_rate_v6.v (revision 9) +++ branches/Virtex6/ML605/v6_pcie_v1_3/source/gtx_tx_sync_rate_v6.v (nonexistent) @@ -1,413 +0,0 @@ - -//----------------------------------------------------------------------------- -// -// (c) Copyright 2009 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information of Xilinx, Inc. -// and is protected under U.S. and international copyright and other -// intellectual property laws. -// -// DISCLAIMER -// -// This disclaimer is not a license and does not grant any rights to the -// materials distributed herewith. Except as otherwise provided in a valid -// license issued to you by Xilinx, and to the maximum extent permitted by -// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -// and (2) Xilinx shall not be liable (whether in contract or tort, including -// negligence, or under any other theory of liability) for any loss or damage -// of any kind or nature related to, arising under or in connection with these -// materials, including for any direct, or any indirect, special, incidental, -// or consequential loss or damage (including loss of data, profits, goodwill, -// or any type of loss or damage suffered as a result of any action brought by -// a third party) even if such damage or loss was reasonably foreseeable or -// Xilinx had been advised of the possibility of the same. -// -// CRITICAL APPLICATIONS -// -// Xilinx products are not designed or intended to be fail-safe, or for use in -// any application requiring fail-safe performance, such as life-support or -// safety devices or systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any other -// applications that could lead to death, personal injury, or severe property -// or environmental damage (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and liability of any use of -// Xilinx products in Critical Applications, subject only to applicable laws -// and regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -// AT ALL TIMES. -// -//----------------------------------------------------------------------------- -// Project : Virtex-6 Integrated Block for PCI Express -// File : gtx_tx_sync_rate_v6.v -////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps -`define DLY #1 - -module GTX_TX_SYNC_RATE_V6 -#( - parameter C_SIMULATION = 0 // Set to 1 for simulation -) -( - output ENPMAPHASEALIGN, - output PMASETPHASE, - output SYNC_DONE, - output OUT_DIV_RESET, - output PCS_RESET, - output USER_PHYSTATUS, - output RATE_CLK_SEL, - input USER_CLK, - input RESET, - input RATE, - input RATEDONE, - input GT_PHYSTATUS, - input RESETDONE, - - // Test bits / status - output [53:0] DEBUG_STATUS, - input [2:0] ENPMA_STATE_MASK, - input [2:0] OUTDIV_STATE_MASK - -); - -// synthesis attribute X_CORE_INFO of TX_SYNC is "v6_gtxwizard_v1_0, Coregen v11.1_ip1"; - -//*******************************Register Declarations************************ - - reg begin_r; - reg phase_align_r; - reg ready_r; - reg [15:0] sync_counter_r; - reg [5:0] count_32_cycles_r; - reg wait_stable_r; - reg phase_align_reset_r; - reg out_div_reset_r; - reg wait_phase_align_reset_r; - reg pcs_reset_r; - reg wait_reset_done_r; - reg gen_phystatus_r; - reg rate_r; - reg guard_r; - reg resetdone_r; - reg resetdone_r2; - reg ratedone_r; - reg ratedone_r2; - reg rate_sel_r; - - reg enpmaphasealign_r; - reg reg_out_div_reset_r; - reg [24:0] rate_duration_count_r; - - -//*******************************Wire Declarations**************************** - - wire count_setphase_complete_i; - wire count_32_complete_i; - wire next_phase_align_c; - wire next_ready_c; - wire next_wait_stable_c; - wire next_phase_align_reset_c; - wire next_out_div_reset_c; - wire next_wait_phase_align_reset_c; - wire next_pcs_reset_c; - wire next_wait_reset_done_c; - wire next_gen_phystatus_c; - wire ratedone_pulse_i; - - wire enpmaphasealign_i; - wire out_div_reset_i; - -//*******************************Main Body of Code**************************** - - - - - //________________________________ State machine __________________________ - // This state machine manages the phase alingment procedure of the GTX. - // The module is held in reset till the usrclk source is stable. In the - // case of buffer bypass where the refclkout is used to clock the usrclks, - // the usrclk stable indication is given the pll_locked signal. - // Once the pll_lock is asserted, state machine goes into the - // wait_stable_r for 32 clock cycles to allow some time to ensure the pll - // is stable. After this, it goes into the phase_align_r state where the - // phase alignment procedure is executed. This involves asserting the - // ENPMAPHASEALIGN and PMASETPHASE for 32768 clock cycles. - // - // If there is a line rate change, the module resets the output divider by - // asserting the signal for 16 clock cycles and resets the phase alignment - // block by de-asserting ENPMAPHASEALIGN signal for 16 clock cycles. The - // phase alignment procedure as stated above is repeated. Afterwards, the - // PCS is reset and a user PHYSTATUS is generated to notify the completion - // of a line rate change procedure. - - // State registers - always @(posedge USER_CLK) - if(RESET) - {begin_r, wait_stable_r, phase_align_r, ready_r, - phase_align_reset_r, out_div_reset_r, wait_phase_align_reset_r, - pcs_reset_r, wait_reset_done_r, - gen_phystatus_r} <= `DLY 10'b10_0000_0000; - else - begin - begin_r <= `DLY 1'b0; - wait_stable_r <= `DLY next_wait_stable_c; - phase_align_r <= `DLY next_phase_align_c; - ready_r <= `DLY next_ready_c; - phase_align_reset_r <= `DLY next_phase_align_reset_c; - out_div_reset_r <= `DLY next_out_div_reset_c; - wait_phase_align_reset_r <= `DLY next_wait_phase_align_reset_c; - pcs_reset_r <= `DLY next_pcs_reset_c; - wait_reset_done_r <= `DLY next_wait_reset_done_c; - gen_phystatus_r <= `DLY next_gen_phystatus_c; - end - - // Next state logic - assign next_ready_c = (((phase_align_r & count_setphase_complete_i) & !guard_r) | gen_phystatus_r) | - (!ratedone_pulse_i & ready_r); - - assign next_phase_align_reset_c = (ratedone_pulse_i & ready_r) | - (phase_align_reset_r & !count_32_complete_i); - - assign next_out_div_reset_c = (phase_align_reset_r & count_32_complete_i)| - (out_div_reset_r & !count_32_complete_i); - - assign next_wait_phase_align_reset_c = (out_div_reset_r & count_32_complete_i) | - (wait_phase_align_reset_r & !count_32_complete_i); - - assign next_wait_stable_c = begin_r | (wait_phase_align_reset_r & count_32_complete_i) | - (wait_stable_r & !count_32_complete_i); - - assign next_phase_align_c = (wait_stable_r & count_32_complete_i) | - (phase_align_r & !count_setphase_complete_i); - - assign next_pcs_reset_c = ((phase_align_r & count_setphase_complete_i) & guard_r); - - assign next_wait_reset_done_c = pcs_reset_r | - (!resetdone_r2 & wait_reset_done_r); - - assign next_gen_phystatus_c = resetdone_r2 & wait_reset_done_r; - - - //_________ Counter for to wait for pll to be stable before sync __________ - always @(posedge USER_CLK) - begin - if (RESET || count_32_complete_i) - count_32_cycles_r <= `DLY 6'b000000; - else if (wait_stable_r || out_div_reset_r || phase_align_reset_r || wait_phase_align_reset_r) - count_32_cycles_r <= `DLY count_32_cycles_r + 1'b1; - end - - assign count_32_complete_i = count_32_cycles_r[5]; - - //_______________ Counter for holding SYNC for SYNC_CYCLES ________________ - always @(posedge USER_CLK) - begin - if (!phase_align_r) - sync_counter_r <= `DLY 16'h0000; - else - sync_counter_r <= `DLY sync_counter_r + 1'b1; - end - - generate - if (C_SIMULATION) begin: for_simulation - // Shorten the cycle to 32 clock cycles for simulation - assign count_setphase_complete_i = sync_counter_r[5]; - end - else begin: for_hardware - // For TXPMASETPHASE: - // - If RATE[0] = 0, PLL_DIVSEL_OUT = 2 => 16,384 USRCLK2 cycles - // - If RATE[0] = 1, PLL_DIVSEL_OUT = 1 => 8,192 USRCLK2 cycles - assign count_setphase_complete_i = (rate_r) ? sync_counter_r[13] : - sync_counter_r[14]; - end - endgenerate - - - //_______________ Assign the phase align ports into the GTX _______________ - - // Assert the ENPMAPHASEALIGN signal when the reset of this module - // gets de-asserted and after a reset of the output dividers. Disabling - // this signal after reset of the output dividers will reset the phase - // alignment module. - //assign ENPMAPHASEALIGN = !(begin_r | phase_align_reset_r | out_div_reset_r | wait_phase_align_reset_r); - - // Masking the bits of each state to play around with the pulse of the - // TXENPMAPHASEALIGN reset (active low signal) - assign enpmaphasealign_i = ~((begin_r || - (phase_align_reset_r && ENPMA_STATE_MASK[2]) || - (out_div_reset_r && ENPMA_STATE_MASK[1]) || - (wait_phase_align_reset_r && ENPMA_STATE_MASK[0]))); - - always @(posedge USER_CLK) - if (RESET) - enpmaphasealign_r <= `DLY 1'b0; - else - enpmaphasealign_r <= enpmaphasealign_i; - - assign ENPMAPHASEALIGN = enpmaphasealign_r; - - assign PMASETPHASE = phase_align_r; - - - //_______________________ Assign the sync_done port _______________________ - - // Assert the SYNC_DONE signal when the phase alignment procedure is - // complete after initialization and when line rate change procedure - // is complete. - assign SYNC_DONE = ready_r & !guard_r; - - - //_______________________ Assign the rest of the ports ____________________ - // Assert the output divider reset for 32 USRCLK2 clock cycles - //assign OUT_DIV_RESET = out_div_reset_r; - - // Masking the bits of each state to play around with the pulse of the - // output divider reset - assign out_div_reset_i= (phase_align_reset_r && OUTDIV_STATE_MASK[2]) || - (out_div_reset_r && OUTDIV_STATE_MASK[1]) || - (wait_phase_align_reset_r && OUTDIV_STATE_MASK[0]); - - always @(posedge USER_CLK) - if (RESET) - reg_out_div_reset_r <= `DLY 1'b0; - else - reg_out_div_reset_r <= out_div_reset_i; - - assign OUT_DIV_RESET = reg_out_div_reset_r; - - // Assert the PCS reset for 1 USRCLK2 clock cycle - assign PCS_RESET = pcs_reset_r; - - - // Assert user phystatus at the end of the line rate change. It is also - // a pass through signal from the GTX when the pulse is not associated - // with a line rate change (in this module this signal is gated by - // guard_r signal) - assign USER_PHYSTATUS = gen_phystatus_r | (GT_PHYSTATUS & !guard_r); - - - ////////////////////////////////////////////////////////////////////////// - // Register the RESETDONE input - ////////////////////////////////////////////////////////////////////////// - always @(posedge USER_CLK) - - begin - if (RESET | pcs_reset_r) - begin - resetdone_r <= `DLY 1'b0; - resetdone_r2 <= `DLY 1'b0; - end - else - begin - resetdone_r <= `DLY RESETDONE; - resetdone_r2 <= `DLY resetdone_r; - end - end - - ////////////////////////////////////////////////////////////////////////// - // Detect an edge on the RATEDONE signal and generate a pulse from it. - // The RATEDONE signal by default is initialized to 1'b1. - ////////////////////////////////////////////////////////////////////////// - always @(posedge USER_CLK) - - begin - if (RESET) - begin - ratedone_r <= `DLY 1'b0; - ratedone_r2 <= `DLY 1'b0; - end - else - begin - ratedone_r <= `DLY RATEDONE; - ratedone_r2 <= `DLY ratedone_r; - end - end - - assign ratedone_pulse_i = ratedone_r & !ratedone_r2; - - ////////////////////////////////////////////////////////////////////////// - // Detect a line rate change. Since this is targeted for PCIe, we only - // need to detect a change on TXRATE[0]/RXRATE[0]: - // TXRATE[1:0] / RXRATE[1:0] = 10 for output divider /2 - // TXRATE[1:0] / RXRATE[1:0] = 11 for output divider /1 - ////////////////////////////////////////////////////////////////////////// - always @(posedge USER_CLK) - begin - rate_r <= `DLY RATE; - end - - assign rate_change_i = rate_r ^ RATE; - - - ////////////////////////////////////////////////////////////////////////// - // Generate an internal "guard" signal to denote that the line rate - // sequence of operation initiated. This signal is driven High when the - // there is a rate change trigger by a change in TXRATE or RXRATE ports. - ////////////////////////////////////////////////////////////////////////// - always @(posedge USER_CLK) - begin - if (RESET | gen_phystatus_r) - guard_r <= `DLY 1'b0; - else if (rate_change_i == 1'b1) - guard_r <= `DLY 1'b1; - end - - - ////////////////////////////////////////////////////////////////////////// - // Generate the BUFGMUX select signal that selects the correct clock to - // used based on a rate change. For PCIe: - // - RATE[0] = 0 => Use 125 MHz USRCLK2 with RATE_CLK_SEL = 0 - // - RATE[0] = 1 => Use 250 MHz USRCLK2 with RATE_CLK_SEL = 1 - // The RATE_CLK_SEL changes based on the RATEDONE signal from the GTX. - // The default of this pin is set to 1'b0. Someone can change it to grab - // the value from a parameter if the reset value has to be another value - // other than 1'b0. - ////////////////////////////////////////////////////////////////////////// - always @(posedge USER_CLK) - begin - if (RESET) - rate_sel_r <= `DLY 1'b0; - else if (ratedone_pulse_i == 1'b1) - rate_sel_r <= `DLY rate_r; - end - - assign RATE_CLK_SEL = rate_sel_r; - - ////////////////////////////////////////////////////////////////////////// - // Create a counter that starts when guard_r is High. After - // guard_r gets de-asserted, the counter stops counting. The counter gets - // reset when there is a rate change applied from the user; this rate - // change pulse occurs one USER_CLK cycle earlier than guard_r. - ////////////////////////////////////////////////////////////////////////// - always @(posedge USER_CLK) - begin - if (RESET | rate_change_i) - rate_duration_count_r <= `DLY 25'b0_0000_0000_0000_0000_0000_0000; - else if (guard_r) - rate_duration_count_r <= `DLY rate_duration_count_r + 1'b1; - else - rate_duration_count_r <= `DLY rate_duration_count_r; - end - - - //Monitoring the signals on ILa - assign DEBUG_STATUS= {sync_counter_r[15:0], //[53:38] - rate_r, //[37] - rate_duration_count_r[24:0],//[36:12] - begin_r, //[11] - wait_stable_r, //[10] - phase_align_r, //[9] - ready_r, //[8] - phase_align_reset_r, //[7] - out_div_reset_r, //[6] - wait_phase_align_reset_r, //[5] - pcs_reset_r, //[4] - wait_reset_done_r, //[3] - gen_phystatus_r, //[2] - guard_r, //[1] - rate_change_i}; //[0] -endmodule Index: branches/Virtex6/ML605/ml605_link_wrapper.v =================================================================== --- branches/Virtex6/ML605/ml605_link_wrapper.v (revision 9) +++ branches/Virtex6/ML605/ml605_link_wrapper.v (nonexistent) @@ -1,181 +0,0 @@ -`include "mgt_parameters.h" - -module ml605_link_wrapper # -( - parameter SIMULATION = 0, - parameter DATAWIDTH = 16, - parameter WORDS = DATAWIDTH/8, - parameter ALIGN_CHAR = `K285, - parameter READY_CHAR0 = `K284, - parameter READY_CHAR1 = `K287 -) -( - input TILE0_REFCLK_PAD_N_IN, - input TILE0_REFCLK_PAD_P_IN, - input RXN_IN, - input RXP_IN, - output wire TXN_OUT, - output wire TXP_OUT, - input wire SFP_LOS, - - output wire tx_clk, - output wire rx_clk, - output wire link_active, - - output wire ctrl2send_stop, - input wire ctrl2send_start, - input wire ctrl2send_end, - input wire [15:0] ctrl2send, - - output wire data2send_stop, - input wire data2send_start, - input wire data2send_end, - input wire [15:0] data2send, - - input wire dlm2send_valid, - input wire [3:0] dlm2send, - - output wire [3:0] dlm_rec, - output wire dlm_rec_valid, - - output wire data_rec_start, - output wire data_rec_end, - output wire [15:0] data_rec, - output wire crc_error_rec, - input wire data_rec_stop, - - output wire ctrl_rec_start, - output wire ctrl_rec_end, - output wire [15:0] ctrl_rec, - input wire ctrl_rec_stop - -); - -`include "cbm_lp_defines.h" - -wire [1:0] TXN_OUT_i; -wire [1:0] TXP_OUT_i; -wire tx_ready0; -wire rx_ready0; -wire [DATAWIDTH-1:0] rx_data0; -wire [WORDS-1:0] rx_charisk0; -wire [DATAWIDTH-1:0] tx_data0; -wire [WORDS-1:0] tx_charisk0; - -wire [(DATAWIDTH-1):0] rx_data2fifo0; -wire [(WORDS-1):0] rx_charisk2fifo0; - -wire [(DATAWIDTH-1):0] rx_data2idlefilter0; -wire [(WORDS-1):0] rx_charisk2idlefilter0; - -wire [(DATAWIDTH-1):0] rx_data2idlemux0; -wire [(WORDS-1):0] rx_charisk2idlemux0; - -reg [(DATAWIDTH-1):0] rx_data2serdes_temp0; -reg [(WORDS-1):0] rx_charisk2serdes_temp0; - -reg [(DATAWIDTH-1):0] rx_data2serdes0; -reg [(WORDS-1):0] rx_charisk2serdes0; - -reg no_idle0; -wire rxfifo_shift_out0; -reg rxfifo_shift_out_del0; - - - - assign TXN_OUT = TXN_OUT_i[0]; - assign TXP_OUT = TXP_OUT_i[0]; - - gtp_det_lat_wrapper_16bit # - ( - .ALIGN_CHAR(`K285), - .READY_CHAR0(`K284), - .READY_CHAR1(`K287), - .SIMULATION(SIMULATION) //some things get adjusted for simulation - ) - gtp_wrapper_i - ( - .TILE0_REFCLK_PAD_N_IN (TILE0_REFCLK_PAD_N_IN), - .TILE0_REFCLK_PAD_P_IN (TILE0_REFCLK_PAD_P_IN), - .GTPRESET_IN (1'b0), - .TILE0_PLLLKDET_OUT ( ), // - .RXN_IN ({1'b0, RXN_IN}), - .RXP_IN ({1'b0, RXP_IN}), - .TXN_OUT (TXN_OUT_i), - .TXP_OUT (TXP_OUT_i), - .SFP_LOS ({1'b0, SFP_LOS}), - - .TX_USRCLK (tx_clk), - .RX_USRCLK0 (rx_clk), - .RX_USRCLK1 ( ), // - .TX_READY0 (tx_ready0), - .TX_READY1 ( ), // - .RX_READY0 (rx_ready0), - .RX_READY1 ( ), // - .RX_DATA0 (rx_data2fifo0), - .RX_DATA1 ( ), // - .RX_CHARISK0 (rx_charisk2fifo0), - .RX_CHARISK1 ( ), // - .TX_DATA0 (tx_data0), - .TX_DATA1 ('b0), - .TX_CHARISK0 (tx_charisk0), - .TX_CHARISK1 ('b0) - ); - - -syncfifo4cbm rx0_fifo -( - .res_n(rx_ready0), - .w_clk(rx_clk), - .r_clk(tx_clk), - .data_in(rx_data2fifo0), - .charisk_in(rx_charisk2fifo0), - .data_out(rx_data0), - .charisk_out(rx_charisk0) -); - - -lp_cbm_top lp_cbm_top_I0( - .clk(tx_clk), - .res_n(tx_ready0), - .link_active(link_active), - .link_clk(), - - .ctrl2send_stop(ctrl2send_stop), - .ctrl2send_start(ctrl2send_start), - .ctrl2send_end(ctrl2send_end), - .ctrl2send(ctrl2send), - .crc_error_send(1'b0), - - .data2send_stop(data2send_stop), - .data2send_start(data2send_start), - .data2send_end(data2send_end), - .data2send(data2send), - - .dlm2send_va(dlm2send_valid), - .dlm2send(dlm2send), - - .dlm_rec_type(dlm_rec), - .dlm_rec_va(dlm_rec_valid), - - .data_rec(data_rec), - .data_rec_start(data_rec_start), - .data_rec_end(data_rec_end), - .data_rec_stop(data_rec_stop), - .crc_error_rec(crc_error_rec), - - .ctrl_rec(ctrl_rec), - .ctrl_rec_start(ctrl_rec_start), - .ctrl_rec_end(ctrl_rec_end), - .ctrl_rec_stop(ctrl_rec_stop), - - .clk_link(tx_clk), - .data_from_link({rx_charisk0, rx_data0}), - .data2link({tx_charisk0, tx_data0}), - - .cable_detected(rx_ready0), - .dll_locked(rx_ready0) -); - - -endmodule \ No newline at end of file Index: branches/Virtex6/ML605/DMA_FSM.vhd =================================================================== --- branches/Virtex6/ML605/DMA_FSM.vhd (revision 9) +++ branches/Virtex6/ML605/DMA_FSM.vhd (nonexistent) @@ -1,963 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Design Name: --- Module Name: DMA_FSM - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- The state machine controls the DMA routine, writes the channel --- buffer, as well as outputs DMA stata. --- --- Dependencies: --- --- Revision 1.00 - Created. 25.07.2007 --- --- Additional Comments: --- ----------------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.abb64Package.all; - - --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity DMA_FSM is - port ( - -- Fixed word for 1st header of TLP: MRd/MWr - TLP_Has_Payload : IN std_logic; - TLP_Hdr_is_4DW : IN std_logic; - DMA_Addr_Inc : IN std_logic; - - DMA_BAR_Number : IN std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0); - - -- FSM control signals - DMA_Start : IN std_logic; - DMA_Start2 : IN std_logic; - DMA_Stop : IN std_logic; - DMA_Stop2 : IN std_logic; - - No_More_Bodies : IN std_logic; - ThereIs_Snout : IN std_logic; - ThereIs_Body : IN std_logic; - ThereIs_Tail : IN std_logic; - ThereIs_Dex : IN std_logic; - - -- Parameters to be written into ChBuf - DMA_PA_Loaded : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); - DMA_PA_Var : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); - DMA_HA_Var : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - DMA_BDA_fsm : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); - BDA_is_64b_fsm : IN std_logic; - - DMA_Snout_Length : IN std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0); - DMA_Body_Length : IN std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0); - DMA_Tail_Length : IN std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0); - - -- Busy/Done conditions - Done_Condition_1 : IN std_logic; - Done_Condition_2 : IN std_logic; - Done_Condition_3 : IN std_logic; - Done_Condition_4 : IN std_logic; - Done_Condition_5 : IN std_logic; - - - -- Channel buffer write - us_MWr_Param_Vec : IN std_logic_vector(6-1 downto 0); - ChBuf_aFull : IN std_logic; - ChBuf_WrEn : OUT std_logic; - ChBuf_WrDin : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0); - - - -- FSM indicators - State_Is_LoadParam : OUT std_logic; - State_Is_Snout : OUT std_logic; - State_Is_Body : OUT std_logic; - State_Is_Tail : OUT std_logic; - DMA_Cmd_Ack : OUT std_logic; - - -- To Tx Port - ChBuf_ValidRd : IN std_logic; - BDA_nAligned : OUT std_logic; - DMA_TimeOut : OUT std_logic; - DMA_Busy : OUT std_logic; - DMA_Done : OUT std_logic; --- DMA_Done_Rise : OUT std_logic; - - -- Tags - Pkt_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0); - Dex_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0); - - -- Common ports - dma_clk : IN std_logic; - dma_reset : IN std_logic - ); - -end entity DMA_FSM; - - - -architecture Behavioral of DMA_FSM is - - -- DMA operation control FSM - type DMAStates is ( - -- dmaST_Init: Initial state at reset. - dmaST_Init - - -- dmaST_Load_Param: Load DMA parameters (PA, HA, BDA and Leng). - , dmaST_Load_Param - - -- dmaST_Snout: 1st TLP might be non-integeral of MAX_SIZE. - , dmaST_Snout - - -- dmaST_Stomp: after every ChBuf write, pause a clock before taking - -- next write. This state checks the availability of - -- the ChBuf (channel buffer) for write. - , dmaST_Stomp - - -- dmaST_Body: TLP's in the middle, always integeral of MAX_SIZE. - , dmaST_Body - - -- dmaST_Tail: the last TLP, similar with the 1st one, whose size - -- should be specially calculated. - , dmaST_Tail - --- -- dmaST_Before_Dex: before writing the MRd TLP (for next descriptor) --- -- information for the next descriptor (if any), --- -- a pause is needed to wait for the ChBuf available. --- , dmaST_Before_Dex - - -- dmaST_NextDex: writing the descriptor MRd TLP information to - -- the ChBuf. - , dmaST_NextDex - - -- dmaST_Await_Dex: after MRd(descriptor) info is written in the ChBuf, - -- the state machine waits for the descriptor's - -- arrival. - , dmaST_Await_Dex - ); - - signal DMA_NextState : DMAStates; - signal DMA_State : DMAStates; - - - -- Busy/Done state bits generation - type FSM_BusyDone is ( - FSM_Idle - , FSM_Busy1 - , FSM_Busy2 - , FSM_Busy3 - , FSM_Busy4 - , FSM_Busy5 - , FSM_Done - ); - - signal BusyDone_NextState : FSM_BusyDone; - signal BusyDone_State : FSM_BusyDone; - - - -- Time-out state - type FSM_Time_Out is ( - toutSt_Idle - , toutSt_CountUp - , toutSt_Pause - ); - - signal DMA_TimeOut_State : FSM_Time_Out; - - -- DMA Start command from MWr channel - signal DMA_Start_r1 : std_logic; - -- DMA Start command from CplD channel - signal DMA_Start2_r1 : std_logic; - -- Registered Dex indicator - signal ThereIs_Dex_reg : std_logic; - signal ThereIs_Snout_reg : std_logic; - signal ThereIs_Body_reg : std_logic; - signal ThereIs_Tail_reg : std_logic; - - -- DMA Stutus monitor - signal BDA_nAligned_i : std_logic; - signal DMA_Busy_i : std_logic; - signal DMA_Done_i : std_logic; - - -- FSM state indicators - signal State_Is_LoadParam_i : std_logic; - signal State_Is_Snout_i : std_logic; - signal State_Is_Body_i : std_logic; - signal State_Is_Tail_i : std_logic; - signal State_Is_AwaitDex_i : std_logic; - - -- Acknowledge for DMA_Start command - signal DMA_Cmd_Ack_i : std_logic; - - - -- channel FIFO Write control - signal ChBuf_WrDin_i : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0); - signal ChBuf_WrEn_i : std_logic; - signal ChBuf_aFull_i : std_logic; - - - -- --------------------------------------------------------------------------------- - -- Time-out calculation : invisible to the user, so moved out of the abbPackage - -- --------------------------------------------------------------------------------- - - signal cnt_DMA_TO : std_logic_vector(C_TOUT_WIDTH-1 downto 0); - signal Tout_Lo_Carry : std_logic; - signal DMA_TimeOut_i : std_logic; - - -- Carry bit, only for better timing - Constant CBIT_TOUT_CARRY : integer := C_TOUT_WIDTH/2; - -begin - - -- As DMA Statuses - BDA_nAligned <= BDA_nAligned_i ; - DMA_Busy <= DMA_Busy_i ; - DMA_Done <= DMA_Done_i ; --- DMA_Done_Rise <= DMA_Done_Rise_i; - DMA_TimeOut <= DMA_TimeOut_i ; - - - -- Abstract buffer write control - ChBuf_WrEn <= ChBuf_WrEn_i; - ChBuf_WrDin <= ChBuf_WrDin_i; - ChBuf_aFull_i <= ChBuf_aFull; - - - -- FSM State indicators - State_Is_LoadParam <= State_Is_LoadParam_i; - State_Is_Snout <= State_Is_Snout_i; - State_Is_Body <= State_Is_Body_i; - State_Is_Tail <= State_Is_Tail_i; - - DMA_Cmd_Ack <= DMA_Cmd_Ack_i; - - --- ----------------------------------------- --- Syn_Delay: DMA_Start --- DMA_Start2 --- - Syn_Delay_DMA_Starts: - process ( dma_clk) - begin - if dma_clk'event and dma_clk = '1' then - DMA_Start_r1 <= DMA_Start; - DMA_Start2_r1 <= DMA_Start2; - end if; - - end process; - - - ----- ----------------------------------------- ----- ----------------------------------------- ----- --- States synchronous: DMA ----- - Syn_DMA_States: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - DMA_State <= dmaST_Init; - elsif dma_clk'event and dma_clk = '1' then - DMA_State <= DMA_NextState; - end if; - - end process; - - - --- Next States: DMA - Comb_DMA_NextState: - process ( - DMA_State - , DMA_Start_r1 - , DMA_Start2_r1 - , ChBuf_aFull_i - - , No_More_Bodies - , ThereIs_Snout --_reg --- , ThereIs_Body - , ThereIs_Tail_reg - , ThereIs_Dex_reg - ) - begin - case DMA_State is - - when dmaST_Init => - if DMA_Start_r1 = '1' then - DMA_NextState <= dmaST_Load_Param; - else - DMA_NextState <= dmaST_Init; - end if; - - - when dmaST_Load_Param => - if ChBuf_aFull_i = '1' then - DMA_NextState <= dmaST_Load_Param; - elsif ThereIs_Dex_reg = '1' then - DMA_NextState <= dmaST_NextDex; - elsif ThereIs_Snout = '1' then - DMA_NextState <= dmaST_Snout; --- elsif ThereIs_Body = '1' then --- DMA_NextState <= dmaST_Stomp; - else - DMA_NextState <= dmaST_Stomp; - end if; - - - when dmaST_NextDex => - if ThereIs_Snout = '1' then - DMA_NextState <= dmaST_Snout; - elsif No_More_Bodies = '0' then - DMA_NextState <= dmaST_Body; - else - DMA_NextState <= dmaST_Await_Dex; - end if; - - - when dmaST_Snout => - DMA_NextState <= dmaST_Stomp; - - - when dmaST_Stomp => - if ChBuf_aFull_i = '1' then - DMA_NextState <= dmaST_Stomp; - elsif No_More_Bodies= '0' then - DMA_NextState <= dmaST_Body; - elsif ThereIs_Tail_reg= '1' then - DMA_NextState <= dmaST_Tail; - elsif ThereIs_Dex_reg= '1' then - DMA_NextState <= dmaST_Await_Dex; - else - DMA_NextState <= dmaST_Init; - end if; - - - when dmaST_Body => - DMA_NextState <= dmaST_Stomp; - - - when dmaST_Tail => - if ThereIs_Dex_reg = '1' then - DMA_NextState <= dmaST_Await_Dex; - else - DMA_NextState <= dmaST_Init; - end if; - - - when dmaST_Await_Dex => - if DMA_Start2_r1 = '1' then - DMA_NextState <= dmaST_Load_Param; - else - DMA_NextState <= dmaST_Await_Dex; - end if; - - - when Others => - DMA_NextState <= dmaST_Init; - - - end case; -- DMA_State - - end process; - - - --- ---------------------------------------------------- --- States synchronous: DMA_Cmd_Ack --- equivalent to State_Is_LoadParam --- - Syn_DMA_Cmd_Ack: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - DMA_Cmd_Ack_i <= '0'; - elsif dma_clk'event and dma_clk = '1' then - - if DMA_NextState = dmaST_Load_Param then - DMA_Cmd_Ack_i <= '1'; - else - DMA_Cmd_Ack_i <= '0'; - end if; - end if; - - end process; - - --- ---------------------------------------------------- --- States synchronous: ThereIs_Dex_reg --- - Syn_ThereIs_Dex_reg: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - ThereIs_Dex_reg <= '0'; - ThereIs_Snout_reg <= '0'; - ThereIs_Body_reg <= '0'; - ThereIs_Tail_reg <= '0'; - - elsif dma_clk'event and dma_clk = '1' then - - if DMA_Start = '1' - or State_Is_LoadParam_i = '1' - or State_Is_AwaitDex_i ='1' - then - ThereIs_Dex_reg <= ThereIs_Dex; - ThereIs_Snout_reg <= ThereIs_Snout; - ThereIs_Body_reg <= ThereIs_Body; - ThereIs_Tail_reg <= ThereIs_Tail; - else - ThereIs_Dex_reg <= ThereIs_Dex_reg; - ThereIs_Snout_reg <= ThereIs_Snout_reg; - ThereIs_Body_reg <= ThereIs_Body_reg; - ThereIs_Tail_reg <= ThereIs_Tail_reg; - end if; - end if; - - end process; - - - --- ------------------------------------------------------------- --- Synchronous reg: --- State_Is_LoadParam --- State_Is_Snout --- State_Is_Body --- State_Is_Tail --- State_Is_AwaitDex --- - FSM_State_Is_i: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - State_Is_LoadParam_i <= '0'; - State_Is_Snout_i <= '0'; - State_Is_Body_i <= '0'; - State_Is_Tail_i <= '0'; - State_Is_AwaitDex_i <= '0'; - - elsif dma_clk'event and dma_clk = '1' then - - if DMA_NextState= dmaST_Load_Param then - State_Is_LoadParam_i <= '1'; - else - State_Is_LoadParam_i <= '0'; - end if; - - if DMA_NextState= dmaST_Snout then - State_Is_Snout_i <= '1'; - else - State_Is_Snout_i <= '0'; - end if; - - if DMA_NextState= dmaST_Body then - State_Is_Body_i <= '1'; - else - State_Is_Body_i <= '0'; - end if; - - if DMA_NextState= dmaST_Tail then - State_Is_Tail_i <= '1'; - else - State_Is_Tail_i <= '0'; - end if; - - if DMA_NextState= dmaST_Await_Dex then - State_Is_AwaitDex_i <= '1'; - else - State_Is_AwaitDex_i <= '0'; - end if; - - end if; - end process; - - - -------------------------------------------------------------------- --- Synchronous Output: DMA_Abstract_Buffer_Write --- --- DMA Channel (downstream and upstream) Buffers (128-bit) definition: --- Note: Type not shows in this buffer --- --- 127 ~ xxx : Peripheral address --- xxy ~ 96 : reserved --- 95 : Address increments --- 94 : Valid --- 93 ~ 30 : Host Address --- 29 ~ 27 : BAR number --- 26 ~ 19 : Tag --- --- 18 ~ 17 : Format --- 16 ~ 14 : TC --- 13 : TD --- 12 : EP --- 11 ~ 10 : Attribute --- 9 ~ 0 : Length --- - FSM_DMA_Abstract_Buffer_Write: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - ChBuf_WrEn_i <= '0'; - ChBuf_WrDin_i <= (OTHERS =>'0'); - - elsif dma_clk'event and dma_clk = '1' then - - case DMA_State is - - when dmaST_NextDex => - ChBuf_WrEn_i <= '1'; - - ChBuf_WrDin_i <= (OTHERS=>'0'); -- must be the first argument - ChBuf_WrDin_i(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT) <= DMA_BDA_fsm; - ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= C_ALL_ZEROS(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT); -- any value - ChBuf_WrDin_i(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT) <= Dex_Tag; - ChBuf_WrDin_i(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT) <= DMA_BAR_Number; - - ChBuf_WrDin_i(C_CHBUF_FMT_BIT_TOP) <= C_TLP_HAS_NO_DATA; --C_MRD_HEAD0_WORD(C_TLP_FMT_BIT_TOP); - ChBuf_WrDin_i(C_CHBUF_FMT_BIT_BOT) <= BDA_is_64b_fsm; - ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= C_NEXT_BD_LENGTH(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2); - - ChBuf_WrDin_i(C_CHBUF_QVALID_BIT) <= '1'; - ChBuf_WrDin_i(C_CHBUF_AINC_BIT) <= DMA_Addr_Inc; -- any value - - ChBuf_WrDin_i(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT) <= C_RELAXED_ORDERING & C_NO_SNOOP; - - when dmaST_Snout => - ChBuf_WrEn_i <= '1'; - - ChBuf_WrDin_i <= (OTHERS=>'0'); -- must be the first argument - ChBuf_WrDin_i(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT) <= DMA_HA_Var; - if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then - ChBuf_WrDin_i(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT) <= DMA_PA_Loaded(C_EP_AWIDTH-1 downto 0); - elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_BRAM_SPACE_BAR, C_ENCODE_BAR_NUMBER) then - ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= DMA_PA_Loaded(C_PRAM_AWIDTH-1+2 downto 0); - elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then - ChBuf_WrDin_i(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT) <= DMA_PA_Loaded(C_DDR_IAWIDTH-1 downto 0); - else - ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= C_ALL_ZEROS(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT); - end if; - - ChBuf_WrDin_i(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT) <= Pkt_Tag; - ChBuf_WrDin_i(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT) <= DMA_BAR_Number; - - ChBuf_WrDin_i(C_CHBUF_FMT_BIT_TOP) <= TLP_Has_Payload; - ChBuf_WrDin_i(C_CHBUF_FMT_BIT_BOT) <= TLP_Hdr_is_4DW; - - if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then - ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Snout_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 3) & '0'; - else - ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Snout_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2); - end if; - - ChBuf_WrDin_i(C_CHBUF_QVALID_BIT) <= '1'; - ChBuf_WrDin_i(C_CHBUF_AINC_BIT) <= DMA_Addr_Inc; - - ChBuf_WrDin_i(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT) <= us_MWr_Param_Vec(2 downto 0); - ChBuf_WrDin_i(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT) <= us_MWr_Param_Vec(5 downto 4); -- C_RELAXED_ORDERING & C_NO_SNOOP; - - when dmaST_Body => - ChBuf_WrEn_i <= '1'; - - ChBuf_WrDin_i <= (OTHERS=>'0'); -- must be the first argument - ChBuf_WrDin_i(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT) <= DMA_HA_Var; - if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then - ChBuf_WrDin_i(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT) <= DMA_PA_Var(C_EP_AWIDTH-1 downto 0); - elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_BRAM_SPACE_BAR, C_ENCODE_BAR_NUMBER) then - ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= DMA_PA_Var(C_PRAM_AWIDTH-1+2 downto 0); - elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then - ChBuf_WrDin_i(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT) <= DMA_PA_Var(C_DDR_IAWIDTH-1 downto 0); - else - ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= C_ALL_ZEROS(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT); - end if; - - ChBuf_WrDin_i(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT) <= Pkt_Tag; - ChBuf_WrDin_i(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT) <= DMA_BAR_Number; - - ChBuf_WrDin_i(C_CHBUF_FMT_BIT_TOP) <= TLP_Has_Payload; - ChBuf_WrDin_i(C_CHBUF_FMT_BIT_BOT) <= TLP_Hdr_is_4DW; - - if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then - ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Body_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 3) & '0'; - else - ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Body_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2); - end if; - - ChBuf_WrDin_i(C_CHBUF_QVALID_BIT) <= '1'; - ChBuf_WrDin_i(C_CHBUF_AINC_BIT) <= DMA_Addr_Inc; - - ChBuf_WrDin_i(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT) <= us_MWr_Param_Vec(2 downto 0); - ChBuf_WrDin_i(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT) <= us_MWr_Param_Vec(5 downto 4); -- C_RELAXED_ORDERING & C_NO_SNOOP; - - - when dmaST_Tail => - ChBuf_WrEn_i <= '1'; - - ChBuf_WrDin_i <= (OTHERS=>'0'); -- must be the first argument - ChBuf_WrDin_i(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT) <= DMA_HA_Var; - if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then - ChBuf_WrDin_i(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT) <= DMA_PA_Var(C_EP_AWIDTH-1 downto 0); - elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_BRAM_SPACE_BAR, C_ENCODE_BAR_NUMBER) then - ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= DMA_PA_Var(C_PRAM_AWIDTH-1+2 downto 0); - elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then - ChBuf_WrDin_i(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT) <= DMA_PA_Var(C_DDR_IAWIDTH-1 downto 0); - else - ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= C_ALL_ZEROS(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT); - end if; - - ChBuf_WrDin_i(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT) <= Pkt_Tag; - ChBuf_WrDin_i(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT) <= DMA_BAR_Number; - - ChBuf_WrDin_i(C_CHBUF_FMT_BIT_TOP) <= TLP_Has_Payload; - ChBuf_WrDin_i(C_CHBUF_FMT_BIT_BOT) <= TLP_Hdr_is_4DW; - - if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then - ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Tail_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 3) & '0'; - else - ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Tail_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2); - end if; - - ChBuf_WrDin_i(C_CHBUF_QVALID_BIT) <= '1'; - ChBuf_WrDin_i(C_CHBUF_AINC_BIT) <= DMA_Addr_Inc; - - ChBuf_WrDin_i(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT) <= us_MWr_Param_Vec(2 downto 0); - ChBuf_WrDin_i(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT) <= us_MWr_Param_Vec(5 downto 4); -- C_RELAXED_ORDERING & C_NO_SNOOP; - - - when OTHERS => - ChBuf_WrEn_i <= '0'; - ChBuf_WrDin_i <= ChBuf_WrDin_i; - - end case; - - end if; - end process; - - - --- ---------------------------------------------- --- Synchronous Latch: BDA_nAligned_i --- : Capture design defect --- - Latch_BDA_nAligned: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - BDA_nAligned_i <= '0'; - - elsif dma_clk'event and dma_clk = '1' then - -- If the lowest 2 bits are not zero, error bit set accordingly, - -- because the logic can not deal with this situation. - -- can be removed. - - if DMA_BDA_fsm(1) ='1' or DMA_BDA_fsm(0) ='1' then - BDA_nAligned_i <= '1'; - else - BDA_nAligned_i <= BDA_nAligned_i; - end if; - - end if; - end process; - - --- States synchronous: BusyDone_States - Syn_BusyDone_States: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - BusyDone_State <= FSM_Idle; - elsif dma_clk'event and dma_clk = '1' then - BusyDone_State <= BusyDone_NextState; - end if; - - end process; - - --- Next States: BusyDone_State - Comb_BusyDone_State: - process ( - BusyDone_State - , DMA_State --- , Done_Condition_1 - , Done_Condition_2 - , Done_Condition_3 - , Done_Condition_4 - , Done_Condition_5 - ) - begin - case BusyDone_State is - - when FSM_Idle => - if DMA_State = dmaST_Load_Param then - BusyDone_NextState <= FSM_Busy1; - else - BusyDone_NextState <= FSM_Idle; - end if; - - when FSM_Busy1 => - if DMA_State = dmaST_Init --- Done_Condition_1='1' - then - BusyDone_NextState <= FSM_Busy2; - else - BusyDone_NextState <= FSM_Busy1; - end if; - - when FSM_Busy2 => - if Done_Condition_2='1' - then - BusyDone_NextState <= FSM_Busy3; - else - BusyDone_NextState <= FSM_Busy2; - end if; - - when FSM_Busy3 => - if Done_Condition_3='1' - then - BusyDone_NextState <= FSM_Busy4; - else - BusyDone_NextState <= FSM_Busy3; - end if; - - when FSM_Busy4 => - if Done_Condition_4='1' - then - BusyDone_NextState <= FSM_Busy5; - else - BusyDone_NextState <= FSM_Busy4; - end if; - - when FSM_Busy5 => - if Done_Condition_5='1' - then - BusyDone_NextState <= FSM_Done; - else - BusyDone_NextState <= FSM_Busy5; - end if; - - when FSM_Done => - if DMA_State = dmaST_Init then - BusyDone_NextState <= FSM_Idle; - else - BusyDone_NextState <= FSM_Done; - end if; - - when Others => - BusyDone_NextState <= FSM_Idle; - - end case; -- BusyDone_State - - end process; - - - --- Synchronous Output: DMA_Busy_i - FSM_Output_DMA_Busy: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - DMA_Busy_i <= '0'; - elsif dma_clk'event and dma_clk = '1' then - - case BusyDone_State is - - when FSM_Idle => - DMA_Busy_i <= '0'; - - when FSM_Busy1 => - DMA_Busy_i <= '1'; - - when FSM_Busy2 => - DMA_Busy_i <= '1'; - - when FSM_Busy3 => - DMA_Busy_i <= '1'; - - when FSM_Busy4 => - DMA_Busy_i <= '1'; - - when FSM_Busy5 => - DMA_Busy_i <= '1'; - - when FSM_Done => - DMA_Busy_i <= '0'; - - when Others => - DMA_Busy_i <= '0'; - - end case; -- BusyDone_State - - end if; - end process; - - --- Synchronous Output: DMA_Done_i - FSM_Output_DMA_Done: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - DMA_Done_i <= '0'; - elsif dma_clk'event and dma_clk = '1' then - - case BusyDone_State is - --- when FSM_Busy1 => --- DMA_Done_i <= '0'; --- --- when FSM_Busy2 => --- DMA_Done_i <= '0'; --- --- when FSM_Busy3 => --- DMA_Done_i <= '0'; --- - when FSM_Done => - DMA_Done_i <= '1'; - - when Others => - DMA_Done_i <= DMA_Done_i; - - end case; -- BusyDone_State - - end if; - end process; - - - --- ---------------------------------------------- --- Time out counter --- Synchronous Output: Counter_DMA_TimeOut_i - FSM_Counter_DMA_TimeOut_i: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - cnt_DMA_TO <= (Others=>'0'); - Tout_Lo_Carry <= '0'; - DMA_TimeOut_State <= toutSt_Idle; - - elsif dma_clk'event and dma_clk = '1' then - - case DMA_TimeOut_State is - - when toutSt_Idle => - cnt_DMA_TO <= (Others=>'0'); - Tout_Lo_Carry <= '0'; - if DMA_Start='1' then - DMA_TimeOut_State <= toutSt_CountUp; - else - DMA_TimeOut_State <= toutSt_Idle; - end if; - - when toutSt_CountUp => - if DMA_Done_i='1' or DMA_Start='1' then - cnt_DMA_TO <= (Others=>'0'); - Tout_Lo_Carry <= '0'; - DMA_TimeOut_State <= toutSt_Idle; - elsif DMA_Stop='1' then - cnt_DMA_TO <= cnt_DMA_TO; - Tout_Lo_Carry <= Tout_Lo_Carry; - DMA_TimeOut_State <= toutSt_Pause; - elsif ChBuf_ValidRd='1' then - cnt_DMA_TO <= (Others=>'0'); - Tout_Lo_Carry <= '0'; - DMA_TimeOut_State <= toutSt_CountUp; - else - cnt_DMA_TO(CBIT_TOUT_CARRY-1 downto 0) <= cnt_DMA_TO(CBIT_TOUT_CARRY-1 downto 0) + '1'; - if cnt_DMA_TO(CBIT_TOUT_CARRY-1 downto 0)=C_ALL_ONES(CBIT_TOUT_CARRY-1 downto 0) then - Tout_Lo_Carry <= '1'; - else - Tout_Lo_Carry <= '0'; - end if; - if Tout_Lo_Carry='1' then - cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_TOUT_CARRY) <= cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_TOUT_CARRY) + '1'; - else - cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_TOUT_CARRY) <= cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_TOUT_CARRY); - end if; - DMA_TimeOut_State <= toutSt_CountUp; - end if; - - when toutSt_Pause => - cnt_DMA_TO <= cnt_DMA_TO; - Tout_Lo_Carry <= Tout_Lo_Carry; - if DMA_Start='1' then - DMA_TimeOut_State <= toutSt_CountUp; - elsif DMA_Done_i='1' then - DMA_TimeOut_State <= toutSt_Idle; - else - DMA_TimeOut_State <= toutSt_Pause; - end if; - - when Others => - cnt_DMA_TO <= cnt_DMA_TO; - Tout_Lo_Carry <= Tout_Lo_Carry; - DMA_TimeOut_State <= toutSt_Idle; - - end case; - - - --- case DMA_State is --- --- when dmaST_Init => --- cnt_DMA_TO <= (Others=>'0'); --- Tout_Lo_Carry <= '0'; --- --- when dmaST_Snout => --- cnt_DMA_TO <= (Others=>'0'); --- Tout_Lo_Carry <= '0'; --- --- --- when Others => --- cnt_DMA_TO(CBIT_CARRY-1 downto 0) <= cnt_DMA_TO(CBIT_CARRY-1 downto 0) + '1'; --- --- if cnt_DMA_TO(CBIT_CARRY-1 downto 0)=C_ALL_ONES(CBIT_CARRY-1 downto 0) then --- Tout_Lo_Carry <= '1'; --- else --- Tout_Lo_Carry <= '0'; --- end if; --- --- if Tout_Lo_Carry='1' then --- cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_CARRY) <= cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_CARRY) + '1'; --- else --- cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_CARRY) <= cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_CARRY); --- end if; --- --- end case; - - end if; - end process; - - --- ---------------------------------------------- --- Time out state bit --- Synchronous Output: DMA_TimeOut_i - FSM_DMA_TimeOut: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - DMA_TimeOut_i <= '0'; - elsif dma_clk'event and dma_clk = '1' then - -- Capture the time-out trigger --- if cnt_DMA_TO(CBIT_TOUT_BOT downto 0) = C_TIME_OUT_VALUE then - if cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_TOUT_BOT) = C_TIME_OUT_VALUE then - DMA_TimeOut_i <= '1'; - else - DMA_TimeOut_i <= DMA_TimeOut_i; - end if; - - end if; - end process; - - -end architecture Behavioral; Index: branches/Virtex6/ML605/class_ctl.vhd =================================================================== --- branches/Virtex6/ML605/class_ctl.vhd (revision 9) +++ branches/Virtex6/ML605/class_ctl.vhd (nonexistent) @@ -1,525 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: ziti --- Engineer: wgao --- --- Create Date: 17:01:32 19 Jun 2009 --- Design Name: --- Module Name: class_ctl - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.abb64Package.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity class_ctl is --- Generic ( --- C_PRO_DAQ_WIDTH : integer := 16 ; --- C_PRO_DLM_WIDTH : integer := 4 ; --- C_PRO_CTL_WIDTH : integer := 16 --- ); - Port ( - - -- CTL Tx - ctrl2send_start : OUT std_logic; - ctrl2send_end : OUT std_logic; - ctrl2send : OUT std_logic_vector(16-1 downto 0); - ctrl2send_stop : IN std_logic; - - -- CTL Rx - ctrl_rec_start : IN std_logic; - ctrl_rec_end : IN std_logic; - ctrl_rec : IN std_logic_vector(16-1 downto 0); - ctrl_rec_stop : OUT std_logic; - - -- Common signals - link_active : IN std_logic_vector(2-1 downto 0); - link_tx_clk : IN std_logic; - link_rx_clk : IN std_logic; - - -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - - -- Fabric side: CTL Rx - ctl_rv : IN std_logic; - ctl_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0); - ctl_rstop : OUT std_logic; - - -- Fabric side: CTL Tx - ctl_ttake : IN std_logic; - ctl_tv : OUT std_logic; - ctl_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0); - ctl_tstop : IN std_logic; - - -- Interrupter trigger - CTL_irq : OUT std_logic; - ctl_status : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0); - - -- Fabric side: Common signals - trn_clk : IN std_logic; - protocol_rst : IN std_logic - - ); -end entity class_ctl; - - -architecture Behavioral of class_ctl is - - -- Standard synchronous FIFO - component sfifo_256x36 - port ( - wr_en : IN std_logic; - din : IN std_logic_VECTOR(36-1 downto 0); - prog_full : OUT std_logic; - full : OUT std_logic; - - rd_en : IN std_logic; - dout : OUT std_logic_VECTOR(36-1 downto 0); - empty : OUT std_logic; - prog_empty: OUT std_logic; - - clk : IN std_logic; - rst : IN std_logic - ); - end component; - - -- Standard asynchronous FIFO - component v6_afifo_256x36 - port ( - wr_clk : IN std_logic; - wr_en : IN std_logic; - din : IN std_logic_VECTOR(36-1 downto 0); - prog_full : OUT std_logic; - full : OUT std_logic; - - rd_clk : IN std_logic; - rd_en : IN std_logic; - dout : OUT std_logic_VECTOR(36-1 downto 0); - empty : OUT std_logic; - prog_empty: OUT std_logic; - - rst : IN std_logic - ); - end component; - - -- FWFT synchronous FIFO - component sfifo_256x36c_fwft - port ( - wr_en : IN std_logic; - din : IN std_logic_VECTOR(36-1 downto 0); - prog_full : OUT std_logic; - full : OUT std_logic; - - rd_en : IN std_logic; - dout : OUT std_logic_VECTOR(36-1 downto 0); - empty : OUT std_logic; - prog_empty: OUT std_logic; - - data_count: OUT std_logic_vector (9-1 downto 0); - - clk : IN std_logic; - rst : IN std_logic - ); - end component; - - -- FWFT asynchronous FIFO - component v6_afifo_256x36c_fwft - port ( - wr_clk : IN std_logic; - wr_en : IN std_logic; - din : IN std_logic_VECTOR(36-1 downto 0); - prog_full : OUT std_logic; - full : OUT std_logic; - - rd_clk : IN std_logic; - rd_en : IN std_logic; - dout : OUT std_logic_VECTOR(36-1 downto 0); - empty : OUT std_logic; - prog_empty : OUT std_logic; - - rd_data_count : OUT std_logic_vector (9-1 downto 0); - - rst : IN std_logic - ); - end component; - - -- Packet counter - component v6_pkt_counter_1024 - port ( - wr_clk : IN std_logic; - wr_en : IN std_logic; - din : IN std_logic_VECTOR(0 downto 0); - prog_full : OUT std_logic; - full : OUT std_logic; - - rd_clk : IN std_logic; - rd_en : IN std_logic; - dout : OUT std_logic_VECTOR(0 downto 0); - empty : OUT std_logic; - prog_empty : OUT std_logic; - - rst : IN std_logic - ); - end component; - - -- Interrupter trigger - signal ctl_reset : std_logic; - signal CTL_irq_i : std_logic; - signal ctl_status_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0); - - -- Fabric side: CTL Tx - signal ctl_tv_i : std_logic; - signal ctl_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0); - signal ctl_rstop_i : std_logic; - - -- protocol side: CTL Send - signal ctrl2send_start_i : std_logic; - signal ctrl2send_end_i : std_logic; - signal ctrl2send_i : std_logic_vector(16-1 downto 0); - signal ctrl_rec_stop_i : std_logic; - - signal ctl_down_buf_rden : std_logic; - signal ctl_down_buf_dout : std_logic_vector(36-1 downto 0); - signal ctl_down_buf_empty : std_logic; - signal ctl_down_buf_afull : std_logic; - - signal ctl_rd_padded : std_logic_vector(36-1 downto 0); - signal ctl_down_buf_rd_valid : std_logic :='0'; - signal ctl_down_buf_read_gap : std_logic; - signal ctl_down_buf_eop : std_logic; - signal ctl_down_buf_eop_r1 : std_logic :='0'; - - signal ctrl2send_stop_r1 : std_logic :='0'; - signal ctl_down_buf_frame_rd : std_logic :='0'; - signal ctl_down_buf_stop_read : std_logic; - signal pc_ctl_down_push : std_logic; - signal pc_ctl_down_pop : std_logic; - signal no_pkts_in_ctl_down_buf : std_logic; - signal no_pkts_in_ctl_down_buf_r1: std_logic :='0'; - - signal ctl_up_buf_wren : std_logic; - signal ctl_up_buf_din : std_logic_vector(36-1 downto 0); - signal ctl_up_buf_din_b1 : std_logic_vector(36-1 downto 0); - signal ctl_up_buf_afull : std_logic; - - signal ctl_up_buf_re : std_logic; - signal ctl_up_buf_dout : std_logic_vector(36-1 downto 0); - signal ctl_up_buf_empty : std_logic; - signal ctl_up_buf_dc_wire : std_logic_vector (9-1 downto 0); - signal ctl_up_buf_dc_r1 : std_logic_vector (9-1 downto 0); - signal ctl_up_buf_dc_plus_r1 : std_logic_vector (9-1 downto 0); - signal ctl_up_buf_dc_i : std_logic_vector (9-1 downto 0); - signal ctl_up_is_writing : std_logic; - signal ctl_up_is_writing_r1 : std_logic; - - signal ctl_up_buf_rd_valid : std_logic; - signal pc_ctl_up_push : std_logic; - signal pc_ctl_up_pop : std_logic; - signal no_pkts_in_ctl_up_buf : std_logic; - signal no_pkts_in_ctl_up_buf_r1 : std_logic; - -begin - - - -- Fabric side: CTL Tx - ctl_tv <= ctl_tv_i ; - ctl_td <= ctl_td_i ; - - ctl_rstop <= ctl_rstop_i ; - - - -- protocol side: CTL Send - ctrl2send_start <= ctrl2send_start_i ; - ctrl2send_end <= ctrl2send_end_i ; - ctrl2send <= ctrl2send_i ; - - ctrl_rec_stop <= ctrl_rec_stop_i ; - ctrl_rec_stop_i <= ctl_up_buf_afull; - - ctl_rstop_i <= ctl_down_buf_afull; - - ctl_status <= ctl_status_i ; - - CTL_irq <= CTL_irq_i ; - CTL_irq_i <= not ctl_up_buf_empty ; - - ctl_status_i <= X"000" & '0' & '0' & ctl_down_buf_afull & ctl_up_buf_empty - & X"0" & '0' & '0' & ctl_up_buf_dc_i & no_pkts_in_ctl_up_buf_r1; - - - -- ------------------------------------------------------------------------------ - -- - -- ------------------------------------------------------------------------------ - Synch_Local_Reset: - process (trn_clk ) - begin - if trn_clk'event and trn_clk = '1' then - ctl_reset <= protocol_rst; - end if; - end process; - - -- ------------------------------------------------------------------------------ - -- CTL buffer from the host - -- ------------------------------------------------------------------------------ - ctl_buf_downstream: - v6_afifo_256x36 - port map ( - wr_clk => trn_clk , -- IN std_logic; - wr_en => ctl_rv , -- IN std_logic; - din => ctl_rd_padded , -- IN std_logic_VECTOR(35 downto 0); - prog_full => ctl_down_buf_afull , -- ctl_rstop_i , -- OUT std_logic; - full => open , -- OUT std_logic; - - rd_clk => link_tx_clk , -- IN std_logic; - rd_en => ctl_down_buf_rden , -- IN std_logic; - dout => ctl_down_buf_dout , -- OUT std_logic_VECTOR(35 downto 0); - prog_empty => open , -- OUT std_logic; - empty => ctl_down_buf_empty , -- OUT std_logic; - - rst => ctl_reset -- IN std_logic - ); - - ctl_rd_padded <= "0000" & ctl_rd; - ctl_down_buf_eop <= ctl_down_buf_dout(16); - ctl_down_buf_read_gap <= ctl_down_buf_eop and not ctl_down_buf_eop_r1; - ctl_down_buf_rden <= ctl_down_buf_frame_rd and not ctl_down_buf_read_gap; - - - -- Packet counter: ABB -> ROC - pc_ctl_buf_downstream: - v6_pkt_counter_1024 - port map ( - wr_clk => trn_clk , -- IN std_logic; - wr_en => pc_ctl_down_push , -- IN std_logic; - din => "1" , -- IN std_logic_VECTOR(0 downto 0); - prog_full => open , -- OUT std_logic; - full => open , -- OUT std_logic; - - rd_clk => link_tx_clk , -- IN std_logic; - rd_en => pc_ctl_down_pop , -- IN std_logic; - dout => open , -- OUT std_logic_VECTOR(0 downto 0); - empty => no_pkts_in_ctl_down_buf , -- OUT std_logic; - prog_empty => open , -- OUT std_logic; - - rst => ctl_reset -- IN std_logic - ); - - - Syn_pc_ctl_down_push: - process (trn_clk, ctl_reset ) - begin - if ctl_reset = '1' then - pc_ctl_down_push <= '0'; - elsif trn_clk'event and trn_clk = '1' then - pc_ctl_down_push <= ctl_rv and ctl_rd(16); - end if; - end process; - - Syn_pc_ctl_down_pop: - process (link_tx_clk, ctl_reset ) - begin - if ctl_reset = '1' then - pc_ctl_down_pop <= '0'; - elsif link_tx_clk'event and link_tx_clk = '1' then - pc_ctl_down_pop <= ctl_down_buf_rd_valid and ctl_down_buf_eop; - end if; - end process; - - --------------------------------------------------- - -- Downstream CTL buffer read and packets number - -- bit[17] : sof - -- bit[16] : eof - -- - Delay_CTL_downstream_frame: - process (link_tx_clk ) - begin - if link_tx_clk'event and link_tx_clk = '1' then - - no_pkts_in_ctl_down_buf_r1 <= no_pkts_in_ctl_down_buf; - ctrl2send_stop_r1 <= ctrl2send_stop; - ctl_down_buf_rd_valid <= ctl_down_buf_rden and not ctl_down_buf_empty; - ctl_down_buf_eop_r1 <= ctl_down_buf_eop; - ctl_down_buf_frame_rd <= not no_pkts_in_ctl_down_buf_r1 - and not ctl_down_buf_read_gap - and not ctl_down_buf_stop_read - ; - end if; - end process; - - -- - Syn_rden_CTL_downstream_buf: - process (link_tx_clk, ctl_reset ) - begin - if ctl_reset = '1' then - ctl_down_buf_stop_read <= '0'; - elsif link_tx_clk'event and link_tx_clk = '1' then - if ctl_down_buf_read_gap='1' and ctrl2send_stop_r1='1' then - ctl_down_buf_stop_read <= '1'; - elsif ctl_down_buf_stop_read='0' and ctrl2send_stop_r1='1' then - ctl_down_buf_stop_read <= '0'; - else - ctl_down_buf_stop_read <= ctrl2send_stop_r1; - end if; - end if; - end process; - - ctrl2send_start_i <= ctl_down_buf_dout(17); - ctrl2send_end_i <= ctl_down_buf_eop and not ctl_down_buf_eop_r1; - ctrl2send_i <= ctl_down_buf_dout(16-1 downto 0); - - - -- ------------------------------------------------------------------------------ - -- CTL buffer to the host - -- ------------------------------------------------------------------------------ - ctl_buf_upstream: - v6_afifo_256x36c_fwft - port map ( - wr_clk => link_rx_clk , -- IN std_logic; - wr_en => ctl_up_buf_wren , -- IN std_logic; - din => ctl_up_buf_din , -- IN std_logic_VECTOR(35 downto 0); - prog_full => ctl_up_buf_afull , -- ctrl_rec_stop_i , -- OUT std_logic; - full => open , -- OUT std_logic; - - rd_clk => trn_clk , -- IN std_logic; - rd_en => ctl_up_buf_re , -- IN std_logic; - dout => ctl_up_buf_dout , -- OUT std_logic_VECTOR(35 downto 0); - prog_empty => open , -- OUT std_logic; - empty => ctl_up_buf_empty , -- OUT std_logic; - - rd_data_count => ctl_up_buf_dc_wire , -- OUT std_logic_vector (9-1 downto 0 ); - - rst => ctl_reset -- IN std_logic - ); - - ctl_up_buf_re <= ctl_ttake; - ctl_up_buf_rd_valid <= ctl_up_buf_re and not ctl_up_buf_empty; - - - -- Special data count for FWFT FIFO - Syn_up_fifo_fwft_dc: - process (trn_clk, ctl_reset ) - begin - if ctl_reset = '1' then - ctl_up_buf_dc_i <= (OTHERS=>'0'); - ctl_up_buf_dc_r1 <= (OTHERS=>'0'); - ctl_up_buf_dc_plus_r1 <= (OTHERS=>'0'); - elsif trn_clk'event and trn_clk = '1' then - ctl_up_buf_dc_r1 <= ctl_up_buf_dc_wire; - ctl_up_buf_dc_plus_r1 <= ctl_up_buf_dc_wire + "10"; - if ctl_up_buf_empty='1' then - ctl_up_buf_dc_i <= ctl_up_buf_dc_r1; - else - ctl_up_buf_dc_i <= ctl_up_buf_dc_plus_r1; - end if; - end if; - end process; - - -- Packet counter: ROC -> ABB - pc_ctl_buf_upstream: - v6_pkt_counter_1024 - port map ( - wr_clk => link_rx_clk , -- IN std_logic; - wr_en => pc_ctl_up_push , -- IN std_logic; - din => "1" , -- IN std_logic_VECTOR(0 downto 0); - prog_full => open , -- OUT std_logic; - full => open , -- OUT std_logic; - - rd_clk => trn_clk , -- IN std_logic; - rd_en => pc_ctl_up_pop , -- IN std_logic; - dout => open , -- OUT std_logic_VECTOR(0 downto 0); - empty => no_pkts_in_ctl_up_buf , -- OUT std_logic; - prog_empty => open , -- OUT std_logic; - - rst => ctl_reset -- IN std_logic - ); - - - Syn_pc_ctl_up_push: - process (link_rx_clk, ctl_reset ) - begin - if ctl_reset = '1' then - pc_ctl_up_push <= '0'; - elsif link_rx_clk'event and link_rx_clk = '1' then - pc_ctl_up_push <= ctl_up_buf_wren and ctl_up_buf_din(16); - end if; - end process; - - Syn_pc_ctl_up_pop: - process (trn_clk, ctl_reset ) - begin - if ctl_reset = '1' then - pc_ctl_up_pop <= '0'; - no_pkts_in_ctl_up_buf_r1 <= '1'; - elsif trn_clk'event and trn_clk = '1' then - pc_ctl_up_pop <= ctl_up_buf_rd_valid and ctl_up_buf_dout(16); - no_pkts_in_ctl_up_buf_r1 <= no_pkts_in_ctl_up_buf; - end if; - end process; - - -- CTL direction: upstream - -- protocol side - Transfer_CTL_upstream_protocol: - process (link_rx_clk, ctl_reset ) - begin - if ctl_reset = '1' then - ctl_up_buf_din_b1 <= (OTHERS=>'0'); - ctl_up_buf_din <= (OTHERS=>'0'); - ctl_up_buf_wren <= '0'; - ctl_up_is_writing <= '0'; - ctl_up_is_writing_r1 <= '0'; - - elsif link_rx_clk'event and link_rx_clk = '1' then - ctl_up_buf_din_b1 <= X"0000" & "00" & ctrl_rec_start & ctrl_rec_end & ctrl_rec; - ctl_up_buf_din <= ctl_up_buf_din_b1; - ctl_up_buf_wren <= (ctl_up_is_writing or ctl_up_is_writing_r1); - if ctrl_rec_start='1' and ctrl_rec_end='1' then - ctl_up_is_writing <= '0'; - ctl_up_is_writing_r1 <= '1'; - elsif ctrl_rec_start='1' then - ctl_up_is_writing <= '1'; - ctl_up_is_writing_r1 <= ctl_up_is_writing; - elsif ctrl_rec_end='1' then - ctl_up_is_writing <= '0'; - ctl_up_is_writing_r1 <= ctl_up_is_writing; - else - ctl_up_is_writing <= ctl_up_is_writing; - ctl_up_is_writing_r1 <= ctl_up_is_writing; - end if; - - end if; - end process; - - - -- CTL direction: upstream - -- fabric side - Transfer_CTL_upstream_fabric: - process (trn_clk, ctl_reset ) - begin - if ctl_reset = '1' then - ctl_tv_i <= '0'; - ctl_td_i <= (OTHERS=>'0'); - elsif trn_clk'event and trn_clk = '1' then - ctl_tv_i <= not ctl_up_buf_empty; - ctl_td_i <= ctl_up_buf_dout(C_DBUS_WIDTH/2-1 downto 0); - end if; - end process; - - -end architecture Behavioral; Index: branches/Virtex6/ML605/Registers.vhd =================================================================== --- branches/Virtex6/ML605/Registers.vhd (revision 9) +++ branches/Virtex6/ML605/Registers.vhd (nonexistent) @@ -1,3071 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Design Name: --- Module Name: Regs_Group - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- --- Revision 1.10 - Readability improved by FOR-LOOP used 19.03.2007 --- --- Revision 1.00 - File Created 06.02.2007 --- --- Additional Comments: --- ----------------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - -library work; -use work.abb64Package.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. -library UNISIM; -use UNISIM.VComponents.all; - -entity Regs_Group is - port ( - - -- DCB protocol interface - protocol_link_act : IN std_logic_vector(2-1 downto 0); - protocol_rst : OUT std_logic; - - -- Fabric side: CTL Rx - ctl_rv : OUT std_logic; - ctl_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0); - - -- Fabric side: CTL Tx - ctl_ttake : OUT std_logic; - ctl_tv : IN std_logic; - ctl_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0); - ctl_tstop : OUT std_logic; - - ctl_reset : OUT std_logic; - ctl_status : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0); - - -- Fabric side: DLM Rx - dlm_tv : OUT std_logic; - dlm_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0); - - -- Fabric side: DLM Tx - dlm_rv : IN std_logic; - dlm_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0); - - -- Event Buffer status + reset - eb_FIFO_Status : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); - eb_FIFO_Rst : OUT std_logic; - eb_FIFO_ow : IN std_logic; - - -- Write interface - Regs_WrEnA : IN std_logic; - Regs_WrMaskA : IN std_logic_vector(2-1 downto 0); - Regs_WrAddrA : IN std_logic_vector(C_EP_AWIDTH-1 downto 0); - Regs_WrDinA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - Regs_WrEnB : IN std_logic; - Regs_WrMaskB : IN std_logic_vector(2-1 downto 0); - Regs_WrAddrB : IN std_logic_vector(C_EP_AWIDTH-1 downto 0); - Regs_WrDinB : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - -- Register Read interface - Regs_RdAddr : IN std_logic_vector(C_EP_AWIDTH-1 downto 0); - Regs_RdQout : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - -- Downstream DMA transferred bytes count up - ds_DMA_Bytes_Add : IN std_logic; - ds_DMA_Bytes : IN std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0); - - -- Registers to/from Downstream Engine - DMA_ds_PA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0); - DMA_ds_HA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0); - DMA_ds_BDA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0); - DMA_ds_Length : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0); - DMA_ds_Control : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0); - dsDMA_BDA_eq_Null : OUT std_logic; -- obsolete - DMA_ds_Status : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); - DMA_ds_Done : IN std_logic; - DMA_ds_Tout : IN std_logic; - - -- Calculation in advance, for better timing - dsHA_is_64b : OUT std_logic; - dsBDA_is_64b : OUT std_logic; - - -- Calculation in advance, for better timing - dsLeng_Hi19b_True : OUT std_logic; - dsLeng_Lo7b_True : OUT std_logic; - - -- Downstream Control Signals - dsDMA_Start : OUT std_logic; - dsDMA_Stop : OUT std_logic; - dsDMA_Start2 : OUT std_logic; - dsDMA_Stop2 : OUT std_logic; - dsDMA_Channel_Rst : OUT std_logic; - dsDMA_Cmd_Ack : IN std_logic; - - - -- Upstream DMA transferred bytes count up - us_DMA_Bytes_Add : IN std_logic; - us_DMA_Bytes : IN std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0); - - -- Registers to/from Upstream Engine - DMA_us_PA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0); - DMA_us_HA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0); - DMA_us_BDA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0); - DMA_us_Length : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0); - DMA_us_Control : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0); - usDMA_BDA_eq_Null : OUT std_logic; -- obsolete - us_MWr_Param_Vec : OUT std_logic_vector(6-1 downto 0); - DMA_us_Status : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); - DMA_us_Done : IN std_logic; - DMA_us_Tout : IN std_logic; - - -- Calculation in advance, for better timing - usHA_is_64b : OUT std_logic; - usBDA_is_64b : OUT std_logic; - - -- Calculation in advance, for better timing - usLeng_Hi19b_True : OUT std_logic; - usLeng_Lo7b_True : OUT std_logic; - - -- Upstream Control Signals - usDMA_Start : OUT std_logic; - usDMA_Stop : OUT std_logic; - usDMA_Start2 : OUT std_logic; - usDMA_Stop2 : OUT std_logic; - usDMA_Channel_Rst : OUT std_logic; - usDMA_Cmd_Ack : IN std_logic; - - -- MRd Channel Reset - MRd_Channel_Rst : OUT std_logic; - - -- Tx module reset - Tx_Reset : OUT std_logic; - - -- to Interrupts Module - Sys_IRQ : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0); - DAQ_irq : IN std_logic; - CTL_irq : IN std_logic; - DLM_irq : IN std_logic; - - -- System error and info - Tx_TimeOut : IN std_logic; - Tx_eb_TimeOut : IN std_logic; - Msg_Routing : OUT std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0); - pcie_link_width : IN std_logic_vector(CINT_BIT_LWIDTH_IN_GSR_TOP-CINT_BIT_LWIDTH_IN_GSR_BOT downto 0); - cfg_dcommand : IN std_logic_vector(16-1 downto 0); - - -- Interrupt Generation Signals - IG_Reset : OUT std_logic; - IG_Host_Clear : OUT std_logic; - IG_Latency : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0); - IG_Num_Assert : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); - IG_Num_Deassert : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); - IG_Asserting : IN std_logic; - - -- Data generator control - DG_is_Running : IN std_logic; - DG_Reset : OUT std_logic; - DG_Mask : OUT std_logic; - - -- Clock and reset - trn_clk : IN std_logic; - trn_lnk_up_n : IN std_logic; - trn_reset_n : IN std_logic - - ); -end Regs_Group; - - -architecture Behavioral of Regs_Group is - - type icapStates is ( icapST_Reset - , icapST_Idle - , icapST_Access - , icapST_Abort - ); - - -- State variables of ICAP - signal FSM_icap : icapStates; - - - ---------------------------------------------------------------------------- - ---------------------------------------------------------------------------- - signal Regs_WrDin_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal Regs_WrAddr_i : std_logic_vector(C_EP_AWIDTH-1 downto 0); - signal Regs_WrMask_i : std_logic_vector(2-1 downto 0); - - ------ Delay signals - signal Regs_WrEn_r1 : std_logic; - signal Regs_WrAddr_r1 : std_logic_vector(C_EP_AWIDTH-1 downto 0); - signal Regs_WrMask_r1 : std_logic_vector(2-1 downto 0); - signal Regs_WrDin_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal Regs_WrEn_r2 : std_logic; - signal Regs_WrDin_r2 : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal Regs_Wr_dma_V_hi_r2 : std_logic; - signal Regs_Wr_dma_nV_hi_r2 : std_logic; - signal Regs_Wr_dma_V_nE_hi_r2 : std_logic; - signal Regs_Wr_dma_V_lo_r2 : std_logic; - signal Regs_Wr_dma_nV_lo_r2 : std_logic; - signal Regs_Wr_dma_V_nE_lo_r2 : std_logic; - signal WrDin_r1_not_Zero_Hi : std_logic_vector(4-1 downto 0); - signal WrDin_r2_not_Zero_Hi : std_logic; - signal WrDin_r1_not_Zero_Lo : std_logic_vector(4-1 downto 0); - signal WrDin_r2_not_Zero_Lo : std_logic; - - -- Calculation in advance, just for better timing - signal Regs_WrDin_Hi19b_True_hq_r2 : std_logic; - signal Regs_WrDin_Lo7b_True_hq_r2 : std_logic; - signal Regs_WrDin_Hi19b_True_lq_r2 : std_logic; - signal Regs_WrDin_Lo7b_True_lq_r2 : std_logic; - - signal Regs_WrEnA_r1 : std_logic; - signal Regs_WrEnB_r1 : std_logic; - signal Regs_WrEnA_r2 : std_logic; - signal Regs_WrEnB_r2 : std_logic; - - -- Register write mux signals - signal Reg_WrMuxer_Hi : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0); - signal Reg_WrMuxer_Lo : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0); - - - -- Signals for Tx reading - signal Regs_RdAddr_i : std_logic_vector(C_EP_AWIDTH-1 downto 0); - signal Regs_RdQout_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - -- Register read mux signals - signal Reg_RdMuxer_Hi : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0); - signal Reg_RdMuxer_Lo : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0); - - -- Optical Link status - signal Opto_Link_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal Opto_Link_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal Opto_Link_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - -- Event Buffer - signal eb_FIFO_Status_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal eb_FIFO_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal eb_FIFO_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal eb_FIFO_Rst_i : std_logic; - signal eb_FIFO_Rst_b1 : std_logic; - signal eb_FIFO_Rst_b2 : std_logic; - signal eb_FIFO_Rst_b3 : std_logic; - signal eb_FIFO_OverWritten : std_logic; - - -- Downstream DMA registers - signal DMA_ds_PA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_ds_HA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_ds_BDA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_ds_Length_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_ds_Control_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_ds_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_ds_Transf_Bytes_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_ds_PA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_ds_HA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_ds_BDA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_ds_Length_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_ds_Control_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_ds_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_ds_Transf_Bytes_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - -- Upstream DMA registers - signal DMA_us_PA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_us_HA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_us_BDA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_us_Length_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_us_Control_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_us_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_us_Transf_Bytes_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_us_PA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_us_HA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_us_BDA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_us_Length_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_us_Control_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_us_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_us_Transf_Bytes_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - - -- System Interrupt Status/Control - signal Sys_IRQ_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal Sys_Int_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal Sys_Int_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal Sys_Int_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - signal Sys_Int_Enable_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal Sys_Int_Enable_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal Sys_Int_Enable_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - - -- Data generator control - signal DG_Reset_i : std_logic; - signal DG_Mask_i : std_logic; - signal DG_is_Available : std_logic; - signal DG_Rst_Counter : std_logic_vector(8-1 downto 0); - signal DG_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DG_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DG_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - -- General Control and Status - signal Sys_Error_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal Sys_Error_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal Sys_Error_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - signal General_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal General_Control_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal General_Control_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - signal General_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal General_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal General_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - -- Hardward version - signal HW_Version_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal HW_Version_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - -- Signal as the source of interrupts - signal IG_Host_Clear_i : std_logic; - signal IG_Reset_i : std_logic; - - -- Interrupt Generator Control - signal IG_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - -- Interrupt Generator Latency - signal IG_Latency_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal IG_Latency_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal IG_Latency_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - -- Interrupt Generator Statistic: Assert number - signal IG_Num_Assert_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal IG_Num_Assert_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal IG_Num_Assert_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - -- Interrupt Generator Statistic: Deassert number - signal IG_Num_Deassert_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal IG_Num_Deassert_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal IG_Num_Deassert_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - -- IntClr character is written - signal Command_is_Host_iClr_Hi : std_logic; - signal Command_is_Host_iClr_Lo : std_logic; - - -- Downstream Registers - signal DMA_ds_PA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_ds_HA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_ds_BDA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_ds_Length_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_ds_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_ds_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_ds_Transf_Bytes_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - signal Last_Ctrl_Word_ds : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - -- Calculation in advance, for better timing - signal dsHA_is_64b_i : std_logic; - signal dsBDA_is_64b_i : std_logic; - - -- Calculation in advance, for better timing - signal dsLeng_Hi19b_True_i : std_logic; - signal dsLeng_Lo7b_True_i : std_logic; - - -- Downstream Control Signals - signal dsDMA_Start_i : std_logic; - signal dsDMA_Stop_i : std_logic; - signal dsDMA_Start2_i : std_logic; - signal dsDMA_Start2_r1 : std_logic; - signal dsDMA_Stop2_i : std_logic; - signal dsDMA_Channel_Rst_i : std_logic; - signal ds_Param_Modified : std_logic; - - - -- Upstream Registers - signal DMA_us_PA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_us_HA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_us_BDA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_us_Length_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_us_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_us_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_us_Transf_Bytes_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - signal Last_Ctrl_Word_us : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - -- Calculation in advance, for better timing - signal usHA_is_64b_i : std_logic; - signal usBDA_is_64b_i : std_logic; - - -- Calculation in advance, for better timing - signal usLeng_Hi19b_True_i : std_logic; - signal usLeng_Lo7b_True_i : std_logic; - - - -- Upstream Control Signals - signal usDMA_Start_i : std_logic; - signal usDMA_Stop_i : std_logic; - signal usDMA_Start2_i : std_logic; - signal usDMA_Start2_r1 : std_logic; - signal usDMA_Stop2_i : std_logic; - signal usDMA_Channel_Rst_i : std_logic; - signal us_Param_Modified : std_logic; - - -- Reset character is written - signal Command_is_Reset_Hi : std_logic; - signal Command_is_Reset_Lo : std_logic; - - -- MRd channel reset - signal MRd_Channel_Rst_i : std_logic; - - -- Tx module reset - signal Tx_Reset_i : std_logic; - - - -- ICAP - signal icap_CLK : std_logic; - signal icap_I : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal icap_CE : std_logic; - signal icap_Write : std_logic; - signal icap_O : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal icap_O_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal icap_O_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal icap_BUSY : std_logic; - - -- DCB protocol interface - signal protocol_rst_i : std_logic; - signal protocol_rst_b1 : std_logic; - signal protocol_rst_b2 : std_logic; - - -- Protocol : CTL - signal ctl_rv_i : std_logic; - signal ctl_rd_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0); - - signal class_CTL_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal class_CTL_Status_o_Hi: std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal class_CTL_Status_o_Lo: std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - signal ctl_td_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0); - signal ctl_td_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0); - signal ctl_td_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0); - - signal ctl_reset_i : std_logic; - signal ctl_ttake_i : std_logic; - signal ctl_tstop_i : std_logic; - signal ctl_t_read_Hi_r1 : std_logic; - signal ctl_t_read_Lo_r1 : std_logic; - signal CTL_read_counter : std_logic_vector(6-1 downto 0); - - -- Protocol : DLM - signal dlm_tv_i : std_logic; - signal dlm_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0); - - signal dlm_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0); - signal dlm_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0); - signal dlm_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0); - -begin - - DG_Available_Bit: if IMP_DATA_GENERATOR generate - DG_is_Available <= '1'; - end generate; - - DG_Unavailable_Bit: if not IMP_DATA_GENERATOR generate - DG_is_Available <= '0'; - end generate; - - -- protocol interface reset - protocol_rst <= protocol_rst_i; - - ctl_rv <= ctl_rv_i; - ctl_rd <= ctl_rd_i; - - ctl_ttake <= ctl_ttake_i; - ctl_tstop <= ctl_tstop_i; - ctl_reset <= ctl_reset_i; - - ctl_tstop_i <= '0'; -- ??? - - dlm_tv <= dlm_tv_i; - dlm_td <= dlm_td_i; - - -- Data generator control - DG_Reset <= DG_Reset_i; - DG_Mask <= DG_Mask_i; - - -- Event buffer reset - eb_FIFO_Rst <= eb_FIFO_Rst_i; - - -- MRd channel reset - MRd_Channel_Rst <= MRd_Channel_Rst_i; - - -- Tx module reset - Tx_Reset <= Tx_Reset_i; - - -- Upstream DMA engine reset - usDMA_Channel_Rst <= usDMA_Channel_Rst_i; - - -- Downstream DMA engine reset - dsDMA_Channel_Rst <= dsDMA_Channel_Rst_i; - - - -- Upstream DMA registers - DMA_us_PA <= DMA_us_PA_i; - DMA_us_HA <= DMA_us_HA_i; - DMA_us_BDA <= DMA_us_BDA_i; - DMA_us_Length <= DMA_us_Length_i; - DMA_us_Control <= DMA_us_Control_i; - usDMA_BDA_eq_Null <= '0'; - DMA_us_Status_i <= DMA_us_Status; - - usHA_is_64b <= usHA_is_64b_i; - usBDA_is_64b <= usBDA_is_64b_i; - - usLeng_Hi19b_True <= usLeng_Hi19b_True_i; - usLeng_Lo7b_True <= usLeng_Lo7b_True_i; - - usDMA_Start <= usDMA_Start_i; - usDMA_Stop <= usDMA_Stop_i; - usDMA_Start2 <= usDMA_Start2_r1; --- usDMA_Start2 <= usDMA_Start2_i; - usDMA_Stop2 <= usDMA_Stop2_i; - - -- Downstream DMA registers - DMA_ds_PA <= DMA_ds_PA_i; - DMA_ds_HA <= DMA_ds_HA_i; - DMA_ds_BDA <= DMA_ds_BDA_i; - DMA_ds_Length <= DMA_ds_Length_i; - DMA_ds_Control <= DMA_ds_Control_i; - dsDMA_BDA_eq_Null <= '0'; - DMA_ds_Status_i <= DMA_ds_Status; - - dsHA_is_64b <= dsHA_is_64b_i; - dsBDA_is_64b <= dsBDA_is_64b_i; - - dsLeng_Hi19b_True <= dsLeng_Hi19b_True_i; - dsLeng_Lo7b_True <= dsLeng_Lo7b_True_i; - - dsDMA_Start <= dsDMA_Start_i; - dsDMA_Stop <= dsDMA_Stop_i; - dsDMA_Start2 <= dsDMA_Start2_r1; --- dsDMA_Start2 <= dsDMA_Start2_i; - dsDMA_Stop2 <= dsDMA_Stop2_i; - - - -- Register to Interrupt handler module - Sys_IRQ <= Sys_IRQ_i; - - -- Message routing method - Msg_Routing <= General_Control_i(C_GCR_MSG_ROUT_BIT_TOP downto C_GCR_MSG_ROUT_BIT_BOT); - - -- us_MWr_TLP_Param - us_MWr_Param_Vec <= General_Control_i(13 downto 8); - - - -- ------------- Interrupt generator generation ---------------------- - Gen_IG: if IMP_INT_GENERATOR generate - - IG_Reset <= IG_Reset_i; - IG_Host_Clear <= IG_Host_Clear_i; -- and Sys_Int_Enable_i(CINT_BIT_INTGEN_IN_ISR); - IG_Latency <= IG_Latency_i; - IG_Num_Assert_i <= IG_Num_Assert; - IG_Num_Deassert_i <= IG_Num_Deassert; - - --- ----------------------------------------------- --- Synchronous Registered: IG_Control_i - SysReg_IntGen_Control: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - IG_Control_i <= (OTHERS => '0'); - IG_Reset_i <= '1'; - IG_Host_Clear_i <= '0'; - - elsif trn_clk'event and trn_clk = '1' then - - if Regs_WrEn_r2='1' - and Reg_WrMuxer_Hi(CINT_ADDR_IG_CONTROL)='1' - then - IG_Control_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32); - IG_Reset_i <= Command_is_Reset_Hi; - IG_Host_Clear_i <= Command_is_Host_iClr_Hi; - elsif Regs_WrEn_r2='1' - and Reg_WrMuxer_Lo(CINT_ADDR_IG_CONTROL)='1' - then - IG_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0); - IG_Reset_i <= Command_is_Reset_Lo; - IG_Host_Clear_i <= Command_is_Host_iClr_Lo; - else - IG_Control_i <= IG_Control_i; - IG_Reset_i <= '0'; - IG_Host_Clear_i <= '0'; - end if; - - end if; - end process; - - --- ----------------------------------------------- --- Synchronous Registered: IG_Latency_i - SysReg_IntGen_Latency: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - IG_Latency_i <= (OTHERS => '0'); - - elsif trn_clk'event and trn_clk = '1' then - - if IG_Reset_i='1' then - IG_Latency_i <= (OTHERS => '0'); - elsif Regs_WrEn_r2='1' - and Reg_WrMuxer_Hi(CINT_ADDR_IG_LATENCY)='1' - then - IG_Latency_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32); - elsif Regs_WrEn_r2='1' - and Reg_WrMuxer_Lo(CINT_ADDR_IG_LATENCY)='1' - then - IG_Latency_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0); - else - IG_Latency_i <= IG_Latency_i; - end if; - - end if; - end process; - - end generate; - - NotGen_IG: if not IMP_INT_GENERATOR generate - - IG_Reset <= '0'; - IG_Host_Clear <= '0'; - IG_Latency <= (OTHERS=>'0'); - IG_Num_Assert_i <= (OTHERS=>'0'); - IG_Num_Deassert_i <= (OTHERS=>'0'); - - IG_Control_i <= (OTHERS=>'0'); - IG_Reset_i <= '0'; - IG_Host_Clear_i <= '0'; - IG_Latency_i <= (OTHERS=>'0'); - - end generate; - - - --- ---------------------------------------------- --- Synchronous Delay : Sys_IRQ_i --- - Synch_Delay_Sys_IRQ: - process ( trn_clk, trn_lnk_up_n ) - begin - if trn_lnk_up_n = '1' then - Sys_IRQ_i <= (OTHERS=>'0'); - - elsif trn_clk'event and trn_clk = '1' then - Sys_IRQ_i(C_NUM_OF_INTERRUPTS-1 downto 0) - <= Sys_Int_Enable_i(C_NUM_OF_INTERRUPTS-1 downto 0) - and Sys_Int_Status_i(C_NUM_OF_INTERRUPTS-1 downto 0); - - end if; - end process; - - --- ---------------------------------------------- --- Registers writing --- - Regs_WrAddr_i <= Regs_WrAddrA and Regs_WrAddrB; - Regs_WrMask_i <= Regs_WrMaskA or Regs_WrMaskB; - Regs_WrDin_i <= Regs_WrDinA or Regs_WrDinB; - --- ---------------------------------------------- --- Registers reading --- - Regs_RdAddr_i <= Regs_RdAddr; - Regs_RdQout <= Regs_RdQout_i; - --- ---------------------------------------------- --- Synchronous Delay : Regs_WrEn --- - Synch_Delay_Regs_WrEn: - process ( trn_clk ) - begin - if trn_clk'event and trn_clk = '1' then - Regs_WrEn_r1 <= Regs_WrEnA or Regs_WrEnB; - Regs_WrEn_r2 <= Regs_WrEn_r1; - - Regs_WrEnA_r1 <= Regs_WrEnA; - Regs_WrEnA_r2 <= Regs_WrEnA_r1; - - Regs_WrEnB_r1 <= Regs_WrEnB; - Regs_WrEnB_r2 <= Regs_WrEnB_r1; - - end if; - end process; - --- ---------------------------------------------- --- Synchronous Delay : Opto_Link_Status --- - Synch_Delay_Opto_Link_Status: - process ( trn_clk ) - begin - if trn_clk'event and trn_clk = '1' then - Opto_Link_Status_i(C_DBUS_WIDTH-1 downto 2) <= (OTHERS=>'0'); - Opto_Link_Status_i(2-1 downto 0) <= protocol_link_act; - end if; - end process; - --- ---------------------------------------------- --- Synchronous Delay : eb_FIFO_Status --- - Synch_Delay_eb_FIFO_Status: - process ( trn_clk ) - begin - if trn_clk'event and trn_clk = '1' then - eb_FIFO_Status_r1 <= eb_FIFO_Status; - end if; - end process; - --- ---------------------------------------------- --- Synchronous Delay : Regs_WrAddr --- - Synch_Delay_Regs_WrAddr: - process ( trn_clk ) - begin - if trn_clk'event and trn_clk = '1' then - Regs_WrAddr_r1 <= Regs_WrAddr_i; - Regs_WrMask_r1 <= Regs_WrMask_i; - end if; - end process; - --- ---------------------------------------------------- --- Synchronous Delay : dsDMA_Start2 --- usDMA_Start2 --- (Special recipe for 64-bit successive descriptors) --- - Synch_Delay_DMA_Start2: - process ( trn_clk ) - begin - if trn_clk'event and trn_clk = '1' then - dsDMA_Start2_r1 <= dsDMA_Start2_i and not dsDMA_Cmd_Ack; - usDMA_Start2_r1 <= usDMA_Start2_i and not usDMA_Cmd_Ack; - end if; - end process; - - --- ---------------------------------------------- --- Synchronous Delay : Regs_WrDin_i --- - Synch_Delay_Regs_WrDin: - process ( trn_clk ) - begin - if trn_clk'event and trn_clk = '1' then - Regs_WrDin_r1 <= Regs_WrDin_i; - Regs_WrDin_r2 <= Regs_WrDin_r1; - - if Regs_WrDin_i(31+32 downto 24+32) = C_ALL_ZEROS(31+32 downto 24+32) then - WrDin_r1_not_Zero_Hi(3) <= '0'; - else - WrDin_r1_not_Zero_Hi(3) <= '1'; - end if; - if Regs_WrDin_i(23+32 downto 16+32) = C_ALL_ZEROS(23+32 downto 16+32) then - WrDin_r1_not_Zero_Hi(2) <= '0'; - else - WrDin_r1_not_Zero_Hi(2) <= '1'; - end if; - if Regs_WrDin_i(15+32 downto 8+32) = C_ALL_ZEROS(15+32 downto 8+32) then - WrDin_r1_not_Zero_Hi(1) <= '0'; - else - WrDin_r1_not_Zero_Hi(1) <= '1'; - end if; - if Regs_WrDin_i(7+32 downto 0+32) = C_ALL_ZEROS(7+32 downto 0+32) then - WrDin_r1_not_Zero_Hi(0) <= '0'; - else - WrDin_r1_not_Zero_Hi(0) <= '1'; - end if; - - if WrDin_r1_not_Zero_Hi = C_ALL_ZEROS(3 downto 0) then - WrDin_r2_not_Zero_Hi <= '0'; - else - WrDin_r2_not_Zero_Hi <= '1'; - end if; - - - if Regs_WrDin_i(31 downto 24) = C_ALL_ZEROS(31 downto 24) then - WrDin_r1_not_Zero_Lo(3) <= '0'; - else - WrDin_r1_not_Zero_Lo(3) <= '1'; - end if; - if Regs_WrDin_i(23 downto 16) = C_ALL_ZEROS(23 downto 16) then - WrDin_r1_not_Zero_Lo(2) <= '0'; - else - WrDin_r1_not_Zero_Lo(2) <= '1'; - end if; - if Regs_WrDin_i(15 downto 8) = C_ALL_ZEROS(15 downto 8) then - WrDin_r1_not_Zero_Lo(1) <= '0'; - else - WrDin_r1_not_Zero_Lo(1) <= '1'; - end if; - if Regs_WrDin_i(7 downto 0) = C_ALL_ZEROS(7 downto 0) then - WrDin_r1_not_Zero_Lo(0) <= '0'; - else - WrDin_r1_not_Zero_Lo(0) <= '1'; - end if; - - if WrDin_r1_not_Zero_Lo = C_ALL_ZEROS(3 downto 0) then - WrDin_r2_not_Zero_Lo <= '0'; - else - WrDin_r2_not_Zero_Lo <= '1'; - end if; - end if; - end process; - - --- ----------------------------------------------------------- --- Synchronous Delay : DMA Commands Write Valid and not End --- - Synch_Delay_dmaCmd_Wr_Valid_and_End: - process ( trn_clk ) - begin - if trn_clk'event and trn_clk = '1' then - Regs_Wr_dma_V_hi_r2 <= Regs_WrEn_r1 - and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32) - ; - Regs_Wr_dma_nV_hi_r2 <= Regs_WrEn_r1 - and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32) - ; - Regs_Wr_dma_V_nE_hi_r2 <= Regs_WrEn_r1 - and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32) - and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_END+32) - ; - - - Regs_Wr_dma_V_lo_r2 <= Regs_WrEn_r1 - and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID) - ; - Regs_Wr_dma_nV_lo_r2 <= Regs_WrEn_r1 - and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID) - ; - Regs_Wr_dma_V_nE_lo_r2 <= Regs_WrEn_r1 - and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID) - and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_END) - ; - end if; - end process; - - - --- ------------------------------------------------ --- Synchronous Delay : Regs_WrDin_Hi19b_True_r2 x2 --- Regs_WrDin_Lo7b_True_r2 x2 --- - Synch_Delay_Regs_WrDin_Hi19b_and_Lo7b_True: - process ( trn_clk ) - begin - if trn_clk'event and trn_clk = '1' then - - if Regs_WrDin_r1(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1+32) - = C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1+32) - then - Regs_WrDin_Hi19b_True_hq_r2 <= '0'; - else - Regs_WrDin_Hi19b_True_hq_r2 <= '1'; - end if; - - if Regs_WrDin_r1(C_MAXSIZE_FLD_BIT_BOT-1+32 downto 2+32) - = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_BOT-1+32 downto 2+32) - then -- ! Lowest 2 bits ignored ! - Regs_WrDin_Lo7b_True_hq_r2 <= '0'; - else - Regs_WrDin_Lo7b_True_hq_r2 <= '1'; - end if; - - if Regs_WrDin_r1(C_DBUS_WIDTH-1-32 downto C_MAXSIZE_FLD_BIT_TOP+1) - = C_ALL_ZEROS(C_DBUS_WIDTH-1-32 downto C_MAXSIZE_FLD_BIT_TOP+1) - then - Regs_WrDin_Hi19b_True_lq_r2 <= '0'; - else - Regs_WrDin_Hi19b_True_lq_r2 <= '1'; - end if; - - if Regs_WrDin_r1(C_MAXSIZE_FLD_BIT_BOT-1 downto 2) - = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_BOT-1 downto 2) - then -- ! Lowest 2 bits ignored ! - Regs_WrDin_Lo7b_True_lq_r2 <= '0'; - else - Regs_WrDin_Lo7b_True_lq_r2 <= '1'; - end if; - - end if; - end process; - - - --- --------------------------------------- --- - Write_DMA_Registers_Mux: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - Reg_WrMuxer_Hi <= (Others => '0'); - Reg_WrMuxer_Lo <= (Others => '0'); - - elsif trn_clk'event and trn_clk = '1' then - - if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) - -- and - Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(0, C_DECODE_BIT_BOT-2) - -- and Regs_WrAddr_r1(2-1 downto 0)="00" - then - Reg_WrMuxer_Hi(0) <= not Regs_WrMask_r1(1); - else - Reg_WrMuxer_Hi(0) <= '0'; - end if; - - FOR k IN 1 TO C_NUM_OF_ADDRESSES-1 LOOP - - if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) - -- and - Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k, C_DECODE_BIT_BOT-2) - -- and Regs_WrAddr_r1(2-1 downto 0)="00" - then - Reg_WrMuxer_Hi(k) <= not Regs_WrMask_r1(1); - else - Reg_WrMuxer_Hi(k) <= '0'; - end if; - - if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) - -- and - Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k-1, C_DECODE_BIT_BOT-2) - -- and Regs_WrAddr_r1(2-1 downto 0)="00" - then - Reg_WrMuxer_Lo(k) <= not Regs_WrMask_r1(0); - else - Reg_WrMuxer_Lo(k) <= '0'; - end if; - - END LOOP; - - end if; - end process; - - - --- ----------------------------------------------- --- System Interrupt Status Control --- ----------------------------------------------- - --- ------------------------------------------------------- --- Synchronous Registered: Sys_Int_Enable_i - SysReg_Sys_Int_Enable: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - Sys_Int_Enable_i <= (OTHERS => '0'); - elsif trn_clk'event and trn_clk = '1' then - - if Regs_WrEn_r2='1' - and Reg_WrMuxer_Hi(CINT_ADDR_IRQ_EN)='1' - then - Sys_Int_Enable_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32); - elsif Regs_WrEn_r2='1' - and Reg_WrMuxer_Lo(CINT_ADDR_IRQ_EN)='1' - then - Sys_Int_Enable_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0); - else - Sys_Int_Enable_i <= Sys_Int_Enable_i; - end if; - - - end if; - end process; - - --- ----------------------------------------------- --- System General Control Register --- ----------------------------------------------- --- ----------------------------------------------- --- Synchronous Registered: General_Control - SysReg_General_Control: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - General_Control_i <= (OTHERS => '0'); - General_Control_i(C_GCR_MSG_ROUT_BIT_TOP downto C_GCR_MSG_ROUT_BIT_BOT) - <= C_TYPE_OF_MSG(C_TLP_TYPE_BIT_BOT+C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT - downto C_TLP_TYPE_BIT_BOT); - - elsif trn_clk'event and trn_clk = '1' then - - if Regs_WrEn_r2='1' - and Reg_WrMuxer_Hi(CINT_ADDR_CONTROL)='1' - then - General_Control_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32); - elsif Regs_WrEn_r2='1' - and Reg_WrMuxer_Lo(CINT_ADDR_CONTROL)='1' - then - General_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0); - else - General_Control_i <= General_Control_i; - end if; - - end if; - end process; - --- ----------------------------------------------- --- Synchronous Registered: DG_Reset_i - SysReg_DGen_Reset: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - DG_Reset_i <= '1'; - DG_Rst_Counter <= (OTHERS=>'0'); - - elsif trn_clk'event and trn_clk = '1' then - - if DG_Rst_Counter=X"FF" then - DG_Rst_Counter <= DG_Rst_Counter; - else - DG_Rst_Counter <= DG_Rst_Counter + '1'; - end if; - - if DG_Rst_Counter(7)='0' then - DG_Reset_i <= '1'; - elsif Regs_WrEn_r2='1' - and Reg_WrMuxer_Hi(CINT_ADDR_DG_CTRL)='1' - then - DG_Reset_i <= Command_is_Reset_Hi; - elsif Regs_WrEn_r2='1' - and Reg_WrMuxer_Lo(CINT_ADDR_DG_CTRL)='1' - then - DG_Reset_i <= Command_is_Reset_Lo; - else - DG_Reset_i <= '0'; - end if; - - end if; - end process; - --- ----------------------------------------------- --- Synchronous Registered: DG_Mask_i - SysReg_DGen_Mask: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - DG_Mask_i <= '0'; - elsif trn_clk'event and trn_clk = '1' then - - if Regs_WrEn_r2='1' - and Reg_WrMuxer_Hi(CINT_ADDR_DG_CTRL)='1' - then - DG_Mask_i <= Regs_WrDin_r2(32+CINT_BIT_DG_MASK); - elsif Regs_WrEn_r2='1' - and Reg_WrMuxer_Lo(CINT_ADDR_DG_CTRL)='1' - then - DG_Mask_i <= Regs_WrDin_r2(CINT_BIT_DG_MASK); - else - DG_Mask_i <= DG_Mask_i; - end if; - - end if; - end process; - --------------------------------------------------------------------------- --- Data generator status --- - Synch_DG_Status_i: - process ( trn_clk, DG_Reset_i ) - begin - if DG_Reset_i = '1' then - DG_Status_i <= (OTHERS=>'0'); - elsif trn_clk'event and trn_clk = '1' then - DG_Status_i(CINT_BIT_DG_MASK) <= DG_Mask_i; - DG_Status_i(CINT_BIT_DG_BUSY) <= DG_is_Running; - end if; - end process; - --- ----------------------------------------------- --- Synchronous Registered: IG_Control_i - SysReg_IntGen_Control: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - IG_Control_i <= (OTHERS => '0'); - IG_Reset_i <= '1'; - IG_Host_Clear_i <= '0'; - - elsif trn_clk'event and trn_clk = '1' then - - if Regs_WrEn_r2='1' - and Reg_WrMuxer_Hi(CINT_ADDR_IG_CONTROL)='1' - then - IG_Control_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32); - IG_Reset_i <= Command_is_Reset_Hi; - IG_Host_Clear_i <= Command_is_Host_iClr_Hi; - elsif Regs_WrEn_r2='1' - and Reg_WrMuxer_Lo(CINT_ADDR_IG_CONTROL)='1' - then - IG_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0); - IG_Reset_i <= Command_is_Reset_Lo; - IG_Host_Clear_i <= Command_is_Host_iClr_Lo; - else - IG_Control_i <= IG_Control_i; - IG_Reset_i <= '0'; - IG_Host_Clear_i <= '0'; - end if; - - end if; - end process; - - --- ----------------------------------------------- --- Synchronous Registered: IG_Latency_i - SysReg_IntGen_Latency: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - IG_Latency_i <= (OTHERS => '0'); - - elsif trn_clk'event and trn_clk = '1' then - - if IG_Reset_i='1' then - IG_Latency_i <= (OTHERS => '0'); - elsif Regs_WrEn_r2='1' - and Reg_WrMuxer_Hi(CINT_ADDR_IG_LATENCY)='1' - then - IG_Latency_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32); - elsif Regs_WrEn_r2='1' - and Reg_WrMuxer_Lo(CINT_ADDR_IG_LATENCY)='1' - then - IG_Latency_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0); - else - IG_Latency_i <= IG_Latency_i; - end if; - - end if; - end process; - - - - --- ------------------------------------------------------ --- Protocol CTL interface --- ------------------------------------------------------ - --- ------------------------------------------------------- --- Synchronous Registered: ctl_rd - Syn_CTL_rd: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - ctl_rd_i <= (OTHERS => '0'); - ctl_rv_i <= '0'; - elsif trn_clk'event and trn_clk = '1' then - - if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_CTL_CLASS)='1' then - ctl_rd_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32); - ctl_rv_i <= '1'; - elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_CTL_CLASS)='1' then - ctl_rd_i <= Regs_WrDin_r2(32-1 downto 0); - ctl_rv_i <= '1'; - else - ctl_rd_i <= ctl_rd_i; - ctl_rv_i <= '0'; - end if; - - end if; - end process; - - --- ----------------------------------------------- --- Synchronous Registered: ctl_reset - SysReg_ctl_reset: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - ctl_reset_i <= '1'; - - elsif trn_clk'event and trn_clk = '1' then - - if Regs_WrEn_r2='1' - and Reg_WrMuxer_Hi(CINT_ADDR_TC_STATUS)='1' - then - ctl_reset_i <= Command_is_Reset_Hi; - elsif Regs_WrEn_r2='1' - and Reg_WrMuxer_Lo(CINT_ADDR_TC_STATUS)='1' - then - ctl_reset_i <= Command_is_Reset_Lo; - else - ctl_reset_i <= '0'; - end if; - - end if; - end process; - - - --- ------------------------------------------------------- --- Synchronous Registered: ctl_td --- ++++++++++++ INT triggering ++++++++++++++++++ - Syn_CTL_td: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - ctl_td_r <= (OTHERS => '0'); - elsif trn_clk'event and trn_clk = '1' then - - if ctl_tv='1' then - ctl_td_r <= ctl_td; - else - ctl_td_r <= ctl_td_r; - end if; - - end if; - end process; - - - --- ------------------------------------------------------ --- Protocol DLM interface --- ------------------------------------------------------ - --- ------------------------------------------------------- --- Synchronous Registered: dlm_td - Syn_DLM_td: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - dlm_td_i <= (OTHERS => '0'); - dlm_tv_i <= '0'; - elsif trn_clk'event and trn_clk = '1' then - - if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DLM_CLASS)='1' then - dlm_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32); - dlm_tv_i <= '1'; - elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DLM_CLASS)='1' then - dlm_td_i <= Regs_WrDin_r2(32-1 downto 0); - dlm_tv_i <= '1'; - else - dlm_td_i <= dlm_td_i; - dlm_tv_i <= '0'; - end if; - - end if; - end process; - - --- ------------------------------------------------------- --- Synchronous Registered: dlm_rd --- ++++++++++++ INT triggering ++++++++++++++++++ - Syn_DLM_rd: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - dlm_rd_r <= (OTHERS => '0'); - elsif trn_clk'event and trn_clk = '1' then - - if dlm_rv='1' then - dlm_rd_r <= dlm_rd; - else - dlm_rd_r <= dlm_rd_r; - end if; - - end if; - end process; - - --- ------------------------------------------------------ --- DMA Upstream Registers --- ------------------------------------------------------ - --- ------------------------------------------------------- --- Synchronous Registered: DMA_us_PA_i - RxTrn_DMA_us_PA: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - DMA_us_PA_i <= (OTHERS => '0'); - elsif trn_clk'event and trn_clk = '1' then - - if usDMA_Channel_Rst_i = '1' then - DMA_us_PA_i <= (OTHERS => '0'); - else - - if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAH)='1' then - DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(64-1 downto 32); - elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAH)='1' then - DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0); - else - DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32); - end if; - - if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAL)='1' then - DMA_us_PA_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32); - elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAL)='1' then - DMA_us_PA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0); - else - DMA_us_PA_i(32-1 downto 0) <= DMA_us_PA_i(32-1 downto 0); - end if; - - end if; - - end if; - end process; - - --- ------------------------------------------------------- --- Synchronous Registered: DMA_us_HA_i - RxTrn_DMA_us_HA: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - DMA_us_HA_i <= (OTHERS => '1'); - usHA_is_64b_i <= '0'; - - elsif trn_clk'event and trn_clk = '1' then - - if usDMA_Channel_Rst_i = '1' then - DMA_us_HA_i <= (OTHERS => '1'); - usHA_is_64b_i <= '0'; - else - - if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAH)='1' then - DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(64-1 downto 32); - usHA_is_64b_i <= WrDin_r2_not_Zero_Hi; - elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAH)='1' then - DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0); - usHA_is_64b_i <= WrDin_r2_not_Zero_Lo; - else - DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32); - usHA_is_64b_i <= usHA_is_64b_i; - end if; - - if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAL)='1' then - DMA_us_HA_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32); - elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAL)='1' then - DMA_us_HA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0); - else - DMA_us_HA_i(32-1 downto 0) <= DMA_us_HA_i(32-1 downto 0); - end if; - - end if; - - end if; - end process; - - --- ------------------------------------------------------- --- Synchronous output: DMA_us_BDA_i - Syn_Output_DMA_us_BDA: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - DMA_us_BDA_i <= (OTHERS =>'0'); - usBDA_is_64b_i <= '0'; - elsif trn_clk'event and trn_clk = '1' then - - if usDMA_Channel_Rst_i = '1' then - DMA_us_BDA_i <= (OTHERS => '0'); - usBDA_is_64b_i <= '0'; - else - - if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAH)='1' then - DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32); - usBDA_is_64b_i <= WrDin_r2_not_Zero_Hi; - elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAH)='1' then - DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0); - usBDA_is_64b_i <= WrDin_r2_not_Zero_Lo; - else - DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32); - usBDA_is_64b_i <= usBDA_is_64b_i; - end if; - - if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAL)='1' then - DMA_us_BDA_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32); - elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAL)='1' then - DMA_us_BDA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0); - else - DMA_us_BDA_i(32-1 downto 0) <= DMA_us_BDA_i(32-1 downto 0); - end if; - - end if; - - end if; - end process; - - - --- ------------------------------------------------------- --- Synchronous Registered: DMA_us_Length_i - RxTrn_DMA_us_Length: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - DMA_us_Length_i <= (OTHERS => '0'); - usLeng_Hi19b_True_i <= '0'; - usLeng_Lo7b_True_i <= '0'; - elsif trn_clk'event and trn_clk = '1' then - - if usDMA_Channel_Rst_i = '1' then - DMA_us_Length_i <= (OTHERS => '0'); - usLeng_Hi19b_True_i <= '0'; - usLeng_Lo7b_True_i <= '0'; - - elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_LENG)='1' then - DMA_us_Length_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32); - usLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_hq_r2; - usLeng_Lo7b_True_i <= Regs_WrDin_Lo7b_True_hq_r2; - elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_LENG)='1' then - DMA_us_Length_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0); - usLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_lq_r2; - usLeng_Lo7b_True_i <= Regs_WrDin_Lo7b_True_lq_r2; - else - DMA_us_Length_i <= DMA_us_Length_i; - usLeng_Hi19b_True_i <= usLeng_Hi19b_True_i; - usLeng_Lo7b_True_i <= usLeng_Lo7b_True_i; - - end if; - - end if; - end process; - - - --- ------------------------------------------------------- --- Synchronous us_Param_Modified - SynReg_us_Param_Modified: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - us_Param_Modified <= '0'; - - elsif trn_clk'event and trn_clk = '1' then - - if usDMA_Channel_Rst_i = '1' - or usDMA_Start_i = '1' - or usDMA_Start2_i = '1' - then - us_Param_Modified <= '0'; - elsif Regs_WrEn_r2='1' and - ( - Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAL) ='1' - or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAL) ='1' - or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAH) ='1' - or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAH) ='1' - or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAL) ='1' - or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAL) ='1' - or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAH)='1' - or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAH)='1' - or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAL)='1' - or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAL)='1' - or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_LENG)='1' - or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_LENG)='1' - ) - then - us_Param_Modified <= '1'; - else - us_Param_Modified <= us_Param_Modified; - - end if; - - end if; - end process; - - - --- ------------------------------------------------------- --- Synchronous output: DMA_us_Control_i - Syn_Output_DMA_us_Control: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - DMA_us_Control_i <= (OTHERS =>'0'); - elsif trn_clk'event and trn_clk = '1' then - - if Regs_Wr_dma_V_nE_Hi_r2='1' - and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1' --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1' --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0' - and us_Param_Modified='1' - and usDMA_Stop_i='0' - then - DMA_us_Control_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32)& X"00"; - elsif Regs_Wr_dma_V_nE_Lo_r2='1' - and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1' --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1' --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0' - and us_Param_Modified='1' - and usDMA_Stop_i='0' - then - DMA_us_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8)& X"00"; - elsif Regs_Wr_dma_nV_Hi_r2='1' - and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1' --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0' - then - DMA_us_Control_i(32-1 downto 0) <= Last_Ctrl_Word_us(32-1 downto 0); - elsif Regs_Wr_dma_nV_Lo_r2='1' - and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1' --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0' - then - DMA_us_Control_i(32-1 downto 0) <= Last_Ctrl_Word_us(32-1 downto 0); - else - DMA_us_Control_i <= DMA_us_Control_i; - end if; - - end if; - end process; - - --- ------------------------------------------------------- --- Synchronous Register: Last_Ctrl_Word_us - Hold_Last_Ctrl_Word_us: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - Last_Ctrl_Word_us <= C_DEF_DMA_CTRL_WORD; - elsif trn_clk'event and trn_clk = '1' then - - if usDMA_Channel_Rst_i = '1' then - Last_Ctrl_Word_us <= C_DEF_DMA_CTRL_WORD; - elsif Regs_Wr_dma_V_nE_Hi_r2='1' - and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1' --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1' --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0' - and us_Param_Modified='1' - and usDMA_Stop_i='0' - then - Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00"; - elsif Regs_Wr_dma_V_nE_Lo_r2='1' - and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1' --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1' --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0' - and us_Param_Modified='1' - and usDMA_Stop_i='0' - then - Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00"; - elsif Regs_Wr_dma_V_nE_Hi_r2='1' - and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1' --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1' --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0' - and us_Param_Modified='1' - and usDMA_Stop_i='0' - then - Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00"; - elsif Regs_Wr_dma_V_nE_Lo_r2='1' - and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1' --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1' --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0' - and us_Param_Modified='1' - and usDMA_Stop_i='0' - then - Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00"; - else - Last_Ctrl_Word_us <= Last_Ctrl_Word_us; - end if; - - end if; - end process; - - --- ------------------------------------------------------- --- Synchronous output: DMA_us_Start_Stop - Syn_Output_DMA_us_Start_Stop: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - usDMA_Start_i <= '0'; - usDMA_Stop_i <= '0'; - elsif trn_clk'event and trn_clk = '1' then - - if Regs_WrEnA_r2='1' - and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1' - and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1' - then - usDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) - and not usDMA_Stop_i - and not Command_is_Reset_Hi - and us_Param_Modified - ; - usDMA_Stop_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) - and not Command_is_Reset_Hi - ; - elsif Regs_WrEnA_r2='1' - and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1' - and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1' - then - usDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) - and not usDMA_Stop_i - and not Command_is_Reset_Lo - and us_Param_Modified - ; - usDMA_Stop_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) - and not Command_is_Reset_Lo - ; - elsif Regs_WrEnA_r2='1' - and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1' - and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0' - then - usDMA_Start_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END) - and us_Param_Modified; - usDMA_Stop_i <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END); - elsif Regs_WrEnA_r2='1' - and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1' - and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0' - then - usDMA_Start_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END) - and us_Param_Modified; - usDMA_Stop_i <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END); - elsif usDMA_Cmd_Ack='1' - then - usDMA_Start_i <= '0'; - usDMA_Stop_i <= usDMA_Stop_i; - else - usDMA_Start_i <= usDMA_Start_i; - usDMA_Stop_i <= usDMA_Stop_i; - end if; - - end if; - end process; - - --- ------------------------------------------------------- --- Synchronous output: DMA_us_Start2_Stop2 - Syn_Output_DMA_us_Start2_Stop2: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - usDMA_Start2_i <= '0'; - usDMA_Stop2_i <= '0'; - elsif trn_clk'event and trn_clk = '1' then - - if usDMA_Channel_Rst_i='1' then - usDMA_Start2_i <= '0'; - usDMA_Stop2_i <= '0'; - elsif Regs_WrEnB_r2='1' - and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1' - and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1' - then - usDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi; - usDMA_Stop2_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Lo; - elsif Regs_WrEnB_r2='1' - and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1' - and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1' - then - usDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo; - usDMA_Stop2_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo; - elsif Regs_WrEnB_r2='1' - and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1' - and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='0' - then - usDMA_Start2_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END); - usDMA_Stop2_i <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END); - elsif Regs_WrEnB_r2='1' - and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1' - and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0' - then - usDMA_Start2_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END); - usDMA_Stop2_i <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END); - elsif usDMA_Cmd_Ack='1' then - usDMA_Start2_i <= '0'; - usDMA_Stop2_i <= usDMA_Stop2_i; - else - usDMA_Start2_i <= usDMA_Start2_i; - usDMA_Stop2_i <= usDMA_Stop2_i; - end if; - - end if; - end process; - - --- ------------------------------------------------------ --- DMA Downstream Registers --- ------------------------------------------------------ - --- ------------------------------------------------------- --- Synchronous Registered: DMA_ds_PA_i - RxTrn_DMA_ds_PA: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - DMA_ds_PA_i <= (OTHERS => '0'); - elsif trn_clk'event and trn_clk = '1' then - - if dsDMA_Channel_Rst_i = '1' then - DMA_ds_PA_i <= (OTHERS => '0'); - else - - if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAH)='1' then - DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32); - elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAH)='1' then - DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0); - else - DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32); - end if; - - if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAL)='1' then - DMA_ds_PA_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32); - elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAL)='1' then - DMA_ds_PA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0); - else - DMA_ds_PA_i(32-1 downto 0) <= DMA_ds_PA_i(32-1 downto 0); - end if; - - end if; - - end if; - end process; - - --- ------------------------------------------------------- --- Synchronous Registered: DMA_ds_HA_i - RxTrn_DMA_ds_HA: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - DMA_ds_HA_i <= (OTHERS => '1'); - dsHA_is_64b_i <= '0'; - elsif trn_clk'event and trn_clk = '1' then - - if dsDMA_Channel_Rst_i = '1' then - DMA_ds_HA_i <= (OTHERS => '1'); - dsHA_is_64b_i <= '0'; - else - - if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAH)='1' then - DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32); - dsHA_is_64b_i <= WrDin_r2_not_Zero_Hi; - elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAH)='1' then - DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0); - dsHA_is_64b_i <= WrDin_r2_not_Zero_Lo; - else - DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32); - dsHA_is_64b_i <= dsHA_is_64b_i; - end if; - - if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAL)='1' then - DMA_ds_HA_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32); - elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAL)='1' then - DMA_ds_HA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0); - else - DMA_ds_HA_i(32-1 downto 0) <= DMA_ds_HA_i(32-1 downto 0); - end if; - - end if; - - end if; - end process; - - --- ------------------------------------------------------- --- Synchronous output: DMA_ds_BDA_i - Syn_Output_DMA_ds_BDA: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - DMA_ds_BDA_i <= (OTHERS =>'0'); - dsBDA_is_64b_i <= '0'; - elsif trn_clk'event and trn_clk = '1' then - - if dsDMA_Channel_Rst_i = '1' then - DMA_ds_BDA_i <= (OTHERS => '0'); - dsBDA_is_64b_i <= '0'; - else - - if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAH)='1' then - DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32); - dsBDA_is_64b_i <= WrDin_r2_not_Zero_Hi; - elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAH)='1' then - DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0); - dsBDA_is_64b_i <= WrDin_r2_not_Zero_Lo; - else - DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32); - dsBDA_is_64b_i <= dsBDA_is_64b_i; - end if; - - if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAL)='1' then - DMA_ds_BDA_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32); - elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAL)='1' then - DMA_ds_BDA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0); - else - DMA_ds_BDA_i(32-1 downto 0) <= DMA_ds_BDA_i(32-1 downto 0); - end if; - - end if; - end if; - end process; - - - --- Synchronous Registered: DMA_ds_Length_i - RxTrn_DMA_ds_Length: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - DMA_ds_Length_i <= (OTHERS => '0'); - dsLeng_Hi19b_True_i <= '0'; - dsLeng_Lo7b_True_i <= '0'; - elsif trn_clk'event and trn_clk = '1' then - - if dsDMA_Channel_Rst_i = '1' then - DMA_ds_Length_i <= (OTHERS => '0'); - dsLeng_Hi19b_True_i <= '0'; - dsLeng_Lo7b_True_i <= '0'; - - elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_LENG)='1' then - DMA_ds_Length_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32); - dsLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_hq_r2; - dsLeng_Lo7b_True_i <= Regs_WrDin_Lo7b_True_hq_r2; - elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_LENG)='1' then - DMA_ds_Length_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0); - dsLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_lq_r2; - dsLeng_Lo7b_True_i <= Regs_WrDin_Lo7b_True_lq_r2; - else - DMA_ds_Length_i <= DMA_ds_Length_i; - dsLeng_Hi19b_True_i <= dsLeng_Hi19b_True_i; - dsLeng_Lo7b_True_i <= dsLeng_Lo7b_True_i; - - end if; - - end if; - end process; - - - --- ------------------------------------------------------- --- Synchronous ds_Param_Modified - SynReg_ds_Param_Modified: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - ds_Param_Modified <= '0'; - - elsif trn_clk'event and trn_clk = '1' then - - if dsDMA_Channel_Rst_i = '1' - or dsDMA_Start_i = '1' - or dsDMA_Start2_i = '1' - then - ds_Param_Modified <= '0'; - elsif Regs_WrEn_r2='1' and - ( --- Reg_WrMuxer(CINT_ADDR_DMA_DS_PAH) ='1' --- or - Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAL) ='1' - or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAL) ='1' - or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAH) ='1' - or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAH) ='1' - or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAL) ='1' - or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAL) ='1' - or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAH)='1' - or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAH)='1' - or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAL)='1' - or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAL)='1' - or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_LENG)='1' - or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_LENG)='1' - ) - then - ds_Param_Modified <= '1'; - else - ds_Param_Modified <= ds_Param_Modified; - - end if; - - end if; - end process; - - - --- ------------------------------------------------------- --- Synchronous output: DMA_ds_Control_i - Syn_Output_DMA_ds_Control: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - DMA_ds_Control_i <= (OTHERS =>'0'); - - elsif trn_clk'event and trn_clk = '1' then - - if Regs_Wr_dma_V_nE_Hi_r2='1' - and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1' --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1' --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)='0' - and ds_Param_Modified='1' - and dsDMA_Stop_i='0' - then - DMA_ds_Control_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32)& X"00"; - elsif Regs_Wr_dma_V_nE_Lo_r2='1' - and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1' --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1' --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0' - and ds_Param_Modified='1' - and dsDMA_Stop_i='0' - then - DMA_ds_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8)& X"00"; - elsif Regs_Wr_dma_nV_Hi_r2='1' - and (Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1' or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1') --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0' - then - DMA_ds_Control_i <= Last_Ctrl_Word_ds; - else - DMA_ds_Control_i <= DMA_ds_Control_i; - end if; - - end if; - end process; - - --- ------------------------------------------------------- --- Synchronous Register: Last_Ctrl_Word_ds - Hold_Last_Ctrl_Word_ds: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - Last_Ctrl_Word_ds <= C_DEF_DMA_CTRL_WORD; - elsif trn_clk'event and trn_clk = '1' then - - if dsDMA_Channel_Rst_i = '1' then - Last_Ctrl_Word_ds <= C_DEF_DMA_CTRL_WORD; - elsif Regs_Wr_dma_V_nE_Hi_r2='1' - and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1' --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1' --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)='0' - and ds_Param_Modified='1' - and dsDMA_Stop_i='0' - then - Last_Ctrl_Word_ds(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00"; - elsif Regs_Wr_dma_V_nE_Lo_r2='1' - and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1' --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1' --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0' - and ds_Param_Modified='1' - and dsDMA_Stop_i='0' - then - Last_Ctrl_Word_ds(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00"; - else - Last_Ctrl_Word_ds <= Last_Ctrl_Word_ds; - end if; - - end if; - end process; - - --- ------------------------------------------------------- --- Synchronous output: DMA_ds_Start_Stop - Syn_Output_DMA_ds_Start_Stop: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - dsDMA_Start_i <= '0'; - dsDMA_Stop_i <= '0'; - - elsif trn_clk'event and trn_clk = '1' then - - if Regs_WrEnA_r2='1' - and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1' - and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1' - then - dsDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) - and not dsDMA_Stop_i - and not Command_is_Reset_Hi - and ds_Param_Modified - ; - dsDMA_Stop_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) - and not Command_is_Reset_Hi - ; - elsif Regs_WrEnA_r2='1' - and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1' - and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1' - then - dsDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) - and not dsDMA_Stop_i - and not Command_is_Reset_Lo - and ds_Param_Modified - ; - dsDMA_Stop_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) - and not Command_is_Reset_Lo - ; - elsif Regs_WrEnA_r2='1' - and (Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1' or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1') - and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='0' - then - dsDMA_Start_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END) - and ds_Param_Modified - ; - dsDMA_Stop_i <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END); - elsif dsDMA_Cmd_Ack='1' - then - dsDMA_Start_i <= '0'; - dsDMA_Stop_i <= dsDMA_Stop_i; - else - dsDMA_Start_i <= dsDMA_Start_i; - dsDMA_Stop_i <= dsDMA_Stop_i; - end if; - - end if; - end process; - - --- ------------------------------------------------------- --- Synchronous output: DMA_ds_Start2_Stop2 - Syn_Output_DMA_ds_Start2_Stop2: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - dsDMA_Start2_i <= '0'; - dsDMA_Stop2_i <= '0'; - - elsif trn_clk'event and trn_clk = '1' then - - if dsDMA_Channel_Rst_i='1' then - dsDMA_Start2_i <= '0'; - dsDMA_Stop2_i <= '0'; - elsif Regs_WrEnB_r2='1' - and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1' - and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1' - then - dsDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi; - dsDMA_Stop2_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi; - elsif Regs_WrEnB_r2='1' - and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1' - and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1' - then - dsDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo; - dsDMA_Stop2_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo; - elsif Regs_WrEnB_r2='1' - and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1' - and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='0' - then - dsDMA_Start2_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END); - dsDMA_Stop2_i <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END); - elsif Regs_WrEnB_r2='1' - and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1' - and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0' - then - dsDMA_Start2_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END); - dsDMA_Stop2_i <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END); - elsif dsDMA_Cmd_Ack='1' then - dsDMA_Start2_i <= '0'; - dsDMA_Stop2_i <= dsDMA_Stop2_i; - else - dsDMA_Start2_i <= dsDMA_Start2_i; - dsDMA_Stop2_i <= dsDMA_Stop2_i; - end if; - - end if; - end process; - - ------------------------------------------------------------------------- --- Reset signals -- ------------------------------------------------------------------------- - --- -------------------------------------- --- Identification: Command_is_Reset --- - Synch_Capture_Command_is_Reset: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - Command_is_Reset_Hi <= '0'; - Command_is_Reset_Lo <= '0'; - - elsif trn_clk'event and trn_clk = '1' then - if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1+32 downto 32)=C_CHANNEL_RST_BITS then - Command_is_Reset_Hi <= '1'; - else - Command_is_Reset_Hi <= '0'; - end if; - - if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1 downto 0)=C_CHANNEL_RST_BITS then - Command_is_Reset_Lo <= '1'; - else - Command_is_Reset_Lo <= '0'; - end if; - end if; - end process; - - --- -------------------------------------- --- Identification: Command_is_Host_iClr --- - Synch_Capture_Command_is_Host_iClr: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - Command_is_Host_iClr_Hi <= '0'; - Command_is_Host_iClr_Lo <= '0'; - - elsif trn_clk'event and trn_clk = '1' then - if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1+32 downto 32)=C_HOST_ICLR_BITS then - Command_is_Host_iClr_Hi <= '1'; - else - Command_is_Host_iClr_Hi <= '0'; - end if; - - if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1 downto 0)=C_HOST_ICLR_BITS then - Command_is_Host_iClr_Lo <= '1'; - else - Command_is_Host_iClr_Lo <= '0'; - end if; - end if; - end process; - -------------------------------------------- --- Synchronous output: usDMA_Channel_Rst_i --- - Syn_Output_usDMA_Channel_Rst: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - usDMA_Channel_Rst_i <= '1'; - elsif trn_clk'event and trn_clk = '1' then - - usDMA_Channel_Rst_i <= (Regs_Wr_dma_V_Hi_r2 - and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL) --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32) - and Command_is_Reset_Hi - ) - or (Regs_Wr_dma_V_LO_r2 - and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL) --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID) - and Command_is_Reset_Lo - ) - ; - end if; - end process; - - - -------------------------------------------- --- Synchronous output: dsDMA_Channel_Rst_i --- - Syn_Output_dsDMA_Channel_Rst: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - dsDMA_Channel_Rst_i <= '1'; - elsif trn_clk'event and trn_clk = '1' then - - dsDMA_Channel_Rst_i <= (Regs_Wr_dma_V_Hi_r2 - and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL) --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32) - and Command_is_Reset_Hi - ) - or - (Regs_Wr_dma_V_Lo_r2 - and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL) --- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID) - and Command_is_Reset_Lo - ) - ; - end if; - end process; - - --- ----------------------------------------------- --- Synchronous output: MRd_Channel_Rst_i --- - Syn_Output_MRd_Channel_Rst: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - MRd_Channel_Rst_i <= '1'; - elsif trn_clk'event and trn_clk = '1' then - - MRd_Channel_Rst_i <= Regs_WrEn_r2 - and ( - (Reg_WrMuxer_Hi(CINT_ADDR_MRD_CTRL) - and Command_is_Reset_Hi) - or - (Reg_WrMuxer_Lo(CINT_ADDR_MRD_CTRL) - and Command_is_Reset_Lo) - ) - ; - end if; - end process; - - --- ----------------------------------------------- --- Synchronous output: Tx_Reset_i --- - Syn_Output_Tx_Reset: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - Tx_Reset_i <= '1'; - elsif trn_clk'event and trn_clk = '1' then - - Tx_Reset_i <= Regs_WrEn_r2 - and ((Reg_WrMuxer_Hi(CINT_ADDR_TX_CTRL) - and Command_is_Reset_Hi) - or (Reg_WrMuxer_Lo(CINT_ADDR_TX_CTRL) - and Command_is_Reset_Lo)) - ; - end if; - end process; - - --- ----------------------------------------------- --- Synchronous output: eb_FIFO_Rst_i --- - Syn_Output_eb_FIFO_Rst: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - eb_FIFO_Rst_i <= '1'; - eb_FIFO_Rst_b3 <= '1'; - eb_FIFO_Rst_b2 <= '1'; - eb_FIFO_Rst_b1 <= '1'; - elsif trn_clk'event and trn_clk = '1' then - - eb_FIFO_Rst_i <= eb_FIFO_Rst_b1 or eb_FIFO_Rst_b2 or eb_FIFO_Rst_b3; - eb_FIFO_Rst_b3 <= eb_FIFO_Rst_b2; - eb_FIFO_Rst_b2 <= eb_FIFO_Rst_b1; - eb_FIFO_Rst_b1 <= Regs_WrEn_r2 - and ((Reg_WrMuxer_Hi(CINT_ADDR_EB_STACON) - and Command_is_Reset_Hi) - or (Reg_WrMuxer_Lo(CINT_ADDR_EB_STACON) - and Command_is_Reset_Lo)) - ; - end if; - end process; - - --- ----------------------------------------------- --- Synchronous output: protocol_rst --- --- !!! reset by trn_reset_n !!! --- - Syn_Output_protocol_rst: - process ( trn_clk, trn_reset_n) - begin - if trn_reset_n = '0' then - protocol_rst_i <= '1'; - protocol_rst_b1 <= '1'; - protocol_rst_b2 <= '1'; - elsif trn_clk'event and trn_clk = '1' then - - protocol_rst_i <= protocol_rst_b1 or protocol_rst_b2; - protocol_rst_b1 <= protocol_rst_b2; - protocol_rst_b2 <= Regs_WrEn_r2 - and ((Reg_WrMuxer_Hi(CINT_ADDR_PROTOCOL_STACON) - and Command_is_Reset_Hi) - or (Reg_WrMuxer_Lo(CINT_ADDR_PROTOCOL_STACON) - and Command_is_Reset_Lo)) - ; - end if; - end process; - - --- ----------------------------------------------- --- Synchronous Calculation: DMA_us_Transf_Bytes --- - Syn_Calc_DMA_us_Transf_Bytes: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - DMA_us_Transf_Bytes_i <= (OTHERS=>'0'); - elsif trn_clk'event and trn_clk = '1' then - - if usDMA_Channel_Rst_i='1' then - DMA_us_Transf_Bytes_i <= (OTHERS=>'0'); - elsif us_DMA_Bytes_Add='1' then - DMA_us_Transf_Bytes_i(32-1 downto 0) - <= DMA_us_Transf_Bytes_i(32-1 downto 0) - + us_DMA_Bytes; - else - DMA_us_Transf_Bytes_i <= DMA_us_Transf_Bytes_i; - end if; - end if; - end process; - - --- ----------------------------------------------- --- Synchronous Calculation: DMA_ds_Transf_Bytes --- - Syn_Calc_DMA_ds_Transf_Bytes: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - DMA_ds_Transf_Bytes_i <= (OTHERS=>'0'); - elsif trn_clk'event and trn_clk = '1' then - - if dsDMA_Channel_Rst_i='1' then - DMA_ds_Transf_Bytes_i <= (OTHERS=>'0'); - elsif ds_DMA_Bytes_Add='1' then - DMA_ds_Transf_Bytes_i(32-1 downto 0) - <= DMA_ds_Transf_Bytes_i(32-1 downto 0) - + ds_DMA_Bytes; - else - DMA_ds_Transf_Bytes_i <= DMA_ds_Transf_Bytes_i; - end if; - end if; - end process; - ----- ------------------------------------------------------- ----- Synchronous Registers: icap_Write_i --- RxTrn_icap_Write: --- process ( trn_clk, trn_lnk_up_n) --- begin --- if trn_lnk_up_n = '1' then --- icap_CLK <= '0'; --- icap_I <= (OTHERS => '0'); --- icap_Write <= '1'; --- icap_CE <= '1'; --- FSM_icap <= icapST_Reset; --- --- elsif trn_clk'event and trn_clk = '1' then --- --- case FSM_icap is --- --- when icapST_Reset => --- icap_CLK <= '0'; --- icap_I <= (OTHERS => '0'); --- icap_Write <= '1'; --- icap_CE <= '1'; --- FSM_icap <= icapST_Idle; --- --- when icapST_Idle => --- --- if Regs_WrEn_r2='1' and Reg_WrMuxer(CINT_ADDR_ICAP)='1' then --- icap_CLK <= '1'; --- icap_I <= Regs_WrDin_r2; --- icap_Write <= '0'; --- icap_CE <= '0'; --- FSM_icap <= icapST_Access; --- elsif Reg_RdMuxer(CINT_ADDR_ICAP)='1' then --- icap_CLK <= '1'; --- icap_I <= icap_I; --- icap_Write <= '1'; --- icap_CE <= '0'; --- FSM_icap <= icapST_Access; --- else --- icap_CLK <= icap_CLK; --- icap_I <= icap_I; --- icap_Write <= icap_Write; --- icap_CE <= icap_CE; --- FSM_icap <= icapST_Idle; --- end if; --- --- --- when icapST_Access => --- icap_CLK <= '1'; --- icap_I <= icap_I; --- icap_Write <= icap_Write; --- icap_CE <= icap_CE; --- FSM_icap <= icapST_Abort; --- --- when icapST_Abort => --- icap_CLK <= '0'; --- icap_I <= icap_I; --- icap_Write <= icap_Write; --- icap_CE <= icap_CE; --- FSM_icap <= icapST_Idle; --- --- when Others => --- icap_CLK <= '0'; --- icap_I <= (OTHERS => '0'); --- icap_Write <= '1'; --- icap_CE <= '1'; --- FSM_icap <= icapST_Idle; --- --- end case; --- --- end if; --- end process; --- - - ----------------------------------------------------------- ---------------- Tx reading registers ------------------- ----------------------------------------------------------- - ----------------------------------------------------------- --- Synch Register: Read Selection --- - Tx_DMA_Reg_RdMuxer: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - Reg_RdMuxer_Hi <= (Others =>'0'); - Reg_RdMuxer_Lo <= (Others =>'0'); - - elsif trn_clk'event and trn_clk = '1' then - - FOR k IN 0 TO C_NUM_OF_ADDRESSES-1 LOOP - if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)= C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) - and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k, C_DECODE_BIT_BOT-2) - and Regs_RdAddr_i(2-1 downto 0)="00" - then - Reg_RdMuxer_Hi(k) <= '1'; - else - Reg_RdMuxer_Hi(k) <= '0'; - end if; - END LOOP; - - if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)= C_ALL_ONES(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) - and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2)=C_ALL_ONES(C_DECODE_BIT_BOT-1 downto 2) - and Regs_RdAddr_i(2-1 downto 0)="00" - then - Reg_RdMuxer_Lo(0) <= '1'; - else - Reg_RdMuxer_Lo(0) <= '0'; - end if; - FOR k IN 1 TO C_NUM_OF_ADDRESSES-1 LOOP - if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)= C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) - and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k-1, C_DECODE_BIT_BOT-2) - and Regs_RdAddr_i(2-1 downto 0)="00" - then - Reg_RdMuxer_Lo(k) <= '1'; - else - Reg_RdMuxer_Lo(k) <= '0'; - end if; - END LOOP; - - end if; - end process; - - ----------------------------------------------------------- --- Synch Register: CTL_TTake --- - Syn_CTL_ttake: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - ctl_ttake_i <= '0'; - ctl_t_read_Hi_r1 <= '0'; - ctl_t_read_Lo_r1 <= '0'; - CTL_read_counter <= (OTHERS=>'0'); - - elsif trn_clk'event and trn_clk = '1' then - ctl_t_read_Hi_r1 <= Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS); - ctl_t_read_Lo_r1 <= Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS); - ctl_ttake_i <= (Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS) and not ctl_t_read_Hi_r1) - or (Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS) and not ctl_t_read_Lo_r1) - ; - if ctl_reset_i='1' then - CTL_read_counter <= (OTHERS=>'0'); - else - CTL_read_counter <= CTL_read_counter + ctl_ttake_i; - end if; - - end if; - end process; - ----------------------------------------------------------- --- Synch Register: class_CTL_Status --- - Syn_class_CTL_Status: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - class_CTL_Status_i <= (OTHERS=>'0'); - - elsif trn_clk'event and trn_clk = '1' then - class_CTL_Status_i(C_DBUS_WIDTH/2-1 downto 0) <= ctl_status; - - end if; - end process; - - --- ------------------------------------------------------- --- - Sys_Int_Status_i <= ( - CINT_BIT_DLM_IN_ISR => DLM_irq , - CINT_BIT_CTL_IN_ISR => CTL_irq , - CINT_BIT_DAQ_IN_ISR => DAQ_irq , - - CINT_BIT_DSTOUT_IN_ISR => DMA_ds_Tout , - CINT_BIT_USTOUT_IN_ISR => DMA_us_Tout , - - CINT_BIT_INTGEN_IN_ISR => IG_Asserting, - CINT_BIT_DS_DONE_IN_ISR => DMA_ds_Done , - CINT_BIT_US_DONE_IN_ISR => DMA_us_Done , - OTHERS => '0' - ); - - -------------------------------------------------------------------------- - -- Upstream Registers - -------------------------------------------------------------------------- - - -- Peripheral Address Start point - DMA_us_PA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) - <= DMA_us_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_PAH)='1' - else (Others=>'0'); - - DMA_us_PA_o_Hi(C_DBUS_WIDTH/2-1 downto 0) - <= DMA_us_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_PAL)='1' - else (Others=>'0'); - - - -- Host Address Start point - DMA_us_HA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) - <= DMA_us_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_HAH)='1' - else (Others=>'0'); - - DMA_us_HA_o_Hi(C_DBUS_WIDTH/2-1 downto 0) - <= DMA_us_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_HAL)='1' - else (Others=>'0'); - - - -- Next Descriptor Address - DMA_us_BDA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) - <= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_BDAH)='1' - else (Others=>'0'); - - DMA_us_BDA_o_Hi(C_DBUS_WIDTH/2-1 downto 0) - <= DMA_us_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_BDAL)='1' - else (Others=>'0'); - - -- Length - DMA_us_Length_o_Hi(32-1 downto 0) - <= DMA_us_Length_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_LENG)='1' - else (Others=>'0'); - - -- Control word - DMA_us_Control_o_Hi(32-1 downto 0) - <= DMA_us_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1' - else (Others=>'0'); - - -- Status (Read only) - DMA_us_Status_o_Hi(32-1 downto 0) - <= DMA_us_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_STA)='1' - else (Others=>'0'); - - -- Tranferred bytes (Read only) - DMA_us_Transf_Bytes_o_Hi(32-1 downto 0) - <= DMA_us_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_US_TRANSF_BC)='1' - else (Others=>'0'); - - - -- Peripheral Address Start point - DMA_us_PA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) - <= DMA_us_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_PAH)='1' - else (Others=>'0'); - - DMA_us_PA_o_Lo(C_DBUS_WIDTH/2-1 downto 0) - <= DMA_us_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_PAL)='1' - else (Others=>'0'); - - - -- Host Address Start point - DMA_us_HA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) - <= DMA_us_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_HAH)='1' - else (Others=>'0'); - - DMA_us_HA_o_Lo(C_DBUS_WIDTH/2-1 downto 0) - <= DMA_us_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_HAL)='1' - else (Others=>'0'); - - - -- Next Descriptor Address - DMA_us_BDA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) - <= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_BDAH)='1' - else (Others=>'0'); - - DMA_us_BDA_o_Lo(C_DBUS_WIDTH/2-1 downto 0) - <= DMA_us_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_BDAL)='1' - else (Others=>'0'); - - -- Length - DMA_us_Length_o_Lo(32-1 downto 0) - <= DMA_us_Length_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_LENG)='1' - else (Others=>'0'); - - -- Control word - DMA_us_Control_o_Lo(32-1 downto 0) - <= DMA_us_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1' - else (Others=>'0'); - - -- Status (Read only) - DMA_us_Status_o_Lo(32-1 downto 0) - <= DMA_us_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_STA)='1' - else (Others=>'0'); - - -- Tranferred bytes (Read only) - DMA_us_Transf_Bytes_o_Lo(32-1 downto 0) - <= DMA_us_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_US_TRANSF_BC)='1' - else (Others=>'0'); - - -------------------------------------------------------------------------- - -- Downstream Registers - -------------------------------------------------------------------------- - - -- Peripheral Address Start point - DMA_ds_PA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) - <= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_PAH)='1' - else (Others=>'0'); - - DMA_ds_PA_o_Hi(C_DBUS_WIDTH/2-1 downto 0) - <= DMA_ds_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_PAL)='1' - else (Others=>'0'); - - -- Host Address Start point - DMA_ds_HA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) - <= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_HAH)='1' - else (Others=>'0'); - - DMA_ds_HA_o_Hi(C_DBUS_WIDTH/2-1 downto 0) - <= DMA_ds_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_HAL)='1' - else (Others=>'0'); - - -- Next Descriptor Address - DMA_ds_BDA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) - <= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_BDAH)='1' - else (Others=>'0'); - - DMA_ds_BDA_o_Hi(C_DBUS_WIDTH/2-1 downto 0) - <= DMA_ds_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_BDAL)='1' - else (Others=>'0'); - - -- Length - DMA_ds_Length_o_Hi(32-1 downto 0) - <= DMA_ds_Length_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_LENG)='1' - else (Others=>'0'); - - -- Control word - DMA_ds_Control_o_Hi(32-1 downto 0) - <= DMA_ds_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1' - else (Others=>'0'); - - -- Status (Read only) - DMA_ds_Status_o_Hi(32-1 downto 0) - <= DMA_ds_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_STA)='1' - else (Others=>'0'); - - -- Tranferred bytes (Read only) - DMA_ds_Transf_Bytes_o_Hi(32-1 downto 0) - <= DMA_ds_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DS_TRANSF_BC)='1' - else (Others=>'0'); - - -- Peripheral Address Start point - DMA_ds_PA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) - <= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_PAH)='1' - else (Others=>'0'); - - DMA_ds_PA_o_Lo(C_DBUS_WIDTH/2-1 downto 0) - <= DMA_ds_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_PAL)='1' - else (Others=>'0'); - - -- Host Address Start point - DMA_ds_HA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) - <= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_HAH)='1' - else (Others=>'0'); - - DMA_ds_HA_o_Lo(C_DBUS_WIDTH/2-1 downto 0) - <= DMA_ds_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_HAL)='1' - else (Others=>'0'); - - -- Next Descriptor Address - DMA_ds_BDA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) - <= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_BDAH)='1' - else (Others=>'0'); - - DMA_ds_BDA_o_Lo(C_DBUS_WIDTH/2-1 downto 0) - <= DMA_ds_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_BDAL)='1' - else (Others=>'0'); - - -- Length - DMA_ds_Length_o_Lo(32-1 downto 0) - <= DMA_ds_Length_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_LENG)='1' - else (Others=>'0'); - - -- Control word - DMA_ds_Control_o_Lo(32-1 downto 0) - <= DMA_ds_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1' - else (Others=>'0'); - - -- Status (Read only) - DMA_ds_Status_o_Lo(32-1 downto 0) - <= DMA_ds_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_STA)='1' - else (Others=>'0'); - - -- Tranferred bytes (Read only) - DMA_ds_Transf_Bytes_o_Lo(32-1 downto 0) - <= DMA_ds_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DS_TRANSF_BC)='1' - else (Others=>'0'); - - - -------------------------------------------------------------------------- - -- CTL - -------------------------------------------------------------------------- - ctl_td_o_Hi(32-1 downto 0) - <= ctl_td_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS)='1' - else (Others=>'0'); - - ctl_td_o_Lo(32-1 downto 0) - <= ctl_td_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS)='1' - else (Others=>'0'); - - -------------------------------------------------------------------------- - -- DLM - -------------------------------------------------------------------------- - dlm_rd_o_Hi(32-1 downto 0) - <= dlm_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DLM_CLASS)='1' - else (Others=>'0'); - - dlm_rd_o_Lo(32-1 downto 0) - <= dlm_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DLM_CLASS)='1' - else (Others=>'0'); - - - -------------------------------------------------------------------------- - -- System Interrupt Status - -------------------------------------------------------------------------- - Sys_Int_Status_o_Hi(32-1 downto 0) - <= (Sys_Int_Status_i(32-1 downto 0) and Sys_Int_Enable_i(32-1 downto 0)) when Reg_RdMuxer_Hi(CINT_ADDR_IRQ_STAT)='1' - else (Others=>'0'); - - Sys_Int_Enable_o_Hi(32-1 downto 0) - <= Sys_Int_Enable_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IRQ_EN)='1' - else (Others=>'0'); - - Sys_Int_Status_o_Lo(32-1 downto 0) - <= (Sys_Int_Status_i(32-1 downto 0) and Sys_Int_Enable_i(32-1 downto 0)) when Reg_RdMuxer_Lo(CINT_ADDR_IRQ_STAT)='1' - else (Others=>'0'); - - Sys_Int_Enable_o_Lo(32-1 downto 0) - <= Sys_Int_Enable_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IRQ_EN)='1' - else (Others=>'0'); - - - -- ---------------------------------------------------------------------------------- - -- ---------------------------------------------------------------------------------- - Gen_IG_Read: if IMP_INT_GENERATOR generate - - -------------------------------------------------------------------------- - -- Interrupt Generator Latency - -------------------------------------------------------------------------- - IG_Latency_o_Hi(32-1 downto 0) - <= IG_Latency_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_LATENCY)='1' - else (Others=>'0'); - - IG_Latency_o_Lo(32-1 downto 0) - <= IG_Latency_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_LATENCY)='1' - else (Others=>'0'); - -------------------------------------------------------------------------- - -- Interrupt Generator Statistics - -------------------------------------------------------------------------- - IG_Num_Assert_o_Hi(32-1 downto 0) - <= IG_Num_Assert_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_NUM_ASSERT)='1' - else (Others=>'0'); - - IG_Num_Deassert_o_Hi(32-1 downto 0) - <= IG_Num_Deassert_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_NUM_DEASSERT)='1' - else (Others=>'0'); - - IG_Num_Assert_o_Lo(32-1 downto 0) - <= IG_Num_Assert_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_NUM_ASSERT)='1' - else (Others=>'0'); - - IG_Num_Deassert_o_Lo(32-1 downto 0) - <= IG_Num_Deassert_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_NUM_DEASSERT)='1' - else (Others=>'0'); - - end generate; - - - NotGen_IG_Read: if not IMP_INT_GENERATOR generate - - IG_Latency_o_Hi(32-1 downto 0) <= (Others=>'0'); - IG_Latency_o_Lo(32-1 downto 0) <= (Others=>'0'); - IG_Num_Assert_o_Hi(32-1 downto 0) <= (Others=>'0'); - IG_Num_Deassert_o_Hi(32-1 downto 0) <= (Others=>'0'); - IG_Num_Assert_o_Lo(32-1 downto 0) <= (Others=>'0'); - IG_Num_Deassert_o_Lo(32-1 downto 0) <= (Others=>'0'); - - end generate; - - - -------------------------------------------------------------------------- - -- System Error - -------------------------------------------------------------------------- - Synch_Sys_Error_i: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - Sys_Error_i <= (OTHERS => '0'); - eb_FIFO_OverWritten <= '0'; - elsif trn_clk'event and trn_clk = '1' then - Sys_Error_i(CINT_BIT_TX_TOUT_IN_SER) <= Tx_TimeOut; - Sys_Error_i(CINT_BIT_EB_TOUT_IN_SER) <= Tx_eb_TimeOut; - Sys_Error_i(CINT_BIT_EB_OVERWRITTEN) <= eb_FIFO_OverWritten; - -- !!!!!!!!!!!!!! capture eb_FIFO overflow, temp cleared by MRd_Channel_Rst_i - eb_FIFO_OverWritten <= (not MRd_Channel_Rst_i) and (eb_FIFO_ow or eb_FIFO_OverWritten); - end if; - end process; - - - -------------------------------------------------------------------------- - -- General Status and Control - -------------------------------------------------------------------------- - Synch_General_Status_i: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - General_Status_i <= (OTHERS => '0'); - elsif trn_clk'event and trn_clk = '1' then - General_Status_i(32-1 downto 32-16) - <= cfg_dcommand; - General_Status_i(CINT_BIT_LWIDTH_IN_GSR_TOP downto CINT_BIT_LWIDTH_IN_GSR_BOT) - <= pcie_link_width; - General_Status_i(CINT_BIT_ICAP_BUSY_IN_GSR) - <= icap_Busy; - General_Status_i(CINT_BIT_DG_AVAIL_IN_GSR) - <= DG_is_Available; - General_Status_i(CINT_BIT_LINK_ACT_IN_GSR+1 downto CINT_BIT_LINK_ACT_IN_GSR) - <= protocol_link_act; - --- General_Status_i(8) <= CTL_read_counter(6-1); ---- DEBUG !!! - end if; - end process; - - - - Sys_Error_o_Hi(32-1 downto 0) - <= Sys_Error_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_ERROR)='1' - else (Others=>'0'); - - General_Status_o_Hi(32-1 downto 0) - <= General_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_STATUS)='1' - else (Others=>'0'); - - General_Control_o_Hi(32-1 downto 0) - <= General_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_CONTROL)='1' - else (Others=>'0'); - - Sys_Error_o_Lo(32-1 downto 0) - <= Sys_Error_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_ERROR)='1' - else (Others=>'0'); - - General_Status_o_Lo(32-1 downto 0) - <= General_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_STATUS)='1' - else (Others=>'0'); - - General_Control_o_Lo(32-1 downto 0) - <= General_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_CONTROL)='1' - else (Others=>'0'); - - - -------------------------------------------------------------------------- - -- ICAP - -------------------------------------------------------------------------- - icap_O_o_Hi(32-1 downto 0) - <= icap_O(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_ICAP)='1' - else (Others=>'0'); - - icap_O_o_Lo(32-1 downto 0) - <= icap_O(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_ICAP)='1' - else (Others=>'0'); - - -------------------------------------------------------------------------- - -- FIFO Statuses (read only) - -------------------------------------------------------------------------- - eb_FIFO_Status_o_Hi(32-1 downto 0) - <= eb_FIFO_Status_r1(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_EB_STACON)='1' - else (Others=>'0'); - - eb_FIFO_Status_o_Lo(32-1 downto 0) - <= eb_FIFO_Status_r1(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_EB_STACON)='1' - else (Others=>'0'); - - -------------------------------------------------------------------------- - -- Optical Link Status - -------------------------------------------------------------------------- - Opto_Link_Status_o_Hi(32-1 downto 0) - <= Opto_Link_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_PROTOCOL_STACON)='1' - else (Others=>'0'); - - Opto_link_Status_o_Lo(32-1 downto 0) - <= Opto_Link_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_PROTOCOL_STACON)='1' - else (Others=>'0'); - - -------------------------------------------------------------------------- - -- Class CTL status - -------------------------------------------------------------------------- - class_CTL_Status_o_Hi(32-1 downto 0) - <= class_CTL_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_TC_STATUS)='1' - else (Others=>'0'); - - class_CTL_Status_o_Lo(32-1 downto 0) - <= class_CTL_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_TC_STATUS)='1' - else (Others=>'0'); - - -------------------------------------------------------------------------- - -- Data generator Status - -------------------------------------------------------------------------- - DG_Status_o_Hi(32-1 downto 0) - <= DG_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DG_CTRL)='1' - else (Others=>'0'); - - DG_Status_o_Lo(32-1 downto 0) - <= DG_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DG_CTRL)='1' - else (Others=>'0'); - - -------------------------------------------------------------------------- - -- Hardware version - -------------------------------------------------------------------------- - HW_Version_o_Hi(32-1 downto 0) - <= C_DESIGN_ID(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_VERSION)='1' - else (Others=>'0'); - - HW_Version_o_Lo(32-1 downto 0) - <= C_DESIGN_ID(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_VERSION)='1' - else (Others=>'0'); - ------------------------------------------------------ --- Sequential : Regs_RdQout_i --- - Synch_Regs_RdQout: - process ( trn_clk, trn_lnk_up_n) - begin - if trn_lnk_up_n = '1' then - Regs_RdQout_i <= (OTHERS =>'0'); - - elsif trn_clk'event and trn_clk = '1' then - - Regs_RdQout_i(64-1 downto 32) <= - HW_Version_o_Hi (32-1 downto 0) - - or Sys_Error_o_Hi (32-1 downto 0) - or General_Status_o_Hi (32-1 downto 0) - or General_Control_o_Hi(32-1 downto 0) - - or Sys_Int_Status_o_Hi (32-1 downto 0) - or Sys_Int_Enable_o_Hi (32-1 downto 0) - --- or DMA_us_PA_o_Hi (C_DBUS_WIDTH-1 downto 32) - or DMA_us_PA_o_Hi (32-1 downto 0) - or DMA_us_HA_o_Hi (C_DBUS_WIDTH-1 downto 32) - or DMA_us_HA_o_Hi (32-1 downto 0) - or DMA_us_BDA_o_Hi (C_DBUS_WIDTH-1 downto 32) - or DMA_us_BDA_o_Hi (32-1 downto 0) - or DMA_us_Length_o_Hi (32-1 downto 0) - or DMA_us_Control_o_Hi (32-1 downto 0) - or DMA_us_Status_o_Hi (32-1 downto 0) - or DMA_us_Transf_Bytes_o_Hi (32-1 downto 0) - --- or DMA_ds_PA_o_Hi (C_DBUS_WIDTH-1 downto 32) - or DMA_ds_PA_o_Hi (32-1 downto 0) - or DMA_ds_HA_o_Hi (C_DBUS_WIDTH-1 downto 32) - or DMA_ds_HA_o_Hi (32-1 downto 0) - or DMA_ds_BDA_o_Hi (C_DBUS_WIDTH-1 downto 32) - or DMA_ds_BDA_o_Hi (32-1 downto 0) - or DMA_ds_Length_o_Hi (32-1 downto 0) - or DMA_ds_Control_o_Hi (32-1 downto 0) - or DMA_ds_Status_o_Hi (32-1 downto 0) - or DMA_ds_Transf_Bytes_o_Hi (32-1 downto 0) - - or IG_Latency_o_Hi (32-1 downto 0) - or IG_Num_Assert_o_Hi (32-1 downto 0) - or IG_Num_Deassert_o_Hi(32-1 downto 0) - - or DG_Status_o_Hi (32-1 downto 0) - or class_CTL_Status_o_Hi (32-1 downto 0) - --- or icap_O_o_Hi (32-1 downto 0) - or Opto_Link_Status_o_Hi (32-1 downto 0) - or eb_FIFO_Status_o_Hi (32-1 downto 0) - or dlm_rd_o_Hi - or ctl_td_o_Hi - ; - - - Regs_RdQout_i(32-1 downto 0) <= - HW_Version_o_Lo (32-1 downto 0) - - or Sys_Error_o_Lo (32-1 downto 0) - or General_Status_o_Lo (32-1 downto 0) - or General_Control_o_Lo(32-1 downto 0) - - or Sys_Int_Status_o_Lo (32-1 downto 0) - or Sys_Int_Enable_o_Lo (32-1 downto 0) - --- or DMA_us_PA_o_Lo (C_DBUS_WIDTH-1 downto 32) - or DMA_us_PA_o_Lo (32-1 downto 0) - or DMA_us_HA_o_Lo (C_DBUS_WIDTH-1 downto 32) - or DMA_us_HA_o_Lo (32-1 downto 0) - or DMA_us_BDA_o_Lo (C_DBUS_WIDTH-1 downto 32) - or DMA_us_BDA_o_Lo (32-1 downto 0) - or DMA_us_Length_o_Lo (32-1 downto 0) - or DMA_us_Control_o_Lo (32-1 downto 0) - or DMA_us_Status_o_Lo (32-1 downto 0) - or DMA_us_Transf_Bytes_o_Lo (32-1 downto 0) - --- or DMA_ds_PA_o_Lo (C_DBUS_WIDTH-1 downto 32) - or DMA_ds_PA_o_Lo (32-1 downto 0) - or DMA_ds_HA_o_Lo (C_DBUS_WIDTH-1 downto 32) - or DMA_ds_HA_o_Lo (32-1 downto 0) - or DMA_ds_BDA_o_Lo (C_DBUS_WIDTH-1 downto 32) - or DMA_ds_BDA_o_Lo (32-1 downto 0) - or DMA_ds_Length_o_Lo (32-1 downto 0) - or DMA_ds_Control_o_Lo (32-1 downto 0) - or DMA_ds_Status_o_Lo (32-1 downto 0) - or DMA_ds_Transf_Bytes_o_Lo (32-1 downto 0) - - or IG_Latency_o_Lo (32-1 downto 0) - or IG_Num_Assert_o_Lo (32-1 downto 0) - or IG_Num_Deassert_o_Lo(32-1 downto 0) - - or DG_Status_o_Lo (32-1 downto 0) - or class_CTL_Status_o_Lo (32-1 downto 0) - --- or icap_O_o_Lo(32-1 downto 0) - or Opto_Link_Status_o_Lo (32-1 downto 0) - or eb_FIFO_Status_o_Lo (32-1 downto 0) - or dlm_rd_o_Lo - or ctl_td_o_Lo - ; - - end if; - end process; - - --- ----------------------------------------------------------------------------- --- -- Implementation codes --- ----------------------------------------------------------------------------- --- Gen_ICAP_width_8: --- if C_ICAP_WIDTH=8 generate --- --- ICAP_VIRTEX4_pcie : --- ICAP_VIRTEX4 --- generic map ( --- ICAP_WIDTH => "X8" -- "X8" or "X32" --- ) --- port map ( --- BUSY => icap_BUSY , -- Busy output --- O => icap_O , -- 8-bit data output --- CE => icap_CE , -- Clock enable input --- CLK => icap_CLK , -- Clock input --- I => icap_I , -- 8-bit data input --- WRITE => icap_WRITE -- Write input --- ); --- --- end generate; --- --- Gen_ICAP_width_32: --- if C_ICAP_WIDTH=32 generate --- --- ICAP_VIRTEX4_pcie : --- ICAP_VIRTEX4 --- generic map ( --- ICAP_WIDTH => "X32" -- "X8" or "X32" --- ) --- port map ( --- BUSY => icap_BUSY , -- Busy output --- O => icap_O , -- 32-bit data output --- CE => icap_CE , -- Clock enable input --- CLK => icap_CLK , -- Clock input --- I => icap_I , -- 32-bit data input --- WRITE => icap_WRITE -- Write input --- ); --- --- end generate; --- - -end Behavioral; Index: branches/Virtex6/ML605/DMA_Calculate.vhd =================================================================== --- branches/Virtex6/ML605/DMA_Calculate.vhd (revision 9) +++ branches/Virtex6/ML605/DMA_Calculate.vhd (nonexistent) @@ -1,1024 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Design Name: --- Module Name: DMA_Calculate - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision 1.20 - Taken out from the original version. 26.07.2007 --- --- Revision 1.10 - Msg inserted. 26.02.2007 --- --- Revision 1.00 - Created. 09.02.2007 --- --- Additional Comments: --- ----------------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.abb64Package.all; - - --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity DMA_Calculate is - port ( - -- Downstream Registers from MWr Channel - DMA_PA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- EP (local) - DMA_HA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- Host (remote) - DMA_BDA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); - DMA_Length : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); - DMA_Control : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - -- Calculation in advance, for better timing - HA_is_64b : IN std_logic; - BDA_is_64b : IN std_logic; - - -- Calculation in advance, for better timing - Leng_Hi19b_True : IN std_logic; - Leng_Lo7b_True : IN std_logic; - - - -- Parameters fed to DMA_FSM - DMA_PA_Loaded : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0); - DMA_PA_Var : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0); - DMA_HA_Var : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - DMA_BDA_fsm : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0); - BDA_is_64b_fsm : OUT std_logic; - - - DMA_Snout_Length : OUT std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0); - DMA_Body_Length : OUT std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0); - DMA_Tail_Length : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0); - - -- Only for downstream channel - DMA_PA_Snout : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0); - DMA_BAR_Number : OUT std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0); - - -- Engine control signals - DMA_Start : IN std_logic; - DMA_Start2 : IN std_logic; -- out of consecutive dex - - -- Control signals to FSM - No_More_Bodies : OUT std_logic; -- No more block(s) of Max_Size - ThereIs_Snout : OUT std_logic; -- 1st packet before Body blocks - ThereIs_Body : OUT std_logic; -- Block(s) of Max_Size - ThereIs_Tail : OUT std_logic; -- Last packet with size less than Max_Size - ThereIs_Dex : OUT std_logic; -- Not the last descriptor - HA64bit : OUT std_logic; -- Host Address is 64-bit - Addr_Inc : OUT std_logic; -- Peripheral Address increase token - - - -- FSM indicators - State_Is_LoadParam : IN std_logic; - State_Is_Snout : IN std_logic; - State_Is_Body : IN std_logic; --- State_Is_Tail : IN std_logic; - - - -- Additional - Param_Max_Cfg : IN std_logic_vector(2 downto 0); - - -- Common ports - dma_clk : IN std_logic; - dma_reset : IN std_logic - ); - -end entity DMA_Calculate; - - - -architecture Behavioral of DMA_Calculate is - - -- Significant bits from the MaXSiZe parameter - signal Max_TLP_Size : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0); - - signal mxsz_left : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT); - signal mxsz_mid : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT); - signal mxsz_right : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT); - - -- Signals masked by MaxSize - signal DMA_Leng_Left_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT); - signal DMA_Leng_Mid_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT); - signal DMA_Leng_Right_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT); - - -- Alias - signal Lo_Leng_Left_Msk_is_True : std_logic; - signal Lo_Leng_Mid_Msk_is_True : std_logic; - signal Lo_Leng_Right_Msk_is_True : std_logic; - - -- Masked values of HA and Length - signal DMA_HA_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0); - signal DMA_Length_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0); - - - -- Indicates whether the DMA_PA is already accepted - signal PA_is_taken : std_logic; - - -- Calculation for the PA of the next DMA, if UPA bit = 0 - signal DMA_PA_next : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_PA_current : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - -- eventual PA parameter for the current DMA transaction - signal DMA_PA_Loaded_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - -- Calculation in advance, only for better timing - signal Carry_PA_plus_Leng : std_logic_vector(CBIT_CARRY downto 0); - signal Carry_PAx_plus_Leng : std_logic_vector(CBIT_CARRY downto 0); - signal Leng_Hi_plus_PA_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto CBIT_CARRY); - signal Leng_Hi_plus_PAx_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto CBIT_CARRY); - - -- DMA parameters from the register module - signal DMA_PA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_HA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_BDA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_Length_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - -- delay - signal State_Is_Snout_r1 : std_logic; - signal State_Is_Body_r1 : std_logic; - - -- from control word - signal Dex_is_Last : std_logic; - signal Engine_Ends : std_logic; - - -- Major FSM control signals - signal ThereIs_Snout_i : std_logic; - signal ThereIs_Body_i : std_logic; - signal ThereIs_Tail_i : std_logic; - signal Snout_Only : std_logic; - - signal ThereIs_Dex_i : std_logic; - signal No_More_Bodies_i : std_logic; - - -- Address/Length combination - signal ALc : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0); - -- Compressed ALc - -- ALc_B bit means the ALc has carry in, making an extra Body block. - signal ALc_B : std_logic; - signal ALc_B_wire : std_logic; - -- ALc_T bit means the ALc has trailer, making a final Tail block. - signal ALc_T : std_logic; - signal ALc_T_wire : std_logic; - - -- Compressed Length - -- Leng_Two bit means Length >= 2 Max_Size. - signal Leng_Two : std_logic; - -- Leng_One bit means Length >= 1 Max_Size. - signal Leng_One : std_logic; - -- Leng_nint bit means Length is not integral of Max_Sizes. - signal Leng_nint : std_logic; - - - signal Length_analysis : std_logic_vector(2 downto 0); - signal Snout_Body_Tail : std_logic_vector(2 downto 0); - - -- Byte counter - signal DMA_Byte_Counter : std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- !!! Elastic - signal Length_minus : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_BC_Carry : std_logic_vector(CBIT_CARRY downto 0); - - -- Remote & Local Address variable - signal DMA_HA_Var_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal DMA_HA_Carry32 : std_logic_vector(C_DBUS_WIDTH/2 downto 0); - signal DMA_PA_Var_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - - -- BDA parameter is buffered for FSM module - signal DMA_BDA_fsm_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal BDA_is_64b_fsm_i : std_logic; - - -- Token bits out of Control word - signal HA64bit_i : std_logic; - signal Addr_Inc_i : std_logic; - signal use_PA : std_logic; - - -- for better timing - signal HA_gap : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0); - - -- - signal DMA_Snout_Length_i : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0); - signal DMA_Tail_Length_i : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0); - -- for better timing - signal raw_Tail_Length : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0); - - signal DMA_PA_Snout_Carry : std_logic_vector(CBIT_CARRY downto 0); - signal DMA_PA_Body_Carry : std_logic_vector(CBIT_CARRY downto 0); - - signal DMA_BAR_Number_i : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0); - -begin - - -- Partition indicators - No_More_Bodies <= No_More_Bodies_i ; - ThereIs_Snout <= ThereIs_Snout_i ; - ThereIs_Body <= ThereIs_Body_i ; - ThereIs_Tail <= ThereIs_Tail_i ; - ThereIs_Dex <= ThereIs_Dex_i ; - HA64bit <= HA64bit_i ; - Addr_Inc <= Addr_Inc_i ; - - -- - DMA_PA_Loaded <= DMA_PA_Loaded_i ; - DMA_PA_Var <= DMA_PA_Var_i ; - DMA_HA_Var <= DMA_HA_Var_i ; - DMA_BDA_fsm <= DMA_BDA_fsm_i ; - BDA_is_64b_fsm <= BDA_is_64b_fsm_i; - - -- Only for downstream channel - DMA_PA_Snout <= DMA_PA_current(C_DBUS_WIDTH-1 downto 0); - DMA_BAR_Number <= DMA_BAR_Number_i; - - -- different lengths - DMA_Snout_Length <= DMA_Snout_Length_i ; - DMA_Body_Length <= Max_TLP_Size ; - DMA_Tail_Length <= DMA_Tail_Length_i ; - - - -- Register stubs - DMA_PA_i <= DMA_PA; - DMA_HA_i <= DMA_HA; - DMA_BDA_i <= DMA_BDA; - DMA_Length_i <= DMA_Length; - DMA_Control_i <= DMA_Control; - - - --- --------------------------------------------------------------- --- Parameters should be captured by the start/start2 and be kept --- in case Pause command comes. --- - Syn_Param_Capture: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - Addr_Inc_i <= '0'; - use_PA <= '0'; - Dex_is_Last <= '0'; - Engine_Ends <= '1'; - DMA_BAR_Number_i <= (OTHERS=>'0'); - - DMA_BDA_fsm_i <= (OTHERS=>'0'); - BDA_is_64b_fsm_i <= '0'; - - elsif dma_clk'event and dma_clk = '1' then - - if DMA_Start ='1' or DMA_Start2 ='1' then - Addr_Inc_i <= DMA_Control_i(CINT_BIT_DMA_CTRL_AINC); - use_PA <= DMA_Control_i(CINT_BIT_DMA_CTRL_UPA); - Dex_is_Last <= DMA_Control_i(CINT_BIT_DMA_CTRL_LAST); - Engine_Ends <= DMA_Control_i(CINT_BIT_DMA_CTRL_END); - DMA_BAR_Number_i <= DMA_Control_i(CINT_BIT_DMA_CTRL_BAR_TOP downto CINT_BIT_DMA_CTRL_BAR_BOT); - - DMA_BDA_fsm_i <= DMA_BDA_i ; - BDA_is_64b_fsm_i <= BDA_is_64b ; - else - Addr_Inc_i <= Addr_Inc_i ; - use_PA <= use_PA ; - Dex_is_Last <= Dex_is_Last ; - Engine_Ends <= Engine_Ends ; - DMA_BAR_Number_i <= DMA_BAR_Number_i; - - DMA_BDA_fsm_i <= DMA_BDA_fsm_i ; - BDA_is_64b_fsm_i <= BDA_is_64b_fsm_i ; - end if; - - end if; - end process; - --- Addr_Inc_i <= DMA_Control_i(CINT_BIT_DMA_CTRL_AINC); --- use_PA <= DMA_Control_i(CINT_BIT_DMA_CTRL_UPA); --- Dex_is_Last <= DMA_Control_i(CINT_BIT_DMA_CTRL_LAST); --- Engine_Ends <= DMA_Control_i(CINT_BIT_DMA_CTRL_END); --- use_Irpt_Done <= not DMA_Control_i(CINT_BIT_DMA_CTRL_EDI); - - - -- Means there is consecutive descriptor(s) - ThereIs_Dex_i <= not Dex_is_Last and not Engine_Ends; - - --- --------------------------------------------------------------- --- PA_i selection --- - Syn_Calc_DMA_PA: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - DMA_PA_current <= (Others=>'0'); --- DMA_BAR_Number_i <= (Others=>'0'); - PA_is_taken <= '0'; - - elsif dma_clk'event and dma_clk = '1' then - - if DMA_Start = '1' and PA_is_taken='0' then - DMA_PA_current <= DMA_PA_i(C_DBUS_WIDTH-1 downto 2) &"00"; - PA_is_taken <= '1'; - elsif DMA_Start2 = '1' and PA_is_taken='0' and DMA_Control_i(CINT_BIT_DMA_CTRL_UPA) = '1' then - DMA_PA_current <= DMA_PA_i(C_DBUS_WIDTH-1 downto 2) &"00"; - PA_is_taken <= '1'; - elsif DMA_Start2 = '1' and PA_is_taken='0' and DMA_Control_i(CINT_BIT_DMA_CTRL_UPA) = '0' then - DMA_PA_current(C_DBUS_WIDTH-1 downto 0) <= DMA_PA_next; - PA_is_taken <= '1'; - else - DMA_PA_current <= DMA_PA_current; - if DMA_Start='0' and DMA_Start2='0' then - PA_is_taken <= '0'; - else - PA_is_taken <= PA_is_taken; - end if; - end if; - - end if; - - end process; - - --- --------------------------------------------------------------- --- PA_next Calculation --- - Syn_Calc_DMA_PA_next: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - DMA_PA_next <= (Others=>'0'); - - elsif dma_clk'event and dma_clk = '1' then - - if DMA_Start = '1' and PA_is_taken='0' then - if DMA_Control_i(CINT_BIT_DMA_CTRL_AINC) = '1' then - DMA_PA_next(CBIT_CARRY-1 downto 0) <= Carry_PA_plus_Leng(CBIT_CARRY-1 downto 0); - DMA_PA_next(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= Leng_Hi_plus_PA_Hi - + Carry_PA_plus_Leng(CBIT_CARRY); - else - DMA_PA_next <= DMA_PA_i(C_DBUS_WIDTH-1 downto 2) &"00"; - end if; - - elsif DMA_Start2 = '1' and PA_is_taken='0' then - if DMA_Control_i(CINT_BIT_DMA_CTRL_AINC) = '1' then - DMA_PA_next(CBIT_CARRY-1 downto 0) <= Carry_PAx_plus_Leng(CBIT_CARRY-1 downto 0); - DMA_PA_next(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= Leng_Hi_plus_PAx_Hi - + Carry_PAx_plus_Leng(CBIT_CARRY); - else - DMA_PA_next <= DMA_PA_next; - end if; - else - DMA_PA_next <= DMA_PA_next; - end if; - - end if; - - end process; - - --- --------------------------------------------------------------- --- Carry_PA_plus_Leng(16 downto 0) --- - Syn_Calc_Carry_PA_plus_Leng: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - Carry_PA_plus_Leng <= (Others=>'0'); - - elsif dma_clk'event and dma_clk = '1' then - Carry_PA_plus_Leng <= ('0'& DMA_PA_i(CBIT_CARRY-1 downto 2) &"00") - + ('0'& DMA_Length_i(CBIT_CARRY-1 downto 2) &"00"); - end if; - - end process; - - --- --------------------------------------------------------------- --- Carry_PAx_plus_Leng(16 downto 0) --- - Syn_Calc_Carry_PAx_plus_Leng: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - Carry_PAx_plus_Leng <= (Others=>'0'); - - elsif dma_clk'event and dma_clk = '1' then - Carry_PAx_plus_Leng <= ('0'& DMA_PA_next (CBIT_CARRY-1 downto 2) &"00") - + ('0'& DMA_Length_i(CBIT_CARRY-1 downto 2) &"00"); - end if; - - end process; - - --- --------------------------------------------------------------- --- Leng_Hi_plus_PA_Hi(31 downto 16) --- - Syn_Calc_Leng_Hi_plus_PA_Hi: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - Leng_Hi_plus_PA_Hi <= (Others=>'0'); - - elsif dma_clk'event and dma_clk = '1' then - Leng_Hi_plus_PA_Hi <= DMA_Length_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) - + DMA_PA_i(C_DBUS_WIDTH-1 downto CBIT_CARRY); - - end if; - - end process; - - --- --------------------------------------------------------------- --- Leng_Hi_plus_PAx_Hi(31 downto 16) --- - Syn_Calc_Leng_Hi_plus_PAx_Hi: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - Leng_Hi_plus_PAx_Hi <= (Others=>'0'); - - elsif dma_clk'event and dma_clk = '1' then - Leng_Hi_plus_PAx_Hi <= DMA_Length_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) - + DMA_PA_next(C_DBUS_WIDTH-1 downto CBIT_CARRY); - - end if; - - end process; - - --- ----------------------------------------------------------------------------------------------------------------------------------- - DMA_Leng_Left_Msk <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_left; - DMA_Leng_Mid_Msk <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_mid; - DMA_Leng_Right_Msk <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right; - --- ----------------------------------------------------------------------------------------------------------------------------------- - DMA_HA_Msk <= (DMA_HA_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right) - & DMA_HA_i(C_MAXSIZE_FLD_BIT_BOT-1 downto 2) - & "00"; - DMA_Length_Msk <= (DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right) - & DMA_Length_i(C_MAXSIZE_FLD_BIT_BOT-1 downto 2) - & "00"; - --- ----------------------------------------------------------------------------------------------------------------------------------- - Lo_Leng_Left_Msk_is_True <= '0' when DMA_Leng_Left_Msk =C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) else '1'; - Lo_Leng_Mid_Msk_is_True <= '0' when DMA_Leng_Mid_Msk =C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) else '1'; - Lo_Leng_Right_Msk_is_True <= '0' when DMA_Leng_Right_Msk=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) else '1'; - - --- ---------------------------------------------------------- --- Synchronous Register: Leng_Info(Compressed Length Information) ---- - Syn_Calc_Parameter_Leng_Info: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - Leng_Two <= '0'; - Leng_One <= '0'; - Leng_nint <= '0'; - - elsif dma_clk'event and dma_clk = '1' then - Leng_Two <= Leng_Hi19b_True or Lo_Leng_Left_Msk_is_True; - Leng_One <= Lo_Leng_Mid_Msk_is_True; - Leng_nint <= Leng_Lo7b_True or Lo_Leng_Right_Msk_is_True; - - end if; - end process; - - --- ----------------------------------------------------------------------------------------------------------------------------------- - ALc_B_wire <= '0' when (ALc(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_mid)=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) - else '1'; - ALc_T_wire <= '0' when (ALc(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right)=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) - and ALc(C_MAXSIZE_FLD_BIT_BOT-1 downto 0)=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_BOT-1 downto 0) - else '1'; --- ----------------------------------------------------------------------------------------------------------------------------------- - --- ------------------------------------------------------- --- Synchronous Register: ALc (Address-Length combination) ---- - Syn_Calc_Parameter_ALc: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - ALc <= (Others=>'0'); - ALc_B <= '0'; - ALc_T <= '0'; - - elsif dma_clk'event and dma_clk = '1' then - - ALc <= DMA_Length_Msk + DMA_HA_Msk; - ALc_B <= ALc_B_wire; - ALc_T <= ALc_T_wire; - - end if; - - end process; - - - -- concatenation of the Length information - Length_analysis <= Leng_Two & Leng_One & Leng_nint; - - -- ------------------------------------------- - -- Analysis on the DMA division - -- truth-table expressions - -- - Comb_S_B_T: - process ( - Length_analysis - , ALc_B - , ALc_T - ) - begin - case Length_analysis is - - -- Zero-length DMA, nothing to send - when "000" => - Snout_Body_Tail <= "000"; - - -- Length < Max_Size. Always Snout and never Body, Tail depends on ALc. - when "001" => - Snout_Body_Tail <= '1' & '0' & (ALc_B and ALc_T); - - -- Length = Max_Size. Division depends only on ALc-Tail. - when "010" => - Snout_Body_Tail <= ALc_T & not ALc_T & ALc_T; - -- Length = (k+1) Max_Size, k>=1. Always Body. Snout and Tail depend on ALc-Tail. - -- Body = Leng_Two or not ALc_T - when "100" => - Snout_Body_Tail <= ALc_T & '1' & ALc_T; - when "110" => - Snout_Body_Tail <= ALc_T & '1' & ALc_T; - - -- Length = (1+d) Max_Size, 0 - Snout_Body_Tail <= '1' & ALc_B & ALc_T; - -- Length = (k+1+d) Max_Size, k>=1, 0 - Snout_Body_Tail <= '1' & '1' & ALc_T; - when "111" => - Snout_Body_Tail <= '1' & '1' & ALc_T; - - -- dealt as zero-length DMA - when Others => - Snout_Body_Tail <= "000"; - - end case; - - end process; - --- ----------------------------------------------- --- Synchronous Register: --- ThereIs_Snout --- ThereIs_Body --- ThereIs_Tail --- - Syn_Calc_Parameters_SBT: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - ThereIs_Snout_i <= '0'; - ThereIs_Body_i <= '0'; - ThereIs_Tail_i <= '0'; - - Snout_Only <= '0'; - - elsif dma_clk'event and dma_clk = '1' then - - ThereIs_Snout_i <= Snout_Body_Tail(2); - ThereIs_Body_i <= Snout_Body_Tail(1); - ThereIs_Tail_i <= Snout_Body_Tail(0); - - Snout_Only <= ALc_T and not Snout_Body_Tail(0); - - end if; - - end process; - - --- ------------------------------------------------------------- --- Synchronous reg: --- HA_gap --- - Syn_Calc_HA_gap: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - HA_gap <= (OTHERS =>'0'); - - elsif dma_clk'event and dma_clk = '1' then - HA_gap <= Max_TLP_Size - DMA_HA_Msk; - end if; - end process; - - --- ------------------------------------------------------------- --- Synchronous reg: --- DMA_PA_Snout_Carry --- - FSM_Calc_DMA_PA_Snout_Carry: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - DMA_PA_Snout_Carry <= (OTHERS =>'0'); - - elsif dma_clk'event and dma_clk = '1' then - DMA_PA_Snout_Carry <= ('0'& DMA_PA_current(CBIT_CARRY-1 downto 0)) + HA_gap; - - end if; - end process; - - --- ------------------------------------------------------------- --- Synchronous reg: --- DMA_PA_Body_Carry --- - FSM_Calc_DMA_PA_Body_Carry: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - DMA_PA_Body_Carry <= (OTHERS =>'0'); - - elsif dma_clk'event and dma_clk = '1' then - DMA_PA_Body_Carry <= ('0'& DMA_PA_Var_i(CBIT_CARRY-1 downto 0)) + Max_TLP_Size; - end if; - end process; - - --- ------------------------------------------------------------------ --- Synchronous Register: Length_minus --- - Sync_Calc_Length_minus: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - Length_minus <= (OTHERS =>'0'); - - elsif dma_clk'event and dma_clk = '1' then - Length_minus <= DMA_Length_i - Max_TLP_Size; - - end if; - end process; - - --- ------------------------------------------------------------- --- Synchronous reg: --- DMA_BC_Carry --- - FSM_Calc_DMA_BC_Carry: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - DMA_BC_Carry <= (OTHERS =>'0'); - - elsif dma_clk'event and dma_clk = '1' then - DMA_BC_Carry <= ('0'& DMA_Byte_Counter(CBIT_CARRY-1 downto 0)) - Max_TLP_Size; - - end if; - end process; - - --- -------------------------------------------- --- Synchronous reg: DMA_Snout_Length --- DMA_Tail_Length --- - FSM_Calc_DMA_Snout_Tail_Lengths: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - DMA_Snout_Length_i <= (OTHERS =>'0'); - DMA_Tail_Length_i <= (OTHERS =>'0'); - raw_Tail_Length <= (OTHERS =>'0'); - - elsif dma_clk'event and dma_clk = '1' then - - DMA_Tail_Length_i(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0) <= (raw_Tail_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto C_MAXSIZE_FLD_BIT_BOT) - and mxsz_right(C_TLP_FLD_WIDTH_OF_LENG+1 downto C_MAXSIZE_FLD_BIT_BOT) - ) & raw_Tail_Length( C_MAXSIZE_FLD_BIT_BOT-1 downto 0); - if State_Is_LoadParam ='1' then - raw_Tail_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0) <= DMA_Length_Msk(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0) - + DMA_HA_Msk(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0); - if Snout_Only='1' then - DMA_Snout_Length_i <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto 2) &"00"; - else - DMA_Snout_Length_i <= Max_TLP_Size - DMA_HA_Msk; - end if; - - else - DMA_Snout_Length_i <= DMA_Snout_Length_i; - raw_Tail_Length <= raw_Tail_Length; - - end if; - - end if; - end process; - - --- ------------------------------------------------------------- --- Synchronous Delays: --- State_Is_Snout_r1 --- State_Is_Body_r1 --- - Syn_Delay_State_is_x: - process ( dma_clk ) - begin - if dma_clk'event and dma_clk = '1' then - State_Is_Snout_r1 <= State_Is_Snout; - State_Is_Body_r1 <= State_Is_Body; - end if; - - end process; - - --- ------------------------------------------------------------- --- Synchronous reg: --- DMA_HA_Carry32 --- - FSM_Calc_DMA_HA_Carry32: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - DMA_HA_Carry32 <= (OTHERS =>'0'); - - elsif dma_clk'event and dma_clk = '1' then - - if State_Is_LoadParam = '1' then - DMA_HA_Carry32 <= '0' & DMA_HA_i(C_DBUS_WIDTH/2-1 downto 2) & "00"; -- temp - - elsif State_Is_Snout = '1' or State_Is_Body = '1' then - DMA_HA_Carry32(C_DBUS_WIDTH/2 downto C_MAXSIZE_FLD_BIT_BOT) <= ('0'& DMA_HA_Var_i(C_DBUS_WIDTH/2-1 downto C_MAXSIZE_FLD_BIT_TOP+1) & - (DMA_HA_Var_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and not mxsz_right) - ) + mxsz_mid; - - else - DMA_HA_Carry32 <= DMA_HA_Carry32; - - end if; - - end if; - end process; - - - --- ------------------------------------------------------------- --- Synchronous reg: --- DMA_HA_Var --- - FSM_Calc_DMA_HA_Var: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - DMA_HA_Var_i <= (OTHERS =>'0'); - - elsif dma_clk'event and dma_clk = '1' then - - if State_Is_LoadParam = '1' then - DMA_HA_Var_i <= DMA_HA_i(C_DBUS_WIDTH-1 downto 2) & "00"; -- temp - - elsif State_Is_Snout_r1 = '1' or State_Is_Body_r1 = '1' then --- elsif State_Is_Snout = '1' or State_Is_Body = '1' then - DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) <= DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) - + DMA_HA_Carry32(C_DBUS_WIDTH/2); - - DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_BOT) <= (DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1) - & (DMA_HA_Var_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and not mxsz_right)) - + mxsz_mid; - DMA_HA_Var_i(C_MAXSIZE_FLD_BIT_BOT-1 downto 0) <= (Others => '0'); -- MaxSize aligned - - else - DMA_HA_Var_i <= DMA_HA_Var_i; - - end if; - - end if; - end process; - - --- ------------------------------------------------------------- --- Synchronous reg: --- HA64bit --- - FSM_Calc_HA64bit: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - HA64bit_i <= '0'; - - elsif dma_clk'event and dma_clk = '1' then - - if State_Is_LoadParam = '1' then - HA64bit_i <= HA_is_64b; - elsif DMA_HA_Carry32(C_DBUS_WIDTH/2) = '1' then - HA64bit_i <= '1'; - else - HA64bit_i <= HA64bit_i; - end if; - - end if; - end process; - - --- ------------------------------------------------------------- --- Synchronous reg: --- DMA_PA_Var --- - FSM_Calc_DMA_PA_Var: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - DMA_PA_Var_i <= (OTHERS =>'0'); - - elsif dma_clk'event and dma_clk = '1' then - - if State_Is_LoadParam = '1' then - if Addr_Inc_i='1' and ThereIs_Snout_i='1' then - DMA_PA_Var_i(CBIT_CARRY-1 downto 0) <= DMA_PA_current(CBIT_CARRY-1 downto 0) - + HA_gap(C_MAXSIZE_FLD_BIT_TOP downto 0); - DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_PA_current(C_DBUS_WIDTH-1 downto CBIT_CARRY); - else - DMA_PA_Var_i(C_DBUS_WIDTH-1 downto 0) <= DMA_PA_current(C_DBUS_WIDTH-1 downto 0); - end if; - - elsif State_Is_Snout_r1 = '1' then ----- elsif State_Is_Snout = '1' then - if Addr_Inc_i= '1' then - DMA_PA_Var_i(CBIT_CARRY-1 downto 0) <= DMA_PA_Var_i(CBIT_CARRY-1 downto 0); - DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) - + DMA_PA_Snout_Carry(CBIT_CARRY); - else - DMA_PA_Var_i <= DMA_PA_Var_i; - end if; - - elsif State_Is_Body_r1 = '1' then ----- elsif State_Is_Body = '1' then - if Addr_Inc_i= '1' then - DMA_PA_Var_i(CBIT_CARRY-1 downto 0) <= DMA_PA_Body_Carry(CBIT_CARRY-1 downto 0); - DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) - + DMA_PA_Body_Carry(CBIT_CARRY); - else - DMA_PA_Var_i <= DMA_PA_Var_i; - end if; - - else - DMA_PA_Var_i <= DMA_PA_Var_i; - - end if; - - end if; - end process; - - --- ------------------------------------------------------------- --- Synchronous reg: --- DMA_PA_Loaded_i --- - FSM_Calc_DMA_PA_Loaded_i: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - DMA_PA_Loaded_i <= (OTHERS =>'0'); - - elsif dma_clk'event and dma_clk = '1' then - - if State_Is_LoadParam = '1' then - DMA_PA_Loaded_i <= DMA_PA_current(C_DBUS_WIDTH-1 downto 0); - else - DMA_PA_Loaded_i <= DMA_PA_Loaded_i; - end if; - - end if; - end process; - - --- ------------------------------------------------------------- --- Synchronous reg: DMA_Byte_Counter ---- - FSM_Calc_DMA_Byte_Counter: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - DMA_Byte_Counter <= (OTHERS =>'0'); - - elsif dma_clk'event and dma_clk = '1' then - - if State_Is_LoadParam = '1' then - if ALc_B='0' and ALc_T='1' then - DMA_Byte_Counter <= Length_minus; - else - DMA_Byte_Counter <= DMA_Length_i(C_DBUS_WIDTH-1 downto 2) & "00"; - end if; - --- elsif State_Is_Body_r1 = '1' then - elsif State_Is_Body = '1' then - DMA_Byte_Counter(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_Byte_Counter(C_DBUS_WIDTH-1 downto CBIT_CARRY) - - DMA_BC_Carry(CBIT_CARRY); - DMA_Byte_Counter(CBIT_CARRY-1 downto C_MAXSIZE_FLD_BIT_BOT) <= DMA_BC_Carry(CBIT_CARRY-1 downto C_MAXSIZE_FLD_BIT_BOT); - else - DMA_Byte_Counter <= DMA_Byte_Counter; - end if; - - end if; - end process; - - --- ------------------------------------------------------------- --- Synchronous reg: No_More_Bodies ---- - FSM_Calc_No_More_Bodies: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then - No_More_Bodies_i <= '0'; - - elsif dma_clk'event and dma_clk = '1' then - - if State_Is_LoadParam = '1' then - No_More_Bodies_i <= not ThereIs_Body_i; - --- elsif State_Is_Body_r1 = '1' then - elsif State_Is_Body = '1' then - if DMA_Byte_Counter(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1)=C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1) - and (DMA_Byte_Counter(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_left)=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) - and (DMA_Byte_Counter(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_mid)/=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) - then - No_More_Bodies_i <= '1'; - else - No_More_Bodies_i <= '0'; - end if; - - else - No_More_Bodies_i <= No_More_Bodies_i; - end if; - - end if; - end process; - - - -- ------------------------------------------ - -- Configuration pamameters: Param_Max_Cfg - -- - Syn_Config_Param_Max_Cfg: - process ( dma_clk, dma_reset) - begin - if dma_reset = '1' then -- 0x0080 Bytes - mxsz_left <= "111110"; -- 6 bits - mxsz_mid <= "000001"; -- 6 bits - mxsz_right <= "000000"; -- 6 bits - - elsif dma_clk'event and dma_clk = '1' then - - case Param_Max_Cfg is - - when "000" => -- 0x0080 Bytes - mxsz_left <= "111110"; - mxsz_mid <= "000001"; - mxsz_right <= "000000"; - - when "001" => -- 0x0100 Bytes - mxsz_left <= "111100"; - mxsz_mid <= "000010"; - mxsz_right <= "000001"; - - when "010" => -- 0x0200 Bytes - mxsz_left <= "111000"; - mxsz_mid <= "000100"; - mxsz_right <= "000011"; - - when "011" => -- 0x0400 Bytes - mxsz_left <= "110000"; - mxsz_mid <= "001000"; - mxsz_right <= "000111"; - - when "100" => -- 0x0800 Bytes - mxsz_left <= "100000"; - mxsz_mid <= "010000"; - mxsz_right <= "001111"; - - when "101" => -- 0x1000 Bytes - mxsz_left <= "000000"; - mxsz_mid <= "100000"; - mxsz_right <= "011111"; - - when Others => -- as 0x0080 Bytes - mxsz_left <= "111110"; - mxsz_mid <= "000001"; - mxsz_right <= "000000"; - - end case; - - end if; - end process; - - Max_TLP_Size <= mxsz_mid & CONV_STD_LOGIC_VECTOR(0, C_MAXSIZE_FLD_BIT_BOT); - - -end architecture Behavioral; Index: branches/Virtex6/ML605/DDR_Blinker.vhd =================================================================== --- branches/Virtex6/ML605/DDR_Blinker.vhd (revision 9) +++ branches/Virtex6/ML605/DDR_Blinker.vhd (nonexistent) @@ -1,216 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: ZITI --- Engineer: wgao --- --- Create Date: 16:38:03 06 Oct 2008 --- Design Name: --- Module Name: DDR_Blink - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.abb64Package.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity DDR_Blink is - Port ( - DDR_blinker : OUT std_logic; - - DDR_Write : IN std_logic; - DDR_Read : IN std_logic; - DDR_Both : IN std_logic; - - ddr_Clock : IN std_logic; - DDr_Rst_n : IN std_logic - ); -end entity DDR_Blink; - - -architecture Behavioral of DDR_Blink is - - - -- Blinking -_-_-_-_ - Constant C_BLINKER_MSB : integer := 15; -- 4; -- 15; - Constant CBIT_SLOW_BLINKER : integer := 11; -- 2; -- 11; - - signal DDR_blinker_i : std_logic; - signal Fast_blinker : std_logic_vector(C_BLINKER_MSB downto 0); - signal Fast_blinker_MSB_r1 : std_logic; - signal Blink_Pulse : std_logic; - signal Slow_blinker : std_logic_vector(CBIT_SLOW_BLINKER downto 0); - - signal DDR_write_extension : std_logic; - signal DDR_write_extension_Cnt: std_logic_vector(1 downto 0); - signal DDR_read_extension : std_logic; - signal DDR_read_extension_Cnt : std_logic_vector(1 downto 0); - - -begin - - - -- - Syn_DDR_Fast_blinker: - process ( ddr_Clock, DDr_Rst_n) - begin - if DDr_Rst_n = '0' then - Fast_blinker <= (OTHERS=>'0'); - Fast_blinker_MSB_r1 <= '0'; - Blink_Pulse <= '0'; - - Slow_blinker <= (OTHERS=>'0'); - - elsif ddr_Clock'event and ddr_Clock = '1' then - Fast_blinker <= Fast_blinker + '1'; - Fast_blinker_MSB_r1 <= Fast_blinker(C_BLINKER_MSB); - Blink_Pulse <= Fast_blinker(C_BLINKER_MSB) and not Fast_blinker_MSB_r1; - - Slow_blinker <= Slow_blinker + Blink_Pulse; - - end if; - end process; - - - -- - Syn_DDR_Write_Extenstion: - process ( ddr_Clock, DDr_Rst_n) - begin - if DDr_Rst_n = '0' then - DDR_write_extension_Cnt <= (OTHERS=>'0'); - DDR_write_extension <= '0'; - - elsif ddr_Clock'event and ddr_Clock = '1' then - - case DDR_write_extension_Cnt is - - when "00" => - if DDR_Write='1' then - DDR_write_extension_Cnt <= "01"; - DDR_write_extension <= '1'; - else - DDR_write_extension_Cnt <= DDR_write_extension_Cnt; - DDR_write_extension <= DDR_write_extension; - end if; - - when "01" => - if Slow_blinker(CBIT_SLOW_BLINKER)='1' then - DDR_write_extension_Cnt <= "11"; - DDR_write_extension <= '1'; - else - DDR_write_extension_Cnt <= DDR_write_extension_Cnt; - DDR_write_extension <= DDR_write_extension; - end if; - - when "11" => - if Slow_blinker(CBIT_SLOW_BLINKER)='0' then - DDR_write_extension_Cnt <= "10"; - DDR_write_extension <= '1'; - else - DDR_write_extension_Cnt <= DDR_write_extension_Cnt; - DDR_write_extension <= DDR_write_extension; - end if; - - when Others => - if Slow_blinker(CBIT_SLOW_BLINKER)='1' then - DDR_write_extension_Cnt <= "00"; - DDR_write_extension <= '0'; - else - DDR_write_extension_Cnt <= DDR_write_extension_Cnt; - DDR_write_extension <= DDR_write_extension; - end if; - - end case; - - end if; - end process; - - - -- - Syn_DDR_Read_Extenstion: - process ( ddr_Clock, DDr_Rst_n) - begin - if DDr_Rst_n = '0' then - DDR_read_extension_Cnt <= (OTHERS=>'0'); - DDR_read_extension <= '1'; - - elsif ddr_Clock'event and ddr_Clock = '1' then - - case DDR_read_extension_Cnt is - - when "00" => - if DDR_Read='1' then - DDR_read_extension_Cnt <= "01"; - DDR_read_extension <= '0'; - else - DDR_read_extension_Cnt <= DDR_read_extension_Cnt; - DDR_read_extension <= DDR_read_extension; - end if; - - when "01" => - if Slow_blinker(CBIT_SLOW_BLINKER)='1' then - DDR_read_extension_Cnt <= "11"; - DDR_read_extension <= '0'; - else - DDR_read_extension_Cnt <= DDR_read_extension_Cnt; - DDR_read_extension <= DDR_read_extension; - end if; - - when "11" => - if Slow_blinker(CBIT_SLOW_BLINKER)='0' then - DDR_read_extension_Cnt <= "10"; - DDR_read_extension <= '0'; - else - DDR_read_extension_Cnt <= DDR_read_extension_Cnt; - DDR_read_extension <= DDR_read_extension; - end if; - - when Others => - if Slow_blinker(CBIT_SLOW_BLINKER)='1' then - DDR_read_extension_Cnt <= "00"; - DDR_read_extension <= '1'; - else - DDR_read_extension_Cnt <= DDR_read_extension_Cnt; - DDR_read_extension <= DDR_read_extension; - end if; - - end case; - - end if; - end process; - - - -- - Syn_DDR_Working_blinker: - process ( ddr_Clock, DDr_Rst_n) - begin - if DDr_Rst_n = '0' then - DDR_Blinker_i <= '0'; - - elsif ddr_Clock'event and ddr_Clock = '1' then - - DDR_Blinker_i <= (Slow_blinker(CBIT_SLOW_BLINKER-2) or DDR_write_extension) and DDR_read_extension; --- DDR_Blinker_i <= Slow_blinker(CBIT_SLOW_BLINKER-2); - - end if; - end process; - - DDR_blinker <= DDR_blinker_i; - -end architecture Behavioral;

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