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URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

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    /pcie_sg_dma
    from Rev 2 to Rev 3
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Rev 2 → Rev 3

/trunk/rtl/protocol_if.vhd File deleted
/trunk/rtl/class_ctl.vhd File deleted
/trunk/rtl/class_dlm.vhd File deleted
/trunk/rtl/pseudo_protocol_module.vhd File deleted
/trunk/rtl/class_daq.vhd File deleted
/trunk/rtl/tlpControl.vhd
39,36 → 39,36
mbuf_UserFull : IN std_logic;
trn_Blinker : OUT std_logic;
 
-- DCB protocol interface
protocol_link_act : IN std_logic_vector(2-1 downto 0);
protocol_rst : OUT std_logic;
-- -- DCB protocol interface
-- protocol_link_act : IN std_logic_vector(2-1 downto 0);
-- protocol_rst : OUT std_logic;
--
-- -- Interrupter triggers
-- DAQ_irq : IN std_logic;
-- CTL_irq : IN std_logic;
-- DLM_irq : IN std_logic;
--
-- -- Fabric side: CTL Rx
-- ctl_rv : OUT std_logic;
-- ctl_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Fabric side: CTL Tx
-- ctl_ttake : OUT std_logic;
-- ctl_tv : IN std_logic;
-- ctl_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- ctl_tstop : OUT std_logic;
--
-- ctl_reset : OUT std_logic;
-- ctl_status : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Fabric side: DLM Rx
-- dlm_tv : OUT std_logic;
-- dlm_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Fabric side: DLM Tx
-- dlm_rv : IN std_logic;
-- dlm_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Interrupter triggers
DAQ_irq : IN std_logic;
CTL_irq : IN std_logic;
DLM_irq : IN std_logic;
 
-- Fabric side: CTL Rx
ctl_rv : OUT std_logic;
ctl_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: CTL Tx
ctl_ttake : OUT std_logic;
ctl_tv : IN std_logic;
ctl_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
ctl_tstop : OUT std_logic;
 
ctl_reset : OUT std_logic;
ctl_status : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: DLM Rx
dlm_tv : OUT std_logic;
dlm_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: DLM Tx
dlm_rv : IN std_logic;
dlm_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Event Buffer FIFO interface
eb_FIFO_we : OUT std_logic;
eb_FIFO_wsof : OUT std_logic;
128,15 → 128,15
DDR_FIFO_Empty : IN std_logic;
DDR_FIFO_RdQout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
-- Data generator table write
tab_we : OUT std_logic_vector(2-1 downto 0);
tab_wa : OUT std_logic_vector(12-1 downto 0);
tab_wd : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- -- Data generator table write
-- tab_we : OUT std_logic_vector(2-1 downto 0);
-- tab_wa : OUT std_logic_vector(12-1 downto 0);
-- tab_wd : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
--
-- DG_is_Running : IN std_logic;
-- DG_Reset : OUT std_logic;
-- DG_Mask : OUT std_logic;
 
DG_is_Running : IN std_logic;
DG_Reset : OUT std_logic;
DG_Mask : OUT std_logic;
 
-- Common interface
trn_clk : IN std_logic;
trn_reset_n : IN std_logic;
371,10 → 371,10
 
Link_Buf_full : IN std_logic;
 
-- Data generator table write
tab_we : OUT std_logic_vector(2-1 downto 0);
tab_wa : OUT std_logic_vector(12-1 downto 0);
tab_wd : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- -- Data generator table write
-- tab_we : OUT std_logic_vector(2-1 downto 0);
-- tab_wa : OUT std_logic_vector(12-1 downto 0);
-- tab_wd : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
-- Interrupt generator signals
IG_Reset : IN std_logic;
501,31 → 501,31
component Regs_Group
port (
 
-- DCB protocol interface
protocol_link_act : IN std_logic_vector(2-1 downto 0);
protocol_rst : OUT std_logic;
-- -- DCB protocol interface
-- protocol_link_act : IN std_logic_vector(2-1 downto 0);
-- protocol_rst : OUT std_logic;
--
-- -- Fabric side: CTL Rx
-- ctl_rv : OUT std_logic;
-- ctl_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Fabric side: CTL Tx
-- ctl_ttake : OUT std_logic;
-- ctl_tv : IN std_logic;
-- ctl_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- ctl_tstop : OUT std_logic;
--
-- ctl_reset : OUT std_logic;
-- ctl_status : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Fabric side: DLM Rx
-- dlm_tv : OUT std_logic;
-- dlm_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Fabric side: DLM Tx
-- dlm_rv : IN std_logic;
-- dlm_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: CTL Rx
ctl_rv : OUT std_logic;
ctl_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: CTL Tx
ctl_ttake : OUT std_logic;
ctl_tv : IN std_logic;
ctl_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
ctl_tstop : OUT std_logic;
 
ctl_reset : OUT std_logic;
ctl_status : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: DLM Rx
dlm_tv : OUT std_logic;
dlm_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: DLM Tx
dlm_rv : IN std_logic;
dlm_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Event Buffer status
eb_FIFO_Status : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
eb_FIFO_Rst : OUT std_logic;
616,9 → 616,9
 
-- to Interrupt module
Sys_IRQ : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DAQ_irq : IN std_logic;
CTL_irq : IN std_logic;
DLM_irq : IN std_logic;
-- DAQ_irq : IN std_logic;
-- CTL_irq : IN std_logic;
-- DLM_irq : IN std_logic;
 
-- System error and info
eb_FIFO_ow : IN std_logic;
636,10 → 636,10
IG_Num_Deassert : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Asserting : IN std_logic;
 
-- Data generator control
DG_is_Running : IN std_logic;
DG_Reset : OUT std_logic;
DG_Mask : OUT std_logic;
-- -- Data generator control
-- DG_is_Running : IN std_logic;
-- DG_Reset : OUT std_logic;
-- DG_Mask : OUT std_logic;
 
-- Common interface
trn_clk : IN std_logic;
1162,10 → 1162,10
Link_Buf_full => Link_Buf_full , -- IN std_logic;
 
 
-- Data generator table write
tab_we => tab_we , -- OUT std_logic_vector(2-1 downto 0);
tab_wa => tab_wa , -- OUT std_logic_vector(12-1 downto 0);
tab_wd => tab_wd , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- -- Data generator table write
-- tab_we => tab_we , -- OUT std_logic_vector(2-1 downto 0);
-- tab_wa => tab_wa , -- OUT std_logic_vector(12-1 downto 0);
-- tab_wd => tab_wd , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
-- Additional
cfg_dcommand => cfg_dcommand , -- IN std_logic_vector(15 downto 0)
1273,31 → 1273,31
Regs_Group
PORT MAP(
 
-- DCB protocol interface
protocol_link_act => protocol_link_act , -- IN std_logic_vector(2-1 downto 0);
protocol_rst => protocol_rst , -- OUT std_logic;
-- -- DCB protocol interface
-- protocol_link_act => protocol_link_act , -- IN std_logic_vector(2-1 downto 0);
-- protocol_rst => protocol_rst , -- OUT std_logic;
--
-- -- Fabric side: CTL Rx
-- ctl_rv => ctl_rv , -- OUT std_logic;
-- ctl_rd => ctl_rd , -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Fabric side: CTL Tx
-- ctl_ttake => ctl_ttake , -- OUT std_logic;
-- ctl_tv => ctl_tv , -- IN std_logic;
-- ctl_td => ctl_td , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- ctl_tstop => ctl_tstop , -- OUT std_logic;
--
-- ctl_reset => ctl_reset , -- OUT std_logic;
-- ctl_status => ctl_status , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Fabric side: DLM Rx
-- dlm_tv => dlm_tv , -- OUT std_logic;
-- dlm_td => dlm_td , -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Fabric side: DLM Tx
-- dlm_rv => dlm_rv , -- IN std_logic;
-- dlm_rd => dlm_rd , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: CTL Rx
ctl_rv => ctl_rv , -- OUT std_logic;
ctl_rd => ctl_rd , -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: CTL Tx
ctl_ttake => ctl_ttake , -- OUT std_logic;
ctl_tv => ctl_tv , -- IN std_logic;
ctl_td => ctl_td , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
ctl_tstop => ctl_tstop , -- OUT std_logic;
 
ctl_reset => ctl_reset , -- OUT std_logic;
ctl_status => ctl_status , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: DLM Rx
dlm_tv => dlm_tv , -- OUT std_logic;
dlm_td => dlm_td , -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: DLM Tx
dlm_rv => dlm_rv , -- IN std_logic;
dlm_rd => dlm_rd , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Event Buffer status + reset
eb_FIFO_Status => eb_FIFO_Status , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
eb_FIFO_Rst => eb_FIFO_Rst , -- OUT std_logic;
1382,9 → 1382,9
 
-- to Interrupt module
Sys_IRQ => Sys_IRQ , -- OUT std_logic_vector(31 downto 0);
DAQ_irq => DAQ_irq , -- IN std_logic;
CTL_irq => CTL_irq , -- IN std_logic;
DLM_irq => DLM_irq , -- IN std_logic;
-- DAQ_irq => DAQ_irq , -- IN std_logic;
-- CTL_irq => CTL_irq , -- IN std_logic;
-- DLM_irq => DLM_irq , -- IN std_logic;
 
-- System error and info
eb_FIFO_ow => eb_FIFO_ow ,
1402,10 → 1402,10
IG_Num_Deassert => IG_Num_Deassert ,
IG_Asserting => IG_Asserting ,
 
-- Data generator control
DG_is_Running => DG_is_Running ,
DG_Reset => DG_Reset ,
DG_Mask => DG_Mask ,
-- -- Data generator control
-- DG_is_Running => DG_is_Running ,
-- DG_Reset => DG_Reset ,
-- DG_Mask => DG_Mask ,
 
-- Common
trn_clk => trn_clk , -- IN std_logic;
/trunk/rtl/Registers.vhd
36,31 → 36,31
entity Regs_Group is
port (
 
-- DCB protocol interface
protocol_link_act : IN std_logic_vector(2-1 downto 0);
protocol_rst : OUT std_logic;
-- -- DCB protocol interface
-- protocol_link_act : IN std_logic_vector(2-1 downto 0);
-- protocol_rst : OUT std_logic;
--
-- -- Fabric side: CTL Rx
-- ctl_rv : OUT std_logic;
-- ctl_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Fabric side: CTL Tx
-- ctl_ttake : OUT std_logic;
-- ctl_tv : IN std_logic;
-- ctl_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- ctl_tstop : OUT std_logic;
--
-- ctl_reset : OUT std_logic;
-- ctl_status : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Fabric side: DLM Rx
-- dlm_tv : OUT std_logic;
-- dlm_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Fabric side: DLM Tx
-- dlm_rv : IN std_logic;
-- dlm_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: CTL Rx
ctl_rv : OUT std_logic;
ctl_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: CTL Tx
ctl_ttake : OUT std_logic;
ctl_tv : IN std_logic;
ctl_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
ctl_tstop : OUT std_logic;
 
ctl_reset : OUT std_logic;
ctl_status : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: DLM Rx
dlm_tv : OUT std_logic;
dlm_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: DLM Tx
dlm_rv : IN std_logic;
dlm_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Event Buffer status + reset
eb_FIFO_Status : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
eb_FIFO_Rst : OUT std_logic;
155,9 → 155,9
 
-- to Interrupts Module
Sys_IRQ : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DAQ_irq : IN std_logic;
CTL_irq : IN std_logic;
DLM_irq : IN std_logic;
-- DAQ_irq : IN std_logic;
-- CTL_irq : IN std_logic;
-- DLM_irq : IN std_logic;
 
-- System error and info
Tx_TimeOut : IN std_logic;
174,10 → 174,10
IG_Num_Deassert : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Asserting : IN std_logic;
 
-- Data generator control
DG_is_Running : IN std_logic;
DG_Reset : OUT std_logic;
DG_Mask : OUT std_logic;
-- -- Data generator control
-- DG_is_Running : IN std_logic;
-- DG_Reset : OUT std_logic;
-- DG_Mask : OUT std_logic;
 
-- Clock and reset
trn_clk : IN std_logic;
190,16 → 190,6
 
architecture Behavioral of Regs_Group is
 
type icapStates is ( icapST_Reset
, icapST_Idle
, icapST_Access
, icapST_Abort
);
 
-- State variables of ICAP
signal FSM_icap : icapStates;
 
 
----------------------------------------------------------------------------
----------------------------------------------------------------------------
signal Regs_WrDin_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
248,10 → 238,10
signal Reg_RdMuxer_Hi : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
signal Reg_RdMuxer_Lo : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
 
-- Optical Link status
signal Opto_Link_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Opto_Link_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Opto_Link_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- -- Optical Link status
-- signal Opto_Link_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- signal Opto_Link_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- signal Opto_Link_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Event Buffer
signal eb_FIFO_Status_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal eb_FIFO_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
306,14 → 296,14
signal Sys_Int_Enable_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
 
-- Data generator control
signal DG_Reset_i : std_logic;
signal DG_Mask_i : std_logic;
signal DG_is_Available : std_logic;
signal DG_Rst_Counter : std_logic_vector(8-1 downto 0);
signal DG_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DG_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DG_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- -- Data generator control
-- signal DG_Reset_i : std_logic;
-- signal DG_Mask_i : std_logic;
-- signal DG_is_Available : std_logic;
-- signal DG_Rst_Counter : std_logic_vector(8-1 downto 0);
-- signal DG_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- signal DG_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- signal DG_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
-- General Control and Status
signal Sys_Error_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
472,27 → 462,27
begin
 
 
DG_is_Available <= '0';
-- DG_is_Available <= '0';
 
-- protocol interface reset
protocol_rst <= protocol_rst_i;
-- -- protocol interface reset
-- protocol_rst <= protocol_rst_i;
--
-- ctl_rv <= ctl_rv_i;
-- ctl_rd <= ctl_rd_i;
--
-- ctl_ttake <= ctl_ttake_i;
-- ctl_tstop <= ctl_tstop_i;
-- ctl_reset <= ctl_reset_i;
--
-- ctl_tstop_i <= '0'; -- ???
--
-- dlm_tv <= dlm_tv_i;
-- dlm_td <= dlm_td_i;
 
ctl_rv <= ctl_rv_i;
ctl_rd <= ctl_rd_i;
-- -- Data generator control
-- DG_Reset <= DG_Reset_i;
-- DG_Mask <= DG_Mask_i;
 
ctl_ttake <= ctl_ttake_i;
ctl_tstop <= ctl_tstop_i;
ctl_reset <= ctl_reset_i;
 
ctl_tstop_i <= '0'; -- ???
 
dlm_tv <= dlm_tv_i;
dlm_td <= dlm_td_i;
 
-- Data generator control
DG_Reset <= DG_Reset_i;
DG_Mask <= DG_Mask_i;
 
-- Event buffer reset
eb_FIFO_Rst <= eb_FIFO_Rst_i;
 
704,17 → 694,17
end if;
end process;
 
-- ----------------------------------------------
-- Synchronous Delay : Opto_Link_Status
--
Synch_Delay_Opto_Link_Status:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
Opto_Link_Status_i(C_DBUS_WIDTH-1 downto 2) <= (OTHERS=>'0');
Opto_Link_Status_i(2-1 downto 0) <= protocol_link_act;
end if;
end process;
---- ----------------------------------------------
---- Synchronous Delay : Opto_Link_Status
----
-- Synch_Delay_Opto_Link_Status:
-- process ( trn_clk )
-- begin
-- if trn_clk'event and trn_clk = '1' then
-- Opto_Link_Status_i(C_DBUS_WIDTH-1 downto 2) <= (OTHERS=>'0');
-- Opto_Link_Status_i(2-1 downto 0) <= protocol_link_act;
-- end if;
-- end process;
 
-- ----------------------------------------------
-- Synchronous Delay : eb_FIFO_Status
1012,79 → 1002,79
end if;
end process;
 
-- -----------------------------------------------
-- Synchronous Registered: DG_Reset_i
SysReg_DGen_Reset:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
DG_Reset_i <= '1';
DG_Rst_Counter <= (OTHERS=>'0');
---- -----------------------------------------------
---- Synchronous Registered: DG_Reset_i
-- SysReg_DGen_Reset:
-- process ( trn_clk, trn_lnk_up_n)
-- begin
-- if trn_lnk_up_n = '1' then
-- DG_Reset_i <= '1';
-- DG_Rst_Counter <= (OTHERS=>'0');
--
-- elsif trn_clk'event and trn_clk = '1' then
--
-- if DG_Rst_Counter=X"FF" then
-- DG_Rst_Counter <= DG_Rst_Counter;
-- else
-- DG_Rst_Counter <= DG_Rst_Counter + '1';
-- end if;
--
-- if DG_Rst_Counter(7)='0' then
-- DG_Reset_i <= '1';
-- elsif Regs_WrEn_r2='1'
-- and Reg_WrMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
-- then
-- DG_Reset_i <= Command_is_Reset_Hi;
-- elsif Regs_WrEn_r2='1'
-- and Reg_WrMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
-- then
-- DG_Reset_i <= Command_is_Reset_Lo;
-- else
-- DG_Reset_i <= '0';
-- end if;
--
-- end if;
-- end process;
--
---- -----------------------------------------------
---- Synchronous Registered: DG_Mask_i
-- SysReg_DGen_Mask:
-- process ( trn_clk, trn_lnk_up_n)
-- begin
-- if trn_lnk_up_n = '1' then
-- DG_Mask_i <= '0';
-- elsif trn_clk'event and trn_clk = '1' then
--
-- if Regs_WrEn_r2='1'
-- and Reg_WrMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
-- then
-- DG_Mask_i <= Regs_WrDin_r2(32+CINT_BIT_DG_MASK);
-- elsif Regs_WrEn_r2='1'
-- and Reg_WrMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
-- then
-- DG_Mask_i <= Regs_WrDin_r2(CINT_BIT_DG_MASK);
-- else
-- DG_Mask_i <= DG_Mask_i;
-- end if;
--
-- end if;
-- end process;
--
----------------------------------------------------------------------------
---- Data generator status
----
-- Synch_DG_Status_i:
-- process ( trn_clk, DG_Reset_i )
-- begin
-- if DG_Reset_i = '1' then
-- DG_Status_i <= (OTHERS=>'0');
-- elsif trn_clk'event and trn_clk = '1' then
-- DG_Status_i(CINT_BIT_DG_MASK) <= DG_Mask_i;
-- DG_Status_i(CINT_BIT_DG_BUSY) <= DG_is_Running;
-- end if;
-- end process;
 
elsif trn_clk'event and trn_clk = '1' then
 
if DG_Rst_Counter=X"FF" then
DG_Rst_Counter <= DG_Rst_Counter;
else
DG_Rst_Counter <= DG_Rst_Counter + '1';
end if;
 
if DG_Rst_Counter(7)='0' then
DG_Reset_i <= '1';
elsif Regs_WrEn_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
then
DG_Reset_i <= Command_is_Reset_Hi;
elsif Regs_WrEn_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
then
DG_Reset_i <= Command_is_Reset_Lo;
else
DG_Reset_i <= '0';
end if;
 
end if;
end process;
 
-- -----------------------------------------------
-- Synchronous Registered: DG_Mask_i
SysReg_DGen_Mask:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
DG_Mask_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
 
if Regs_WrEn_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
then
DG_Mask_i <= Regs_WrDin_r2(32+CINT_BIT_DG_MASK);
elsif Regs_WrEn_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
then
DG_Mask_i <= Regs_WrDin_r2(CINT_BIT_DG_MASK);
else
DG_Mask_i <= DG_Mask_i;
end if;
 
end if;
end process;
 
--------------------------------------------------------------------------
-- Data generator status
--
Synch_DG_Status_i:
process ( trn_clk, DG_Reset_i )
begin
if DG_Reset_i = '1' then
DG_Status_i <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
DG_Status_i(CINT_BIT_DG_MASK) <= DG_Mask_i;
DG_Status_i(CINT_BIT_DG_BUSY) <= DG_is_Running;
end if;
end process;
 
-- -----------------------------------------------
-- Synchronous Registered: IG_Control_i
SysReg_IntGen_Control:
process ( trn_clk, trn_lnk_up_n)
1148,133 → 1138,133
 
 
 
-- ------------------------------------------------------
-- Protocol CTL interface
-- ------------------------------------------------------
---- ------------------------------------------------------
---- Protocol CTL interface
---- ------------------------------------------------------
--
---- -------------------------------------------------------
---- Synchronous Registered: ctl_rd
-- Syn_CTL_rd:
-- process ( trn_clk, trn_lnk_up_n)
-- begin
-- if trn_lnk_up_n = '1' then
-- ctl_rd_i <= (OTHERS => '0');
-- ctl_rv_i <= '0';
-- elsif trn_clk'event and trn_clk = '1' then
--
-- if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_CTL_CLASS)='1' then
-- ctl_rd_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
-- ctl_rv_i <= '1';
-- elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_CTL_CLASS)='1' then
-- ctl_rd_i <= Regs_WrDin_r2(32-1 downto 0);
-- ctl_rv_i <= '1';
-- else
-- ctl_rd_i <= ctl_rd_i;
-- ctl_rv_i <= '0';
-- end if;
--
-- end if;
-- end process;
--
--
---- -----------------------------------------------
---- Synchronous Registered: ctl_reset
-- SysReg_ctl_reset:
-- process ( trn_clk, trn_lnk_up_n)
-- begin
-- if trn_lnk_up_n = '1' then
-- ctl_reset_i <= '1';
--
-- elsif trn_clk'event and trn_clk = '1' then
--
-- if Regs_WrEn_r2='1'
-- and Reg_WrMuxer_Hi(CINT_ADDR_TC_STATUS)='1'
-- then
-- ctl_reset_i <= Command_is_Reset_Hi;
-- elsif Regs_WrEn_r2='1'
-- and Reg_WrMuxer_Lo(CINT_ADDR_TC_STATUS)='1'
-- then
-- ctl_reset_i <= Command_is_Reset_Lo;
-- else
-- ctl_reset_i <= '0';
-- end if;
--
-- end if;
-- end process;
--
--
--
---- -------------------------------------------------------
---- Synchronous Registered: ctl_td
---- ++++++++++++ INT triggering ++++++++++++++++++
-- Syn_CTL_td:
-- process ( trn_clk, trn_lnk_up_n)
-- begin
-- if trn_lnk_up_n = '1' then
-- ctl_td_r <= (OTHERS => '0');
-- elsif trn_clk'event and trn_clk = '1' then
--
-- if ctl_tv='1' then
-- ctl_td_r <= ctl_td;
-- else
-- ctl_td_r <= ctl_td_r;
-- end if;
--
-- end if;
-- end process;
--
--
--
---- ------------------------------------------------------
---- Protocol DLM interface
---- ------------------------------------------------------
--
---- -------------------------------------------------------
---- Synchronous Registered: dlm_td
-- Syn_DLM_td:
-- process ( trn_clk, trn_lnk_up_n)
-- begin
-- if trn_lnk_up_n = '1' then
-- dlm_td_i <= (OTHERS => '0');
-- dlm_tv_i <= '0';
-- elsif trn_clk'event and trn_clk = '1' then
--
-- if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DLM_CLASS)='1' then
-- dlm_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
-- dlm_tv_i <= '1';
-- elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DLM_CLASS)='1' then
-- dlm_td_i <= Regs_WrDin_r2(32-1 downto 0);
-- dlm_tv_i <= '1';
-- else
-- dlm_td_i <= dlm_td_i;
-- dlm_tv_i <= '0';
-- end if;
--
-- end if;
-- end process;
--
--
---- -------------------------------------------------------
---- Synchronous Registered: dlm_rd
---- ++++++++++++ INT triggering ++++++++++++++++++
-- Syn_DLM_rd:
-- process ( trn_clk, trn_lnk_up_n)
-- begin
-- if trn_lnk_up_n = '1' then
-- dlm_rd_r <= (OTHERS => '0');
-- elsif trn_clk'event and trn_clk = '1' then
--
-- if dlm_rv='1' then
-- dlm_rd_r <= dlm_rd;
-- else
-- dlm_rd_r <= dlm_rd_r;
-- end if;
--
-- end if;
-- end process;
 
-- -------------------------------------------------------
-- Synchronous Registered: ctl_rd
Syn_CTL_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
ctl_rd_i <= (OTHERS => '0');
ctl_rv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
 
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_CTL_CLASS)='1' then
ctl_rd_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
ctl_rv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_CTL_CLASS)='1' then
ctl_rd_i <= Regs_WrDin_r2(32-1 downto 0);
ctl_rv_i <= '1';
else
ctl_rd_i <= ctl_rd_i;
ctl_rv_i <= '0';
end if;
 
end if;
end process;
 
 
-- -----------------------------------------------
-- Synchronous Registered: ctl_reset
SysReg_ctl_reset:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
ctl_reset_i <= '1';
 
elsif trn_clk'event and trn_clk = '1' then
 
if Regs_WrEn_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_TC_STATUS)='1'
then
ctl_reset_i <= Command_is_Reset_Hi;
elsif Regs_WrEn_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_TC_STATUS)='1'
then
ctl_reset_i <= Command_is_Reset_Lo;
else
ctl_reset_i <= '0';
end if;
 
end if;
end process;
 
 
 
-- -------------------------------------------------------
-- Synchronous Registered: ctl_td
-- ++++++++++++ INT triggering ++++++++++++++++++
Syn_CTL_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
ctl_td_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
 
if ctl_tv='1' then
ctl_td_r <= ctl_td;
else
ctl_td_r <= ctl_td_r;
end if;
 
end if;
end process;
 
 
 
-- ------------------------------------------------------
-- Protocol DLM interface
-- ------------------------------------------------------
 
-- -------------------------------------------------------
-- Synchronous Registered: dlm_td
Syn_DLM_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
dlm_td_i <= (OTHERS => '0');
dlm_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
 
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DLM_CLASS)='1' then
dlm_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
dlm_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DLM_CLASS)='1' then
dlm_td_i <= Regs_WrDin_r2(32-1 downto 0);
dlm_tv_i <= '1';
else
dlm_td_i <= dlm_td_i;
dlm_tv_i <= '0';
end if;
 
end if;
end process;
 
 
-- -------------------------------------------------------
-- Synchronous Registered: dlm_rd
-- ++++++++++++ INT triggering ++++++++++++++++++
Syn_DLM_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
dlm_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
 
if dlm_rv='1' then
dlm_rd_r <= dlm_rd;
else
dlm_rd_r <= dlm_rd_r;
end if;
 
end if;
end process;
 
 
-- ------------------------------------------------------
-- DMA Upstream Registers
-- ------------------------------------------------------
 
2302,78 → 2292,6
end if;
end process;
 
---- -------------------------------------------------------
---- Synchronous Registers: icap_Write_i
-- RxTrn_icap_Write:
-- process ( trn_clk, trn_lnk_up_n)
-- begin
-- if trn_lnk_up_n = '1' then
-- icap_CLK <= '0';
-- icap_I <= (OTHERS => '0');
-- icap_Write <= '1';
-- icap_CE <= '1';
-- FSM_icap <= icapST_Reset;
--
-- elsif trn_clk'event and trn_clk = '1' then
--
-- case FSM_icap is
--
-- when icapST_Reset =>
-- icap_CLK <= '0';
-- icap_I <= (OTHERS => '0');
-- icap_Write <= '1';
-- icap_CE <= '1';
-- FSM_icap <= icapST_Idle;
--
-- when icapST_Idle =>
--
-- if Regs_WrEn_r2='1' and Reg_WrMuxer(CINT_ADDR_ICAP)='1' then
-- icap_CLK <= '1';
-- icap_I <= Regs_WrDin_r2;
-- icap_Write <= '0';
-- icap_CE <= '0';
-- FSM_icap <= icapST_Access;
-- elsif Reg_RdMuxer(CINT_ADDR_ICAP)='1' then
-- icap_CLK <= '1';
-- icap_I <= icap_I;
-- icap_Write <= '1';
-- icap_CE <= '0';
-- FSM_icap <= icapST_Access;
-- else
-- icap_CLK <= icap_CLK;
-- icap_I <= icap_I;
-- icap_Write <= icap_Write;
-- icap_CE <= icap_CE;
-- FSM_icap <= icapST_Idle;
-- end if;
--
--
-- when icapST_Access =>
-- icap_CLK <= '1';
-- icap_I <= icap_I;
-- icap_Write <= icap_Write;
-- icap_CE <= icap_CE;
-- FSM_icap <= icapST_Abort;
--
-- when icapST_Abort =>
-- icap_CLK <= '0';
-- icap_I <= icap_I;
-- icap_Write <= icap_Write;
-- icap_CE <= icap_CE;
-- FSM_icap <= icapST_Idle;
--
-- when Others =>
-- icap_CLK <= '0';
-- icap_I <= (OTHERS => '0');
-- icap_Write <= '1';
-- icap_CE <= '1';
-- FSM_icap <= icapST_Idle;
--
-- end case;
--
-- end if;
-- end process;
--
 
 
----------------------------------------------------------
2426,55 → 2344,55
end process;
 
 
----------------------------------------------------------
-- Synch Register: CTL_TTake
--
Syn_CTL_ttake:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
ctl_ttake_i <= '0';
ctl_t_read_Hi_r1 <= '0';
ctl_t_read_Lo_r1 <= '0';
CTL_read_counter <= (OTHERS=>'0');
------------------------------------------------------------
---- Synch Register: CTL_TTake
----
-- Syn_CTL_ttake:
-- process ( trn_clk, trn_lnk_up_n)
-- begin
-- if trn_lnk_up_n = '1' then
-- ctl_ttake_i <= '0';
-- ctl_t_read_Hi_r1 <= '0';
-- ctl_t_read_Lo_r1 <= '0';
-- CTL_read_counter <= (OTHERS=>'0');
--
-- elsif trn_clk'event and trn_clk = '1' then
-- ctl_t_read_Hi_r1 <= Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS);
-- ctl_t_read_Lo_r1 <= Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS);
-- ctl_ttake_i <= (Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS) and not ctl_t_read_Hi_r1)
-- or (Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS) and not ctl_t_read_Lo_r1)
-- ;
-- if ctl_reset_i='1' then
-- CTL_read_counter <= (OTHERS=>'0');
-- else
-- CTL_read_counter <= CTL_read_counter + ctl_ttake_i;
-- end if;
--
-- end if;
-- end process;
--
------------------------------------------------------------
---- Synch Register: class_CTL_Status
----
-- Syn_class_CTL_Status:
-- process ( trn_clk, trn_lnk_up_n)
-- begin
-- if trn_lnk_up_n = '1' then
-- class_CTL_Status_i <= (OTHERS=>'0');
--
-- elsif trn_clk'event and trn_clk = '1' then
-- class_CTL_Status_i(C_DBUS_WIDTH/2-1 downto 0) <= ctl_status;
--
-- end if;
-- end process;
 
elsif trn_clk'event and trn_clk = '1' then
ctl_t_read_Hi_r1 <= Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS);
ctl_t_read_Lo_r1 <= Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS);
ctl_ttake_i <= (Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS) and not ctl_t_read_Hi_r1)
or (Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS) and not ctl_t_read_Lo_r1)
;
if ctl_reset_i='1' then
CTL_read_counter <= (OTHERS=>'0');
else
CTL_read_counter <= CTL_read_counter + ctl_ttake_i;
end if;
 
end if;
end process;
 
----------------------------------------------------------
-- Synch Register: class_CTL_Status
--
Syn_class_CTL_Status:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
class_CTL_Status_i <= (OTHERS=>'0');
 
elsif trn_clk'event and trn_clk = '1' then
class_CTL_Status_i(C_DBUS_WIDTH/2-1 downto 0) <= ctl_status;
 
end if;
end process;
 
 
-- -------------------------------------------------------
--
Sys_Int_Status_i <= (
CINT_BIT_DLM_IN_ISR => DLM_irq ,
CINT_BIT_CTL_IN_ISR => CTL_irq ,
CINT_BIT_DAQ_IN_ISR => DAQ_irq ,
-- CINT_BIT_DLM_IN_ISR => DLM_irq ,
-- CINT_BIT_CTL_IN_ISR => CTL_irq ,
-- CINT_BIT_DAQ_IN_ISR => DAQ_irq ,
 
CINT_BIT_DSTOUT_IN_ISR => DMA_ds_Tout ,
CINT_BIT_USTOUT_IN_ISR => DMA_us_Tout ,
2812,10 → 2730,10
<= pcie_link_width;
General_Status_i(CINT_BIT_ICAP_BUSY_IN_GSR)
<= icap_Busy;
General_Status_i(CINT_BIT_DG_AVAIL_IN_GSR)
<= DG_is_Available;
General_Status_i(CINT_BIT_LINK_ACT_IN_GSR+1 downto CINT_BIT_LINK_ACT_IN_GSR)
<= protocol_link_act;
-- General_Status_i(CINT_BIT_DG_AVAIL_IN_GSR)
-- <= DG_is_Available;
-- General_Status_i(CINT_BIT_LINK_ACT_IN_GSR+1 downto CINT_BIT_LINK_ACT_IN_GSR)
-- <= protocol_link_act;
 
-- General_Status_i(8) <= CTL_read_counter(6-1); ---- DEBUG !!!
end if;
2870,40 → 2788,40
<= eb_FIFO_Status_r1(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_EB_STACON)='1'
else (Others=>'0');
 
--------------------------------------------------------------------------
-- Optical Link Status
--------------------------------------------------------------------------
Opto_Link_Status_o_Hi(32-1 downto 0)
<= Opto_Link_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_PROTOCOL_STACON)='1'
else (Others=>'0');
-- --------------------------------------------------------------------------
-- -- Optical Link Status
-- --------------------------------------------------------------------------
-- Opto_Link_Status_o_Hi(32-1 downto 0)
-- <= Opto_Link_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_PROTOCOL_STACON)='1'
-- else (Others=>'0');
--
-- Opto_link_Status_o_Lo(32-1 downto 0)
-- <= Opto_Link_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_PROTOCOL_STACON)='1'
-- else (Others=>'0');
--
-- --------------------------------------------------------------------------
-- -- Class CTL status
-- --------------------------------------------------------------------------
-- class_CTL_Status_o_Hi(32-1 downto 0)
-- <= class_CTL_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_TC_STATUS)='1'
-- else (Others=>'0');
--
-- class_CTL_Status_o_Lo(32-1 downto 0)
-- <= class_CTL_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_TC_STATUS)='1'
-- else (Others=>'0');
--
-- --------------------------------------------------------------------------
-- -- Data generator Status
-- --------------------------------------------------------------------------
-- DG_Status_o_Hi(32-1 downto 0)
-- <= DG_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
-- else (Others=>'0');
--
-- DG_Status_o_Lo(32-1 downto 0)
-- <= DG_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
-- else (Others=>'0');
 
Opto_link_Status_o_Lo(32-1 downto 0)
<= Opto_Link_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_PROTOCOL_STACON)='1'
else (Others=>'0');
 
--------------------------------------------------------------------------
-- Class CTL status
--------------------------------------------------------------------------
class_CTL_Status_o_Hi(32-1 downto 0)
<= class_CTL_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_TC_STATUS)='1'
else (Others=>'0');
 
class_CTL_Status_o_Lo(32-1 downto 0)
<= class_CTL_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_TC_STATUS)='1'
else (Others=>'0');
 
--------------------------------------------------------------------------
-- Data generator Status
--------------------------------------------------------------------------
DG_Status_o_Hi(32-1 downto 0)
<= DG_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
else (Others=>'0');
 
DG_Status_o_Lo(32-1 downto 0)
<= DG_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
else (Others=>'0');
 
--------------------------------------------------------------------------
-- Hardware version
--------------------------------------------------------------------------
HW_Version_o_Hi(32-1 downto 0)
2961,14 → 2879,14
or IG_Num_Assert_o_Hi (32-1 downto 0)
or IG_Num_Deassert_o_Hi(32-1 downto 0)
 
or DG_Status_o_Hi (32-1 downto 0)
or class_CTL_Status_o_Hi (32-1 downto 0)
-- or DG_Status_o_Hi (32-1 downto 0)
-- or class_CTL_Status_o_Hi (32-1 downto 0)
 
-- or icap_O_o_Hi (32-1 downto 0)
or Opto_Link_Status_o_Hi (32-1 downto 0)
-- or Opto_Link_Status_o_Hi (32-1 downto 0)
or eb_FIFO_Status_o_Hi (32-1 downto 0)
or dlm_rd_o_Hi
or ctl_td_o_Hi
-- or dlm_rd_o_Hi
-- or ctl_td_o_Hi
;
 
 
3008,14 → 2926,14
or IG_Num_Assert_o_Lo (32-1 downto 0)
or IG_Num_Deassert_o_Lo(32-1 downto 0)
 
or DG_Status_o_Lo (32-1 downto 0)
or class_CTL_Status_o_Lo (32-1 downto 0)
-- or DG_Status_o_Lo (32-1 downto 0)
-- or class_CTL_Status_o_Lo (32-1 downto 0)
 
-- or icap_O_o_Lo(32-1 downto 0)
or Opto_Link_Status_o_Lo (32-1 downto 0)
-- or Opto_Link_Status_o_Lo (32-1 downto 0)
or eb_FIFO_Status_o_Lo (32-1 downto 0)
or dlm_rd_o_Lo
or ctl_td_o_Lo
-- or dlm_rd_o_Lo
-- or ctl_td_o_Lo
;
 
end if;
3022,46 → 2940,4
end process;
 
 
-- -----------------------------------------------------------------------------
-- -- Implementation codes
-- -----------------------------------------------------------------------------
-- Gen_ICAP_width_8:
-- if C_ICAP_WIDTH=8 generate
--
-- ICAP_VIRTEX4_pcie :
-- ICAP_VIRTEX4
-- generic map (
-- ICAP_WIDTH => "X8" -- "X8" or "X32"
-- )
-- port map (
-- BUSY => icap_BUSY , -- Busy output
-- O => icap_O , -- 8-bit data output
-- CE => icap_CE , -- Clock enable input
-- CLK => icap_CLK , -- Clock input
-- I => icap_I , -- 8-bit data input
-- WRITE => icap_WRITE -- Write input
-- );
--
-- end generate;
--
-- Gen_ICAP_width_32:
-- if C_ICAP_WIDTH=32 generate
--
-- ICAP_VIRTEX4_pcie :
-- ICAP_VIRTEX4
-- generic map (
-- ICAP_WIDTH => "X32" -- "X8" or "X32"
-- )
-- port map (
-- BUSY => icap_BUSY , -- Busy output
-- O => icap_O , -- 32-bit data output
-- CE => icap_CE , -- Clock enable input
-- CLK => icap_CLK , -- Clock input
-- I => icap_I , -- 32-bit data input
-- WRITE => icap_WRITE -- Write input
-- );
--
-- end generate;
--
 
end Behavioral;
/trunk/rtl/tx_Mem_Reader.vhd
145,6 → 145,7
signal eb_FIFO_RdEn_Mask_r1 : std_logic;
signal eb_FIFO_RdEn_Mask_r2 : std_logic;
signal ebFIFO_Rd_1DW : std_logic;
signal ebFIFO_Rd_1DW_r1 : std_logic;
signal eb_FIFO_qout_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal eb_FIFO_qout_shift : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal eb_FIFO_qout_swapped : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
190,9 → 191,9
-- signal TxTLP_eof_n_r2 : std_logic;
 
signal TimeOut_Counter : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal TimeOut_Indic_TX : std_logic;
signal TimeOut_Indic_eb_CplD : std_logic;
signal TimeOut_Indic_eb_MWr : std_logic;
signal TimeOut_Indic_TX : std_logic;
signal TimeOut_Indic_eb_CplD : std_logic;
signal TimeOut_Indic_eb_MWr : std_logic;
signal TO_Cnt_Rst : std_logic;
signal Tx_TimeOut_i : std_logic;
signal Tx_eb_TimeOut_i : std_logic;
742,7 → 743,8
if trn_clk'event and trn_clk = '1' then
mbuf_WE_i <= DDR_FIFO_Write_mbuf_r1
or Regs_Write_mbuf_r2
or (eb_FIFO_Write_mbuf_r1 or (Shift_1st_QWord_k and eb_FIFO_RdEn_Mask_rise_r1))
or (eb_FIFO_Write_mbuf_r1 or (Shift_1st_QWord_k
and eb_FIFO_RdEn_Mask_rise_r1 and not ebFIFO_Rd_1DW_r1))
;
end if;
end process;
779,6 → 781,7
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
ebFIFO_Rd_1DW_r1 <= ebFIFO_Rd_1DW;
eb_FIFO_RdEn_Mask_rise <= eb_FIFO_RdEn_Mask and not eb_FIFO_RdEn_Mask_r1;
eb_FIFO_RdEn_Mask_rise_r1 <= eb_FIFO_RdEn_Mask_rise;
eb_FIFO_RdEn_Mask_rise_r2 <= eb_FIFO_RdEn_Mask_rise_r1;
833,13 → 836,13
process ( trn_clk, TO_Cnt_Rst )
begin
if TO_Cnt_Rst='1' then
TimeOut_Counter <= (OTHERS=>'0');
TimeOut_Indic_TX <= '0';
TimeOut_Indic_eb_CplD <= '0';
TimeOut_Counter <= (OTHERS=>'0');
TimeOut_Indic_TX <= '0';
TimeOut_Indic_eb_CplD <= '0';
TimeOut_Indic_eb_MWr <= '0';
elsif trn_clk'event and trn_clk = '1' then
TimeOut_Counter(21 downto 0) <= TimeOut_Counter(21 downto 0) + '1';
 
 
if TimeOut_Counter(21 downto 10)=X"FFF" then
-- if TimeOut_Counter(4 downto 1)=X"F" then
TimeOut_Indic_TX <= '1';
846,14 → 849,14
else
TimeOut_Indic_TX <= '0';
end if;
 
 
if TimeOut_Counter(7 downto 4)=X"F" then
-- if TimeOut_Counter(3 downto 0)=X"F" then
TimeOut_Indic_eb_CplD <= '1';
else
TimeOut_Indic_eb_CplD <= '0';
TimeOut_Indic_eb_CplD <= '1';
else
TimeOut_Indic_eb_CplD <= '0';
end if;
 
 
if TimeOut_Counter(10 downto 7)=X"F" then
-- if TimeOut_Counter(3 downto 0)=X"F" then
TimeOut_Indic_eb_MWr <= '1';
860,7 → 863,7
else
TimeOut_Indic_eb_MWr <= '0';
end if;
 
 
end if;
end process;
 
/trunk/rtl/v5pcieDMA.vhd
267,7 → 267,7
-- -----------------------------------------------------------------------
-- FIFO module
-- 16K x 8B
component eb_wrapper
component FIFO_wrapper
port (
wr_clk : IN std_logic;
wr_en : IN std_logic;
314,268 → 314,268
signal tab_wa : STD_LOGIC_VECTOR (12-1 downto 0);
signal tab_wd : STD_LOGIC_VECTOR (C_DBUS_WIDTH-1 downto 0);
 
signal dg_running : STD_LOGIC;
signal dg_mask : STD_LOGIC;
signal dg_rst : STD_LOGIC;
-- signal dg_running : STD_LOGIC;
-- signal dg_mask : STD_LOGIC;
-- signal dg_rst : STD_LOGIC;
--
-- -- debug signal
-- signal dg_debug_led : STD_LOGIC;
--
-- -- Protocol Interface module
-- COMPONENT protocol_IF
-- PORT (
-- -- DAQ Tx
-- data2send_start : OUT std_logic;
-- data2send_end : OUT std_logic;
-- data2send : OUT std_logic_vector(64-1 downto 0);
-- crc_error_send : OUT std_logic;
-- data2send_stop : IN std_logic;
--
-- -- DAQ Rx
-- data_rec_start : IN std_logic;
-- data_rec_end : IN std_logic;
-- data_rec : IN std_logic_vector(64-1 downto 0);
-- crc_error_rec : IN std_logic;
-- data_rec_stop : OUT std_logic;
--
-- -- CTL Tx
-- ctrl2send_start : OUT std_logic;
-- ctrl2send_end : OUT std_logic;
-- ctrl2send : OUT std_logic_vector(16-1 downto 0);
-- ctrl2send_stop : IN std_logic;
--
-- -- CTL Rx
-- ctrl_rec_start : IN std_logic;
-- ctrl_rec_end : IN std_logic;
-- ctrl_rec : IN std_logic_vector(16-1 downto 0);
-- ctrl_rec_stop : OUT std_logic;
--
-- -- DLM Tx
-- dlm2send_va : OUT std_logic;
-- dlm2send_type : OUT std_logic_vector(4-1 downto 0);
--
-- -- DLM Rx
-- dlm_rec_va : IN std_logic;
-- dlm_rec_type : IN std_logic_vector(4-1 downto 0);
--
-- -- Common signals
-- link_tx_clk : IN std_logic;
-- link_rx_clk : IN std_logic;
-- link_active : IN std_logic_vector(2-1 downto 0);
-- protocol_clk : OUT std_logic;
-- protocol_res_n : OUT std_logic;
--
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--
-- -- Fabric side: DAQ Rx
-- daq_rv : IN std_logic;
-- daq_rsof : IN std_logic;
-- daq_reof : IN std_logic;
-- daq_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- daq_rstop : OUT std_logic;
--
-- -- Fabric side: DAQ Tx
-- daq_tv : OUT std_logic;
-- daq_tsof : OUT std_logic;
-- daq_teof : OUT std_logic;
-- daq_td : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- daq_tstop : IN std_logic;
--
-- -- Fabric side: DLM Rx
-- dlm_tv : IN std_logic;
-- dlm_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Fabric side: DLM Tx
-- dlm_rv : OUT std_logic;
-- dlm_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Fabric side: CTL Rx
-- ctl_rv : IN std_logic;
-- ctl_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- ctl_rstop : OUT std_logic;
--
-- -- Fabric side: CTL Tx
-- ctl_ttake : IN std_logic;
-- ctl_tv : OUT std_logic;
-- ctl_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- ctl_tstop : IN std_logic;
--
-- ctl_reset : IN std_logic;
-- ctl_status : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Interrupter triggers
-- DAQ_irq : OUT std_logic;
-- CTL_irq : OUT std_logic;
-- DLM_irq : OUT std_logic;
--
-- -- Data generator table write port
-- tab_sel : IN STD_LOGIC;
-- tab_we : IN STD_LOGIC_VECTOR (2-1 downto 0);
-- tab_wa : IN STD_LOGIC_VECTOR (12-1 downto 0);
-- tab_wd : IN STD_LOGIC_VECTOR (64-1 downto 0);
--
-- -- DG control/status signal
-- dg_running : OUT STD_LOGIC;
-- dg_mask : IN STD_LOGIC;
-- dg_rst : IN STD_LOGIC;
--
-- -- DG debug signal
-- daq_start_led : OUT STD_LOGIC;
--
-- -- Fabric side: Common signals
-- trn_clk : IN std_logic;
-- protocol_link_act : OUT std_logic_vector(2-1 downto 0);
-- protocol_rst : IN std_logic
-- );
-- END COMPONENT;
--
-- -- DAQ Tx
-- signal data2send_start : std_logic;
-- signal data2send_end : std_logic;
-- signal data2send : std_logic_vector(64-1 downto 0);
-- signal crc_error_send : std_logic;
-- signal data2send_stop : std_logic
-- := '0';
--
-- -- DAQ Rx
-- signal data_rec_start : std_logic;
-- signal data_rec_end : std_logic;
-- signal data_rec : std_logic_vector(64-1 downto 0);
-- signal crc_error_rec : std_logic;
-- signal data_rec_stop : std_logic;
--
-- -- CTL Tx
-- signal ctrl2send_start : std_logic;
-- signal ctrl2send_end : std_logic;
-- signal ctrl2send : std_logic_vector(16-1 downto 0);
-- signal ctrl2send_stop : std_logic;
--
-- -- CTL Rx
-- signal ctrl_rec_start : std_logic;
-- signal ctrl_rec_end : std_logic;
-- signal ctrl_rec : std_logic_vector(16-1 downto 0);
-- signal ctrl_rec_stop : std_logic;
--
-- -- DLM Tx
-- signal dlm2send_va : std_logic;
-- signal dlm2send_type : std_logic_vector(4-1 downto 0);
---- signal dlm2send_va_i : std_logic;
---- signal dlm2send_type_i : std_logic_vector(4-1 downto 0);
--
-- -- DLM Rx
-- signal dlm_rec_va : std_logic;
-- signal dlm_rec_type : std_logic_vector(4-1 downto 0);
---- signal dlm_rec_va_i : std_logic;
---- signal dlm_rec_type_i : std_logic_vector(4-1 downto 0);
--
--
-- -- Common signals
-- signal link_rx_clk : std_logic;
-- signal link_tx_clk : std_logic;
-- signal link_active : std_logic_vector(2-1 downto 0);
-- signal protocol_clk : std_logic;
-- signal protocol_res_n : std_logic;
--
--
-- -- Fabric side: DAQ Rx
-- signal daq_rv : std_logic;
-- signal daq_rsof : std_logic;
-- signal daq_reof : std_logic;
-- signal daq_rd : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- signal daq_rstop : std_logic;
--
-- -- Fabric side: DAQ Tx
-- signal daq_tv : std_logic;
-- signal daq_tsof : std_logic;
-- signal daq_teof : std_logic;
-- signal daq_td : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- signal daq_tstop : std_logic;
--
-- -- Fabric side: DLM Rx
-- signal dlm_tv : std_logic;
-- signal dlm_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Fabric side: DLM Tx
-- signal dlm_rv : std_logic;
-- signal dlm_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Fabric side: CTL Rx
-- signal ctl_rv : std_logic;
-- signal ctl_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- signal ctl_rstop : std_logic;
--
-- -- Fabric side: CTL Tx
-- signal ctl_ttake : std_logic;
-- signal ctl_tv : std_logic;
-- signal ctl_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- signal ctl_tstop : std_logic;
--
-- signal ctl_reset : std_logic;
-- signal ctl_status : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Interrupter triggers
-- signal DAQ_irq : std_logic;
-- signal CTL_irq : std_logic;
-- signal DLM_irq : std_logic;
--
-- -- Fabric side: Common signals
-- signal protocol_link_act : std_logic_vector(2-1 downto 0);
-- signal protocol_rst : std_logic;
--
--
-- -- Pseudo link module, to be replaced by the real optical link
-- COMPONENT pseudo_protocol_module
-- PORT (
-- -- DAQ Tx
-- data2send_start : IN std_logic;
-- data2send_end : IN std_logic;
-- data2send : IN std_logic_vector(64-1 downto 0);
-- crc_error_send : IN std_logic;
-- data2send_stop : OUT std_logic;
--
-- -- DAQ Rx
-- data_rec_start : OUT std_logic;
-- data_rec_end : OUT std_logic;
-- data_rec : OUT std_logic_vector(64-1 downto 0);
-- crc_error_rec : OUT std_logic;
-- data_rec_stop : IN std_logic;
--
-- -- CTL Tx
-- ctrl2send_start : IN std_logic;
-- ctrl2send_end : IN std_logic;
-- ctrl2send : IN std_logic_vector(16-1 downto 0);
-- ctrl2send_stop : OUT std_logic;
--
-- -- CTL Rx
-- ctrl_rec_start : OUT std_logic;
-- ctrl_rec_end : OUT std_logic;
-- ctrl_rec : OUT std_logic_vector(16-1 downto 0);
-- ctrl_rec_stop : IN std_logic;
--
-- -- DLM Tx
-- dlm2send_va : IN std_logic;
-- dlm2send_type : IN std_logic_vector(4-1 downto 0);
--
-- -- DLM Rx
-- dlm_rec_va : OUT std_logic;
-- dlm_rec_type : OUT std_logic_vector(4-1 downto 0);
--
-- -- dummy pin input
-- dummy_pin_in : IN std_logic_vector(3-1 downto 0);
--
-- -- Common interface
-- link_tx_clk : OUT std_logic;
-- link_rx_clk : OUT std_logic;
-- link_active : OUT std_logic_vector(2-1 downto 0);
-- clk : IN std_logic;
-- res_n : IN std_logic
-- );
-- END COMPONENT;
--
--
-- signal Link_Buf_full : std_logic;
 
-- debug signal
signal dg_debug_led : STD_LOGIC;
 
-- Protocol Interface module
COMPONENT protocol_IF
PORT (
-- DAQ Tx
data2send_start : OUT std_logic;
data2send_end : OUT std_logic;
data2send : OUT std_logic_vector(64-1 downto 0);
crc_error_send : OUT std_logic;
data2send_stop : IN std_logic;
 
-- DAQ Rx
data_rec_start : IN std_logic;
data_rec_end : IN std_logic;
data_rec : IN std_logic_vector(64-1 downto 0);
crc_error_rec : IN std_logic;
data_rec_stop : OUT std_logic;
 
-- CTL Tx
ctrl2send_start : OUT std_logic;
ctrl2send_end : OUT std_logic;
ctrl2send : OUT std_logic_vector(16-1 downto 0);
ctrl2send_stop : IN std_logic;
 
-- CTL Rx
ctrl_rec_start : IN std_logic;
ctrl_rec_end : IN std_logic;
ctrl_rec : IN std_logic_vector(16-1 downto 0);
ctrl_rec_stop : OUT std_logic;
 
-- DLM Tx
dlm2send_va : OUT std_logic;
dlm2send_type : OUT std_logic_vector(4-1 downto 0);
 
-- DLM Rx
dlm_rec_va : IN std_logic;
dlm_rec_type : IN std_logic_vector(4-1 downto 0);
 
-- Common signals
link_tx_clk : IN std_logic;
link_rx_clk : IN std_logic;
link_active : IN std_logic_vector(2-1 downto 0);
protocol_clk : OUT std_logic;
protocol_res_n : OUT std_logic;
 
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
 
-- Fabric side: DAQ Rx
daq_rv : IN std_logic;
daq_rsof : IN std_logic;
daq_reof : IN std_logic;
daq_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
daq_rstop : OUT std_logic;
 
-- Fabric side: DAQ Tx
daq_tv : OUT std_logic;
daq_tsof : OUT std_logic;
daq_teof : OUT std_logic;
daq_td : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
daq_tstop : IN std_logic;
 
-- Fabric side: DLM Rx
dlm_tv : IN std_logic;
dlm_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: DLM Tx
dlm_rv : OUT std_logic;
dlm_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: CTL Rx
ctl_rv : IN std_logic;
ctl_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
ctl_rstop : OUT std_logic;
 
-- Fabric side: CTL Tx
ctl_ttake : IN std_logic;
ctl_tv : OUT std_logic;
ctl_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
ctl_tstop : IN std_logic;
 
ctl_reset : IN std_logic;
ctl_status : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Interrupter triggers
DAQ_irq : OUT std_logic;
CTL_irq : OUT std_logic;
DLM_irq : OUT std_logic;
 
-- Data generator table write port
tab_sel : IN STD_LOGIC;
tab_we : IN STD_LOGIC_VECTOR (2-1 downto 0);
tab_wa : IN STD_LOGIC_VECTOR (12-1 downto 0);
tab_wd : IN STD_LOGIC_VECTOR (64-1 downto 0);
 
-- DG control/status signal
dg_running : OUT STD_LOGIC;
dg_mask : IN STD_LOGIC;
dg_rst : IN STD_LOGIC;
 
-- DG debug signal
daq_start_led : OUT STD_LOGIC;
 
-- Fabric side: Common signals
trn_clk : IN std_logic;
protocol_link_act : OUT std_logic_vector(2-1 downto 0);
protocol_rst : IN std_logic
);
END COMPONENT;
 
-- DAQ Tx
signal data2send_start : std_logic;
signal data2send_end : std_logic;
signal data2send : std_logic_vector(64-1 downto 0);
signal crc_error_send : std_logic;
signal data2send_stop : std_logic
:= '0';
 
-- DAQ Rx
signal data_rec_start : std_logic;
signal data_rec_end : std_logic;
signal data_rec : std_logic_vector(64-1 downto 0);
signal crc_error_rec : std_logic;
signal data_rec_stop : std_logic;
 
-- CTL Tx
signal ctrl2send_start : std_logic;
signal ctrl2send_end : std_logic;
signal ctrl2send : std_logic_vector(16-1 downto 0);
signal ctrl2send_stop : std_logic;
 
-- CTL Rx
signal ctrl_rec_start : std_logic;
signal ctrl_rec_end : std_logic;
signal ctrl_rec : std_logic_vector(16-1 downto 0);
signal ctrl_rec_stop : std_logic;
 
-- DLM Tx
signal dlm2send_va : std_logic;
signal dlm2send_type : std_logic_vector(4-1 downto 0);
-- signal dlm2send_va_i : std_logic;
-- signal dlm2send_type_i : std_logic_vector(4-1 downto 0);
 
-- DLM Rx
signal dlm_rec_va : std_logic;
signal dlm_rec_type : std_logic_vector(4-1 downto 0);
-- signal dlm_rec_va_i : std_logic;
-- signal dlm_rec_type_i : std_logic_vector(4-1 downto 0);
 
 
-- Common signals
signal link_rx_clk : std_logic;
signal link_tx_clk : std_logic;
signal link_active : std_logic_vector(2-1 downto 0);
signal protocol_clk : std_logic;
signal protocol_res_n : std_logic;
 
 
-- Fabric side: DAQ Rx
signal daq_rv : std_logic;
signal daq_rsof : std_logic;
signal daq_reof : std_logic;
signal daq_rd : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal daq_rstop : std_logic;
 
-- Fabric side: DAQ Tx
signal daq_tv : std_logic;
signal daq_tsof : std_logic;
signal daq_teof : std_logic;
signal daq_td : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal daq_tstop : std_logic;
 
-- Fabric side: DLM Rx
signal dlm_tv : std_logic;
signal dlm_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: DLM Tx
signal dlm_rv : std_logic;
signal dlm_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: CTL Rx
signal ctl_rv : std_logic;
signal ctl_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal ctl_rstop : std_logic;
 
-- Fabric side: CTL Tx
signal ctl_ttake : std_logic;
signal ctl_tv : std_logic;
signal ctl_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal ctl_tstop : std_logic;
 
signal ctl_reset : std_logic;
signal ctl_status : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Interrupter triggers
signal DAQ_irq : std_logic;
signal CTL_irq : std_logic;
signal DLM_irq : std_logic;
 
-- Fabric side: Common signals
signal protocol_link_act : std_logic_vector(2-1 downto 0);
signal protocol_rst : std_logic;
 
 
-- Pseudo link module, to be replaced by the real optical link
COMPONENT pseudo_protocol_module
PORT (
-- DAQ Tx
data2send_start : IN std_logic;
data2send_end : IN std_logic;
data2send : IN std_logic_vector(64-1 downto 0);
crc_error_send : IN std_logic;
data2send_stop : OUT std_logic;
 
-- DAQ Rx
data_rec_start : OUT std_logic;
data_rec_end : OUT std_logic;
data_rec : OUT std_logic_vector(64-1 downto 0);
crc_error_rec : OUT std_logic;
data_rec_stop : IN std_logic;
 
-- CTL Tx
ctrl2send_start : IN std_logic;
ctrl2send_end : IN std_logic;
ctrl2send : IN std_logic_vector(16-1 downto 0);
ctrl2send_stop : OUT std_logic;
 
-- CTL Rx
ctrl_rec_start : OUT std_logic;
ctrl_rec_end : OUT std_logic;
ctrl_rec : OUT std_logic_vector(16-1 downto 0);
ctrl_rec_stop : IN std_logic;
 
-- DLM Tx
dlm2send_va : IN std_logic;
dlm2send_type : IN std_logic_vector(4-1 downto 0);
 
-- DLM Rx
dlm_rec_va : OUT std_logic;
dlm_rec_type : OUT std_logic_vector(4-1 downto 0);
 
-- dummy pin input
dummy_pin_in : IN std_logic_vector(3-1 downto 0);
 
-- Common interface
link_tx_clk : OUT std_logic;
link_rx_clk : OUT std_logic;
link_active : OUT std_logic_vector(2-1 downto 0);
clk : IN std_logic;
res_n : IN std_logic
);
END COMPONENT;
 
 
signal Link_Buf_full : std_logic;
 
 
------------- COMPONENT Declaration: tlpControl ------
--
component tlpControl
584,38 → 584,38
mbuf_UserFull : IN std_logic;
trn_Blinker : OUT std_logic;
 
-- DCB protocol interface
protocol_link_act : IN std_logic_vector(2-1 downto 0);
protocol_rst : OUT std_logic;
-- -- DCB protocol interface
-- protocol_link_act : IN std_logic_vector(2-1 downto 0);
-- protocol_rst : OUT std_logic;
--
-- -- Interrupter triggers
-- DAQ_irq : IN std_logic;
-- CTL_irq : IN std_logic;
-- DLM_irq : IN std_logic;
--
-- -- Fabric side: CTL Rx
-- ctl_rv : OUT std_logic;
-- ctl_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Fabric side: CTL Tx
-- ctl_ttake : OUT std_logic;
-- ctl_tv : IN std_logic;
-- ctl_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- ctl_tstop : OUT std_logic;
--
-- ctl_reset : OUT std_logic;
-- ctl_status : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Fabric side: DLM Rx
-- dlm_tv : OUT std_logic;
-- dlm_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Fabric side: DLM Tx
-- dlm_rv : IN std_logic;
-- dlm_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- Link_Buf_full : IN std_logic;
 
-- Interrupter triggers
DAQ_irq : IN std_logic;
CTL_irq : IN std_logic;
DLM_irq : IN std_logic;
 
-- Fabric side: CTL Rx
ctl_rv : OUT std_logic;
ctl_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: CTL Tx
ctl_ttake : OUT std_logic;
ctl_tv : IN std_logic;
ctl_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
ctl_tstop : OUT std_logic;
 
ctl_reset : OUT std_logic;
ctl_status : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: DLM Rx
dlm_tv : OUT std_logic;
dlm_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: DLM Tx
dlm_rv : IN std_logic;
dlm_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
Link_Buf_full : IN std_logic;
 
-- Event Buffer FIFO interface
eb_FIFO_we : OUT std_logic;
eb_FIFO_wsof : OUT std_logic;
674,16 → 674,16
DDR_FIFO_Empty : IN std_logic;
DDR_FIFO_RdQout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
-- Data generator table write
tab_we : OUT std_logic_vector(2-1 downto 0);
tab_wa : OUT std_logic_vector(12-1 downto 0);
tab_wd : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- -- Data generator table write
-- tab_we : OUT std_logic_vector(2-1 downto 0);
-- tab_wa : OUT std_logic_vector(12-1 downto 0);
-- tab_wd : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
--
-- -- Data generator control
-- DG_is_Running : IN std_logic;
-- DG_Reset : OUT std_logic;
-- DG_Mask : OUT std_logic;
 
-- Data generator control
DG_is_Running : IN std_logic;
DG_Reset : OUT std_logic;
DG_Mask : OUT std_logic;
 
-- Transaction layer interface
trn_lnk_up_n : IN std_logic;
trn_rsrc_dsc_n : IN std_logic;
1049,10 → 1049,9
end generate;
 
 
-- DAQ_irq <= eb_empty;
 
DAQ_irq <= eb_empty;
 
 
-- ---------------------------------------------------------------
-- tlp control module
--
1063,38 → 1062,38
mbuf_UserFull => '0' ,
trn_Blinker => trn_Blinker ,
 
-- DCB protocol interface
protocol_link_act => protocol_link_act , -- IN std_logic_vector(2-1 downto 0);
protocol_rst => protocol_rst , -- OUT std_logic;
-- -- DCB protocol interface
-- protocol_link_act => protocol_link_act , -- IN std_logic_vector(2-1 downto 0);
-- protocol_rst => protocol_rst , -- OUT std_logic;
--
-- Link_Buf_Full => daq_rstop , -- IN std_logic;
--
-- -- Interrupter triggers
-- DAQ_irq => DAQ_irq , -- IN std_logic;
-- CTL_irq => CTL_irq , -- IN std_logic;
-- DLM_irq => DLM_irq , -- IN std_logic;
--
-- -- Fabric side: CTL Rx
-- ctl_rv => ctl_rv , -- OUT std_logic;
-- ctl_rd => ctl_rd , -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Fabric side: CTL Tx
-- ctl_ttake => ctl_ttake , -- OUT std_logic;
-- ctl_tv => ctl_tv , -- IN std_logic;
-- ctl_td => ctl_td , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- ctl_tstop => ctl_tstop , -- OUT std_logic;
--
-- ctl_reset => ctl_reset , -- OUT std_logic;
-- ctl_status => ctl_status , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Fabric side: DLM Rx
-- dlm_tv => dlm_tv , -- OUT std_logic;
-- dlm_td => dlm_td , -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--
-- -- Fabric side: DLM Tx
-- dlm_rv => dlm_rv , -- IN std_logic;
-- dlm_rd => dlm_rd , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
Link_Buf_Full => daq_rstop , -- IN std_logic;
 
-- Interrupter triggers
DAQ_irq => DAQ_irq , -- IN std_logic;
CTL_irq => CTL_irq , -- IN std_logic;
DLM_irq => DLM_irq , -- IN std_logic;
 
-- Fabric side: CTL Rx
ctl_rv => ctl_rv , -- OUT std_logic;
ctl_rd => ctl_rd , -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: CTL Tx
ctl_ttake => ctl_ttake , -- OUT std_logic;
ctl_tv => ctl_tv , -- IN std_logic;
ctl_td => ctl_td , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
ctl_tstop => ctl_tstop , -- OUT std_logic;
 
ctl_reset => ctl_reset , -- OUT std_logic;
ctl_status => ctl_status , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: DLM Rx
dlm_tv => dlm_tv , -- OUT std_logic;
dlm_td => dlm_td , -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Fabric side: DLM Tx
dlm_rv => dlm_rv , -- IN std_logic;
dlm_rd => dlm_rd , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
-- Event Buffer FIFO interface
eb_FIFO_we => eb_we , -- OUT std_logic;
eb_FIFO_wsof => eb_wsof , -- OUT std_logic;
1156,14 → 1155,14
DDR_FIFO_Empty => DDR_FIFO_Empty , -- IN std_logic;
DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
-- Data generator table write
tab_we => tab_we , -- OUT std_logic_vector(2-1 downto 0);
tab_wa => tab_wa , -- OUT std_logic_vector(12-1 downto 0);
tab_wd => tab_wd , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- -- Data generator table write
-- tab_we => tab_we , -- OUT std_logic_vector(2-1 downto 0);
-- tab_wa => tab_wa , -- OUT std_logic_vector(12-1 downto 0);
-- tab_wd => tab_wd , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
DG_is_Running => dg_running , -- IN std_logic;
DG_Reset => dg_rst , -- OUT STD_LOGIC;
DG_Mask => dg_mask , -- OUT STD_LOGIC
-- DG_is_Running => dg_running , -- IN std_logic;
-- DG_Reset => dg_rst , -- OUT STD_LOGIC;
-- DG_Mask => dg_mask , -- OUT STD_LOGIC
 
-------------------
-- Transaction Interface
1263,18 → 1262,18
-- Event Buffer wrapper
--
 
LEDs_IO_pin(0) <= trn_reset_n xor Format_Shower;
LEDs_IO_pin(1) <= trn_lnk_up_n xor DDR_Blinker;
LEDs_IO_pin(2) <= link_active(0);
LEDs_IO_pin(3) <= link_active(1); -- dg_debug_led;
LEDs_IO_pin(0) <= trn_reset_n;
LEDs_IO_pin(1) <= trn_lnk_up_n;
LEDs_IO_pin(2) <= Format_Shower;
LEDs_IO_pin(3) <= DDR_Blinker;
 
 
event_buffer0:
eb_wrapper
queue_buffer:
FIFO_wrapper
port map (
wr_clk => trn_clk , -- eb_wclk ,
wr_en => eb_we_up ,
din => eb_din_up ,
wr_en => eb_we ,
din => eb_din ,
pfull => eb_pfull ,
full => eb_full ,
 
1304,186 → 1303,186
eb_FIFO_Status(2) <= eb_full; -- daq_rstop;
eb_FIFO_Status(1) <= eb_pfull;
eb_FIFO_Status(0) <= eb_empty;
eb_FIFO_ow <= eb_we_up and eb_full;
eb_FIFO_ow <= eb_we and eb_full;
 
 
--
-- .......................
--
daq_rv <= eb_we;
daq_rsof <= eb_wsof;
daq_reof <= eb_weof;
daq_rd <= eb_din(C_DBUS_WIDTH-1 downto 0);
-- --
-- -- .......................
-- --
--
-- daq_rv <= eb_we;
-- daq_rsof <= eb_wsof;
-- daq_reof <= eb_weof;
-- daq_rd <= eb_din(C_DBUS_WIDTH-1 downto 0);
--
-- eb_we_up <= daq_tv or self_feed_daq;
-- eb_din_up <= C_ALL_ZEROS(72-1 downto C_DBUS_WIDTH+2) & daq_tsof & daq_teof & daq_td;
-- daq_tstop <= eb_pfull;
--
--
-- --
-- -- Protocol Interface
-- --
-- ABB_DCB_Interface0:
-- protocol_IF
-- port map (
-- -- DAQ Tx
-- data2send_start => data2send_start , -- OUT std_logic;
-- data2send_end => data2send_end , -- OUT std_logic;
-- data2send => data2send , -- OUT std_logic_vector(16-1 downto 0);
-- crc_error_send => crc_error_send , -- OUT std_logic;
-- data2send_stop => data2send_stop , -- IN std_logic;
--
-- -- DAQ Rx
-- data_rec_start => data_rec_start , -- IN std_logic;
-- data_rec_end => data_rec_end , -- IN std_logic;
-- data_rec => data_rec , -- IN std_logic_vector(16-1 downto 0);
-- crc_error_rec => crc_error_rec , -- IN std_logic;
-- data_rec_stop => data_rec_stop , -- OUT std_logic;
--
-- -- CTL Tx
-- ctrl2send_start => ctrl2send_start , -- OUT std_logic;
-- ctrl2send_end => ctrl2send_end , -- OUT std_logic;
-- ctrl2send => ctrl2send , -- OUT std_logic_vector(16-1 downto 0);
-- ctrl2send_stop => ctrl2send_stop , -- IN std_logic;
--
-- -- CTL Rx
-- ctrl_rec_start => ctrl_rec_start , -- IN std_logic;
-- ctrl_rec_end => ctrl_rec_end , -- IN std_logic;
-- ctrl_rec => ctrl_rec , -- IN std_logic_vector(16-1 downto 0);
-- ctrl_rec_stop => ctrl_rec_stop , -- OUT std_logic;
--
-- -- DLM Tx
-- dlm2send_va => dlm2send_va , -- OUT std_logic;
-- dlm2send_type => dlm2send_type , -- OUT std_logic_vector(4-1 downto 0);
--
-- -- DLM Rx
-- dlm_rec_va => dlm_rec_va , -- IN std_logic;
-- dlm_rec_type => dlm_rec_type , -- IN std_logic_vector(4-1 downto 0);
--
-- -- Common signals
-- link_tx_clk => link_tx_clk , -- IN std_logic;
-- link_rx_clk => link_rx_clk , -- IN std_logic;
-- link_active => link_active , -- IN std_logic_vector(2-1 downto 0);
-- protocol_clk => protocol_clk , -- OUT std_logic;
-- protocol_res_n => protocol_res_n , -- OUT std_logic;
--
--
-- -- Fabric side: DAQ Rx
-- daq_rv => daq_rv , -- IN std_logic;
-- daq_rsof => daq_rsof , -- IN std_logic;
-- daq_reof => daq_reof , -- IN std_logic;
-- daq_rd => daq_rd , -- IN std_logic_vector(64-1 downto 0);
-- daq_rstop => daq_rstop , -- OUT std_logic;
--
-- -- Fabric side: DAQ Tx
-- daq_tv => daq_tv , -- OUT std_logic;
-- daq_tsof => daq_tsof , -- OUT std_logic;
-- daq_teof => daq_teof , -- OUT std_logic;
-- daq_td => daq_td , -- OUT std_logic_vector(64-1 downto 0);
-- daq_tstop => daq_tstop , -- IN std_logic;
--
-- -- Fabric side: CTL Rx
-- ctl_rv => ctl_rv , -- IN std_logic;
-- ctl_rd => ctl_rd , -- IN std_logic_vector(32-1 downto 0);
-- ctl_rstop => ctl_rstop , -- OUT std_logic;
--
-- -- Fabric side: CTL Tx
-- ctl_ttake => ctl_ttake , -- IN std_logic;
-- ctl_tv => ctl_tv , -- OUT std_logic;
-- ctl_td => ctl_td , -- OUT std_logic_vector(32-1 downto 0);
-- ctl_tstop => ctl_tstop , -- IN std_logic;
--
-- ctl_reset => ctl_reset , -- IN std_logic;
-- ctl_status => ctl_status , -- OUT std_logic_vector(32-1 downto 0);
--
-- -- Fabric side: DLM Rx
-- dlm_tv => dlm_tv , -- IN std_logic;
-- dlm_td => dlm_td , -- IN std_logic_vector(4-1 downto 0);
--
-- -- Fabric side: DLM Tx
-- dlm_rv => dlm_rv , -- OUT std_logic;
-- dlm_rd => dlm_rd , -- OUT std_logic_vector(4-1 downto 0);
--
-- -- Interrupter triggers
-- DAQ_irq => open, -- DAQ_irq , -- OUT std_logic;
-- CTL_irq => CTL_irq , -- OUT std_logic;
-- DLM_irq => DLM_irq , -- OUT std_logic;
--
-- -- Data generator table write port
-- tab_sel => '1' , -- IN STD_LOGIC;
-- tab_we => tab_we , -- IN STD_LOGIC_VECTOR (2-1 downto 0);
-- tab_wa => tab_wa , -- IN STD_LOGIC_VECTOR (12-1 downto 0);
-- tab_wd => tab_wd , -- IN STD_LOGIC_VECTOR (64-1 downto 0);
--
-- -- DG control/status signal
-- dg_running => dg_running , -- OUT STD_LOGIC;
-- dg_mask => dg_mask , -- IN STD_LOGIC;
-- dg_rst => dg_rst , -- IN STD_LOGIC
--
-- -- DG debug signal
-- daq_start_led => dg_debug_led , -- OUT STD_LOGIC;
--
-- -- Fabric side: Common signals
-- trn_clk => trn_clk , -- IN std_logic;
-- protocol_link_act => protocol_link_act , -- OUT std_logic_vector(2-1 downto 0);
-- protocol_rst => protocol_rst -- IN std_logic
-- );
--
--
-- --
-- -- Module emulating the link
-- --
--
-- DCB_Link_module0:
-- pseudo_protocol_module
-- port map (
-- -- DAQ Tx
-- data2send_start => data2send_start , -- IN std_logic;
-- data2send_end => data2send_end , -- IN std_logic;
-- data2send => data2send , -- IN std_logic_vector(16-1 downto 0);
-- crc_error_send => crc_error_send , -- IN std_logic;
-- data2send_stop => data2send_stop , -- OUT std_logic;
--
-- -- DAQ Rx
-- data_rec_start => data_rec_start , -- OUT std_logic;
-- data_rec_end => data_rec_end , -- OUT std_logic;
-- data_rec => data_rec , -- OUT std_logic_vector(16-1 downto 0);
-- crc_error_rec => crc_error_rec , -- OUT std_logic;
-- data_rec_stop => data_rec_stop , -- IN std_logic;
--
-- -- CTL Tx
-- ctrl2send_start => ctrl2send_start , -- IN std_logic;
-- ctrl2send_end => ctrl2send_end , -- IN std_logic;
-- ctrl2send => ctrl2send , -- IN std_logic_vector(16-1 downto 0);
-- ctrl2send_stop => ctrl2send_stop , -- OUT std_logic;
--
-- -- CTL Rx
-- ctrl_rec_start => ctrl_rec_start , -- OUT std_logic;
-- ctrl_rec_end => ctrl_rec_end , -- OUT std_logic;
-- ctrl_rec => ctrl_rec , -- OUT std_logic_vector(16-1 downto 0);
-- ctrl_rec_stop => ctrl_rec_stop , -- IN std_logic;
--
-- -- DLM Tx
-- dlm2send_va => dlm2send_va , -- IN std_logic;
-- dlm2send_type => dlm2send_type , -- IN std_logic_vector(4-1 downto 0);
--
-- -- DLM Rx
-- dlm_rec_va => dlm_rec_va , -- OUT std_logic;
-- dlm_rec_type => dlm_rec_type , -- OUT std_logic_vector(4-1 downto 0);
--
-- -- dummy pin input !!!! not really exists
-- dummy_pin_in => "000", -- dummy_pin_in , -- IN std_logic_vector(3-1 downto 0);
---- dummy_pin_in => dummy_pin_in , -- IN std_logic_vector(3-1 downto 0);
--
-- -- Common interface
-- link_tx_clk => link_tx_clk , -- OUT std_logic;
-- link_rx_clk => link_rx_clk , -- OUT std_logic;
-- link_active => link_active , -- OUT std_logic_vector(2-1 downto 0);
-- clk => protocol_clk , -- IN std_logic;
-- res_n => protocol_res_n -- IN std_logic
-- );
 
eb_we_up <= daq_tv or self_feed_daq;
eb_din_up <= C_ALL_ZEROS(72-1 downto C_DBUS_WIDTH+2) & daq_tsof & daq_teof & daq_td;
daq_tstop <= eb_pfull;
 
 
--
-- Protocol Interface
--
ABB_DCB_Interface0:
protocol_IF
port map (
-- DAQ Tx
data2send_start => data2send_start , -- OUT std_logic;
data2send_end => data2send_end , -- OUT std_logic;
data2send => data2send , -- OUT std_logic_vector(16-1 downto 0);
crc_error_send => crc_error_send , -- OUT std_logic;
data2send_stop => data2send_stop , -- IN std_logic;
 
-- DAQ Rx
data_rec_start => data_rec_start , -- IN std_logic;
data_rec_end => data_rec_end , -- IN std_logic;
data_rec => data_rec , -- IN std_logic_vector(16-1 downto 0);
crc_error_rec => crc_error_rec , -- IN std_logic;
data_rec_stop => data_rec_stop , -- OUT std_logic;
 
-- CTL Tx
ctrl2send_start => ctrl2send_start , -- OUT std_logic;
ctrl2send_end => ctrl2send_end , -- OUT std_logic;
ctrl2send => ctrl2send , -- OUT std_logic_vector(16-1 downto 0);
ctrl2send_stop => ctrl2send_stop , -- IN std_logic;
 
-- CTL Rx
ctrl_rec_start => ctrl_rec_start , -- IN std_logic;
ctrl_rec_end => ctrl_rec_end , -- IN std_logic;
ctrl_rec => ctrl_rec , -- IN std_logic_vector(16-1 downto 0);
ctrl_rec_stop => ctrl_rec_stop , -- OUT std_logic;
 
-- DLM Tx
dlm2send_va => dlm2send_va , -- OUT std_logic;
dlm2send_type => dlm2send_type , -- OUT std_logic_vector(4-1 downto 0);
 
-- DLM Rx
dlm_rec_va => dlm_rec_va , -- IN std_logic;
dlm_rec_type => dlm_rec_type , -- IN std_logic_vector(4-1 downto 0);
 
-- Common signals
link_tx_clk => link_tx_clk , -- IN std_logic;
link_rx_clk => link_rx_clk , -- IN std_logic;
link_active => link_active , -- IN std_logic_vector(2-1 downto 0);
protocol_clk => protocol_clk , -- OUT std_logic;
protocol_res_n => protocol_res_n , -- OUT std_logic;
 
 
-- Fabric side: DAQ Rx
daq_rv => daq_rv , -- IN std_logic;
daq_rsof => daq_rsof , -- IN std_logic;
daq_reof => daq_reof , -- IN std_logic;
daq_rd => daq_rd , -- IN std_logic_vector(64-1 downto 0);
daq_rstop => daq_rstop , -- OUT std_logic;
 
-- Fabric side: DAQ Tx
daq_tv => daq_tv , -- OUT std_logic;
daq_tsof => daq_tsof , -- OUT std_logic;
daq_teof => daq_teof , -- OUT std_logic;
daq_td => daq_td , -- OUT std_logic_vector(64-1 downto 0);
daq_tstop => daq_tstop , -- IN std_logic;
 
-- Fabric side: CTL Rx
ctl_rv => ctl_rv , -- IN std_logic;
ctl_rd => ctl_rd , -- IN std_logic_vector(32-1 downto 0);
ctl_rstop => ctl_rstop , -- OUT std_logic;
 
-- Fabric side: CTL Tx
ctl_ttake => ctl_ttake , -- IN std_logic;
ctl_tv => ctl_tv , -- OUT std_logic;
ctl_td => ctl_td , -- OUT std_logic_vector(32-1 downto 0);
ctl_tstop => ctl_tstop , -- IN std_logic;
 
ctl_reset => ctl_reset , -- IN std_logic;
ctl_status => ctl_status , -- OUT std_logic_vector(32-1 downto 0);
 
-- Fabric side: DLM Rx
dlm_tv => dlm_tv , -- IN std_logic;
dlm_td => dlm_td , -- IN std_logic_vector(4-1 downto 0);
 
-- Fabric side: DLM Tx
dlm_rv => dlm_rv , -- OUT std_logic;
dlm_rd => dlm_rd , -- OUT std_logic_vector(4-1 downto 0);
 
-- Interrupter triggers
DAQ_irq => open, -- DAQ_irq , -- OUT std_logic;
CTL_irq => CTL_irq , -- OUT std_logic;
DLM_irq => DLM_irq , -- OUT std_logic;
 
-- Data generator table write port
tab_sel => '1' , -- IN STD_LOGIC;
tab_we => tab_we , -- IN STD_LOGIC_VECTOR (2-1 downto 0);
tab_wa => tab_wa , -- IN STD_LOGIC_VECTOR (12-1 downto 0);
tab_wd => tab_wd , -- IN STD_LOGIC_VECTOR (64-1 downto 0);
 
-- DG control/status signal
dg_running => dg_running , -- OUT STD_LOGIC;
dg_mask => dg_mask , -- IN STD_LOGIC;
dg_rst => dg_rst , -- IN STD_LOGIC
 
-- DG debug signal
daq_start_led => dg_debug_led , -- OUT STD_LOGIC;
 
-- Fabric side: Common signals
trn_clk => trn_clk , -- IN std_logic;
protocol_link_act => protocol_link_act , -- OUT std_logic_vector(2-1 downto 0);
protocol_rst => protocol_rst -- IN std_logic
);
 
 
--
-- Module emulating the link
--
 
DCB_Link_module0:
pseudo_protocol_module
port map (
-- DAQ Tx
data2send_start => data2send_start , -- IN std_logic;
data2send_end => data2send_end , -- IN std_logic;
data2send => data2send , -- IN std_logic_vector(16-1 downto 0);
crc_error_send => crc_error_send , -- IN std_logic;
data2send_stop => data2send_stop , -- OUT std_logic;
 
-- DAQ Rx
data_rec_start => data_rec_start , -- OUT std_logic;
data_rec_end => data_rec_end , -- OUT std_logic;
data_rec => data_rec , -- OUT std_logic_vector(16-1 downto 0);
crc_error_rec => crc_error_rec , -- OUT std_logic;
data_rec_stop => data_rec_stop , -- IN std_logic;
 
-- CTL Tx
ctrl2send_start => ctrl2send_start , -- IN std_logic;
ctrl2send_end => ctrl2send_end , -- IN std_logic;
ctrl2send => ctrl2send , -- IN std_logic_vector(16-1 downto 0);
ctrl2send_stop => ctrl2send_stop , -- OUT std_logic;
 
-- CTL Rx
ctrl_rec_start => ctrl_rec_start , -- OUT std_logic;
ctrl_rec_end => ctrl_rec_end , -- OUT std_logic;
ctrl_rec => ctrl_rec , -- OUT std_logic_vector(16-1 downto 0);
ctrl_rec_stop => ctrl_rec_stop , -- IN std_logic;
 
-- DLM Tx
dlm2send_va => dlm2send_va , -- IN std_logic;
dlm2send_type => dlm2send_type , -- IN std_logic_vector(4-1 downto 0);
 
-- DLM Rx
dlm_rec_va => dlm_rec_va , -- OUT std_logic;
dlm_rec_type => dlm_rec_type , -- OUT std_logic_vector(4-1 downto 0);
 
-- dummy pin input !!!! not really exists
dummy_pin_in => "000", -- dummy_pin_in , -- IN std_logic_vector(3-1 downto 0);
-- dummy_pin_in => dummy_pin_in , -- IN std_logic_vector(3-1 downto 0);
 
-- Common interface
link_tx_clk => link_tx_clk , -- OUT std_logic;
link_rx_clk => link_rx_clk , -- OUT std_logic;
link_active => link_active , -- OUT std_logic_vector(2-1 downto 0);
clk => protocol_clk , -- IN std_logic;
res_n => protocol_res_n -- IN std_logic
);
 
 
 
end Behavioral;
/trunk/rtl/FIFO_Wrapper.vhd
4,7 → 4,7
--
-- Create Date: 16:37:22 12 Feb 2009
-- Design Name:
-- Module Name: eb_wrapper - Behavioral
-- Module Name: FIFO_wrapper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
30,7 → 30,7
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity eb_wrapper is
entity FIFO_wrapper is
Generic (
C_ASYNFIFO_WIDTH : integer := 72
);
50,10 → 50,10
data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
rst : IN std_logic
);
end entity eb_wrapper;
end entity FIFO_wrapper;
 
 
architecture Behavioral of eb_wrapper is
architecture Behavioral of FIFO_wrapper is
 
--- 16384 x 72
component eb_fifo
/trunk/sim/tf64_pcie_trn.v
0,0 → 1,2214
`timescale 1ns / 1ps
 
////////////////////////////////////////////////////////////////////////////////
// Company: ziti, Uni. HD
// Engineer: wgao
// weng.ziti@gmail.com
//
// Create Date: 16:54:18 04 Nov 2008
// Design Name: tlpControl
// Module Name: tf64_pcie_trn.v
// Project Name: PCIE_SG_DMA
// Target Device:
// Tool versions:
// Description: PIO and DMA are both simulated.
//
// Verilog Test Fixture created by ISE for module: tlpControl
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
//
// Revision 1.00 - Released to OpenCores.org 14.09.2011
//
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
 
 
//`define RANDOM_SEQUENCE
 
/* Time parameters */
`define T_HALF_CYCLE_CLK 4.0
`define T_HALF_CYCLE_MEMCLK 5.0
`define T_DELAY_AFTER 0.0
`define T_DELTA 0.1
`define T_PIO_INTERVAL 50.0
`define T_DMA_INTERVAL 300.0
//`define T_DMA_TURN_AROUND 100.0
//`define T_STATISTIC_INTERVAL 10000.0
`define T_RX_NO_FC_PERIOD 1900000.0
`define T_TX_NO_FC_PERIOD 1500000.0
 
/* Memory size for simulation */
`define C_ARRAY_DIMENSION 4096
 
/* Start indices */
`define PIO_START_INDEX 'H0300
`define DMA_START_INDEX 'H0000
 
/* Request completion boundary */
`define C_RCB_16_DW 'H10
`define C_RCB_32_DW 'H20
 
/* BAR */
`define C_BAR0_HIT 7'H7E
`define C_BAR1_HIT 7'H7D
`define C_BAR2_HIT 7'H7B
`define C_BAR3_HIT 7'H77
`define C_BAR4_HIT 7'H6F
`define C_BAR5_HIT 7'H5F
`define C_BAR6_HIT 7'H3F
`define C_NO_BAR_HIT 7'H7F
 
 
/* Requester ID and Completer ID */
`define C_HOST_WRREQ_ID 16'H0ABC
`define C_HOST_RDREQ_ID 16'HE1E2
`define C_HOST_CPLD_ID 16'HC01D
 
/* 1st header */
`define HEADER0_MWR3_ 32'H40000000
`define HEADER0_MWR4_ 32'H60000000
`define HEADER0_MRD3_ 32'H00000000
`define HEADER0_MRD4_ 32'H20000000
`define HEADER0_CPLD 32'H4A000000
`define HEADER0_CPL 32'H0A000000
`define HEADER0_MSG 32'H34000001
 
/* Message codes */
`define C_MSG_CODE_INTA 8'H20
`define C_MSG_CODE_INTA_N 8'H24
 
/* Payload type */
`define USE_PRIVATE 1
`define USE_PUBLIC 0
 
/* General registers */
`define C_ADDR_VERSION 32'H0000
`define C_ADDR_IRQ_STAT 32'H0008
`define C_ADDR_IRQ_EN 32'H0010
`define C_ADDR_GSR 32'H0020
`define C_ADDR_GCR 32'H0028
 
/* Control registers for special ports */
`define C_ADDR_MRD_CTRL 32'H0074
`define C_ADDR_TX_CTRL 32'H0078
`define C_ADDR_ICAP 32'H007C
`define C_ADDR_EB_STACON 32'H0090
 
/* Downstream DMA channel registers */
`define C_ADDR_DMA_DS_PAH 32'H0050
`define C_ADDR_DMA_DS_CTRL 32'H006C
`define C_ADDR_DMA_DS_STA 32'H0070
 
/* Upstream DMA channel registers */
`define C_ADDR_DMA_US_PAH 32'H002C
`define C_ADDR_DMA_US_CTRL 32'H0048
`define C_ADDR_DMA_US_STA 32'H004C
 
/* DMA-specific constants */
`define C_DMA_RST_CMD 32'H0200000A
 
 
module tf64_pcie_trn();
 
// Inputs
reg trn_reset_n;
reg trn_lnk_up_n;
reg trn_clk;
reg trn_rsof_n;
reg trn_reof_n;
reg [63:0] trn_rd;
reg [7:0] trn_rrem_n;
reg trn_rsrc_rdy_n;
wire trn_rdst_rdy_n;
reg [6:0] trn_rbar_hit_n;
wire trn_rnp_ok_n;
reg trn_rerrfwd_n;
reg trn_rsrc_dsc_n;
wire trn_tsof_n;
wire trn_teof_n;
wire [63:0] trn_td;
wire [7:0] trn_trem_n;
wire trn_tsrc_rdy_n;
reg trn_tdst_rdy_n;
wire trn_terrfwd_n;
wire trn_tsrc_dsc_n;
reg trn_tdst_dsc_n;
reg [3:0] trn_tbuf_av;
// reg cfg_interrupt_rdy_n;
// reg [2:0] cfg_interrupt_mmenable;
// reg cfg_interrupt_msienable;
// reg [7:0] cfg_interrupt_do;
reg [5:0] pcie_link_width;
reg [15:0] cfg_dcommand;
reg [15:0] localID;
 
// Outputs
wire DDR_wr_v;
wire DDR_wr_sof;
wire DDR_wr_eof;
wire DDR_wr_Shift;
wire [1:0] DDR_wr_Mask;
wire [63:0] DDR_wr_din;
wire DDR_wr_full;
wire DDR_rdc_v;
wire DDR_rdc_sof;
wire DDR_rdc_eof;
wire DDR_rdc_Shift;
wire [63:0] DDR_rdc_din;
wire DDR_rdc_full;
wire DDR_FIFO_RdEn;
wire DDR_FIFO_Empty;
wire [63:0] DDR_FIFO_RdQout;
reg mbuf_UserFull;
wire DDR_Ready;
wire trn_Blinker;
reg mem_clk;
 
// FIFO
wire eb_FIFO_we;
wire [64-1:00] eb_FIFO_din;
wire eb_FIFO_re;
wire [72-1:00] eb_FIFO_qout;
wire [64-1:00] eb_FIFO_Status;
wire eb_FIFO_Rst;
 
wire eb_pfull;
wire eb_full;
wire eb_pempty;
wire eb_empty;
 
wire [27-1:0] eb_FIFO_Data_Count;
 
// flow control toggles
reg Rx_No_Flow_Control;
reg Tx_No_Flow_Control;
 
// message counters
reg [31:00] Accum_Msg_INTA = 0;
reg [31:00] Accum_Msg_INTA_n = 0;
 
// random seed
reg [127: 0] Op_Random;
 
// Generated Array
reg [15:00] ii;
reg [31:00] D_Array[`C_ARRAY_DIMENSION-1:00];
 
//
reg [ 7: 0] FSM_Trn;
reg [31: 0] Hdr_Array[3:0];
reg [31: 0] Private_Array[15:0];
reg [10: 0] Rx_TLP_Length;
reg [ 7: 0] Rx_MWr_Tag;
reg [ 4: 0] Rx_MRd_Tag;
reg [31:00] Tx_MRd_Addr;
reg [31:00] Tx_MRd_Leng;
reg [10: 0] tx_MRd_Length;
reg [ 7: 0] tx_MRd_Tag;
reg [ 7: 0] tx_MRd_Tag_k;
 
reg [31:00] DMA_PA;
reg [63:00] DMA_HA;
reg [63:00] DMA_BDA;
reg [31:00] DMA_Leng;
reg [31:00] DMA_L1;
reg [31:00] DMA_L2;
reg [02:00] DMA_bar;
reg DMA_ds_is_Last;
reg DMA_us_is_Last;
reg [31:00] CplD_Index;
 
reg Desc_tx_MRd_Valid;
reg [10:00] Desc_tx_MRd_Leng;
reg [31:00] Desc_tx_MRd_Addr;
reg [07:00] Desc_tx_MRd_TAG;
reg tx_MRd_come;
 
reg [63:00] PIO_Addr;
reg [31:00] PIO_Leng;
reg [ 3:00] PIO_1st_BE;
reg [ 6:00] PIO_bar;
//
wire DBG_dma_start;
 
 
 
// Instantiate the Unit Under Test (UUT)
tlpControl uut (
.mbuf_UserFull(mbuf_UserFull),
.trn_Blinker(trn_Blinker),
.eb_FIFO_we (eb_FIFO_we ) , // : OUT std_logic;
.eb_FIFO_din (eb_FIFO_din ) , // : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
.eb_FIFO_re (eb_FIFO_re ) , // : OUT std_logic;
.eb_FIFO_empty (eb_empty ) , // : IN std_logic;
.eb_FIFO_qout (eb_FIFO_qout[63:0] ) , // : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
.eb_FIFO_Data_Count (eb_FIFO_Data_Count ) , // : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
.eb_FIFO_Status (eb_FIFO_Status) , // : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
.eb_FIFO_Rst (eb_FIFO_Rst ) , // : OUT std_logic;
.Link_Buf_full (eb_pfull ) ,
.DMA_ds_Start (DBG_dma_start),
.DDR_Ready (DDR_Ready),
.DDR_wr_sof(DDR_wr_sof),
.DDR_wr_eof(DDR_wr_eof),
.DDR_wr_v(DDR_wr_v),
.DDR_wr_FA( ),
.DDR_wr_Shift(DDR_wr_Shift),
.DDR_wr_Mask(DDR_wr_Mask),
.DDR_wr_din(DDR_wr_din),
.DDR_wr_full(DDR_wr_full),
.DDR_rdc_sof(DDR_rdc_sof),
.DDR_rdc_eof(DDR_rdc_eof),
.DDR_rdc_v(DDR_rdc_v),
.DDR_rdc_FA( ),
.DDR_rdc_Shift(DDR_rdc_Shift),
.DDR_rdc_din(DDR_rdc_din),
.DDR_rdc_full(DDR_rdc_full),
.DDR_FIFO_RdEn(DDR_FIFO_RdEn),
.DDR_FIFO_Empty(DDR_FIFO_Empty),
.DDR_FIFO_RdQout(DDR_FIFO_RdQout),
.trn_clk(trn_clk),
.trn_reset_n(trn_reset_n),
.trn_lnk_up_n(trn_lnk_up_n),
.trn_rsof_n(trn_rsof_n),
.trn_reof_n(trn_reof_n),
.trn_rd(trn_rd),
.trn_rrem_n(trn_rrem_n),
.trn_rerrfwd_n(trn_rerrfwd_n),
.trn_rsrc_rdy_n(trn_rsrc_rdy_n),
.trn_rdst_rdy_n(trn_rdst_rdy_n),
.trn_rnp_ok_n(trn_rnp_ok_n),
.trn_rsrc_dsc_n(trn_rsrc_dsc_n),
.trn_rbar_hit_n(trn_rbar_hit_n),
.trn_tsof_n(trn_tsof_n),
.trn_teof_n(trn_teof_n),
.trn_td(trn_td),
.trn_trem_n(trn_trem_n),
.trn_terrfwd_n(trn_terrfwd_n),
.trn_tsrc_rdy_n(trn_tsrc_rdy_n),
.trn_tdst_rdy_n(trn_tdst_rdy_n),
.trn_tsrc_dsc_n(trn_tsrc_dsc_n),
.trn_tdst_dsc_n(trn_tdst_dsc_n),
.trn_tbuf_av(trn_tbuf_av),
// .cfg_interrupt_n(cfg_interrupt_n),
// .cfg_interrupt_rdy_n(cfg_interrupt_rdy_n),
// .cfg_interrupt_mmenable(cfg_interrupt_mmenable),
// .cfg_interrupt_msienable(cfg_interrupt_msienable),
// .cfg_interrupt_di(cfg_interrupt_di),
// .cfg_interrupt_do(cfg_interrupt_do),
// .cfg_interrupt_assert_n(cfg_interrupt_assert_n),
.pcie_link_width(pcie_link_width),
.cfg_dcommand(cfg_dcommand),
.localID(localID)
);
 
 
 
// Instantiate the BRAM module
bram_Control
bram_controller(
.DDR_wr_sof(DDR_wr_sof),
.DDR_wr_eof(DDR_wr_eof),
.DDR_wr_v(DDR_wr_v),
.DDR_wr_FA(1'b0),
.DDR_wr_Shift(DDR_wr_Shift),
.DDR_wr_Mask(DDR_wr_Mask),
.DDR_wr_din(DDR_wr_din),
// .DDR_wr_full(DDR_wr_full),
.DDR_rdc_sof(DDR_rdc_sof),
.DDR_rdc_eof(DDR_rdc_eof),
.DDR_rdc_v(DDR_rdc_v),
.DDR_rdc_FA(1'b0),
.DDR_rdc_Shift(DDR_rdc_Shift),
.DDR_rdc_din(DDR_rdc_din),
.DDR_rdc_full(DDR_rdc_full),
.DDR_FIFO_RdEn(DDR_FIFO_RdEn),
.DDR_FIFO_Empty(DDR_FIFO_Empty),
.DDR_FIFO_RdQout(DDR_FIFO_RdQout),
.DBG_dma_start(DBG_dma_start),
.DDR_Ready(DDR_Ready),
.DDR_blinker(DDR_blinker),
.Sim_Zeichen(Sim_Zeichen),
.mem_clk(mem_clk),
.trn_clk(trn_clk),
.trn_reset_n(trn_reset_n)
);
 
assign DDR_wr_full = 0;
 
 
// Instantiate the FIFO module
FIFO_wrapper
queue_buffer(
.wr_clk ( trn_clk ),
.wr_en ( eb_FIFO_we ),
.din ( {8'H0, eb_FIFO_din} ),
.pfull ( eb_pfull ),
.full ( eb_full ),
 
.rd_clk ( trn_clk ),
.rd_en ( eb_FIFO_re ),
.dout ( eb_FIFO_qout ),
.pempty ( eb_pempty ),
.empty ( eb_empty ),
.data_count ( eb_FIFO_Data_Count[14:1]),
 
.rst ( eb_FIFO_Rst )
);
 
assign eb_FIFO_Data_Count[26:15] = 0;
assign eb_FIFO_Data_Count[0] = 0;
assign eb_FIFO_Status = {34'H0, eb_FIFO_Data_Count, eb_pfull, eb_empty};
 
 
 
// initialiation
initial begin
// Initialize Inputs
trn_clk = 0;
mem_clk = 1;
trn_reset_n = 0;
trn_lnk_up_n = 1;
trn_rerrfwd_n = 1;
trn_rsrc_dsc_n = 1;
trn_tdst_dsc_n = 1;
trn_tbuf_av = -1;
 
// cfg_interrupt_rdy_n = 0;
// cfg_interrupt_mmenable = 0;
// cfg_interrupt_msienable = 0;
// cfg_interrupt_do = 0;
 
mbuf_UserFull = 0;
pcie_link_width = 'H19;
cfg_dcommand = 'H2000;
localID = 'HD841;
 
Rx_No_Flow_Control = 0;
Tx_No_Flow_Control = 0;
 
// Wait some nanoseconds for global reset to finish
#100;
trn_reset_n = 1;
trn_lnk_up_n = 0;
 
#10000;
// $stop();
 
end
 
// trn_clk toggles
always #`T_HALF_CYCLE_CLK
trn_clk = ~trn_clk;
 
// mem_clk toggles
always #`T_HALF_CYCLE_MEMCLK
mem_clk = ~mem_clk;
 
// Randoms generated for process flow
always @(posedge trn_clk) begin
Op_Random[ 31:00] = $random();
Op_Random[ 63:32] = $random();
Op_Random[ 95:64] = $random();
Op_Random[127:96] = $random();
end
 
 
/// Rx Flow Control
always # `T_RX_NO_FC_PERIOD
Rx_No_Flow_Control = ~Rx_No_Flow_Control;
 
/// Tx Flow Control
always # `T_TX_NO_FC_PERIOD
Tx_No_Flow_Control = ~Tx_No_Flow_Control;
 
// Signal prepared for trn_rsrc_rdy_n
reg trn_rsrc_rdy_n_seed;
always @(posedge trn_clk) begin
trn_rsrc_rdy_n_seed <= Op_Random[8] & Op_Random[10] & ~Rx_No_Flow_Control;
end
 
// trn_tdst_rdy_n
always @(posedge trn_clk )
begin
# `T_DELAY_AFTER
trn_tdst_rdy_n <= (Op_Random[24] & Op_Random[21] & ~Tx_No_Flow_Control) | ~trn_reset_n;
end
 
 
 
// Initialization mem in host
initial begin
for (ii = 0; ii< `C_ARRAY_DIMENSION; ii= ii+1) begin
`ifdef RANDOM_SEQUENCE
D_Array[ii] <= $random ();
`else
D_Array[ii] <= Inv_Endian ('H8760_0000 + ii + 1);
`endif
end
end
 
 
// Simulation procedure
initial begin
 
// Simulation Initialization
FSM_Trn <= 'H00;
Gap_Insert_Rx;
 
PIO_bar <= -1;
DMA_bar <= 'H1;
Rx_MWr_Tag <= 'H80;
Rx_MRd_Tag <= 'H20;
 
 
// Initialization: TLP
# 400
Rx_TLP_Length <= 'H01;
 
# `T_DELTA // reset TX module
Hdr_Array[0] <= `HEADER0_MWR3_ | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_WRREQ_ID, Rx_MWr_Tag, 4'Hf, 4'Hf};
Hdr_Array[2] <= `C_ADDR_TX_CTRL;
Private_Array[0] <= 'H0000000A;
 
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H0, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
 
 
# `T_DELTA // Test MRd with 4-DW header BAR[0]
Hdr_Array[0] <= `HEADER0_MRD4_ | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_RDREQ_ID, 8'HA1, 4'Hf, 4'Hf};
Hdr_Array[2] <= -1;
Hdr_Array[3] <= `C_ADDR_VERSION;
 
 
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H0, `C_BAR0_HIT);
Gap_Insert_Rx;
 
 
# 100
Rx_TLP_Length <= 'H01;
 
 
# `T_DELTA // reset upstream DMA channel
Hdr_Array[0] <= `HEADER0_MWR3_ | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_WRREQ_ID, Rx_MWr_Tag, 4'Hf, 4'Hf};
Hdr_Array[2] <= `C_ADDR_DMA_US_CTRL;
Private_Array[0] <= `C_DMA_RST_CMD;
 
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H0, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
 
# `T_DELTA // reset downstream DMA channel
Hdr_Array[0] <= `HEADER0_MWR4_ | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_WRREQ_ID, Rx_MWr_Tag, 4'Hf, 4'Hf};
Hdr_Array[2] <= -1;
Hdr_Array[3] <= `C_ADDR_DMA_DS_CTRL;
Private_Array[0] <= `C_DMA_RST_CMD;
 
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H0, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
 
 
# `T_DELTA // reset Event Buffer FIFO
Hdr_Array[0] <= `HEADER0_MWR3_ | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_WRREQ_ID, Rx_MWr_Tag, 4'Hf, 4'Hf};
Hdr_Array[2] <= `C_ADDR_EB_STACON;
Private_Array[0] <= 'H0000000A;
 
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H0, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
 
 
# `T_DELTA // Enable INTerrupts
Hdr_Array[0] <= `HEADER0_MWR3_ | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_WRREQ_ID, Rx_MWr_Tag, 4'Hf, 4'Hf};
Hdr_Array[2] <= `C_ADDR_IRQ_EN;
Private_Array[0] <= 'H0000_0003;
 
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H0, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
 
 
 
 
/////////////////////////////////////////////////////////////////////
// PIO simulation //
/////////////////////////////////////////////////////////////////////
 
 
# `T_PIO_INTERVAL
;
 
FSM_Trn <= 'H04;
 
// ///////////////////////////////////////////////////////////////////
// PIO write & read BAR[0]
 
PIO_Addr <= `C_ADDR_DMA_US_PAH + 'H8;
PIO_bar <= `C_BAR0_HIT;
PIO_1st_BE <= 4'Hf;
Gap_Insert_Rx;
Hdr_Array[0] <= `HEADER0_MWR3_ | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_WRREQ_ID, Rx_MWr_Tag, 4'Hf, PIO_1st_BE};
Hdr_Array[2] <= {PIO_Addr[31:2], 2'b00};
Private_Array[0] <= 'HF000_8888;
Rx_TLP_Length <= 'H01;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H0, PIO_bar);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
 
# `T_PIO_INTERVAL
;
 
# `T_DELTA
Hdr_Array[0] <= `HEADER0_MRD3_ | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_RDREQ_ID, 3'H3, Rx_MRd_Tag, 4'Hf, PIO_1st_BE};
Hdr_Array[2] <= {PIO_Addr[31:2], 2'b00};
 
# `T_DELTA
TLP_Feed_Rx(`USE_PUBLIC, `PIO_START_INDEX, PIO_bar);
Rx_MRd_Tag <= Rx_MRd_Tag + 1;
Gap_Insert_Rx;
 
FSM_Trn <= 'H08;
 
 
 
// ///////////////////////////////////////////////////////////////////
// PIO write & read BAR[1]
PIO_Addr <= 'H8000;
PIO_bar <= `C_BAR1_HIT;
PIO_1st_BE <= 4'Hf;
Gap_Insert_Rx;
Hdr_Array[0] <= `HEADER0_MWR3_ | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_WRREQ_ID, Rx_MWr_Tag, 4'Hf, PIO_1st_BE};
Hdr_Array[2] <= {PIO_Addr[31:2], 2'b00};
Private_Array[0] <= 'HA1111111;
Rx_TLP_Length <= 'H01;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H0, PIO_bar);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
 
# `T_PIO_INTERVAL
;
 
# `T_DELTA
Hdr_Array[0] <= `HEADER0_MRD3_ | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_RDREQ_ID, 3'H3, Rx_MRd_Tag, 4'Hf, PIO_1st_BE};
Hdr_Array[2] <= {PIO_Addr[31:2], 2'b00};
 
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, `PIO_START_INDEX, PIO_bar);
Rx_MRd_Tag <= Rx_MRd_Tag + 1;
Gap_Insert_Rx;
 
FSM_Trn <= 'H10;
 
 
 
// ///////////////////////////////////////////////////////////////////
// PIO write & read BAR[2]
// NOTE: FIFO address is 64-bit aligned, only the lower 32-bit is
// accessible by BAR[2] PIO write and is returned in BAR[2]
// PIO read.
PIO_Addr <= 'H0;
PIO_bar <= `C_BAR2_HIT;
PIO_1st_BE <= 4'Hf;
Gap_Insert_Rx;
Hdr_Array[0] <= `HEADER0_MWR3_ | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_WRREQ_ID, Rx_MWr_Tag, 4'Hf, PIO_1st_BE};
Hdr_Array[2] <= {PIO_Addr[31:2], 2'b00};
Private_Array[0] <= 'HB222_2222;
Rx_TLP_Length <= 'H01;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H0, PIO_bar);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
 
# `T_PIO_INTERVAL
;
 
# `T_DELTA
Hdr_Array[0] <= `HEADER0_MRD3_ | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_RDREQ_ID, 3'H3, Rx_MRd_Tag, 4'Hf, PIO_1st_BE};
Hdr_Array[2] <= {PIO_Addr[31:2], 2'b00};
 
# `T_DELTA
TLP_Feed_Rx(`USE_PUBLIC, `PIO_START_INDEX, PIO_bar);
Rx_MRd_Tag <= Rx_MRd_Tag + 1;
Gap_Insert_Rx;
 
FSM_Trn <= 'H14;
 
 
 
# `T_DMA_INTERVAL
;
 
 
// ///////////////////////////////////////////////////////////////////
// DMA write & read BAR[1]
// Single-descriptor case
 
DMA_PA <= 'H1234;
DMA_HA <= 'H5000;
DMA_BDA <= 'Hffff;
DMA_Leng <= 'H0100;
DMA_bar <= 'H1;
DMA_ds_is_Last <= 'B1;
 
# `T_DELTA
// Initial DMA descriptor
Private_Array[0] <= -1;
Private_Array[1] <= DMA_PA[31:00]; //'H0300;
Private_Array[2] <= DMA_HA[63:32]; // 0;
Private_Array[3] <= DMA_HA[31:00]; // 'H4000;
Private_Array[4] <= DMA_BDA[63:32]; // 0;
Private_Array[5] <= DMA_BDA[31:00]; //'H0BDA0090;
Private_Array[6] <= DMA_Leng; //'H100;
Private_Array[7] <= {4'H0
,3'H1, DMA_ds_is_Last
,3'H0, 1'B1
,1'B0, DMA_bar
,1'B1
,15'H0
};
 
 
// DMA write
 
Rx_TLP_Length <= 'H01;
 
# `T_DELTA
Hdr_Array[0] <= `HEADER0_MWR3_ | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_WRREQ_ID, Rx_MWr_Tag, 4'Hf, 4'Hf};
Hdr_Array[2] <= `C_ADDR_DMA_DS_PAH;
 
// Write PA_H
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H0, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write PA_L
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H1, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write HA_H
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H2, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write HA_L
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H3, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write BDA_H
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H4, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write BDA_L
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H5, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write LENG
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H6, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write CTRL and start the DMA
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H7, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
 
FSM_Trn <= 'H18;
 
 
// feeding the payload CplD
wait (tx_MRd_come);
Gap_Insert_Rx;
tx_MRd_come <= 'B0;
Tx_MRd_Leng <= DMA_Leng>>2;
Tx_MRd_Addr <= DMA_HA[31:0];
tx_MRd_Tag_k <= tx_MRd_Tag;
CplD_Index <= 'H0;
 
Gap_Insert_Rx;
Rx_TLP_Length <= 'H10;
 
# `T_DELTA
Hdr_Array[0] <= `HEADER0_CPLD | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_CPLD_ID, 4'H0, Tx_MRd_Leng[9:0], 2'b00};
Hdr_Array[2] <= {localID, tx_MRd_Tag_k, 1'b0, Tx_MRd_Addr[6:0]};
Tx_MRd_Leng <= Tx_MRd_Leng - Rx_TLP_Length;
Tx_MRd_Addr <= Tx_MRd_Addr + Rx_TLP_Length;
# `T_DELTA
TLP_Feed_Rx(`USE_PUBLIC, CplD_Index, `C_NO_BAR_HIT);
CplD_Index <= CplD_Index + Rx_TLP_Length;
Gap_Insert_Rx;
 
Hdr_Array[0] <= `HEADER0_CPLD | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_CPLD_ID, 4'H0, Tx_MRd_Leng[9:0], 2'b00};
Hdr_Array[2] <= {localID, tx_MRd_Tag_k, 1'b0, Tx_MRd_Addr[6:0]};
Tx_MRd_Leng <= Tx_MRd_Leng - Rx_TLP_Length;
Tx_MRd_Addr <= Tx_MRd_Addr + Rx_TLP_Length;
# `T_DELTA
TLP_Feed_Rx(`USE_PUBLIC, CplD_Index, `C_NO_BAR_HIT);
CplD_Index <= CplD_Index + Rx_TLP_Length;
// Gap_Insert_Rx;
 
Hdr_Array[0] <= `HEADER0_CPLD | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_CPLD_ID, 4'H0, Tx_MRd_Leng[9:0], 2'b00};
Hdr_Array[2] <= {localID, tx_MRd_Tag_k, 1'b0, Tx_MRd_Addr[6:0]};
Tx_MRd_Leng <= Tx_MRd_Leng - Rx_TLP_Length;
Tx_MRd_Addr <= Tx_MRd_Addr + Rx_TLP_Length;
# `T_DELTA
TLP_Feed_Rx(`USE_PUBLIC, CplD_Index, `C_NO_BAR_HIT);
CplD_Index <= CplD_Index + Rx_TLP_Length;
Gap_Insert_Rx;
 
Hdr_Array[0] <= `HEADER0_CPLD | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_CPLD_ID, 4'H0, Tx_MRd_Leng[9:0], 2'b00};
Hdr_Array[2] <= {localID, tx_MRd_Tag_k, 1'b0, Tx_MRd_Addr[6:0]};
Tx_MRd_Leng <= Tx_MRd_Leng - Rx_TLP_Length;
Tx_MRd_Addr <= Tx_MRd_Addr + Rx_TLP_Length;
# `T_DELTA
TLP_Feed_Rx(`USE_PUBLIC, CplD_Index, `C_NO_BAR_HIT);
CplD_Index <= CplD_Index + Rx_TLP_Length;
Gap_Insert_Rx;
 
 
FSM_Trn <= 'H1C;
 
# `T_DMA_INTERVAL
;
 
 
 
// DMA read
 
Rx_TLP_Length <= 'H01;
 
# `T_DELTA
Hdr_Array[0] <= `HEADER0_MWR3_ | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_WRREQ_ID, Rx_MWr_Tag, 4'Hf, 4'Hf};
Hdr_Array[2] <= `C_ADDR_DMA_US_PAH;
 
// Write PA_H
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H0, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write PA_L
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H1, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write HA_H
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H2, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write HA_L
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H3, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write BDA_H
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H4, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write BDA_L
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H5, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write LENG
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H6, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write CTRL and start the DMA
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H7, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
 
FSM_Trn <= 'H20;
 
# (`T_DMA_INTERVAL*4)
;
 
 
//////////////////////////////////////////////////////////////////////////////////
 
Rx_TLP_Length <= 'H01;
# `T_DELTA // reset downstream DMA channel
Hdr_Array[0] <= `HEADER0_MWR3_ | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_WRREQ_ID, Rx_MWr_Tag, 4'Hf, 4'Hf};
Hdr_Array[2] <= `C_ADDR_DMA_DS_CTRL;
Private_Array[0] <= `C_DMA_RST_CMD;
 
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H0, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
 
Rx_TLP_Length <= 'H01;
# `T_DELTA // reset upstream DMA channel
Hdr_Array[0] <= `HEADER0_MWR3_ | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_WRREQ_ID, Rx_MWr_Tag, 4'Hf, 4'Hf};
Hdr_Array[2] <= `C_ADDR_DMA_US_CTRL;
Private_Array[0] <= `C_DMA_RST_CMD;
 
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H0, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
 
//////////////////////////////////////////////////////////////////////////////////
 
 
FSM_Trn <= 'H24;
 
 
# `T_PIO_INTERVAL
;
 
 
 
// ///////////////////////////////////////////////////////////////////
// DMA write & read BAR[2]
// Multiple-descriptor case
//
 
DMA_PA <= 'H789ABC;
DMA_HA <= 'HDF0000;
DMA_BDA <= 'H0BDABDA0;
DMA_Leng <= 'H0208;
# `T_DELTA
DMA_L1 <= 'H0100;
# `T_DELTA
DMA_L2 <= DMA_Leng - DMA_L1;
DMA_bar <= 'H2;
DMA_ds_is_Last <= 'B0;
 
# `T_DELTA
// Initial DMA descriptor
Private_Array[0] <= -1;
Private_Array[1] <= DMA_PA[31:00];
Private_Array[2] <= DMA_HA[63:32]; // 0;
Private_Array[3] <= DMA_HA[31:00];
Private_Array[4] <= DMA_BDA[63:32]; // 0;
Private_Array[5] <= DMA_BDA[31:00];
Private_Array[6] <= DMA_L1;
Private_Array[7] <= {4'H0
,3'H1, DMA_ds_is_Last
,3'H0, 1'B1
,1'B0, DMA_bar
,1'B1
,15'H0
};
 
Rx_TLP_Length <= 'H01;
 
# `T_DELTA
Hdr_Array[0] <= `HEADER0_MWR3_ | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_WRREQ_ID, Rx_MWr_Tag, 4'Hf, 4'Hf};
Hdr_Array[2] <= `C_ADDR_DMA_DS_PAH;
 
// Write PA_H
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H0, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write PA_L
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H1, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write HA_H
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H2, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write HA_L
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H3, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write BDA_H
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H4, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write BDA_L
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H5, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write LENG
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H6, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write CTRL and start the DMA
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H7, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
 
FSM_Trn <= 'H28;
 
 
// feeding the descriptor CplD
wait (Desc_tx_MRd_Valid);
Gap_Insert_Rx;
Desc_tx_MRd_Valid <= 'B0;
DMA_ds_is_Last <= 'B1;
Gap_Insert_Rx;
 
// Initial DMA descriptor
Private_Array[0] <= 0;
Private_Array[1] <= DMA_PA[31:00] + 'H500;
Private_Array[2] <= DMA_HA[63:32]; // 0;
Private_Array[3] <= DMA_HA[31:00] + 'H500;
Private_Array[4] <= -1; // dont-care
Private_Array[5] <= -1; // dont-care
Private_Array[6] <= DMA_L2;
Private_Array[7] <= {4'H0
,3'H1, DMA_ds_is_Last
,3'H0, 1'B1
,1'B0, DMA_bar
,1'B1
,15'H0
};
 
Rx_TLP_Length <= 'H08;
Gap_Insert_Rx;
Hdr_Array[0] <= `HEADER0_CPLD | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_CPLD_ID, 4'H0, Rx_TLP_Length[9:0], 2'b00};
Hdr_Array[2] <= {localID, Desc_tx_MRd_TAG, 1'b0, DMA_BDA[6:0]};
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 0, `C_NO_BAR_HIT);
Gap_Insert_Rx;
 
 
// feeding the payload CplD
wait (tx_MRd_come);
Gap_Insert_Rx;
tx_MRd_come <= 'B0;
Tx_MRd_Leng <= DMA_L1>>2;
Tx_MRd_Addr <= DMA_HA[31:0];
tx_MRd_Tag_k <= tx_MRd_Tag;
CplD_Index <= 'H0;
 
Gap_Insert_Rx;
Rx_TLP_Length <= 'H10;
 
# `T_DELTA
Hdr_Array[0] <= `HEADER0_CPLD | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_CPLD_ID, 4'H0, Tx_MRd_Leng[9:0], 2'b00};
Hdr_Array[2] <= {localID, tx_MRd_Tag_k, 1'b0, Tx_MRd_Addr[6:0]};
Tx_MRd_Leng <= Tx_MRd_Leng - Rx_TLP_Length;
Tx_MRd_Addr <= Tx_MRd_Addr + Rx_TLP_Length;
# `T_DELTA
TLP_Feed_Rx(`USE_PUBLIC, CplD_Index, `C_NO_BAR_HIT);
CplD_Index <= CplD_Index + Rx_TLP_Length;
Gap_Insert_Rx;
 
Hdr_Array[0] <= `HEADER0_CPLD | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_CPLD_ID, 4'H0, Tx_MRd_Leng[9:0], 2'b00};
Hdr_Array[2] <= {localID, tx_MRd_Tag_k, 1'b0, Tx_MRd_Addr[6:0]};
Tx_MRd_Leng <= Tx_MRd_Leng - Rx_TLP_Length;
Tx_MRd_Addr <= Tx_MRd_Addr + Rx_TLP_Length;
# `T_DELTA
TLP_Feed_Rx(`USE_PUBLIC, CplD_Index, `C_NO_BAR_HIT);
CplD_Index <= CplD_Index + Rx_TLP_Length;
// Gap_Insert_Rx;
 
Hdr_Array[0] <= `HEADER0_CPLD | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_CPLD_ID, 4'H0, Tx_MRd_Leng[9:0], 2'b00};
Hdr_Array[2] <= {localID, tx_MRd_Tag_k, 1'b0, Tx_MRd_Addr[6:0]};
Tx_MRd_Leng <= Tx_MRd_Leng - Rx_TLP_Length;
Tx_MRd_Addr <= Tx_MRd_Addr + Rx_TLP_Length;
# `T_DELTA
TLP_Feed_Rx(`USE_PUBLIC, CplD_Index, `C_NO_BAR_HIT);
CplD_Index <= CplD_Index + Rx_TLP_Length;
// Gap_Insert_Rx;
 
Hdr_Array[0] <= `HEADER0_CPLD | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_CPLD_ID, 4'H0, Tx_MRd_Leng[9:0], 2'b00};
Hdr_Array[2] <= {localID, tx_MRd_Tag_k, 1'b0, Tx_MRd_Addr[6:0]};
Tx_MRd_Leng <= Tx_MRd_Leng - Rx_TLP_Length;
Tx_MRd_Addr <= Tx_MRd_Addr + Rx_TLP_Length;
# `T_DELTA
TLP_Feed_Rx(`USE_PUBLIC, CplD_Index, `C_NO_BAR_HIT);
CplD_Index <= CplD_Index + Rx_TLP_Length;
Gap_Insert_Rx;
 
 
FSM_Trn <= 'H2C;
 
 
// feeding the payload CplD (2nd descriptor)
wait (tx_MRd_come);
Gap_Insert_Rx;
tx_MRd_come <= 'B0;
Tx_MRd_Leng <= (DMA_L2>>2) - 'H2;
Tx_MRd_Addr <= DMA_HA[31:0] + 'H500;
tx_MRd_Tag_k <= tx_MRd_Tag_k + 'H1;
CplD_Index <= 'H40;
 
Gap_Insert_Rx;
Rx_TLP_Length <= 'H10;
 
# `T_DELTA
Hdr_Array[0] <= `HEADER0_CPLD | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_CPLD_ID, 4'H0, Tx_MRd_Leng[9:0], 2'b00};
Hdr_Array[2] <= {localID, tx_MRd_Tag_k, 1'b0, Tx_MRd_Addr[6:0]};
Tx_MRd_Leng <= Tx_MRd_Leng - Rx_TLP_Length;
Tx_MRd_Addr <= Tx_MRd_Addr + Rx_TLP_Length;
# `T_DELTA
TLP_Feed_Rx(`USE_PUBLIC, CplD_Index, `C_NO_BAR_HIT);
CplD_Index <= CplD_Index + Rx_TLP_Length;
Gap_Insert_Rx;
 
Hdr_Array[0] <= `HEADER0_CPLD | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_CPLD_ID, 4'H0, Tx_MRd_Leng[9:0], 2'b00};
Hdr_Array[2] <= {localID, tx_MRd_Tag_k, 1'b0, Tx_MRd_Addr[6:0]};
Tx_MRd_Leng <= Tx_MRd_Leng - Rx_TLP_Length;
Tx_MRd_Addr <= Tx_MRd_Addr + Rx_TLP_Length;
# `T_DELTA
TLP_Feed_Rx(`USE_PUBLIC, CplD_Index, `C_NO_BAR_HIT);
CplD_Index <= CplD_Index + Rx_TLP_Length;
// Gap_Insert_Rx;
 
Hdr_Array[0] <= `HEADER0_CPLD | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_CPLD_ID, 4'H0, Tx_MRd_Leng[9:0], 2'b00};
Hdr_Array[2] <= {localID, tx_MRd_Tag_k, 1'b0, Tx_MRd_Addr[6:0]};
Tx_MRd_Leng <= Tx_MRd_Leng - Rx_TLP_Length;
Tx_MRd_Addr <= Tx_MRd_Addr + Rx_TLP_Length;
# `T_DELTA
TLP_Feed_Rx(`USE_PUBLIC, CplD_Index, `C_NO_BAR_HIT);
CplD_Index <= CplD_Index + Rx_TLP_Length;
Gap_Insert_Rx;
 
Hdr_Array[0] <= `HEADER0_CPLD | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_CPLD_ID, 4'H0, Tx_MRd_Leng[9:0], 2'b00};
Hdr_Array[2] <= {localID, tx_MRd_Tag_k, 1'b0, Tx_MRd_Addr[6:0]};
Tx_MRd_Leng <= Tx_MRd_Leng - Rx_TLP_Length;
Tx_MRd_Addr <= Tx_MRd_Addr + Rx_TLP_Length;
# `T_DELTA
TLP_Feed_Rx(`USE_PUBLIC, CplD_Index, `C_NO_BAR_HIT);
CplD_Index <= CplD_Index + Rx_TLP_Length;
Gap_Insert_Rx;
 
Rx_TLP_Length <= 'H02;
Tx_MRd_Leng <= 'H2;
tx_MRd_Tag_k <= tx_MRd_Tag_k + 'H1;
# `T_DELTA
Hdr_Array[0] <= `HEADER0_CPLD | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_CPLD_ID, 4'H0, Tx_MRd_Leng[9:0], 2'b00};
Hdr_Array[2] <= {localID, tx_MRd_Tag_k, 1'b0, Tx_MRd_Addr[6:0]};
Tx_MRd_Leng <= Tx_MRd_Leng - Rx_TLP_Length;
Tx_MRd_Addr <= Tx_MRd_Addr + Rx_TLP_Length;
# `T_DELTA
TLP_Feed_Rx(`USE_PUBLIC, CplD_Index, `C_NO_BAR_HIT);
CplD_Index <= CplD_Index + Rx_TLP_Length;
Gap_Insert_Rx;
 
FSM_Trn <= 'H30;
 
 
 
# (`T_DMA_INTERVAL*2)
;
 
DMA_us_is_Last <= 'B0;
# `T_DELTA
// DMA read
Private_Array[0] <= 0;
Private_Array[1] <= DMA_PA[31:00];
Private_Array[2] <= DMA_HA[63:32]; // 0;
Private_Array[3] <= DMA_HA[31:00];
Private_Array[4] <= DMA_BDA[63:32]; // 0;
Private_Array[5] <= DMA_BDA[31:00] + 'H10000;
Private_Array[6] <= DMA_L1;
Private_Array[7] <= {4'H0
,3'H1, DMA_us_is_Last
,3'H0, 1'B1
,1'B0, DMA_bar
,1'B1
,15'H0
};
Rx_TLP_Length <= 'H01;
 
# `T_DELTA
Hdr_Array[0] <= `HEADER0_MWR3_ | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_WRREQ_ID, Rx_MWr_Tag, 4'Hf, 4'Hf};
Hdr_Array[2] <= `C_ADDR_DMA_US_PAH;
 
// Write PA_H
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H0, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write PA_L
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H1, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write HA_H
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H2, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write HA_L
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H3, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write BDA_H
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H4, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write BDA_L
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H5, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write LENG
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H6, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
// Write CTRL and start the DMA
Hdr_Array[2] <= Hdr_Array[2] + 'H4;
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H7, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
Gap_Insert_Rx;
 
 
FSM_Trn <= 'H34;
 
 
// feeding the descriptor CplD
wait (Desc_tx_MRd_Valid);
Gap_Insert_Rx;
Desc_tx_MRd_Valid <= 'B0;
DMA_us_is_Last <= 'B1;
Gap_Insert_Rx;
 
// Initial DMA descriptor
Private_Array[0] <= 0;
Private_Array[1] <= DMA_PA[31:00] + 'H500;
Private_Array[2] <= DMA_HA[63:32]; // 0;
Private_Array[3] <= DMA_HA[31:00] + 'H500;
Private_Array[4] <= -1; // dont-care
Private_Array[5] <= -1; // dont-care
Private_Array[6] <= DMA_L2;
Private_Array[7] <= {4'H0
,3'H1, DMA_us_is_Last
,3'H0, 1'B1
,1'B0, DMA_bar
,1'B1
,15'H0
};
 
Rx_TLP_Length <= 'H08;
Gap_Insert_Rx;
Hdr_Array[0] <= `HEADER0_CPLD | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_CPLD_ID, 4'H0, Rx_TLP_Length[9:0], 2'b00};
Hdr_Array[2] <= {localID, Desc_tx_MRd_TAG, 1'b0, DMA_BDA[6:0]};
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 0, `C_NO_BAR_HIT);
Gap_Insert_Rx;
 
 
 
FSM_Trn <= 'H38;
 
# (`T_DMA_INTERVAL*8)
;
 
 
//////////////////////////////////////////////////////////////////////////////////
 
Rx_TLP_Length <= 'H01;
# `T_DELTA // reset downstream DMA channel
Hdr_Array[0] <= `HEADER0_MWR3_ | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_WRREQ_ID, Rx_MWr_Tag, 4'Hf, 4'Hf};
Hdr_Array[2] <= `C_ADDR_DMA_DS_CTRL;
Private_Array[0] <= `C_DMA_RST_CMD;
 
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H0, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
 
Rx_TLP_Length <= 'H01;
# `T_DELTA // reset upstream DMA channel
Hdr_Array[0] <= `HEADER0_MWR3_ | Rx_TLP_Length[9:0];
Hdr_Array[1] <= {`C_HOST_WRREQ_ID, Rx_MWr_Tag, 4'Hf, 4'Hf};
Hdr_Array[2] <= `C_ADDR_DMA_US_CTRL;
Private_Array[0] <= `C_DMA_RST_CMD;
 
# `T_DELTA
TLP_Feed_Rx(`USE_PRIVATE, 'H0, `C_BAR0_HIT);
Rx_MWr_Tag <= Rx_MWr_Tag + 1;
Gap_Insert_Rx;
 
//////////////////////////////////////////////////////////////////////////////////
 
 
FSM_Trn <= 'H40;
 
 
end
 
 
 
 
// ========================================== //
// Checking and verification //
// //
reg Err_signal;
// //
// //
// ========================================== //
 
// TLP format check out Rx
// in case stimuli incorrect: verification over verification
reg [ 7: 0] FSM_Rx_Fmt;
reg [10: 0] rxchk_TLP_Length;
reg rxchk_TLP_Has_Data;
reg rxchk_TLP_4DW_Hdr;
reg rxchk_Mem_TLP;
always @(negedge trn_clk )
if (!trn_reset_n) begin
FSM_Rx_Fmt <= 0;
end
else begin
 
case (FSM_Rx_Fmt)
 
'H00: begin
FSM_Rx_Fmt <= 'H010;
end
 
'H10: begin
if ( trn_rsrc_rdy_n | trn_rdst_rdy_n) begin
FSM_Rx_Fmt <= 'H10;
end
else if (~trn_reof_n) begin
$display ("\n %t:\n !! Unexpected trn_reof_n !!", $time);
Err_signal <= 1;
end
else if (~trn_rsof_n&trn_reof_n) begin
rxchk_TLP_Has_Data <= trn_rd[30+32];
rxchk_TLP_4DW_Hdr <= trn_rd[29+32];
rxchk_TLP_Length[10] <= (trn_rd[9+32:0+32]=='H0);
rxchk_TLP_Length[9:0] <= trn_rd[9+32:0+32];
if (trn_rd[28+32:25+32]) rxchk_Mem_TLP <= 0; // Msg or MsgD
else rxchk_Mem_TLP <= 1; // MWr, MRd or Cpl/D
FSM_Rx_Fmt <= 'H12;
end
else begin
$display ("\n %t:\n !! trn_rsof_n error!", $time);
Err_signal <= 1;
end
end
 
 
'H12: begin
if ( trn_rsrc_rdy_n | trn_rdst_rdy_n) begin
FSM_Rx_Fmt <= 'H12;
end
else if (!trn_rsof_n) begin
$display ("\n %t:\n !! trn_rsof_n error! should be 1.", $time);
Err_signal <= 1;
end
else begin
if (rxchk_TLP_4DW_Hdr & rxchk_TLP_Has_Data) begin
if (trn_reof_n) begin
Err_signal <= 0;
FSM_Rx_Fmt <= 'H20;
end
else begin
Err_signal <= 1;
$display ("\n %t:\n !! trn_reof_n error (4-Header, with Payload)! should be 1.", $time);
end
end
else if (rxchk_TLP_4DW_Hdr & !rxchk_TLP_Has_Data) begin
if (trn_reof_n) begin
Err_signal <= 1;
$display ("\n %t:\n !! trn_reof_n error (4-Header, no Payload)! should be 0.", $time);
end
else if (trn_rrem_n=='H00) begin
Err_signal <= 0;
FSM_Rx_Fmt <= 'H10;
end
else begin
Err_signal <= 1;
$display ("\n %t:\n !! trn_rrem_n error (4-Header, no Payload)!", $time);
end
end
else if (!rxchk_TLP_4DW_Hdr & !rxchk_TLP_Has_Data) begin
if (trn_reof_n) begin
Err_signal <= 1;
$display ("\n %t:\n !! trn_reof_n error (3-Header, with Payload)! should be 0.", $time);
end
else if (trn_rrem_n=='H0f) begin
Err_signal <= 0;
FSM_Rx_Fmt <= 'H10;
end
else begin
Err_signal <= 1;
$display ("\n %t:\n !! trn_rrem_n error (3-Header, no Payload)!", $time);
end
end
else if (rxchk_TLP_Length=='H1) begin // (!rxchk_TLP_4DW_Hdr & rxchk_TLP_Has_Data)
if (trn_reof_n) begin
Err_signal <= 1;
$display ("\n %t:\n !! trn_reof_n error (3-Header, with Payload)! should be 0.", $time);
end
else if (trn_rrem_n=='H00) begin
Err_signal <= 0;
FSM_Rx_Fmt <= 'H10;
end
else begin
Err_signal <= 1;
$display ("\n %t:\n !! trn_rrem_n error (3-Header, no Payload)!", $time);
end
end
else begin // (!rxchk_TLP_4DW_Hdr & rxchk_TLP_Has_Data) & (rxchk_TLP_Length>'H1)
if (trn_reof_n) begin
Err_signal <= 0;
rxchk_TLP_Length <= rxchk_TLP_Length - 1;
FSM_Rx_Fmt <= 'H20;
end
else begin
Err_signal <= 1;
$display ("\n %t:\n !! trn_reof_n error (3-Header, no Payload)! should be 1.", $time);
end
end
 
// Address-Length combination check
if (rxchk_TLP_4DW_Hdr) begin
if (({1'b0, trn_rd[11:2]} + rxchk_TLP_Length[9:0])>11'H400) begin
$display ("\n\n %t:\n !! Rx 4KB straddled !!", $time);
$display ("\n Address=%08X Length=%04X (%04X bytes)\n\n", trn_rd[31:0], rxchk_TLP_Length, rxchk_TLP_Length<<2);
// Err_signal <= 1;
end
if (trn_rd[63:32]=='H0 && rxchk_Mem_TLP==1) begin
$display ("\n %t:\n !! Rx TLP should not be 4-DW headher !!", $time);
Err_signal <= 1;
end
end
else begin
if (({1'b0, trn_rd[11+32:2+32]} + rxchk_TLP_Length[9:0])>11'H400) begin
$display ("\n\n %t:\n !! Rx 4KB straddled !!", $time);
$display ("\n Address=%08X Length=%04X (%04X bytes)\n\n", trn_rd[63:32], rxchk_TLP_Length, rxchk_TLP_Length<<2);
// Err_signal <= 1;
end
end
end
end
 
 
'H20: begin
if ( trn_rsrc_rdy_n | trn_rdst_rdy_n) begin
FSM_Rx_Fmt <= 'H20;
end
else if (rxchk_TLP_Length==2) begin
if (trn_rrem_n=='H00 && trn_reof_n==0) begin
FSM_Rx_Fmt <= 'H10;
end
else begin
$display ("\n %t:\n !! trn_reof_n/trn_rrem_n error !!", $time);
Err_signal <= 1;
end
end
else if (rxchk_TLP_Length==1) begin
if (trn_rrem_n=='H0f && trn_reof_n==0) begin
FSM_Rx_Fmt <= 'H10;
end
else begin
$display ("\n %t:\n !! trn_reof_n/trn_rrem_n error !!", $time);
Err_signal <= 1;
end
end
else if (rxchk_TLP_Length==0) begin
$display ("\n %t:\n !! Rx TLP Length error !!", $time);
Err_signal <= 1;
end
else if (!trn_reof_n) begin
$display ("\n %t:\n !! trn_reof_n too early !!", $time);
Err_signal <= 1;
end
else begin
rxchk_TLP_Length <= rxchk_TLP_Length - 2;
FSM_Rx_Fmt <= 'H20;
end
end
 
default: begin
FSM_Rx_Fmt <= 'H00;
end
 
endcase
end
 
 
 
 
// TLP format check by Tx
reg [ 7: 0] FSM_TLP_Fmt;
reg [10: 0] tx_TLP_Length;
reg [12: 0] tx_TLP_Address;
reg tx_TLP_Has_Data;
reg tx_TLP_is_CplD;
reg tx_TLP_4DW_Hdr;
reg tx_Mem_TLP;
always @(negedge trn_clk )
if (!trn_reset_n) begin
FSM_TLP_Fmt <= 0;
end
else begin
 
case (FSM_TLP_Fmt)
 
'H00: begin
FSM_TLP_Fmt <= 'H010;
end
 
'H10: begin
if ( trn_tsrc_rdy_n | trn_tdst_rdy_n) begin
FSM_TLP_Fmt <= 'H10;
end
else if (~trn_teof_n) begin
$display ("\n %t:\n !! Unexpected trn_teof_n !!", $time);
Err_signal <= 1;
end
else if (~trn_tsof_n&trn_teof_n) begin
tx_TLP_Has_Data <= trn_td[30+32];
tx_TLP_4DW_Hdr <= trn_td[29+32];
tx_TLP_Length[10] <= (trn_td[9+32:0+32]=='H0);
tx_TLP_Length[9:0] <= trn_td[9+32:0+32];
tx_TLP_is_CplD <= trn_td[27+32];
if (trn_td[28+32:25+32]) tx_Mem_TLP <= 0; // Msg or MsgD
else tx_Mem_TLP <= 1; // MWr, MRd or Cpl/D
FSM_TLP_Fmt <= 'H12;
if (trn_td[31:16] == localID) begin
Err_signal <= 0;
end
else begin
$display ("\n %t:\n !! Tx Bad TLP ReqID for TLP !!", $time);
Err_signal <= 1;
end
end
else begin
$display ("\n %t:\n !! trn_tsof_n error!", $time);
Err_signal <= 1;
end
end
 
 
'H12: begin
if ( trn_tsrc_rdy_n | trn_tdst_rdy_n) begin
FSM_TLP_Fmt <= 'H12;
end
else if (!trn_tsof_n) begin
$display ("\n %t:\n !! trn_tsof_n error! should be 1.", $time);
Err_signal <= 1;
end
else begin
if (tx_TLP_4DW_Hdr & tx_TLP_Has_Data) begin
if (trn_teof_n) begin
Err_signal <= 0;
FSM_TLP_Fmt <= 'H20;
end
else begin
Err_signal <= 1;
$display ("\n %t:\n !! trn_teof_n error (4-Header, with Payload)! should be 1.", $time);
end
end
else if (tx_TLP_4DW_Hdr & !tx_TLP_Has_Data) begin
if (trn_teof_n) begin
Err_signal <= 1;
$display ("\n %t:\n !! trn_teof_n error (4-Header, no Payload)! should be 0.", $time);
end
else if (trn_trem_n=='H00) begin
Err_signal <= 0;
FSM_TLP_Fmt <= 'H10;
end
else begin
Err_signal <= 1;
$display ("\n %t:\n !! trn_trem_n error (4-Header, no Payload)!", $time);
end
end
else if (!tx_TLP_4DW_Hdr & !tx_TLP_Has_Data) begin
if (trn_teof_n) begin
Err_signal <= 1;
$display ("\n %t:\n !! trn_teof_n error (3-Header, with Payload)! should be 0.", $time);
end
else if (trn_trem_n=='H0f) begin
Err_signal <= 0;
FSM_TLP_Fmt <= 'H10;
end
else begin
Err_signal <= 1;
$display ("\n %t:\n !! trn_trem_n error (3-Header, no Payload)!", $time);
end
end
else if (tx_TLP_Length=='H1) begin // (!tx_TLP_4DW_Hdr & tx_TLP_Has_Data)
if (trn_teof_n) begin
Err_signal <= 1;
$display ("\n %t:\n !! trn_teof_n error (3-Header, with Payload)! should be 0.", $time);
end
else if (trn_trem_n=='H00) begin
if (tx_TLP_is_CplD && (trn_td[31+32:16+32]==`C_HOST_RDREQ_ID)) begin
Err_signal <= 0;
FSM_TLP_Fmt <= 'H10;
end
else if (tx_TLP_is_CplD) begin
Err_signal <= 1;
$display ("\n %t:\n !! CplD Requester ID Wrong (TLP Length ==1 )!! ", $time);
end
else begin
Err_signal <= 0;
FSM_TLP_Fmt <= 'H10;
end
end
else begin
Err_signal <= 1;
$display ("\n %t:\n !! trn_trem_n error (3-Header, no Payload)!", $time);
end
end
else begin // (!tx_TLP_4DW_Hdr & tx_TLP_Has_Data) & (tx_TLP_Length>'H1)
if (trn_teof_n) begin
if (tx_TLP_is_CplD && (trn_td[31+32:16+32]==`C_HOST_RDREQ_ID)) begin
tx_TLP_Length <= tx_TLP_Length - 1;
FSM_TLP_Fmt <= 'H20;
end
else if (tx_TLP_is_CplD) begin
Err_signal <= 1;
$display ("\n %t:\n !! CplD Requester ID Wrong (TLP Length !=1 )!! ", $time);
end
else begin
tx_TLP_Length <= tx_TLP_Length - 1;
FSM_TLP_Fmt <= 'H20;
end
end
else begin
Err_signal <= 1;
$display ("\n %t:\n !! trn_teof_n error (3-Header, no Payload)! should be 1.", $time);
end
end
 
// Address-Length combination check
if (tx_TLP_4DW_Hdr) begin
if (({1'b0, trn_td[11:2]} + tx_TLP_Length[9:0])>11'H400) begin
$display ("\n %t:\n !! Tx 4KB straddled !!", $time);
$display ("\n Address=%08X Length=%04X (%04X bytes)\n", trn_td[31:0], tx_TLP_Length, tx_TLP_Length<<2);
Err_signal <= 1;
end
if (trn_td[63:32]=='H0 && tx_Mem_TLP==1) begin
$display ("\n %t:\n !! Tx TLP should not be 4-DW headher !!", $time);
Err_signal <= 1;
end
end
else begin
if (({1'b0, trn_td[11+32:2+32]} + tx_TLP_Length[9:0])>11'H400) begin
$display ("\n %t:\n !! Tx 4KB straddled !!", $time);
$display ("\n Address=%08X Length=%04X (%04X bytes)\n", trn_td[63:32], tx_TLP_Length, tx_TLP_Length<<2);
Err_signal <= 1;
end
end
 
end
end
 
 
'H20: begin
if ( trn_tsrc_rdy_n | trn_tdst_rdy_n) begin
FSM_TLP_Fmt <= 'H20;
end
else if (tx_TLP_Length==2) begin
if (trn_trem_n=='H00 && trn_teof_n==0) begin
FSM_TLP_Fmt <= 'H10;
end
else begin
$display ("\n %t:\n !! trn_teof_n/trn_trem_n error !!\n", $time);
Err_signal <= 1;
end
end
else if (tx_TLP_Length==1) begin
if (trn_trem_n=='H0f && trn_teof_n==0) begin
FSM_TLP_Fmt <= 'H10;
end
else begin
$display ("\n %t:\n !! trn_teof_n/trn_trem_n error !!\n", $time);
Err_signal <= 1;
end
end
else if (tx_TLP_Length==0) begin
$display ("\n %t:\n !! Tx TLP Length error !!", $time);
Err_signal <= 1;
end
else if (!trn_teof_n) begin
$display ("\n %t:\n !! trn_teof_n too early !!", $time);
Err_signal <= 1;
end
else begin
tx_TLP_Length <= tx_TLP_Length - 2;
FSM_TLP_Fmt <= 'H20;
end
end
 
default: begin
FSM_TLP_Fmt <= 'H00;
end
 
endcase
end
 
 
 
 
//************************************************//
//************************************************//
//************************************************//
 
reg [ 7:00] FSM_Tx_Desc_MRd;
// Descriptors MRd
always @(negedge trn_clk )
if (!trn_reset_n) begin
FSM_Tx_Desc_MRd <= 0;
Desc_tx_MRd_Valid <= 0;
end
else begin
 
case (FSM_Tx_Desc_MRd)
 
'H00: begin
FSM_Tx_Desc_MRd <= 'H10;
end
 
'H10: begin
case ({ trn_tsrc_rdy_n
, trn_tdst_rdy_n
, trn_tsof_n
, trn_td[15]
})
 
'B0001:
if ( (trn_td[31+32:24+32]=='H00 || trn_td[31+32:24+32]=='H20)
&&(trn_td[9+32:32]=='H8)) begin
Desc_tx_MRd_Leng[10] <= (trn_td[9+32:32]==0);
Desc_tx_MRd_Leng[9:0] <= trn_td[9+32:32];
Desc_tx_MRd_TAG <= trn_td[15:8];
FSM_Tx_Desc_MRd <= 'H31;
end
else begin
FSM_Tx_Desc_MRd <= 'H10;
end
 
default: begin
FSM_Tx_Desc_MRd <= 'H10;
end
 
endcase
end
 
 
'H31: begin // Low 32 bits Address
if (trn_tsrc_rdy_n|trn_tdst_rdy_n) begin
FSM_Tx_Desc_MRd <= 'H31;
end
else begin
Desc_tx_MRd_Addr <= trn_td[31:00];
Desc_tx_MRd_Valid <= 1;
FSM_Tx_Desc_MRd <= 'H10;
end
end
 
 
default: begin
FSM_Tx_Desc_MRd <= 'H00;
end
 
endcase
end
 
 
 
// DMA MRd out of Tx
reg [ 7: 0] FSM_Tx_MRd;
reg tx_DMA_MRd_A64b;
always @(negedge trn_clk )
if (!trn_reset_n) begin
FSM_Tx_MRd <= 0;
tx_MRd_come <= 0;
end
else begin
 
case (FSM_Tx_MRd)
 
'H00: begin
FSM_Tx_MRd <= 'H10;
end
 
'H10: begin
case ({ trn_tsrc_rdy_n
, trn_tdst_rdy_n
, trn_tsof_n
, trn_td[15]
})
 
'B0000:
case (trn_td[31+32:24+32])
'H00: begin // 3-dw header
tx_MRd_Length[9:0] <= trn_td[9+32:32];
tx_MRd_Length[10] <= (trn_td[9+32:32]=='H0)?1:0;
tx_MRd_Tag <= trn_td[15:8];
FSM_Tx_MRd <= 'H30;
tx_DMA_MRd_A64b <= 0;
end
 
'H20: begin // 4-dw header
tx_MRd_Length[9:0] <= trn_td[9+32:32];
tx_MRd_Length[10] <= (trn_td[9+32:32]=='H0)?1:0;
tx_MRd_Tag <= trn_td[15:8];
FSM_Tx_MRd <= 'H30;
tx_DMA_MRd_A64b <= 1;
end
 
default: begin
FSM_Tx_MRd <= 'H10; // Idle
end
endcase
 
default: begin
FSM_Tx_MRd <= 'H10;
end
 
endcase
end
 
 
'H30: begin
if (trn_tsrc_rdy_n|trn_tdst_rdy_n) begin
FSM_Tx_MRd <= 'H30;
end
else if( trn_td[1:0]==0) begin
FSM_Tx_MRd <= 'H10;
tx_MRd_come <= 'B1;
end
else begin
$display ("\n %t:\n !! Bad TLP Address for Tx MRd !!", $time);
Err_signal <= 1;
end
end
 
default: begin
FSM_Tx_MRd <= 'H00;
end
 
endcase
end
 
 
 
// Msg checking ...
reg [7: 0] fsm_Tx_Msg;
reg [3: 0] tx_Msg_Tag_Lo;
always @(negedge trn_clk )
if (!trn_reset_n) begin
fsm_Tx_Msg <= 0;
tx_Msg_Tag_Lo <= 1;
end
 
else begin
 
case (fsm_Tx_Msg)
 
'H00: begin
fsm_Tx_Msg <= 'H10;
end
 
'H10: begin
case ({ trn_tsrc_rdy_n
, trn_tdst_rdy_n
, trn_tsof_n
})
 
'B000:
if (trn_td[31+32:28+32]=='H3) begin
fsm_Tx_Msg <= 'H30;
if ( trn_td[11:8] != tx_Msg_Tag_Lo ) begin
$display ("\n %t:\n !! Msg Tag bad !!", $time, trn_td[11:8]);
Err_signal <= 1;
end
else if ( trn_td[7:0] == `C_MSG_CODE_INTA ) begin
// fsm_Tx_Msg <= 'H30;
Accum_Msg_INTA <= Accum_Msg_INTA + 1;
end
else if ( trn_td[7:0] == `C_MSG_CODE_INTA_N ) begin
// fsm_Tx_Msg <= 'H30;
Accum_Msg_INTA_n <= Accum_Msg_INTA_n + 1;
end
else begin
$display ("\n %t:\n !! Bad Msg code (0x%2x) !!", $time, trn_td[7:0]);
Err_signal <= 1;
end
end
else begin
fsm_Tx_Msg <= 'H10;
end
 
default: begin
fsm_Tx_Msg <= 'H10;
end
 
endcase
end
 
 
'H30: begin
if (trn_tsrc_rdy_n|trn_tdst_rdy_n) begin
fsm_Tx_Msg <= 'H30;
end
else if (trn_td) begin
$display ("\n %t:\n !! Msg data bad!!", $time);
Err_signal <= 1;
end
else begin
fsm_Tx_Msg <= 'H10;
tx_Msg_Tag_Lo <= tx_Msg_Tag_Lo + 1;
end
end
 
 
default: begin
fsm_Tx_Msg <= 'H00;
end
 
endcase
end
 
 
 
// ================================================= //
// ======= Interrupt uneven checking ======= //
// ================================================= //
always @ Accum_Msg_INTA
if (Accum_Msg_INTA>Accum_Msg_INTA_n+1) begin
$display("\n\n INTA overrun at %t\n\n", $time);
Err_signal <= 1;
end
 
//
always @ Accum_Msg_INTA_n
if (Accum_Msg_INTA_n>Accum_Msg_INTA) begin
$display("\n\n #INTA overrun at %t\n\n", $time);
Err_signal <= 1;
end
 
 
 
 
// ***************************************** //
// Tasks //
// ***************************************** //
 
///////////////////////////////////////////////
// Wait for the next positive clock event //
///////////////////////////////////////////////
task To_the_next_Event;
begin
wait (!trn_clk);
wait (trn_clk);
# `T_DELAY_AFTER ;
end
endtask
 
///////////////////////////////////////////////
// Wait for the next negative clock event //
///////////////////////////////////////////////
task To_the_next_Tx_Data;
begin
wait (trn_clk);
wait (!trn_clk);
# `T_DELAY_AFTER ;
end
endtask
 
 
///////////////////////////////////////////////
// Insert GAP //
///////////////////////////////////////////////
task Gap_Insert_Rx;
begin
To_the_next_Event;
trn_rsof_n <= 1;
trn_reof_n <= 1;
trn_rsrc_rdy_n <= 1;
trn_rbar_hit_n <= `C_NO_BAR_HIT;
trn_rd <= -1;
trn_rrem_n <= -1;
end
endtask
 
 
///////////////////////////////////////////////
// //
// Feed TLP to Rx: MRd, MWr, Cpl/D, Msg //
// //
///////////////////////////////////////////////
task TLP_Feed_Rx;
input Use_Private_Array; // Public or private
input [11:0] IndexA; // Start point in the Array
input [ 6:0] BAR_Hit_N; // Which BAR is hit
 
// integer hdr_Leng;
reg TLP_has_Payload;
reg TLP_hdr_4DW;
reg [10:0] jr;
reg [10:0] payload_Leng;
 
begin
 
// TLP format extraction
TLP_has_Payload <= Hdr_Array[0][30] ;
// hdr_Leng <= Hdr_Array[0][29] + 3;
TLP_hdr_4DW <= Hdr_Array[0][29];
 
// Header #0
To_the_next_Event;
trn_rsof_n <= 0;
trn_reof_n <= 1;
trn_rsrc_rdy_n <= 0;
trn_rbar_hit_n <= BAR_Hit_N;
trn_rd <= {Hdr_Array[0], Hdr_Array[1]};
trn_rrem_n <= 0;
 
payload_Leng <= {Hdr_Array[0][9:0]?1'b0:1'b1, Hdr_Array[0][9:0]};
 
// Header words # 1
for (jr=1; jr<2; jr=jr+1) begin
To_the_next_Event;
trn_rsrc_rdy_n <= trn_rsrc_rdy_n_seed;
if (trn_rsrc_rdy_n_seed) begin
trn_rsof_n <= trn_rsof_n;
trn_rd <= trn_rd;
trn_rrem_n <= trn_rrem_n;
trn_reof_n <= trn_reof_n;
// #0.1 jr <= jr-1;
jr = jr-1; // !! not <= !!
end
else begin
trn_rsof_n <= 1;
if (TLP_hdr_4DW) begin
trn_rrem_n <= 'H00;
trn_rd <= {Hdr_Array[2], Hdr_Array[3]};
end
else if (TLP_has_Payload) begin
trn_rrem_n <= 'H00;
if (Use_Private_Array)
trn_rd <= {Hdr_Array[2],Inv_Endian (Private_Array[IndexA])};
else
trn_rd <= {Hdr_Array[2],Inv_Endian (D_Array[IndexA])};
end
else begin
trn_rrem_n <= 'H0f;
trn_rd <= {Hdr_Array[2], 32'H0};
end
if (payload_Leng<='H1 && TLP_hdr_4DW==0) begin
trn_reof_n <= 0;
end
else if (!TLP_has_Payload) begin
trn_reof_n <= 0;
end
else begin
trn_reof_n <= 1;
end
end
end // Header done.
 
// Payload data ...
if ((TLP_has_Payload && TLP_hdr_4DW) || (TLP_has_Payload && (payload_Leng>'H1) && !TLP_hdr_4DW))
 
for (jr=(!TLP_hdr_4DW); jr<payload_Leng; jr=jr+2) begin
To_the_next_Event;
trn_rsrc_rdy_n <= trn_rsrc_rdy_n_seed;
if (trn_rsrc_rdy_n_seed) begin
trn_rd <= trn_rd;
trn_rrem_n <= trn_rrem_n;
trn_reof_n <= trn_reof_n;
// #0.1 jr <= jr-1;
jr = jr-2; // !! not <= !!
end
else begin
if (jr==payload_Leng-1 || jr==payload_Leng-2) begin
trn_reof_n <= 0;
end
else begin
trn_reof_n <= 1;
end
 
if (jr==payload_Leng-1) begin
trn_rrem_n <= 'H0f;
if (Use_Private_Array)
trn_rd <= {Inv_Endian(Private_Array[IndexA+jr]), 32'Hffff_ffff};
else
trn_rd <= {Inv_Endian(D_Array[IndexA+jr]), 32'Hffff_ffff};
end
else begin
trn_rrem_n <= 'H00;
if (Use_Private_Array)
trn_rd <= {Inv_Endian(Private_Array[IndexA+jr]), Inv_Endian(Private_Array[IndexA+jr+1])};
else
trn_rd <= {Inv_Endian(D_Array[IndexA+jr]), Inv_Endian(D_Array[IndexA+jr+1])};
end
 
 
end
end
// Payload done.
 
end
endtask
 
 
/////////////////////////////////////////////
// //
// Function - Endian Inversion 64-bit //
// //
/////////////////////////////////////////////
function [31:00] Inv_Endian;
input [31:00] Data;
begin
Inv_Endian = {Data[ 7: 0], Data[15: 8], Data[23:16], Data[31:24]};
end
endfunction
 
 
endmodule
/trunk/xise/dma_top.gise
22,38 → 22,13
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="dma_top.xise"/>
 
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="../cores/afifo_1024x72.asy" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../cores/afifo_1024x72.ngc" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="../cores/afifo_1024x72.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VERILOG" xil_pn:name="../cores/afifo_1024x72.v" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="../cores/afifo_1024x72.veo" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../cores/afifo_1024x72.vhd" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="../cores/afifo_1024x72.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_ASY" xil_pn:name="../cores/afifo_256x36.asy" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../cores/afifo_256x36.ngc" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="../cores/afifo_256x36.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VERILOG" xil_pn:name="../cores/afifo_256x36.v" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="../cores/afifo_256x36.veo" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../cores/afifo_256x36.vhd" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="../cores/afifo_256x36.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_ASY" xil_pn:name="../cores/afifo_256x36c_fwft.asy" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../cores/afifo_256x36c_fwft.ngc" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="../cores/afifo_256x36c_fwft.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VERILOG" xil_pn:name="../cores/afifo_256x36c_fwft.v" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="../cores/afifo_256x36c_fwft.veo" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../cores/afifo_256x36c_fwft.vhd" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="../cores/afifo_256x36c_fwft.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_ASY" xil_pn:name="../cores/afifo_8x8.asy" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../cores/afifo_8x8.ngc" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="../cores/afifo_8x8.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VERILOG" xil_pn:name="../cores/afifo_8x8.v" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="../cores/afifo_8x8.veo" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../cores/afifo_8x8.vhd" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="../cores/afifo_8x8.vho" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../cores/bram4096x64.ngc" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VERILOG" xil_pn:name="../cores/bram4096x64.v" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="../cores/bram4096x64.veo" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../cores/bram4096x64.vhd" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHDL" xil_pn:name="../cores/bram4096x64.vhd" xil_pn:origination="imported">
<branch xil_pn:name="Implementation"/>
<branch xil_pn:name="BehavioralSim"/>
</file>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="../cores/bram4096x64.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_ASY" xil_pn:name="../cores/eb_fifo_counted.asy" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../cores/eb_fifo_counted.ngc" xil_pn:origination="imported"/>
60,37 → 35,153
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="../cores/eb_fifo_counted.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VERILOG" xil_pn:name="../cores/eb_fifo_counted.v" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="../cores/eb_fifo_counted.veo" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../cores/eb_fifo_counted.vhd" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHDL" xil_pn:name="../cores/eb_fifo_counted.vhd" xil_pn:origination="imported">
<branch xil_pn:name="Implementation"/>
<branch xil_pn:name="BehavioralSim"/>
</file>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="../cores/eb_fifo_counted.vho" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../cores/mBuf_128x72.ngc" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VERILOG" xil_pn:name="../cores/mBuf_128x72.v" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="../cores/mBuf_128x72.veo" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../cores/mBuf_128x72.vhd" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHDL" xil_pn:name="../cores/mBuf_128x72.vhd" xil_pn:origination="imported">
<branch xil_pn:name="Implementation"/>
<branch xil_pn:name="BehavioralSim"/>
</file>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="../cores/mBuf_128x72.vho" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../cores/pkt_counter_1024.ngc" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VERILOG" xil_pn:name="../cores/pkt_counter_1024.v" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="../cores/pkt_counter_1024.veo" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../cores/pkt_counter_1024.vhd" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="../cores/pkt_counter_1024.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_ASY" xil_pn:name="../cores/prim_FIFO_plain.asy" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../cores/prim_FIFO_plain.ngc" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="../cores/prim_FIFO_plain.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VERILOG" xil_pn:name="../cores/prim_FIFO_plain.v" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="../cores/prim_FIFO_plain.veo" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../cores/prim_FIFO_plain.vhd" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHDL" xil_pn:name="../cores/prim_FIFO_plain.vhd" xil_pn:origination="imported">
<branch xil_pn:name="Implementation"/>
<branch xil_pn:name="BehavioralSim"/>
</file>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="../cores/prim_FIFO_plain.vho" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../cores/v5pcie_ep_blk_plus_4x.ngc" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VERILOG" xil_pn:name="../cores/v5pcie_ep_blk_plus_4x.v" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="../cores/v5pcie_ep_blk_plus_4x.veo" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../cores/v5pcie_ep_blk_plus_4x.vhd" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHDL" xil_pn:name="../cores/v5pcie_ep_blk_plus_4x.vhd" xil_pn:origination="imported">
<branch xil_pn:name="Implementation"/>
<branch xil_pn:name="BehavioralSim"/>
</file>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="../cores/v5pcie_ep_blk_plus_4x.vho" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../cores/v5sfifo_15x128.ngc" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VERILOG" xil_pn:name="../cores/v5sfifo_15x128.v" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="../cores/v5sfifo_15x128.veo" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../cores/v5sfifo_15x128.vhd" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHDL" xil_pn:name="../cores/v5sfifo_15x128.vhd" xil_pn:origination="imported">
<branch xil_pn:name="Implementation"/>
<branch xil_pn:name="BehavioralSim"/>
</file>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="../cores/v5sfifo_15x128.vho" xil_pn:origination="imported"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="tf64_pcie_trn.fdo"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="v5pcieDMA_guide.ncd" xil_pn:origination="imported"/>
</files>
 
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1316006425" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1316006425">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1316006425" xil_pn:in_ck="288365123420918390" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1316006425">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="../rtl/DDR_Blinker.vhd"/>
<outfile xil_pn:name="../rtl/DMA_Calculate.vhd"/>
<outfile xil_pn:name="../rtl/DMA_FSM.vhd"/>
<outfile xil_pn:name="../rtl/FF_tagram64x36.vhd"/>
<outfile xil_pn:name="../rtl/FIFO_Wrapper.vhd"/>
<outfile xil_pn:name="../rtl/Interrupts.vhd"/>
<outfile xil_pn:name="../rtl/Registers.vhd"/>
<outfile xil_pn:name="../rtl/RxIn_Delays.vhd"/>
<outfile xil_pn:name="../rtl/Tx_Output_Arbitor.vhd"/>
<outfile xil_pn:name="../rtl/bram_Control.vhd"/>
<outfile xil_pn:name="../rtl/pkg_dma.vhd"/>
<outfile xil_pn:name="../rtl/rx_CplD_Channel.vhd"/>
<outfile xil_pn:name="../rtl/rx_MRd_Channel.vhd"/>
<outfile xil_pn:name="../rtl/rx_MWr_Channel.vhd"/>
<outfile xil_pn:name="../rtl/rx_Transact.vhd"/>
<outfile xil_pn:name="../rtl/rx_dsDMA_Channel.vhd"/>
<outfile xil_pn:name="../rtl/rx_usDMA_Channel.vhd"/>
<outfile xil_pn:name="../rtl/tlpControl.vhd"/>
<outfile xil_pn:name="../rtl/tx_Mem_Reader.vhd"/>
<outfile xil_pn:name="../rtl/tx_Transact.vhd"/>
<outfile xil_pn:name="../rtl/v5pcieDMA.vhd"/>
<outfile xil_pn:name="../sim/tf64_pcie_trn.v"/>
</transform>
<transform xil_pn:end_ts="1316006425" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-9077629223179277692" xil_pn:start_ts="1316006425">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1316006425" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="1166899318583090546" xil_pn:start_ts="1316006425">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1316006425" xil_pn:in_ck="584967772436445401" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="694583080691470134" xil_pn:start_ts="1316006425">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="../cores/bram4096x64.ngc"/>
<outfile xil_pn:name="../cores/bram4096x64.vhd"/>
<outfile xil_pn:name="../cores/eb_fifo_counted.ngc"/>
<outfile xil_pn:name="../cores/eb_fifo_counted.vhd"/>
<outfile xil_pn:name="../cores/mBuf_128x72.ngc"/>
<outfile xil_pn:name="../cores/mBuf_128x72.vhd"/>
<outfile xil_pn:name="../cores/prim_FIFO_plain.ngc"/>
<outfile xil_pn:name="../cores/prim_FIFO_plain.vhd"/>
<outfile xil_pn:name="../cores/v5pcie_ep_blk_plus_4x.ngc"/>
<outfile xil_pn:name="../cores/v5pcie_ep_blk_plus_4x.vhd"/>
<outfile xil_pn:name="../cores/v5sfifo_15x128.ngc"/>
<outfile xil_pn:name="../cores/v5sfifo_15x128.vhd"/>
</transform>
<transform xil_pn:end_ts="1316006425" xil_pn:in_ck="-4617413950069613313" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1316006425">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="../cores/bram4096x64.vhd"/>
<outfile xil_pn:name="../cores/eb_fifo_counted.vhd"/>
<outfile xil_pn:name="../cores/mBuf_128x72.vhd"/>
<outfile xil_pn:name="../cores/prim_FIFO_plain.vhd"/>
<outfile xil_pn:name="../cores/v5pcie_ep_blk_plus_4x.vhd"/>
<outfile xil_pn:name="../cores/v5sfifo_15x128.vhd"/>
<outfile xil_pn:name="../rtl/DDR_Blinker.vhd"/>
<outfile xil_pn:name="../rtl/DMA_Calculate.vhd"/>
<outfile xil_pn:name="../rtl/DMA_FSM.vhd"/>
<outfile xil_pn:name="../rtl/FF_tagram64x36.vhd"/>
<outfile xil_pn:name="../rtl/FIFO_Wrapper.vhd"/>
<outfile xil_pn:name="../rtl/Interrupts.vhd"/>
<outfile xil_pn:name="../rtl/Registers.vhd"/>
<outfile xil_pn:name="../rtl/RxIn_Delays.vhd"/>
<outfile xil_pn:name="../rtl/Tx_Output_Arbitor.vhd"/>
<outfile xil_pn:name="../rtl/bram_Control.vhd"/>
<outfile xil_pn:name="../rtl/pkg_dma.vhd"/>
<outfile xil_pn:name="../rtl/rx_CplD_Channel.vhd"/>
<outfile xil_pn:name="../rtl/rx_MRd_Channel.vhd"/>
<outfile xil_pn:name="../rtl/rx_MWr_Channel.vhd"/>
<outfile xil_pn:name="../rtl/rx_Transact.vhd"/>
<outfile xil_pn:name="../rtl/rx_dsDMA_Channel.vhd"/>
<outfile xil_pn:name="../rtl/rx_usDMA_Channel.vhd"/>
<outfile xil_pn:name="../rtl/tlpControl.vhd"/>
<outfile xil_pn:name="../rtl/tx_Mem_Reader.vhd"/>
<outfile xil_pn:name="../rtl/tx_Transact.vhd"/>
<outfile xil_pn:name="../rtl/v5pcieDMA.vhd"/>
<outfile xil_pn:name="../sim/tf64_pcie_trn.v"/>
</transform>
<transform xil_pn:end_ts="1316006426" xil_pn:in_ck="-4617413950069613313" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="-7601116106744018358" xil_pn:start_ts="1316006425">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="tf64_pcie_trn.fdo"/>
</transform>
</transforms>
 
</generated_project>
/trunk/xise/dma_top.xise
15,10 → 15,6
<version xil_pn:ise_version="12.4" xil_pn:schema_version="2"/>
 
<files>
<file xil_pn:name="../rtl/protocol_if.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../rtl/Registers.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
59,26 → 55,14
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../rtl/class_dlm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../rtl/rx_dsDMA_Channel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../rtl/class_ctl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../rtl/tx_Transact.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../rtl/class_daq.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../rtl/tlpControl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
103,10 → 87,6
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../rtl/pseudo_protocol_module.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../cores/prim_FIFO_plain.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
119,18 → 99,10
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../cores/afifo_256x36.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../cores/eb_fifo_counted.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../cores/afifo_256x36c_fwft.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../cores/mBuf_128x72.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
139,14 → 111,6
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../cores/afifo_8x8.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../cores/afifo_1024x72.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../rtl/DMA_FSM.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
162,9 → 126,11
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../cores/pkt_counter_1024.xco" xil_pn:type="FILE_COREGEN">
<file xil_pn:name="../sim/tf64_pcie_trn.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
</file>
</files>
 
399,7 → 365,7
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Base Name" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="v5pcieDMA" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
476,8 → 442,8
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="SelectMAP Abort Sequence" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/ddr2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.ddr2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tf64_pcie_trn" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.tf64_pcie_trn" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
570,7 → 536,7
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|tf" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|tf64_pcie_trn" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="Optic_v5DMA" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex5" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
/trunk/docs/ug_PCIeDMA_v1.2.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/docs/ug_PCIeDMA_v1.2.pdf
trunk/docs/ug_PCIeDMA_v1.2.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/cores/afifo_8x8.ngc =================================================================== --- trunk/cores/afifo_8x8.ngc (revision 2) +++ trunk/cores/afifo_8x8.ngc (nonexistent) @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.5e 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\ No newline at end of file Index: trunk/cores/afifo_256x36.ngc =================================================================== --- trunk/cores/afifo_256x36.ngc (revision 2) +++ trunk/cores/afifo_256x36.ngc (nonexistent) @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.5e 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\ No newline at end of file Index: trunk/cores/pkt_counter_1024.ngc =================================================================== --- trunk/cores/pkt_counter_1024.ngc (revision 2) +++ trunk/cores/pkt_counter_1024.ngc (nonexistent) @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.5e 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