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https://opencores.org/ocsvn/pit/pit/trunk
Subversion Repositories pit
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- This comparison shows the changes necessary to convert path
/pit/trunk
- from Rev 16 to Rev 17
- ↔ Reverse comparison
Rev 16 → Rev 17
/rtl/verilog/pit_wb_bus.v
86,7 → 86,7
assign module_sel = wb_cyc_i && wb_stb_i; |
assign wb_wacc = module_sel && wb_we_i && (wb_ack_o || SINGLE_CYCLE); |
assign wb_racc = module_sel && !wb_we_i; |
assign wb_ack_o = SINGLE_CYCLE ? module_sel : bus_wait_state; |
assign wb_ack_o = SINGLE_CYCLE ? module_sel : (bus_wait_state && module_sel); |
assign wb_dat_o = SINGLE_CYCLE ? rd_data_mux : rd_data_reg; |
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// generate acknowledge output signal, By using register all accesses takes two cycles. |