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https://opencores.org/ocsvn/pit/pit/trunk
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- This comparison shows the changes necessary to convert path
/pit
- from Rev 11 to Rev 12
- ↔ Reverse comparison
Rev 11 → Rev 12
/trunk/rtl/verilog/pit_wb_bus.v
41,7 → 41,7
parameter SINGLE_CYCLE = 1'b0) |
( |
// Wishbone Signals |
output reg [DWIDTH-1:0] wb_dat_o, // databus output |
output [DWIDTH-1:0] wb_dat_o, // databus output |
output wb_ack_o, // bus cycle acknowledge output |
input wb_clk_i, // master clock input |
input wb_rst_i, // synchronous active high reset |
62,11 → 62,15
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// registers |
reg bus_wait_state; // Holdoff wb_ack_o for one clock to add wait state |
reg bus_wait_state; // Holdoff wb_ack_o for one clock to add wait state |
reg [DWIDTH-1:0] rd_data_mux; // Pseudo Register, WISHBONE Read Data Mux |
reg [DWIDTH-1:0] rd_data_reg; // Latch for WISHBONE Read Data |
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// Wires |
wire eight_bit_bus; |
wire module_sel; // This module is selected for bus transaction |
wire wb_wacc; // WISHBONE Write Strobe |
wire wb_racc; // WISHBONE Read Access (Clock gating signal) |
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// |
// module body |
79,8 → 83,11
assign sync_reset = wb_rst_i; |
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// generate wishbone signals |
assign wb_wacc = wb_cyc_i && wb_stb_i && wb_we_i && (wb_ack_o || SINGLE_CYCLE); |
assign wb_ack_o = SINGLE_CYCLE ? wb_cyc_i && wb_stb_i : bus_wait_state; |
assign module_sel = wb_cyc_i && wb_stb_i; |
assign wb_wacc = module_sel && wb_we_i && (wb_ack_o || SINGLE_CYCLE); |
assign wb_racc = module_sel && !wb_we_i; |
assign wb_ack_o = SINGLE_CYCLE ? module_sel : bus_wait_state; |
assign wb_dat_o = SINGLE_CYCLE ? rd_data_mux : rd_data_reg; |
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// generate acknowledge output signal, By using register all accesses takes two cycles. |
// Accesses in back to back clock cycles are not possable. |
90,22 → 97,27
else if (sync_reset) |
bus_wait_state <= 1'b0; |
else |
bus_wait_state <= wb_cyc_i && wb_stb_i && !bus_wait_state; |
bus_wait_state <= module_sel && !bus_wait_state; |
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// assign data read bus -- DAT_O |
always @(posedge wb_clk_i) |
case ({eight_bit_bus, wb_adr_i}) // synopsys parallel_case |
if ( wb_racc ) // Clock gate for power saving |
rd_data_reg <= rd_data_mux; |
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// WISHBONE Read Data Mux |
always @* |
case ({eight_bit_bus, wb_adr_i}) // synopsys parallel_case |
// 8 bit Bus, 8 bit Granularity |
4'b1_000: wb_dat_o <= read_regs[ 7: 0]; // 8 bit read address 0 |
4'b1_001: wb_dat_o <= read_regs[15: 8]; // 8 bit read address 1 |
4'b1_010: wb_dat_o <= read_regs[23:16]; // 8 bit read address 2 |
4'b1_011: wb_dat_o <= read_regs[31:24]; // 8 bit read address 3 |
4'b1_100: wb_dat_o <= read_regs[39:32]; // 8 bit read address 4 |
4'b1_101: wb_dat_o <= read_regs[47:40]; // 8 bit read address 5 |
4'b1_000: rd_data_mux <= read_regs[ 7: 0]; // 8 bit read address 0 |
4'b1_001: rd_data_mux <= read_regs[15: 8]; // 8 bit read address 1 |
4'b1_010: rd_data_mux <= read_regs[23:16]; // 8 bit read address 2 |
4'b1_011: rd_data_mux <= read_regs[31:24]; // 8 bit read address 3 |
4'b1_100: rd_data_mux <= read_regs[39:32]; // 8 bit read address 4 |
4'b1_101: rd_data_mux <= read_regs[47:40]; // 8 bit read address 5 |
// 16 bit Bus, 16 bit Granularity |
4'b0_000: wb_dat_o <= read_regs[15: 0]; // 16 bit read access address 0 |
4'b0_001: wb_dat_o <= read_regs[31:16]; |
4'b0_010: wb_dat_o <= read_regs[47:32]; |
4'b0_000: rd_data_mux <= read_regs[15: 0]; // 16 bit read access address 0 |
4'b0_001: rd_data_mux <= read_regs[31:16]; |
4'b0_010: rd_data_mux <= read_regs[47:32]; |
endcase |
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// generate wishbone write register strobes -- one hot if 8 bit bus |