OpenCores

DecodeTesting/bench/vhdl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: DecodeTesting/bench =================================================================== --- DecodeTesting/bench (nonexistent) +++ DecodeTesting/bench (revision 4)

DecodeTesting/bench Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: DecodeTesting/rtl/vhdl/slayer.vhd =================================================================== --- DecodeTesting/rtl/vhdl/slayer.vhd (nonexistent) +++ DecodeTesting/rtl/vhdl/slayer.vhd (revision 4) @@ -0,0 +1,81 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Substitution layer of Present cipher. Simple logic. ---- +---- For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity slayer is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); +end slayer; + +architecture Behavioral of slayer is + + begin + output <= x"C" when input = x"0" else + x"5" when input = x"1" else + x"6" when input = x"2" else + x"B" when input = x"3" else + x"9" when input = x"4" else + x"0" when input = x"5" else + x"A" when input = x"6" else + x"D" when input = x"7" else + x"3" when input = x"8" else + x"E" when input = x"9" else + x"F" when input = x"A" else + x"8" when input = x"B" else + x"4" when input = x"C" else + x"7" when input = x"D" else + x"1" when input = x"E" else + x"2" when input = x"F" else + "ZZZZ"; + end Behavioral; \ No newline at end of file Index: DecodeTesting/rtl/vhdl/PresentDecodeComm.vhd =================================================================== --- DecodeTesting/rtl/vhdl/PresentDecodeComm.vhd (nonexistent) +++ DecodeTesting/rtl/vhdl/PresentDecodeComm.vhd (revision 4) @@ -0,0 +1,273 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Top level part of 'pure' Present decode with RS-232 ---- +---- communication with PC. It contains all suitable components ---- +---- with links between each others. For more informations see ---- +---- below and http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity PresentDecodeComm is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_64: integer := 64; + w_80: integer := 80 + ); + port ( + DATA_RXD : in STD_LOGIC; + CLK : in STD_LOGIC; + RESET : in STD_LOGIC; + DATA_TXD : out STD_LOGIC + ); +end PresentDecodeComm; + +architecture Behavioral of PresentDecodeComm is + +-- Shift register is used for translation 8 bit input of RS-232 data (both RXD and TXD) +-- 64 bit and 80 bit data in dependence of the data type (key, text, result). SM ocntrols it +-- If data are not fully retrieved, last received data are shifted by 8 bits. This is repeated +-- 8 times for text and output value (8 x 8 bits) or 10 times (10 x 8 bits) for key. +-- Width of the word is fully configurable. +component ShiftReg is + generic ( + length_1 : integer := 8; + length_2 : integer := w_64; + internal_data : integer := w_64 + ); + port ( + input : in STD_LOGIC_VECTOR(length_1 - 1 downto 0); + output : out STD_LOGIC_VECTOR(length_2 - 1 downto 0); + en : in STD_LOGIC; + shift : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); +end component ShiftReg; + +-- Component given by Digilent in Eval board for RS-232 communication +component Rs232RefComp is + Port ( + TXD : out std_logic := '1'; + RXD : in std_logic; + CLK : in std_logic; --Master Clock + DBIN : in std_logic_vector (7 downto 0); --Data Bus in + DBOUT : out std_logic_vector (7 downto 0); --Data Bus out + RDA : inout std_logic; --Read Data Available + TBE : inout std_logic := '1'; --Transfer Bus Empty + RD : in std_logic; --Read Strobe + WR : in std_logic; --Write Strobe + PE : out std_logic; --Parity Error Flag + FE : out std_logic; --Frame Error Flag + OE : out std_logic; --Overwrite Error Flag + RST : in std_logic := '0'); --Master Reset +end component Rs232RefComp; + +-- Present decoder - nothing special +component PresentFullDecoder is + generic ( + w_64: integer := 64; + w_80: integer := 80 + ); + port( + ciphertext : in std_logic_vector(w_64 - 1 downto 0); + key : in std_logic_vector(w_80 - 1 downto 0); + plaintext : out std_logic_vector(w_64 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end component PresentFullDecoder; + +-- State machine +component PresentDecodeCommSM is + port ( + clk : in STD_LOGIC; + reset : in STD_LOGIC; + RDAsig : in STD_LOGIC; + TBEsig : in STD_LOGIC; + RDsig : out STD_LOGIC; + WRsig : out STD_LOGIC; + textDataEn : out STD_LOGIC; + textDataShift : out STD_LOGIC; + keyDataEn : out STD_LOGIC; + keyDataShift : out STD_LOGIC; + ciphDataEn : out STD_LOGIC; + ciphDataShift : out STD_LOGIC; + startSig : out STD_LOGIC; + readySig : in STD_LOGIC + ); +end component PresentDecodeCommSM; + +--Signals +signal keyText : STD_LOGIC_VECTOR(w_80 - 1 downto 0); +signal plaintext : STD_LOGIC_VECTOR(w_64 - 1 downto 0); +signal ciphertext : STD_LOGIC_VECTOR(w_64 - 1 downto 0); + +signal dataTXD : STD_LOGIC_VECTOR(7 downto 0); +signal dataRXD : STD_LOGIC_VECTOR(7 downto 0); +signal RDAsig : STD_LOGIC; +signal TBEsig : STD_LOGIC; +signal RDsig : STD_LOGIC; +signal WRsig : STD_LOGIC; +signal PEsig : STD_LOGIC; +signal FEsig : STD_LOGIC; +signal OEsig : STD_LOGIC; + +signal keyDataEn : STD_LOGIC; +signal keyDataShift : STD_LOGIC; + +signal textDataEn : STD_LOGIC; +signal textDataShift : STD_LOGIC; + +signal ciphDataEn : STD_LOGIC; +signal ciphDataShift : STD_LOGIC; + +signal startSig : STD_LOGIC; +signal readySig : STD_LOGIC; + +begin + + -- Connections + RS232 : Rs232RefComp + Port map( + TXD => DATA_TXD, + RXD => DATA_RXD, + CLK => clk, + DBIN => dataTXD, + DBOUT => dataRXD, + RDA => RDAsig, + TBE => TBEsig, + RD => RDsig, + WR => WRsig, + PE => PEsig, + FE => FEsig, + OE => OEsig, + RST => reset + ); + + textReg : ShiftReg + generic map( + length_1 => 8, + length_2 => w_64, + internal_data => w_64 + ) + port map( + input => dataRXD, + output => plaintext, + en => textDataEn, + shift => textDataShift, + clk => clk, + reset => reset + ); + + keyReg : ShiftReg + generic map( + length_1 => 8, + length_2 => w_80, + internal_data => w_80 + ) + port map( + input => dataRXD, + output => keyText, + en => keyDataEn, + shift => keyDataShift, + clk => clk, + reset => reset + ); + + present :PresentFullDecoder + port map( + ciphertext => plaintext, + key => keyText, + plaintext => ciphertext, + start => startSig, + clk => clk, + reset => reset, + ready => readySig + ); + + outReg : ShiftReg + generic map( + length_1 => w_64, + length_2 => 8, + internal_data => w_64 + ) + port map( + input => ciphertext, + output => dataTXD, + en => ciphDataEn, + shift => ciphDataShift, + clk => clk, + reset => reset + ); + + SM : PresentDecodeCommSM + port map( + clk => clk, + reset => reset, + RDAsig => RDAsig, + TBEsig => TBEsig, + RDsig => RDsig, + WRsig => WRsig, + textDataEn => textDataEn, + textDataShift => textDataShift, + keyDataEn => keyDataEn, + keyDataShift => keyDataShift, + ciphDataEn => ciphDataEn, + ciphDataShift => ciphDataShift, + startSig => startSig, + readySig => readySig + ); + +end Behavioral; + Index: DecodeTesting/rtl/vhdl/PresentDecodeCommSM.vhd =================================================================== --- DecodeTesting/rtl/vhdl/PresentDecodeCommSM.vhd (nonexistent) +++ DecodeTesting/rtl/vhdl/PresentDecodeCommSM.vhd (revision 4) @@ -0,0 +1,426 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- State machine of 'pure' Present decoder with RS-232 ---- +---- communication with PC. Some names can be unclear because of ---- +---- the same type used as in PresentCommSM (in fact the same cycle---- +---- For more informations see below. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.kody.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity PresentDecodeCommSM is + port ( + clk : in STD_LOGIC; + reset : in STD_LOGIC; + RDAsig : in STD_LOGIC; + TBEsig : in STD_LOGIC; + RDsig : out STD_LOGIC; + WRsig : out STD_LOGIC; + textDataEn : out STD_LOGIC; + textDataShift : out STD_LOGIC; + keyDataEn : out STD_LOGIC; + keyDataShift : out STD_LOGIC; + ciphDataEn : out STD_LOGIC; + ciphDataShift : out STD_LOGIC; + startSig : out STD_LOGIC; + readySig : in STD_LOGIC + ); +end PresentDecodeCommSM; + +architecture Behavioral of PresentDecodeCommSM is + +-- counter used for determine number of readed/sended data (key, cipher, result) +component counter is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); +end component counter; + +-- signals + +signal state : stany_comm := NOP; +signal next_state : stany_comm := NOP; + +-- modify for variable key size +signal serialDataCtrCt : STD_LOGIC; +signal serialDataCtrOut : STD_LOGIC_VECTOR(3 downto 0); +signal serialDataCtrReset : STD_LOGIC; +signal ctrReset : STD_LOGIC; +-- DO NOT MODIFY!!! +signal shiftDataCtrCt : STD_LOGIC; +signal shiftDataCtrOut : STD_LOGIC_VECTOR(2 downto 0); + +begin + ctrReset <= serialDataCtrReset or reset; + SM : process(state, RDAsig, TBEsig, shiftDataCtrOut, serialDataCtrOut, readySig) + begin + case state is + -- No operation - waiting for incoming data + when NOP => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + -- data has come + if (RDAsig = '1') then + next_state <= READ_DATA_TEXT; + else + next_state <= NOP; + end if; + -- Cipher data enable and read data + when READ_DATA_TEXT => + RDsig <= '1'; + WRsig <= '0'; + textDataEn <= '1'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + -- counter of retrieved bytes + serialDataCtrCt <= '1'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + next_state <= DECODE_READ_TEXT; + -- Cipher data readed, stop counter and check if proper number of byte + -- was readed + when DECODE_READ_TEXT => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + -- 8 bytes should be readed + if (serialDataCtrOut(3 downto 0) = "1000") then + -- 8 bytes was readed + next_state <= TEMP_STATE; + else + -- 8 bytes was not readed + next_state <= MOVE_TEXT; + end if; + -- Reset counter for next reading + when TEMP_STATE => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '1'; + next_state <= NOP_FOR_KEY; + -- Here data are shfted in shift register - another shift counter are used + when MOVE_TEXT => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '1'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '1'; + serialDataCtrReset <= '0'; + if (shiftDataCtrOut(2 downto 0) = "111") then + next_state <= NOP; + else + next_state <= MOVE_TEXT; + end if; + -- "No operation 2" waiting for data - it could be optimized in way, + -- that waiting for key and text could be the same state, but it was + -- intentionally separated. + when NOP_FOR_KEY => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + -- data has come + if (RDAsig = '1') then + next_state <= READ_DATA_KEY; + else + next_state <= NOP_FOR_KEY; + end if; + -- Key data enable and read data + when READ_DATA_KEY => + RDsig <= '1'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '1'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + -- counter of retrieved bytes + serialDataCtrCt <= '1'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + next_state <= DECODE_READ_KEY; + -- Data readed, stop counter and check if proper number of byte + -- was readed + when DECODE_READ_KEY => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + -- 10 bytes should be readed + if (serialDataCtrOut(3 downto 0) = "1010") then + -- 10 bytes was readed + next_state <= TEMP2_STATE; + else + -- 10 bytes was not readed + next_state <= MOVE_KEY; + end if; + -- Reset counter for next reading + when TEMP2_STATE => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '1'; + next_state <= PRESENT_ENCODE; + -- Here data are shfted in shift register - another shift counter are used + when MOVE_KEY => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '1'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '1'; + serialDataCtrReset <= '0'; + if (shiftDataCtrOut(2 downto 0) = "111") then + next_state <= NOP_FOR_KEY; + else + next_state <= MOVE_KEY; + end if; + -- All suitable data was readed Present encode start + when PRESENT_ENCODE => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataShift <= '0'; + startSig <= '1'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + -- change state if Present result ready + if (readySig = '1') then + ciphDataEn <= '1'; + next_state <= WRITE_OUT; + else + ciphDataEn <= '0'; + next_state <= PRESENT_ENCODE; + end if; + -- similar control of writing result as during reading + when WRITE_OUT => + RDsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '1'; + serialDataCtrCt <= '1'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + if (serialDataCtrOut = "1000") then + WRsig <= '0'; + next_state <= TEMP_OUT; + else + WRsig <= '1'; + next_state <= MOVE_OUT; + end if; + -- all data was sended - start new Present encode cycle + when TEMP_OUT => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '1'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '1'; + next_state <= NOP; + when MOVE_OUT => + if (TBEsig = '0') then + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '1'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + next_state <= MOVE_OUT; + else + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '1'; + startSig <= '1'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '1'; + serialDataCtrReset <= '0'; + if (shiftDataCtrOut = "111") then + next_state <= WRITE_OUT; + else + next_state <= MOVE_OUT; + end if; + end if; + end case; + end process SM; + + state_modifier : process (clk, reset) + begin + if (clk = '1' and clk'Event) then + if (reset = '1') then + state <= NOP; + else + state <= next_state; + end if; + end if; + end process state_modifier; + + -- counter for controling number of bytes of readed data + dataCounter : counter + generic map( + w_5 => 4 + ) + port map ( + cnt_res => serialDataCtrCt, + num => serialDataCtrOut, + clk => clk, + reset => ctrReset + ); + + -- counter for controling number of shifted bits of readed data + shiftCounter : counter + generic map( + w_5 => 3 + ) + port map ( + cnt_res => shiftDataCtrCt, + num => shiftDataCtrOut, + clk => clk, + reset => reset + ); + +end Behavioral; + Index: DecodeTesting/rtl/vhdl/keyupd.vhd =================================================================== --- DecodeTesting/rtl/vhdl/keyupd.vhd (nonexistent) +++ DecodeTesting/rtl/vhdl/keyupd.vhd (revision 4) @@ -0,0 +1,86 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Key update module for present cipher it is 'signal ---- +---- mixing' made by rotation left by 61 bits, using one s-box, ---- +---- and output of the counter. For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity keyupd is + generic( + w_80: integer := 80; + w_5 : integer := 5; + w_4 : integer := 4); + port( + key : in std_logic_vector(w_80-1 downto 0); + num : in std_logic_vector(w_5-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); +end keyupd; + +architecture Behavioral of keyupd is + + component slayer is + generic(w_4: integer := 4); + port( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + signal changed : std_logic_vector(w_4-1 downto 0); + signal changin : std_logic_vector(w_4-1 downto 0); + signal keytemp : std_logic_vector(w_80-1 downto 0); + + begin + s1: slayer port map(input => changin, output => changed); + changin <= keytemp(79 downto 76); + keytemp <= key(18 downto 0) & key(79 downto 19); + keyout(79 downto 76)<= changed; + keyout(75 downto 20) <= keytemp(75 downto 20); + keyout(19 downto 15)<= keytemp(19 downto 15) xor num; + keyout(14 downto 0) <= keytemp(14 downto 0); + end Behavioral; \ No newline at end of file Index: DecodeTesting/rtl/vhdl/kody.vhd =================================================================== --- DecodeTesting/rtl/vhdl/kody.vhd (nonexistent) +++ DecodeTesting/rtl/vhdl/kody.vhd (revision 4) @@ -0,0 +1,59 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- This file contains types and constant used by this ---- +---- implementation of Present project ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +package kody is + -- type for PresentStateMachine to control the datapath & circuit -- + type stany is (NOP, SM_START, SM_READY); + type decode_states is (NOP, KG_START, DEC_START, DEC_READY); + type stany_comm is (NOP, READ_DATA_KEY, DECODE_READ_KEY, MOVE_KEY, TEMP_STATE, TEMP2_STATE, TEMP_OUT, + NOP_FOR_KEY, READ_DATA_TEXT, DECODE_READ_TEXT, MOVE_TEXT, + PRESENT_ENCODE, WRITE_OUT, MOVE_OUT); +end kody; \ No newline at end of file Index: DecodeTesting/rtl/vhdl/PresentStateMachine.vhd =================================================================== --- DecodeTesting/rtl/vhdl/PresentStateMachine.vhd (nonexistent) +++ DecodeTesting/rtl/vhdl/PresentStateMachine.vhd (revision 4) @@ -0,0 +1,130 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- State machine for Present encoder. For more informations ---- +---- see below. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.kody.ALL; + +entity PresentStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); +end PresentStateMachine; + +architecture Behavioral of PresentStateMachine is + + signal state : stany; + signal next_state : stany; + + begin + States : process(state, start, num) + begin + case state is + ---- Waiting for start + when NOP => + ready <= '0'; + cnt_res <= '0'; + ctrl_mux <= '0'; + RegEn <= '0'; + if (start = '1') then + next_state <= SM_START; + else + next_state <= NOP; + end if; + -- Decoding + when SM_START => + ready <= '0'; + RegEn <= '1'; + cnt_res <= '1'; + if (start = '1') then + -- control during first start + if (num = "00000") then + ctrl_mux <= '0'; + next_state <= SM_START; + -- last iteration + elsif (num = "11111") then + ctrl_mux <= '1'; + next_state <= SM_READY; + -- rest iterations + else + ctrl_mux <= '1'; + next_state <= SM_START; + end if; + else + ctrl_mux <= '0'; + next_state <= NOP; + end if; + -- Decoding end + when SM_READY => + cnt_res <= '0'; + RegEn <= '0'; + ready <= '1'; + if (start = '1') then + ctrl_mux <= '1'; + next_state <= SM_READY; + else + ctrl_mux <= '0'; + next_state <= NOP; + end if; + end case; + end process States; + + SM : process (clk, reset) + begin + if (reset = '1') then + state <= NOP; + elsif (clk'Event and clk = '1') then + state <= next_state; + end if; + end process SM; + + end Behavioral; + Index: DecodeTesting/rtl/vhdl/AsyncMux.vhd =================================================================== --- DecodeTesting/rtl/vhdl/AsyncMux.vhd (nonexistent) +++ DecodeTesting/rtl/vhdl/AsyncMux.vhd (revision 4) @@ -0,0 +1,73 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Simple construction of multiplexer. Nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity AsyncMux is + generic ( + width : integer := 64 + ); + port ( + input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); + input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(width - 1 downto 0) + ); +end AsyncMux; + +architecture Behavioral of AsyncMux is + +begin + output <= input0 when (ctrl = '0') else + input1; +end Behavioral; + Index: DecodeTesting/rtl/vhdl/pLayer_inv.vhd =================================================================== --- DecodeTesting/rtl/vhdl/pLayer_inv.vhd (nonexistent) +++ DecodeTesting/rtl/vhdl/pLayer_inv.vhd (revision 4) @@ -0,0 +1,125 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Permutation layer of Present decoder. Simple signal ---- +---- mixing, but in inverse way as cipher. For more information see---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity pLayer_inv is + generic(w_64 : integer := 64); + port ( + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_64-1 downto 0) + ); +end pLayer_inv; + +architecture Behavioral of pLayer_inv is +begin + output(0) <= input(0); + output(1) <= input(16); + output(2) <= input(32); + output(3) <= input(48); + output(4) <= input(1); + output(5) <= input(17); + output(6) <= input(33); + output(7) <= input(49); + output(8) <= input(2); + output(9) <= input(18); + output(10) <= input(34); + output(11) <= input(50); + output(12) <= input(3); + output(13) <= input(19); + output(14) <= input(35); + output(15) <= input(51); + output(16) <= input(4); + output(17) <= input(20); + output(18) <= input(36); + output(19) <= input(52); + output(20) <= input(5); + output(21) <= input(21); + output(22) <= input(37); + output(23) <= input(53); + output(24) <= input(6); + output(25) <= input(22); + output(26) <= input(38); + output(27) <= input(54); + output(28) <= input(7); + output(29) <= input(23); + output(30) <= input(39); + output(31) <= input(55); + output(32) <= input(8); + output(33) <= input(24); + output(34) <= input(40); + output(35) <= input(56); + output(36) <= input(9); + output(37) <= input(25); + output(38) <= input(41); + output(39) <= input(57); + output(40) <= input(10); + output(41) <= input(26); + output(42) <= input(42); + output(43) <= input(58); + output(44) <= input(11); + output(45) <= input(27); + output(46) <= input(43); + output(47) <= input(59); + output(48) <= input(12); + output(49) <= input(28); + output(50) <= input(44); + output(51) <= input(60); + output(52) <= input(13); + output(53) <= input(29); + output(54) <= input(45); + output(55) <= input(61); + output(56) <= input(14); + output(57) <= input(30); + output(58) <= input(46); + output(59) <= input(62); + output(60) <= input(15); + output(61) <= input(31); + output(62) <= input(47); + output(63) <= input(63); +end Behavioral; \ No newline at end of file Index: DecodeTesting/rtl/vhdl/PresentEncKeyGen.vhd =================================================================== --- DecodeTesting/rtl/vhdl/PresentEncKeyGen.vhd (nonexistent) +++ DecodeTesting/rtl/vhdl/PresentEncKeyGen.vhd (revision 4) @@ -0,0 +1,170 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Key generator of Present encoder. It is only those part ---- +---- which is needed for key and cipher decoding by Present ---- +---- decoder. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity PresentEncKeyGen is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_80: integer := 80 + ); + port( + key : in std_logic_vector(w_80 - 1 downto 0); + key_end : out std_logic_vector(w_80 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end PresentEncKeyGen; + +architecture Behavioral of PresentEncKeyGen is + + component Reg is + generic(width : integer := w_80); + port( + input : in STD_LOGIC_VECTOR(width - 1 downto 0); + output : out STD_LOGIC_VECTOR(width - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); + end component Reg; + + component AsyncMux is + generic ( + width : integer := 80 + ); + port ( + input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); + input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(width - 1 downto 0) + ); + end component AsyncMux; + + component PresentStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); + end component; + + component keyupd is + generic( + w_5 : integer := 5; + w_80: integer := 80 + ); + port( + num : in std_logic_vector(w_5-1 downto 0); + key : in std_logic_vector(w_80-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); + end component; + + component counter is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); + end component; + + -- signals + + signal keynum : std_logic_vector (w_5-1 downto 0); + signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0); + signal ready_sig, mux_ctrl, cnt_res, RegEn : std_logic; + + begin + + -- connections + + mux_80: AsyncMux generic map(width => w_80) port map( + input0 => key, + input1 => kupd, + ctrl => mux_ctrl, + output => keyToReg + ); + regKey : Reg generic map(width => w_80) port map( + input => keyToReg, + output => keyfout, + enable => RegEn, + clk => clk, + reset => reset + ); + mixer: keyupd port map( + key => keyfout, + num => keynum, + keyout => kupd + ); + SM: PresentStateMachine port map( + start => start, + reset => reset, + ready => ready_sig, + cnt_res => cnt_res, + ctrl_mux => mux_ctrl, + clk => clk, + num => keynum, + RegEn => RegEn + ); + count: counter port map( + clk => clk, + reset => reset, + cnt_res => cnt_res, + num => keynum + ); + key_end <= keyfout; + ready <= ready_sig; +end Behavioral; Index: DecodeTesting/rtl/vhdl/slayer_inv.vhd =================================================================== --- DecodeTesting/rtl/vhdl/slayer_inv.vhd (nonexistent) +++ DecodeTesting/rtl/vhdl/slayer_inv.vhd (revision 4) @@ -0,0 +1,81 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Inverse substitution layer of Present decoder. Simple ---- +---- logic. For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity slayer_inv is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); +end slayer_inv; + +architecture Behavioral of slayer_inv is + + begin + output <= x"0" when input = x"C" else + x"1" when input = x"5" else + x"2" when input = x"6" else + x"3" when input = x"B" else + x"4" when input = x"9" else + x"5" when input = x"0" else + x"6" when input = x"A" else + x"7" when input = x"D" else + x"8" when input = x"3" else + x"9" when input = x"E" else + x"A" when input = x"F" else + x"B" when input = x"8" else + x"C" when input = x"4" else + x"D" when input = x"7" else + x"E" when input = x"1" else + x"F" when input = x"2" else + "ZZZZ"; + end Behavioral; \ No newline at end of file Index: DecodeTesting/rtl/vhdl/ShiftReg.vhd =================================================================== --- DecodeTesting/rtl/vhdl/ShiftReg.vhd (nonexistent) +++ DecodeTesting/rtl/vhdl/ShiftReg.vhd (revision 4) @@ -0,0 +1,95 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Shift register with parallel input/output. Nothing special---- +---- except configuration - it enables wider input than output and ---- +---- inverse config. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ShiftReg is + generic ( + length_1 : integer := 8; + length_2 : integer := 64; + internal_data : integer := 64 + ); + port ( + input : in STD_LOGIC_VECTOR(length_1 - 1 downto 0); + output : out STD_LOGIC_VECTOR(length_2 - 1 downto 0); + en : in STD_LOGIC; + shift : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); +end ShiftReg; + +architecture Behavioral of ShiftReg is + +signal data : STD_LOGIC_VECTOR(internal_data - 1 downto 0); + +begin + reg : process (clk, reset, data) + begin + if (clk'event and clk = '1') then + if (reset = '1') then + data <= (others => '0'); + elsif (en = '1') then + data(internal_data - 1 downto internal_data - length_1) <= input; + else + if (shift = '1') then + data <= '0' & data(internal_data - 1 downto 1); + end if; + end if; + end if; + output <= data(length_2 - 1 downto 0); + end process reg; + +end Behavioral; + Index: DecodeTesting/rtl/vhdl/keyupd_inv.vhd =================================================================== --- DecodeTesting/rtl/vhdl/keyupd_inv.vhd (nonexistent) +++ DecodeTesting/rtl/vhdl/keyupd_inv.vhd (revision 4) @@ -0,0 +1,88 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Inverse Key update module for present cipher decoding ---- +---- it is 'signal mixing' made by rotation right by 61 bits, ---- +---- using one s-box, and output of the counter. Note, that order ---- +---- of this operatins must be inverse in comparison with key_upd. ---- +---- For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity keyupd_inv is + generic( + w_80: integer := 80; + w_5 : integer := 5; + w_4 : integer := 4); + port( + key : in std_logic_vector(w_80-1 downto 0); + num : in std_logic_vector(w_5-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); +end keyupd_inv; + +architecture Behavioral of keyupd_inv is + + component slayer_inv is + generic(w_4: integer := 4); + port( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + signal changed : std_logic_vector(w_4-1 downto 0); + signal changin : std_logic_vector(w_4-1 downto 0); + signal keytemp : std_logic_vector(w_80-1 downto 0); + + begin + s1: slayer_inv port map(input => changin, output => changed); + changin <= key(79 downto 76); + keytemp(79 downto 76)<= changed; + keytemp(75 downto 20) <= key(75 downto 20); + keytemp(19 downto 15)<= key(19 downto 15) xor num; + keytemp(14 downto 0) <= key(14 downto 0); + keyout <= keytemp(60 downto 0) & keytemp(79 downto 61); + end Behavioral; \ No newline at end of file Index: DecodeTesting/rtl/vhdl/Reg.vhd =================================================================== --- DecodeTesting/rtl/vhdl/Reg.vhd (nonexistent) +++ DecodeTesting/rtl/vhdl/Reg.vhd (revision 4) @@ -0,0 +1,83 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Register - nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Reg is + generic(width : integer := 64); + port( + input : in STD_LOGIC_VECTOR(width - 1 downto 0); + output : out STD_LOGIC_VECTOR(width - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); +end Reg; + +architecture Behavioral of Reg is + +signal reg : STD_LOGIC_VECTOR(width - 1 downto 0); + +begin + clock : process(clk, reset) + begin + if (reset = '1') then + reg <= (others => '0'); + elsif (clk = '1' and clk'Event) then + if (enable = '1') then + reg <= input; + end if; + end if; + end process clock; + output <= reg; +end Behavioral; + Index: DecodeTesting/rtl/vhdl/PresentDecodeCommImpl.ucf =================================================================== --- DecodeTesting/rtl/vhdl/PresentDecodeCommImpl.ucf (nonexistent) +++ DecodeTesting/rtl/vhdl/PresentDecodeCommImpl.ucf (revision 4) @@ -0,0 +1,7 @@ +NET "DATA_RXD" LOC= "R7" | IOSTANDARD= LVTTL | SLEW= FAST ; +NET "DATA_TXD" LOC= "M14" | IOSTANDARD= LVTTL | DRIVE= 8 | SLEW= FAST ; +NET "CLK" LOC= "C9" | IOSTANDARD= LVCMOS33 | SLEW= FAST ; +NET "CLK" TNM_NET = "clk_group"; +TIMESPEC "TS_CLK" = PERIOD "clk_group" 20 ns HIGH 40%; +NET "RESET" LOC= "K17" | IOSTANDARD= LVTTL | PULLDOWN; +SYSTEM_JITTER = 1 ns; \ No newline at end of file Index: DecodeTesting/rtl/vhdl/counter.vhd =================================================================== --- DecodeTesting/rtl/vhdl/counter.vhd (nonexistent) +++ DecodeTesting/rtl/vhdl/counter.vhd (revision 4) @@ -0,0 +1,73 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Typical construction of 5bit counter. It is counting up. ---- +---- Nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity counter is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); +end counter; + +architecture Behavioral of counter is + signal cnt : std_logic_vector(w_5-1 downto 0) := (others => '0'); + begin + licznik : process (clk, reset, cnt) + begin + if (reset = '1') then + cnt <= (others => '0'); + elsif (clk'Event and clk = '1') then + if (cnt_res = '1') then + cnt <= cnt + 1; + end if; + end if; + end process licznik; + num <= cnt; + end Behavioral; + Index: DecodeTesting/rtl/vhdl/PresentDecStateMachine.vhd =================================================================== --- DecodeTesting/rtl/vhdl/PresentDecStateMachine.vhd (nonexistent) +++ DecodeTesting/rtl/vhdl/PresentDecStateMachine.vhd (revision 4) @@ -0,0 +1,135 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- State machine for Present decoder. It is only part of ---- +---- "inverse Present", not key gen. For more informations see ---- +---- below. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.kody.ALL; + +entity PresentDecStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); +end PresentDecStateMachine; + +architecture Behavioral of PresentDecStateMachine is + + signal state : stany; + signal next_state : stany; + + begin + States : process(state, start, num) + begin + case state is + ---- Waiting for start + when NOP => + ready <= '0'; + cnt_res <= '0'; + ctrl_mux <= '0'; + if (start = '1') then + RegEn <= '1'; + next_state <= SM_START; + else + RegEn <= '0'; + next_state <= NOP; + end if; + -- Decoding + when SM_START => + ready <= '0'; + cnt_res <= '1'; + if (start = '1') then + -- control during first start + if (num = "11111") then + RegEn <= '1'; + ctrl_mux <= '1'; + next_state <= SM_START; + -- last iteration + elsif (num = "00000") then + RegEn <= '0'; + ctrl_mux <= '1'; + next_state <= SM_READY; + -- rest iterations + else + RegEn <= '1'; + ctrl_mux <= '1'; + next_state <= SM_START; + end if; + else + RegEn <= '0'; + ctrl_mux <= '0'; + next_state <= NOP; + end if; + -- Decoding end + when SM_READY => + cnt_res <= '0'; + RegEn <= '0'; + ready <= '1'; + if (start = '1') then + ctrl_mux <= '1'; + next_state <= SM_READY; + else + ctrl_mux <= '0'; + next_state <= NOP; + end if; + end case; + end process States; + + SM : process (clk, reset) + begin + if (reset = '1') then + state <= NOP; + elsif (clk'Event and clk = '1') then + state <= next_state; + end if; + end process SM; + + end Behavioral; + Index: DecodeTesting/rtl/vhdl/RS232RefComp.vhd =================================================================== --- DecodeTesting/rtl/vhdl/RS232RefComp.vhd (nonexistent) +++ DecodeTesting/rtl/vhdl/RS232RefComp.vhd (revision 4) @@ -0,0 +1,406 @@ +------------------------------------------------------------------------ +-- RS232RefCom.vhd +------------------------------------------------------------------------ +-- Author: Dan Pederson +-- Copyright 2004 Digilent, Inc. +------------------------------------------------------------------------ +-- Description: This file defines a UART which tranfers data from +-- serial form to parallel form and vice versa. +------------------------------------------------------------------------ +-- Revision History: +-- 07/15/04 (Created) DanP +-- 02/25/08 (Created) ClaudiaG: made use of the baudDivide constant +-- in the Clock Dividing Processes +------------------------------------------------------------------------ + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Rs232RefComp is + Port ( + TXD : out std_logic := '1'; + RXD : in std_logic; + CLK : in std_logic; --Master Clock + DBIN : in std_logic_vector (7 downto 0); --Data Bus in + DBOUT : out std_logic_vector (7 downto 0); --Data Bus out + RDA : inout std_logic; --Read Data Available + TBE : inout std_logic := '1'; --Transfer Bus Empty + RD : in std_logic; --Read Strobe + WR : in std_logic; --Write Strobe + PE : out std_logic; --Parity Error Flag + FE : out std_logic; --Frame Error Flag + OE : out std_logic; --Overwrite Error Flag + RST : in std_logic := '0'); --Master Reset +end Rs232RefComp; + +architecture Behavioral of Rs232RefComp is +------------------------------------------------------------------------ +-- Component Declarations +------------------------------------------------------------------------ + +------------------------------------------------------------------------ +-- Local Type Declarations +------------------------------------------------------------------------ + --Receive state machine + type rstate is ( + strIdle, --Idle state + strEightDelay, --Delays for 8 clock cycles + strGetData, --Shifts in the 8 data bits, and checks parity + strCheckStop --Sets framing error flag if Stop bit is wrong + ); + + type tstate is ( + sttIdle, --Idle state + sttTransfer, --Move data into shift register + sttShift --Shift out data + ); + + type TBEstate is ( + stbeIdle, + stbeSetTBE, + stbeWaitLoad, + stbeWaitWrite + ); + + +------------------------------------------------------------------------ +-- Signal Declarations +------------------------------------------------------------------------ + constant baudDivide : std_logic_vector(7 downto 0) := "00001101"; --Baud Rate dividor, set now for a rate of 9600. + --Found by dividing 50MHz by 9600 and 16. + signal rdReg : std_logic_vector(7 downto 0) := "00000000"; --Receive holding register + signal rdSReg : std_logic_vector(9 downto 0) := "1111111111"; --Receive shift register + signal tfReg : std_logic_vector(7 downto 0); --Transfer holding register + signal tfSReg : std_logic_vector(10 downto 0) := "11111111111"; --Transfer shift register + signal clkDiv : std_logic_vector(8 downto 0) := "000000000"; --used for rClk + signal rClkDiv : std_logic_vector(3 downto 0) := "0000"; --used for tClk + signal ctr : std_logic_vector(3 downto 0) := "0000"; --used for delay times + signal tfCtr : std_logic_vector(3 downto 0) := "0000"; --used to delay in transfer + signal rClk : std_logic := '0'; --Receiving Clock + signal tClk : std_logic; --Transfering Clock + signal dataCtr : std_logic_vector(3 downto 0) := "0000"; --Counts the number of read data bits + signal parError: std_logic; --Parity error bit + signal frameError: std_logic; --Frame error bit + signal CE : std_logic; --Clock enable for the latch + signal ctRst : std_logic := '0'; + signal load : std_logic := '0'; + signal shift : std_logic := '0'; + signal par : std_logic; + signal tClkRST : std_logic := '0'; + signal rShift : std_logic := '0'; + signal dataRST : std_logic := '0'; + signal dataIncr: std_logic := '0'; + + signal strCur : rstate := strIdle; --Current state in the Receive state machine + signal strNext : rstate; --Next state in the Receive state machine + signal sttCur : tstate := sttIdle; --Current state in the Transfer state machine + signal sttNext : tstate; --Next state in the Transfer staet machine + signal stbeCur : TBEstate := stbeIdle; + signal stbeNext: TBEstate; + +------------------------------------------------------------------------ +-- Module Implementation +------------------------------------------------------------------------ + +begin + frameError <= not rdSReg(9); + parError <= not ( rdSReg(8) xor (((rdSReg(0) xor rdSReg(1)) xor (rdSReg(2) xor rdSReg(3))) xor ((rdSReg(4) xor rdSReg(5)) xor (rdSReg(6) xor rdSReg(7)))) ); + DBOUT <= rdReg; + tfReg <= DBIN; + par <= not ( ((tfReg(0) xor tfReg(1)) xor (tfReg(2) xor tfReg(3))) xor ((tfReg(4) xor tfReg(5)) xor (tfReg(6) xor tfReg(7))) ); + +--Clock Dividing Functions-- + + process (CLK, clkDiv) --set up clock divide for rClk + begin + if (Clk = '1' and Clk'event) then + if (clkDiv = baudDivide) then + clkDiv <= "000000000"; + else + clkDiv <= clkDiv +1; + end if; + end if; + end process; + + process (clkDiv, rClk, CLK) --Define rClk + begin + if CLK = '1' and CLK'Event then + if clkDiv = baudDivide then + rClk <= not rClk; + else + rClk <= rClk; + end if; + end if; + end process; + + process (rClk) --set up clock divide for tClk + begin + if (rClk = '1' and rClk'event) then + rClkDiv <= rClkDiv +1; + end if; + end process; + + tClk <= rClkDiv(3); --define tClk + + process (rClk, ctRst) --set up a counter based on rClk + begin + if rClk = '1' and rClk'Event then + if ctRst = '1' then + ctr <= "0000"; + else + ctr <= ctr +1; + end if; + end if; + end process; + + process (tClk, tClkRST) --set up a counter based on tClk + begin + if (tClk = '1' and tClk'event) then + if tClkRST = '1' then + tfCtr <= "0000"; + else + tfCtr <= tfCtr +1; + end if; + end if; + end process; + + --This process controls the error flags-- + process (rClk, RST, RD, CE) + begin + if RD = '1' or RST = '1' then + FE <= '0'; + OE <= '0'; + RDA <= '0'; + PE <= '0'; + elsif rClk = '1' and rClk'event then + if CE = '1' then + FE <= frameError; + OE <= RDA; + RDA <= '1'; + PE <= parError; + rdReg(7 downto 0) <= rdSReg (7 downto 0); + end if; + end if; + end process; + + --This process controls the receiving shift register-- + process (rClk, rShift) + begin + if rClk = '1' and rClk'Event then + if rShift = '1' then + rdSReg <= (RXD & rdSReg(9 downto 1)); + end if; + end if; + end process; + + --This process controls the dataCtr to keep track of shifted values-- + process (rClk, dataRST) + begin + if (rClk = '1' and rClk'event) then + if dataRST = '1' then + dataCtr <= "0000"; + elsif dataIncr = '1' then + dataCtr <= dataCtr +1; + end if; + end if; + end process; + + --Receiving State Machine-- + process (rClk, RST) + begin + if rClk = '1' and rClk'Event then + if RST = '1' then + strCur <= strIdle; + else + strCur <= strNext; + end if; + end if; + end process; + + --This process generates the sequence of steps needed receive the data + + process (strCur, ctr, RXD, dataCtr, rdSReg, rdReg, RDA) + begin + case strCur is + + when strIdle => + dataIncr <= '0'; + rShift <= '0'; + dataRst <= '0'; + + CE <= '0'; + if RXD = '0' then + ctRst <= '1'; + strNext <= strEightDelay; + else + ctRst <= '0'; + strNext <= strIdle; + end if; + + when strEightDelay => + dataIncr <= '0'; + rShift <= '0'; + CE <= '0'; + + if ctr(2 downto 0) = "111" then + ctRst <= '1'; + dataRST <= '1'; + strNext <= strGetData; + else + ctRst <= '0'; + dataRST <= '0'; + strNext <= strEightDelay; + end if; + + when strGetData => + CE <= '0'; + dataRst <= '0'; + if ctr(3 downto 0) = "1111" then + ctRst <= '1'; + dataIncr <= '1'; + rShift <= '1'; + else + ctRst <= '0'; + dataIncr <= '0'; + rShift <= '0'; + end if; + + if dataCtr = "1010" then + strNext <= strCheckStop; + else + strNext <= strGetData; + end if; + + when strCheckStop => + dataIncr <= '0'; + rShift <= '0'; + dataRst <= '0'; + ctRst <= '0'; + + CE <= '1'; + strNext <= strIdle; + + end case; + + end process; + + --TBE State Machine-- + process (CLK, RST) + begin + if CLK = '1' and CLK'Event then + if RST = '1' then + stbeCur <= stbeIdle; + else + stbeCur <= stbeNext; + end if; + end if; + end process; + + --This process gererates the sequence of events needed to control the TBE flag-- + process (stbeCur, CLK, WR, DBIN, load) + begin + + case stbeCur is + + when stbeIdle => + TBE <= '1'; + if WR = '1' then + stbeNext <= stbeSetTBE; + else + stbeNext <= stbeIdle; + end if; + + when stbeSetTBE => + TBE <= '0'; + if load = '1' then + stbeNext <= stbeWaitLoad; + else + stbeNext <= stbeSetTBE; + end if; + + when stbeWaitLoad => + if load = '0' then + stbeNext <= stbeWaitWrite; + else + stbeNext <= stbeWaitLoad; + end if; + + when stbeWaitWrite => + if WR = '0' then + stbeNext <= stbeIdle; + else + stbeNext <= stbeWaitWrite; + end if; + end case; + end process; + + --This process loads and shifts out the transfer shift register-- + process (load, shift, tClk, tfSReg) + begin + TXD <= tfsReg(0); + if tClk = '1' and tClk'Event then + if load = '1' then + tfSReg (10 downto 0) <= ('1' & par & tfReg(7 downto 0) &'0'); + end if; + if shift = '1' then + + tfSReg (10 downto 0) <= ('1' & tfSReg(10 downto 1)); + end if; + end if; + end process; + + -- Transfer State Machine-- + process (tClk, RST) + begin + if (tClk = '1' and tClk'Event) then + if RST = '1' then + sttCur <= sttIdle; + else + sttCur <= sttNext; + end if; + end if; + end process; + + -- This process generates the sequence of steps needed transfer the data-- + process (sttCur, tfCtr, tfReg, TBE, tclk) + begin + + case sttCur is + + when sttIdle => + tClkRST <= '0'; + shift <= '0'; + load <= '0'; + if TBE = '1' then + sttNext <= sttIdle; + else + sttNext <= sttTransfer; + end if; + + when sttTransfer => + shift <= '0'; + load <= '1'; + tClkRST <= '1'; + sttNext <= sttShift; + + + when sttShift => + shift <= '1'; + load <= '0'; + tClkRST <= '0'; + if tfCtr = "1100" then + sttNext <= sttIdle; + else + sttNext <= sttShift; + end if; + end case; + end process; + +end Behavioral; \ No newline at end of file Index: DecodeTesting/rtl/vhdl/FullDecoderSM.vhd =================================================================== --- DecodeTesting/rtl/vhdl/FullDecoderSM.vhd (nonexistent) +++ DecodeTesting/rtl/vhdl/FullDecoderSM.vhd (revision 4) @@ -0,0 +1,134 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- State machine for Present decoder. It controls entire ---- +---- environment for decoding. We can feature 2 'steady states' ---- +---- and 2 'running states'. For more informations see below ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.kody.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FullDecoderSM is + port( + key_gen_start : out std_logic; + key_gen_ready : in std_logic; + decode_start : out std_logic; + decode_ready : in std_logic; + full_decoder_start :in std_logic; + full_decoder_ready : out std_logic; + clk, reset :in std_logic + ); +end FullDecoderSM; + +architecture Behavioral of FullDecoderSM is + + signal state : decode_states; + signal next_state : decode_states; + +begin + + states : process(state, full_decoder_start, key_gen_ready, decode_ready) + begin + case state is + ---- It is No operation - waiting for proper data in the input ---- + when NOP => + key_gen_start <= '0'; + decode_start <= '0'; + full_decoder_ready <= '0'; + if (full_decoder_start = '1') then + next_state <= KG_START; + else + next_state <= NOP; + end if; + ---- It is running key generator for decoding + when KG_START => + key_gen_start <= '1'; + decode_start <= '0'; + full_decoder_ready <= '0'; + if (key_gen_ready = '1') then + next_state <= DEC_START; + else + next_state <= KG_START; + end if; + ---- enerated key for decoding is ready. Now we are decoding ---- + when DEC_START => + key_gen_start <= '1'; + decode_start <= '1'; + full_decoder_ready <= '0'; + if (decode_ready = '1') then + next_state <= DEC_READY; + else + next_state <= DEC_START; + end if; + ---- Decoding was ended. Waiting for user retrieving data ---- + ---- and give information about new operation ---- + when DEC_READY => + key_gen_start <= '1'; + decode_start <= '1'; + full_decoder_ready <= '1'; + if (full_decoder_start = '1') then + next_state <= DEC_READY; + else + next_state <= NOP; + end if; + end case; + end process states; + + SM : process (clk, reset) + begin + if (reset = '1') then + state <= NOP; + elsif (clk'Event and clk = '1') then + state <= next_state; + end if; + end process SM; + +end Behavioral; + Index: DecodeTesting/rtl/vhdl/PresentFullDecoder.vhd =================================================================== --- DecodeTesting/rtl/vhdl/PresentFullDecoder.vhd (nonexistent) +++ DecodeTesting/rtl/vhdl/PresentFullDecoder.vhd (revision 4) @@ -0,0 +1,170 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Present decoder with suitable key generator for decoding ---- +---- (basing on given encode key). ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity PresentFullDecoder is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port( + ciphertext : in std_logic_vector(w_64 - 1 downto 0); + key : in std_logic_vector(w_80 - 1 downto 0); + plaintext : out std_logic_vector(w_64 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end PresentFullDecoder; + +architecture Behavioral of PresentFullDecoder is + +-- Key generator component +component PresentEncKeyGen is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_80: integer := 80 + ); + port( + key : in std_logic_vector(w_80 - 1 downto 0); + key_end : out std_logic_vector(w_80 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end component PresentEncKeyGen; + +-- 'pure' Present decoder +component PresentDec is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port( + plaintext : in std_logic_vector(w_64 - 1 downto 0); + key : in std_logic_vector(w_80 - 1 downto 0); + ciphertext : out std_logic_vector(w_64 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end component PresentDec; + +component FullDecoderSM is + port( + key_gen_start : out std_logic; + key_gen_ready : in std_logic; + decode_start : out std_logic; + decode_ready : in std_logic; + full_decoder_start :in std_logic; + full_decoder_ready : out std_logic; + clk, reset :in std_logic + ); +end component FullDecoderSM; + +-- signals + +signal key_gen_output : std_logic_vector(w_80 - 1 downto 0); + +signal key_gen_start : std_logic; +signal key_gen_ready : std_logic; + +signal decode_start : std_logic; +signal decode_ready : std_logic; + +begin + + -- connections + + keyGen : PresentEncKeyGen + port map( + key => key, + key_end => key_gen_output, + start => key_gen_start, + clk => clk, + reset => reset, + ready => key_gen_ready + ); + + decoder : PresentDec + port map( + plaintext => ciphertext, + key => key_gen_output, + ciphertext => plaintext, + start => decode_start, + clk => clk, + reset => reset, + ready => decode_ready + ); + + SM : FullDecoderSM + port map( + key_gen_start => key_gen_start, + key_gen_ready => key_gen_ready, + decode_start => decode_start, + decode_ready => decode_ready, + full_decoder_start => start, + full_decoder_ready => ready, + clk => clk, + reset => reset + ); + +end Behavioral; Index: DecodeTesting/rtl/vhdl/counter_inv.vhd =================================================================== --- DecodeTesting/rtl/vhdl/counter_inv.vhd (nonexistent) +++ DecodeTesting/rtl/vhdl/counter_inv.vhd (revision 4) @@ -0,0 +1,73 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Typical construction of 5bit counter. It is counting ---- +---- down. Nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity counter_inv is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); +end counter_inv; + +architecture Behavioral of counter_inv is + signal cnt : std_logic_vector(w_5-1 downto 0) := (others => '0'); + begin + licznik : process (clk, reset, cnt) + begin + if (reset = '1') then + cnt <= (others => '1'); + elsif (clk'Event and clk = '1') then + if (cnt_res = '1') then + cnt <= cnt - 1; + end if; + end if; + end process licznik; + num <= cnt; + end Behavioral; + Index: DecodeTesting/rtl/vhdl/PresentDec.vhd =================================================================== --- DecodeTesting/rtl/vhdl/PresentDec.vhd (nonexistent) +++ DecodeTesting/rtl/vhdl/PresentDec.vhd (revision 4) @@ -0,0 +1,220 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Top level of present decoder. It contains 'Key generator' ---- +---- from encoder and 'inverse Present' for decoding the cipher. ---- +---- For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity PresentDec is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port( + plaintext : in std_logic_vector(w_64 - 1 downto 0); + key : in std_logic_vector(w_80 - 1 downto 0); + ciphertext : out std_logic_vector(w_64 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end PresentDec; + +architecture Behavioral of PresentDec is + + component Reg is + generic(width : integer := w_64); + port( + input : in STD_LOGIC_VECTOR(width - 1 downto 0); + output : out STD_LOGIC_VECTOR(width - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); + end component Reg; + + component AsyncMux is + generic ( + width : integer := 64 + ); + port ( + input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); + input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(width - 1 downto 0) + ); + end component AsyncMux; + + component PresentDecStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); + end component; + + -- INVERSE substitution layer for decoding + component slayer_inv is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + -- INVERSE permutation layer for decoding + component pLayer_inv is + generic(w_64 : integer := 64); + port( + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_64-1 downto 0) + ); + end component; + + -- INVERSE key update for decoding + component keyupd_inv is + generic( + w_5 : integer := 5; + w_80: integer := 80 + ); + port( + num : in std_logic_vector(w_5-1 downto 0); + key : in std_logic_vector(w_80-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); + end component; + + -- INVERSE counter for decoding. It is counting down!!! + component counter_inv is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); + end component; + + -- signals + signal keynum : std_logic_vector (w_5-1 downto 0); + signal toXor, ciph, P, Pout, textToReg : std_logic_vector (w_64-1 downto 0); + signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0); + signal ready_sig, mux_ctrl, cnt_res, RegEn : std_logic; + + begin + + -- connections + mux_64: AsyncMux generic map(width => w_64) port map( + input0 => plaintext, + input1 => Pout, + ctrl => mux_ctrl, + output => textToReg + ); + regText : Reg generic map(width => w_64) port map( + input => textToReg, + output => toXor, + enable => RegEn, + clk => clk, + reset => reset + ); + mux_80: AsyncMux generic map(width => w_80) port map( + input0 => key, + input1 => kupd, + ctrl => mux_ctrl, + output => keyToReg + ); + regKey : Reg generic map(width => w_80) port map( + input => keyToReg, + output => keyfout, + enable => RegEn, + clk => clk, + reset => reset + ); + slayers_inv : for N in 15 downto 0 generate + s_x: slayer_inv port map( + input => P(4*N+3 downto 4*N), + output => Pout(4*N+3 downto 4*N) + ); + end generate slayers_inv; + p1: pLayer_inv port map( + input => ciph, + output => P + ); + mixer: keyupd_inv port map( + key => keyfout, + num => keynum, + keyout => kupd + ); + SM: PresentDecStateMachine port map( + start => start, + reset => reset, + ready => ready_sig, + cnt_res => cnt_res, + ctrl_mux => mux_ctrl, + clk => clk, + num => keynum, + RegEn => RegEn + ); + count: counter_inv port map( + clk => clk, + reset => reset, + cnt_res => cnt_res, + num => keynum + ); + ciph <= toXor xor keyfout(79 downto 16); + ciphertext <= ciph; + ready <= ready_sig; +end Behavioral; Index: DecodeTesting/rtl/vhdl =================================================================== --- DecodeTesting/rtl/vhdl (nonexistent) +++ DecodeTesting/rtl/vhdl (revision 4)

DecodeTesting/rtl/vhdl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: DecodeTesting/rtl =================================================================== --- DecodeTesting/rtl (nonexistent) +++ DecodeTesting/rtl (revision 4)

DecodeTesting/rtl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: DecodeTesting/doc/src =================================================================== --- DecodeTesting/doc/src (nonexistent) +++ DecodeTesting/doc/src (revision 4)

DecodeTesting/doc/src Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: DecodeTesting/doc =================================================================== --- DecodeTesting/doc (nonexistent) +++ DecodeTesting/doc (revision 4)

DecodeTesting/doc Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: DecodeTesting/sim =================================================================== --- DecodeTesting/sim (nonexistent) +++ DecodeTesting/sim (revision 4)

DecodeTesting/sim Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: DecodeTesting/sw/JavaTests/PresentCommTesting/rxtxSerial.dll =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: DecodeTesting/sw/JavaTests/PresentCommTesting/rxtxSerial.dll =================================================================== --- DecodeTesting/sw/JavaTests/PresentCommTesting/rxtxSerial.dll (nonexistent) +++ DecodeTesting/sw/JavaTests/PresentCommTesting/rxtxSerial.dll (revision 4)

DecodeTesting/sw/JavaTests/PresentCommTesting/rxtxSerial.dll Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: DecodeTesting/sw/JavaTests/PresentCommTesting/.classpath =================================================================== --- DecodeTesting/sw/JavaTests/PresentCommTesting/.classpath (nonexistent) +++ DecodeTesting/sw/JavaTests/PresentCommTesting/.classpath (revision 4) @@ -0,0 +1,9 @@ + + + + + + + + + Index: DecodeTesting/sw/JavaTests/PresentCommTesting/.project =================================================================== --- DecodeTesting/sw/JavaTests/PresentCommTesting/.project (nonexistent) +++ DecodeTesting/sw/JavaTests/PresentCommTesting/.project (revision 4) @@ -0,0 +1,17 @@ + + + PresentCommTesting + + + + + + org.eclipse.jdt.core.javabuilder + + + + + + org.eclipse.jdt.core.javanature + + Index: DecodeTesting/sw/JavaTests/PresentCommTesting/lib/commons-lang3-3.1.jar =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: DecodeTesting/sw/JavaTests/PresentCommTesting/lib/commons-lang3-3.1.jar =================================================================== --- DecodeTesting/sw/JavaTests/PresentCommTesting/lib/commons-lang3-3.1.jar (nonexistent) +++ DecodeTesting/sw/JavaTests/PresentCommTesting/lib/commons-lang3-3.1.jar (revision 4)

DecodeTesting/sw/JavaTests/PresentCommTesting/lib/commons-lang3-3.1.jar Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: DecodeTesting/sw/JavaTests/PresentCommTesting/lib/RXTXcomm.jar =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: DecodeTesting/sw/JavaTests/PresentCommTesting/lib/RXTXcomm.jar =================================================================== --- DecodeTesting/sw/JavaTests/PresentCommTesting/lib/RXTXcomm.jar (nonexistent) +++ DecodeTesting/sw/JavaTests/PresentCommTesting/lib/RXTXcomm.jar (revision 4)

DecodeTesting/sw/JavaTests/PresentCommTesting/lib/RXTXcomm.jar Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: DecodeTesting/sw/JavaTests/PresentCommTesting/lib =================================================================== --- DecodeTesting/sw/JavaTests/PresentCommTesting/lib (nonexistent) +++ DecodeTesting/sw/JavaTests/PresentCommTesting/lib (revision 4)

DecodeTesting/sw/JavaTests/PresentCommTesting/lib Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen/PresentDataGenerator.java =================================================================== --- DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen/PresentDataGenerator.java (nonexistent) +++ DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen/PresentDataGenerator.java (revision 4) @@ -0,0 +1,90 @@ +package pl.com.kgajewski.serialcomm.datagen; +import java.io.BufferedWriter; +import java.io.File; +import java.io.FileWriter; +import java.io.IOException; + +import org.apache.commons.lang3.StringUtils; + + +public class PresentDataGenerator { + public static void main(String[] args) { + String drive = "e:\\"; + String data = "a112ffc72f68417b"; + String key = "00000000000000000000"; + + String data2 = "3333dcd3213210d2"; + String key2 = "ffffffffffffffffffff"; + + try { + System.out.println("key"); + File f1 = new File(drive + "key.txt"); + f1.createNewFile(); + formatDataFromHex(key, f1); + + System.out.println("data"); + File f2 = new File(drive + "data.txt"); + f1.createNewFile(); + formatDataFromHex(data, f2); + + System.out.println("key2"); + File f3 = new File(drive + "key2.txt"); + f3.createNewFile(); + formatDataFromHex(key2, f3); + + System.out.println("data2"); + File f4 = new File(drive + "data2.txt"); + f4.createNewFile(); + formatDataFromHex(data2, f4); + + } catch (IOException e1) { + // TODO Auto-generated catch block + e1.printStackTrace(); + } + + } + + private static void formatDataFromHex(String str, File f) throws IOException { + BufferedWriter bfw = new BufferedWriter(new FileWriter(f)); + for (int i = str.length(); i > 0; i -= 2) { + String substr = str.substring(i - 2, i); + + parseByteStringHex(bfw, substr); + } + bfw.close(); + } + + private static void parseByteStringHex(BufferedWriter bfw, String str) + throws IOException { + Integer i = Integer.valueOf(str, 16); + String s = Integer.toString(i, 2); + String tmp = ""; + for (int j = 8 - s.length(); j > 0; j--) { + tmp = tmp.concat("0"); + } + parseByteString(bfw, tmp + s); + } + + private static void parseByteString(BufferedWriter bfw, String str) + throws IOException { + int ones = 0; + bfw.write(str); + bfw.write("\n"); + str = StringUtils.reverse(str); + + for (int j = 0; j < str.length(); j++) { + bfw.write(str.charAt(j)); + bfw.write("\n"); + if (str.charAt(j) == '1') { + ones++; + } + } + if (ones % 2 == 1) { + bfw.write("0"); + } else { + bfw.write("1"); + } + bfw.write("\n"); + } + +} Index: DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen =================================================================== --- DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen (nonexistent) +++ DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen (revision 4)

DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Communication.java =================================================================== --- DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Communication.java (nonexistent) +++ DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Communication.java (revision 4) @@ -0,0 +1,261 @@ +package pl.com.kgajewski.serialcomm.gui; + +import gnu.io.CommPort; +import gnu.io.CommPortIdentifier; +import gnu.io.PortInUseException; +import gnu.io.SerialPort; +import gnu.io.SerialPortEvent; +import gnu.io.SerialPortEventListener; + +import java.io.IOException; +import java.io.InputStream; +import java.io.OutputStream; +import java.math.BigInteger; +import java.util.Enumeration; +import java.util.HashMap; +import java.util.TooManyListenersException; + +import org.apache.commons.lang3.ArrayUtils; +import org.apache.commons.lang3.StringUtils; +import org.eclipse.swt.graphics.Color; + +public class Communication implements SerialPortEventListener { + + //passed from main GUI + Window window = null; + + // just a boolean flag that i use for enabling + // and disabling buttons depending on whether the program + // is connected to a serial port or not + private boolean bConnected = false; + + // the timeout value for connecting with the port + final static int TIMEOUT = 2000; + + // for containing the ports that will be found + private Enumeration ports = null; + // map the port names to CommPortIdentifiers + private HashMap portMap = new HashMap(); + + // this is the object that contains the opened port + private CommPortIdentifier selectedPortIdentifier = null; + private SerialPort serialPort = null; + + // input and output streams for sending and receiving data + private InputStream input = null; + private OutputStream output = null; + + public Communication(Window window) { + this.window = window; + } + + // a string for recording what goes on in the program + // this string is written to the GUI + String logText = ""; + + // search for all the serial ports + // pre style="font-size: 11px;": none + // post: adds all the found ports to a combo box on the GUI + public void searchForPorts() { + ports = CommPortIdentifier.getPortIdentifiers(); + + while (ports.hasMoreElements()) { + CommPortIdentifier curPort = (CommPortIdentifier) ports + .nextElement(); + + // get only serial ports + if (curPort.getPortType() == CommPortIdentifier.PORT_SERIAL) { + window.combo.add(curPort.getName()); + portMap.put(curPort.getName(), curPort); + } + } + } + + // connect to the selected port in the combo box + // pre style="font-size: 11px;": ports are already found by using the + // searchForPorts + // method + // post: the connected comm port is stored in commPort, otherwise, + // an exception is generated + public void connect() { + if (window.combo.getSelectionIndex() >= 0) { + String selectedPort = (String) window.combo.getItem(window.combo.getSelectionIndex()); + selectedPortIdentifier = (CommPortIdentifier) portMap + .get(selectedPort); + + CommPort commPort = null; + + try { + // the method below returns an object of type CommPort + commPort = selectedPortIdentifier.open("pl.com.kgajewski.cerialcomm", + TIMEOUT); + // the CommPort object can be casted to a SerialPort object + serialPort = (SerialPort) commPort; + serialPort.setSerialPortParams(115200,SerialPort.DATABITS_8,SerialPort.STOPBITS_1,SerialPort.PARITY_ODD); + + // for controlling GUI elements + setConnected(true); + + // logging + logText = selectedPort + " opened successfully."; + window.text.setForeground(new Color(window.shell.getDisplay(), 0, 0, 0)); + window.appendText(logText + "\n"); + + // CODE ON SETTING BAUD RATE ETC OMITTED + // XBEE PAIR ASSUMED TO HAVE SAME SETTINGS ALREADY + + // enables the controls on the GUI if a successful connection is + // made + window.toggleControls(); + + } catch (PortInUseException e) { + logText = selectedPort + " is in use. (" + e.toString() + ")"; + + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } catch (Exception e) { + logText = "Failed to open " + selectedPort + "(" + e.toString() + + ")"; + window.appendText(logText + "\n"); + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + } + } + } + // open the input and output streams + // pre style="font-size: 11px;": an open port + // post: initialized input and output streams for use to communicate data + public boolean initIOStream() { + // return value for whether opening the streams is successful or not + boolean successful = false; + + try { + // + input = serialPort.getInputStream(); + output = serialPort.getOutputStream(); + + successful = true; + return successful; + } catch (IOException e) { + logText = "I/O Streams failed to open. (" + e.toString() + ")"; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + return successful; + } + } + + // starts the event listener that knows whenever data is available to be + // read + // pre style="font-size: 11px;": an open serial port + // post: an event listener for the serial port that knows when data is + // received + public void initListener() { + try { + serialPort.addEventListener(this); + serialPort.notifyOnDataAvailable(true); + } catch (TooManyListenersException e) { + logText = "Too many listeners. (" + e.toString() + ")"; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } + } + + //disconnect the serial port + //pre style="font-size: 11px;": an open serial port + //post: closed serial port + public void disconnect() + { + //close the serial port + try + { + serialPort.removeEventListener(); + serialPort.close(); + input.close(); + output.close(); + setConnected(false); + window.toggleControls(); + + logText = "Disconnected."; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } + catch (Exception e) + { + logText = "Failed to close " + serialPort.getName() + + "(" + e.toString() + ")"; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } + } + + //what happens when data is received + //pre style="font-size: 11px;": serial event is triggered + //post: processing on the data it reads + public void serialEvent(SerialPortEvent evt) { + if (evt.getEventType() == SerialPortEvent.DATA_AVAILABLE) + { + try + { + byte [] buffer = new byte[10]; + int n = input.read(buffer); + if (n > 0) + { + if (n == 1) { + BigInteger command = new BigInteger(new byte []{0, buffer[0]}); + final String s = "Command = " + command.toString(16) + "\n"; + window.appendText(s); + } else { + buffer = ArrayUtils.subarray(buffer, 0, buffer.length - 2); + buffer = ArrayUtils.add(buffer, (byte)0); + ArrayUtils.reverse(buffer); + BigInteger data = new BigInteger(buffer); + window.appendText(data.toString(16) + "\n"); + } + } + else + { + window.appendText("\n"); + } + } + catch (Exception e) + { + logText = "Failed to read data. (" + e.toString() + ")"; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } + } + } + + //method that can be called to send data + //pre style="font-size: 11px;": open serial port + //post: data sent to the other device + public void writeData(String str) + { + try + { + for (int i = str.length()-1; i > 0; i -= 2) { + String s = str.substring(i-1, i+1); + byte b = (byte)(Integer.parseInt(s, 16) & 0xFF); + output.write(b); + Thread.sleep(1); + } + } + catch (Exception e) + { + logText = "Failed to write data. (" + e.toString() + ")"; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } + } + + final public boolean getConnected() + { + return bConnected; + } + + public void setConnected(boolean bConnected) + { + this.bConnected = bConnected; + } + + +} Index: DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Window.java =================================================================== --- DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Window.java (nonexistent) +++ DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Window.java (revision 4) @@ -0,0 +1,159 @@ +package pl.com.kgajewski.serialcomm.gui; + +import org.eclipse.swt.SWT; +import org.eclipse.swt.events.MouseAdapter; +import org.eclipse.swt.events.MouseEvent; +import org.eclipse.swt.widgets.Button; +import org.eclipse.swt.widgets.Combo; +import org.eclipse.swt.widgets.Composite; +import org.eclipse.swt.widgets.Display; +import org.eclipse.swt.widgets.Label; +import org.eclipse.swt.widgets.Shell; +import org.eclipse.swt.widgets.Text; + +public class Window { + + //Communicator object + Communication communication = null; + public Display display; + protected Shell shell; + public Text text; + private Text data; + private Text key; + public Combo combo; + private Button btnConnect; + private Button btnDisconnect; + private Button btnSendData; + + public void toggleControls() + { + if (communication.getConnected() == true) + { + btnDisconnect.setEnabled(true); + btnConnect.setEnabled(false); + btnSendData.setEnabled(true); + } + else + { + btnDisconnect.setEnabled(false); + btnConnect.setEnabled(true); + btnSendData.setEnabled(false); + } + } + + /** + * Launch the application. + * + * @param args + */ + public static void main(String[] args) { + try { + Window window = new Window(); + window.open(); + } catch (Exception e) { + e.printStackTrace(); + } + } + + /** + * Open the window. + */ + public void open() { + display = Display.getDefault(); + createContents(); + communication = new Communication(this); + communication.searchForPorts(); + toggleControls(); + shell.open(); + shell.layout(); + while (!shell.isDisposed()) { + if (!display.readAndDispatch()) { + display.sleep(); + } + } + } + + /** + * Create contents of the window. + */ + protected void createContents() { + shell = new Shell(); + shell.setSize(470, 274); + shell.setText("SWT Application"); + shell.setLayout(null); + + Composite composite = new Composite(shell, SWT.NONE); + composite.setBounds(0, 0, 444, 236); + + text = new Text(composite, SWT.BORDER | SWT.MULTI); + this.text.setBounds(107, 126, 327, 105); + + combo = new Combo(composite, SWT.NONE); + combo.setBounds(10, 10, 91, 23); + + btnConnect = new Button(composite, SWT.NONE); + btnConnect.addMouseListener(new MouseAdapter() { + @Override + public void mouseUp(MouseEvent arg0) { + communication.connect(); + if (communication.getConnected() == true) + { + if (communication.initIOStream() == true) + { + communication.initListener(); + } + } + } + }); + btnConnect.setBounds(107, 10, 75, 25); + btnConnect.setText("Connect"); + + btnDisconnect = new Button(composite, SWT.NONE); + btnDisconnect.addMouseListener(new MouseAdapter() { + @Override + public void mouseUp(MouseEvent arg0) { + communication.disconnect(); + } + }); + btnDisconnect.setBounds(188, 10, 75, 25); + btnDisconnect.setText("Disconnect"); + + Label lblLog = new Label(composite, SWT.NONE); + lblLog.setBounds(107, 105, 186, 15); + lblLog.setText("Log"); + + data = new Text(composite, SWT.BORDER); + data.setBounds(45, 39, 248, 21); + + key = new Text(composite, SWT.BORDER); + key.setBounds(45, 66, 248, 21); + + btnSendData = new Button(composite, SWT.NONE); + btnSendData.addMouseListener(new MouseAdapter() { + @Override + public void mouseUp(MouseEvent arg0) { + communication.writeData(data.getText()); + communication.writeData(key.getText()); + } + }); + btnSendData.setBounds(10, 100, 75, 25); + btnSendData.setText("Send"); + + Label lblData = new Label(composite, SWT.NONE); + lblData.setBounds(10, 39, 29, 15); + lblData.setText("Data"); + + Label lblKey = new Label(composite, SWT.NONE); + lblKey.setBounds(10, 66, 55, 15); + lblKey.setText("Key"); + } + + public void appendText(final String s) { + display.syncExec(new Runnable() { + public void run() { + text.append(s); + } + }); + + } +} Index: DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui =================================================================== --- DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui (nonexistent) +++ DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui (revision 4)

DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm =================================================================== --- DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm (nonexistent) +++ DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm (revision 4)

DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski =================================================================== --- DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski (nonexistent) +++ DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski (revision 4)

DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com =================================================================== --- DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com (nonexistent) +++ DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com (revision 4)

DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl/com Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl =================================================================== --- DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl (nonexistent) +++ DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl (revision 4)

DecodeTesting/sw/JavaTests/PresentCommTesting/src/pl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: DecodeTesting/sw/JavaTests/PresentCommTesting/src =================================================================== --- DecodeTesting/sw/JavaTests/PresentCommTesting/src (nonexistent) +++ DecodeTesting/sw/JavaTests/PresentCommTesting/src (revision 4)

DecodeTesting/sw/JavaTests/PresentCommTesting/src Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: DecodeTesting/sw/JavaTests/PresentCommTesting/bin =================================================================== --- DecodeTesting/sw/JavaTests/PresentCommTesting/bin (nonexistent) +++ DecodeTesting/sw/JavaTests/PresentCommTesting/bin (revision 4)

DecodeTesting/sw/JavaTests/PresentCommTesting/bin Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: DecodeTesting/sw/JavaTests/PresentCommTesting/rxtxParallel.dll =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: DecodeTesting/sw/JavaTests/PresentCommTesting/rxtxParallel.dll =================================================================== --- DecodeTesting/sw/JavaTests/PresentCommTesting/rxtxParallel.dll (nonexistent) +++ DecodeTesting/sw/JavaTests/PresentCommTesting/rxtxParallel.dll (revision 4)

DecodeTesting/sw/JavaTests/PresentCommTesting/rxtxParallel.dll Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: DecodeTesting/sw/JavaTests/PresentCommTesting/.settings/org.eclipse.jdt.core.prefs =================================================================== --- DecodeTesting/sw/JavaTests/PresentCommTesting/.settings/org.eclipse.jdt.core.prefs (nonexistent) +++ DecodeTesting/sw/JavaTests/PresentCommTesting/.settings/org.eclipse.jdt.core.prefs (revision 4) @@ -0,0 +1,11 @@ +eclipse.preferences.version=1 +org.eclipse.jdt.core.compiler.codegen.inlineJsrBytecode=enabled +org.eclipse.jdt.core.compiler.codegen.targetPlatform=1.6 +org.eclipse.jdt.core.compiler.codegen.unusedLocal=preserve +org.eclipse.jdt.core.compiler.compliance=1.6 +org.eclipse.jdt.core.compiler.debug.lineNumber=generate +org.eclipse.jdt.core.compiler.debug.localVariable=generate +org.eclipse.jdt.core.compiler.debug.sourceFile=generate +org.eclipse.jdt.core.compiler.problem.assertIdentifier=error +org.eclipse.jdt.core.compiler.problem.enumIdentifier=error +org.eclipse.jdt.core.compiler.source=1.6 Index: DecodeTesting/sw/JavaTests/PresentCommTesting/.settings =================================================================== --- DecodeTesting/sw/JavaTests/PresentCommTesting/.settings (nonexistent) +++ DecodeTesting/sw/JavaTests/PresentCommTesting/.settings (revision 4)

DecodeTesting/sw/JavaTests/PresentCommTesting/.settings Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: DecodeTesting/sw/JavaTests/PresentCommTesting =================================================================== --- DecodeTesting/sw/JavaTests/PresentCommTesting (nonexistent) +++ DecodeTesting/sw/JavaTests/PresentCommTesting (revision 4)

DecodeTesting/sw/JavaTests/PresentCommTesting Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: DecodeTesting/sw/JavaTests =================================================================== --- DecodeTesting/sw/JavaTests (nonexistent) +++ DecodeTesting/sw/JavaTests (revision 4)

DecodeTesting/sw/JavaTests Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: DecodeTesting/sw =================================================================== --- DecodeTesting/sw (nonexistent) +++ DecodeTesting/sw (revision 4)

DecodeTesting/sw Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: DecodeTesting/syn/XC3ES500 =================================================================== --- DecodeTesting/syn/XC3ES500 (nonexistent) +++ DecodeTesting/syn/XC3ES500 (revision 4)

DecodeTesting/syn/XC3ES500 Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: DecodeTesting/syn =================================================================== --- DecodeTesting/syn (nonexistent) +++ DecodeTesting/syn (revision 4)

DecodeTesting/syn Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Decode/keyupd_invTB.vhd =================================================================== --- Decode/keyupd_invTB.vhd (revision 3) +++ Decode/keyupd_invTB.vhd (nonexistent) @@ -1,106 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:00:18 05/16/2010 --- Design Name: --- Module Name: C:/Users/gajos/Desktop/Polibuda/vhdl/projekt/szyfrator/keyupdTB.vhd --- Project Name: szyfrator --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: keyupd --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.all; -USE ieee.numeric_std.ALL; - -ENTITY keyupd_invTB IS -END keyupd_invTB; - -ARCHITECTURE behavior OF keyupd_invTB IS - - -- Component Declaration for the Unit Under Test (UUT) - - COMPONENT keyupd_inv - PORT( - key : IN std_logic_vector(79 downto 0); - num : IN std_logic_vector(4 downto 0); - keyout : OUT std_logic_vector(79 downto 0)--; - --clk, reset : std_logic - ); - END COMPONENT; - - - --Inputs - signal key : std_logic_vector(79 downto 0) := (others => '0'); - signal num : std_logic_vector(4 downto 0) := (others => '0'); - signal clk : std_logic := '0'; - signal reset : std_logic := '0'; - - --Outputs - signal keyout : std_logic_vector(79 downto 0); - - constant clk_period : time := 1ns; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: keyupd_inv PORT MAP ( - key => key, - num => num, - keyout => keyout--, - --clk => clk, - --reset => reset - ); - - -- No clocks detected in port list. Replace clk below with - -- appropriate port name - - clk_process :process - begin - clk <= '0'; - wait for clk_period/2; - clk <= '1'; - wait for clk_period/2; - end process; - - - -- Stimulus process - stim_proc: process - begin - -- hold reset state for 100ms. - reset <= '1'; - wait for 100ns; - reset <='0'; - wait for clk_period; - key <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - num <= "00001"; - wait for clk_period; - key <= x"c0000000000000008000"; - num <= "00010"; - wait for clk_period; - key <= x"50001800000000010000"; - num <= "00011"; - wait for clk_period; - key <= x"8ba27a0eb8783ac96d59"; - num <= "11111"; - wait for clk_period; - assert false severity failure; - end process; -END; \ No newline at end of file Index: Decode/PresentEncKeyGen.vhd =================================================================== --- Decode/PresentEncKeyGen.vhd (revision 3) +++ Decode/PresentEncKeyGen.vhd (nonexistent) @@ -1,140 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 18:02:34 05/15/2010 --- Design Name: --- Module Name: PresentEnc - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: - --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity PresentEncKeyGen is - generic ( - w_2: integer := 2; - w_4: integer := 4; - w_5: integer := 5; - w_80: integer := 80 - ); - port( - key : in std_logic_vector(w_80 - 1 downto 0); - key_end : out std_logic_vector(w_80 - 1 downto 0); - start, clk, reset : in std_logic; - ready : out std_logic - ); -end PresentEncKeyGen; - -architecture Behavioral of PresentEncKeyGen is - - component Reg is - generic(width : integer := w_80); - port( - input : in STD_LOGIC_VECTOR(width - 1 downto 0); - output : out STD_LOGIC_VECTOR(width - 1 downto 0); - enable : in STD_LOGIC; - clk : in STD_LOGIC; - reset : in STD_LOGIC - ); - end component Reg; - - component AsyncMux is - generic ( - width : integer := 80 - ); - port ( - input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); - input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); - ctrl : in STD_LOGIC; - output : out STD_LOGIC_VECTOR(width - 1 downto 0) - ); - end component AsyncMux; - - component PresentStateMachine is - generic ( - w_5 : integer := 5 - ); - port ( - clk, reset, start : in std_logic; - ready, cnt_res, ctrl_mux, RegEn: out std_logic; - num : in std_logic_vector (w_5-1 downto 0) - ); - end component; - - component keyupd is - generic( - w_5 : integer := 5; - w_80: integer := 80 - ); - port( - num : in std_logic_vector(w_5-1 downto 0); - key : in std_logic_vector(w_80-1 downto 0); - keyout : out std_logic_vector(w_80-1 downto 0) - ); - end component; - - component counter is - generic ( - w_5 : integer := 5 - ); - port ( - clk, reset, cnt_res : in std_logic; - num : out std_logic_vector (w_5-1 downto 0) - ); - end component; - - signal keynum : std_logic_vector (w_5-1 downto 0); - signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0); - signal ready_sig, mux_ctrl, cnt_res, RegEn : std_logic; - - begin - mux_80: AsyncMux generic map(width => w_80) port map( - input0 => key, - input1 => kupd, - ctrl => mux_ctrl, - output => keyToReg - ); - regKey : Reg generic map(width => w_80) port map( - input => keyToReg, - output => keyfout, - enable => RegEn, - clk => clk, - reset => reset - ); - mixer: keyupd port map( - key => keyfout, - num => keynum, - keyout => kupd - ); - SM: PresentStateMachine port map( - start => start, - reset => reset, - ready => ready_sig, - cnt_res => cnt_res, - ctrl_mux => mux_ctrl, - clk => clk, - num => keynum, - RegEn => RegEn - ); - count: counter port map( - clk => clk, - reset => reset, - cnt_res => cnt_res, - num => keynum - ); - key_end <= keyfout; - ready <= ready_sig; -end Behavioral; Index: Decode/pLayer_inv.vhd =================================================================== --- Decode/pLayer_inv.vhd (revision 3) +++ Decode/pLayer_inv.vhd (nonexistent) @@ -1,99 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 16:06:24 05/13/2010 --- Design Name: --- Module Name: pLayer - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity pLayer_inv is - generic(w_64 : integer := 64); - port ( - input : in std_logic_vector(w_64-1 downto 0); - output : out std_logic_vector(w_64-1 downto 0) - ); -end pLayer_inv; - -architecture Behavioral of pLayer_inv is -begin - output(0) <= input(0); - output(1) <= input(16); - output(2) <= input(32); - output(3) <= input(48); - output(4) <= input(1); - output(5) <= input(17); - output(6) <= input(33); - output(7) <= input(49); - output(8) <= input(2); - output(9) <= input(18); - output(10) <= input(34); - output(11) <= input(50); - output(12) <= input(3); - output(13) <= input(19); - output(14) <= input(35); - output(15) <= input(51); - output(16) <= input(4); - output(17) <= input(20); - output(18) <= input(36); - output(19) <= input(52); - output(20) <= input(5); - output(21) <= input(21); - output(22) <= input(37); - output(23) <= input(53); - output(24) <= input(6); - output(25) <= input(22); - output(26) <= input(38); - output(27) <= input(54); - output(28) <= input(7); - output(29) <= input(23); - output(30) <= input(39); - output(31) <= input(55); - output(32) <= input(8); - output(33) <= input(24); - output(34) <= input(40); - output(35) <= input(56); - output(36) <= input(9); - output(37) <= input(25); - output(38) <= input(41); - output(39) <= input(57); - output(40) <= input(10); - output(41) <= input(26); - output(42) <= input(42); - output(43) <= input(58); - output(44) <= input(11); - output(45) <= input(27); - output(46) <= input(43); - output(47) <= input(59); - output(48) <= input(12); - output(49) <= input(28); - output(50) <= input(44); - output(51) <= input(60); - output(52) <= input(13); - output(53) <= input(29); - output(54) <= input(45); - output(55) <= input(61); - output(56) <= input(14); - output(57) <= input(30); - output(58) <= input(46); - output(59) <= input(62); - output(60) <= input(15); - output(61) <= input(31); - output(62) <= input(47); - output(63) <= input(63); -end Behavioral; \ No newline at end of file Index: Decode/Reg.vhd =================================================================== --- Decode/Reg.vhd (revision 3) +++ Decode/Reg.vhd (nonexistent) @@ -1,60 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 23:41:41 06/24/2013 --- Design Name: --- Module Name: Reg - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity Reg is - generic(width : integer := 64); - port( - input : in STD_LOGIC_VECTOR(width - 1 downto 0); - output : out STD_LOGIC_VECTOR(width - 1 downto 0); - enable : in STD_LOGIC; - clk : in STD_LOGIC; - reset : in STD_LOGIC - ); -end Reg; - -architecture Behavioral of Reg is - -signal reg : STD_LOGIC_VECTOR(width - 1 downto 0); - -begin - clock : process(clk, reset) - begin - if (reset = '1') then - reg <= (others => '0'); - elsif (clk = '1' and clk'Event) then - if (enable = '1') then - reg <= input; - end if; - end if; - end process clock; - output <= reg; -end Behavioral; - Index: Decode/PresentDecStateMachine.vhd =================================================================== --- Decode/PresentDecStateMachine.vhd (revision 3) +++ Decode/PresentDecStateMachine.vhd (nonexistent) @@ -1,104 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:17:10 04/02/2011 --- Design Name: --- Module Name: PresentStateMachine - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.NUMERIC_STD.ALL; -use work.kody.ALL; - -entity PresentDecStateMachine is - generic ( - w_5 : integer := 5 - ); - port ( - clk, reset, start : in std_logic; - ready, cnt_res, ctrl_mux, RegEn: out std_logic; - num : in std_logic_vector (w_5-1 downto 0) - ); -end PresentDecStateMachine; - -architecture Behavioral of PresentDecStateMachine is - - signal state : stany; - signal next_state : stany; - - begin - States : process(state, start, num) - begin - case state is - when NOP => - ready <= '0'; - cnt_res <= '0'; - ctrl_mux <= '0'; - if (start = '1') then - RegEn <= '1'; - next_state <= SM_START; - else - RegEn <= '0'; - next_state <= NOP; - end if; - when SM_START => - ready <= '0'; - cnt_res <= '1'; - if (start = '1') then - if (num = "11111") then - RegEn <= '1'; - ctrl_mux <= '1'; - next_state <= SM_START; - elsif (num = "00000") then - RegEn <= '0'; - ctrl_mux <= '1'; - next_state <= SM_READY; - else - RegEn <= '1'; - ctrl_mux <= '1'; - next_state <= SM_START; - end if; - else - RegEn <= '0'; - ctrl_mux <= '0'; - next_state <= NOP; - end if; - when SM_READY => - cnt_res <= '0'; - RegEn <= '0'; - ready <= '1'; - if (start = '1') then - ctrl_mux <= '1'; - next_state <= SM_READY; - else - ctrl_mux <= '0'; - next_state <= NOP; - end if; - end case; - end process States; - - SM : process (clk, reset) - begin - if (reset = '1') then - state <= NOP; - elsif (clk'Event and clk = '1') then - state <= next_state; - end if; - end process SM; - - end Behavioral; - Index: Decode/slayer_inv.vhd =================================================================== --- Decode/slayer_inv.vhd (revision 3) +++ Decode/slayer_inv.vhd (nonexistent) @@ -1,55 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 13:48:15 05/13/2010 --- Design Name: --- Module Name: permutation - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity slayer_inv is - generic ( - w_4 : integer := 4 - ); - port ( - input : in std_logic_vector(w_4-1 downto 0); - output : out std_logic_vector(w_4-1 downto 0) - ); -end slayer_inv; - -architecture Behavioral of slayer_inv is - - begin - output <= x"0" when input = x"C" else - x"1" when input = x"5" else - x"2" when input = x"6" else - x"3" when input = x"B" else - x"4" when input = x"9" else - x"5" when input = x"0" else - x"6" when input = x"A" else - x"7" when input = x"D" else - x"8" when input = x"3" else - x"9" when input = x"E" else - x"A" when input = x"F" else - x"B" when input = x"8" else - x"C" when input = x"4" else - x"D" when input = x"7" else - x"E" when input = x"1" else - x"F" when input = x"2" else - "ZZZZ"; - end Behavioral; \ No newline at end of file Index: Decode/PresentDec.vhd =================================================================== --- Decode/PresentDec.vhd (revision 3) +++ Decode/PresentDec.vhd (nonexistent) @@ -1,186 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 18:02:34 05/15/2010 --- Design Name: --- Module Name: PresentEnc - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: - --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity PresentDec is - generic ( - w_2: integer := 2; - w_4: integer := 4; - w_5: integer := 5; - w_32: integer := 32; - w_64: integer := 64; - w_80: integer := 80 - ); - port( - plaintext : in std_logic_vector(w_64 - 1 downto 0); - key : in std_logic_vector(w_80 - 1 downto 0); - ciphertext : out std_logic_vector(w_64 - 1 downto 0); - start, clk, reset : in std_logic; - ready : out std_logic - ); -end PresentDec; - -architecture Behavioral of PresentDec is - - component Reg is - generic(width : integer := w_64); - port( - input : in STD_LOGIC_VECTOR(width - 1 downto 0); - output : out STD_LOGIC_VECTOR(width - 1 downto 0); - enable : in STD_LOGIC; - clk : in STD_LOGIC; - reset : in STD_LOGIC - ); - end component Reg; - - component AsyncMux is - generic ( - width : integer := 64 - ); - port ( - input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); - input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); - ctrl : in STD_LOGIC; - output : out STD_LOGIC_VECTOR(width - 1 downto 0) - ); - end component AsyncMux; - - component PresentDecStateMachine is - generic ( - w_5 : integer := 5 - ); - port ( - clk, reset, start : in std_logic; - ready, cnt_res, ctrl_mux, RegEn: out std_logic; - num : in std_logic_vector (w_5-1 downto 0) - ); - end component; - - component slayer_inv is - generic ( - w_4 : integer := 4 - ); - port ( - input : in std_logic_vector(w_4-1 downto 0); - output : out std_logic_vector(w_4-1 downto 0) - ); - end component; - - component pLayer_inv is - generic(w_64 : integer := 64); - port( - input : in std_logic_vector(w_64-1 downto 0); - output : out std_logic_vector(w_64-1 downto 0) - ); - end component; - - component keyupd_inv is - generic( - w_5 : integer := 5; - w_80: integer := 80 - ); - port( - num : in std_logic_vector(w_5-1 downto 0); - key : in std_logic_vector(w_80-1 downto 0); - keyout : out std_logic_vector(w_80-1 downto 0) - ); - end component; - - component counter_inv is - generic ( - w_5 : integer := 5 - ); - port ( - clk, reset, cnt_res : in std_logic; - num : out std_logic_vector (w_5-1 downto 0) - ); - end component; - - signal keynum : std_logic_vector (w_5-1 downto 0); - signal toXor, ciph, P, Pout, textToReg : std_logic_vector (w_64-1 downto 0); - signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0); - signal ready_sig, mux_ctrl, cnt_res, RegEn : std_logic; - - begin - mux_64: AsyncMux generic map(width => w_64) port map( - input0 => plaintext, - input1 => Pout, - ctrl => mux_ctrl, - output => textToReg - ); - regText : Reg generic map(width => w_64) port map( - input => textToReg, - output => toXor, - enable => RegEn, - clk => clk, - reset => reset - ); - mux_80: AsyncMux generic map(width => w_80) port map( - input0 => key, - input1 => kupd, - ctrl => mux_ctrl, - output => keyToReg - ); - regKey : Reg generic map(width => w_80) port map( - input => keyToReg, - output => keyfout, - enable => RegEn, - clk => clk, - reset => reset - ); - slayers_inv : for N in 15 downto 0 generate - s_x: slayer_inv port map( - input => P(4*N+3 downto 4*N), - output => Pout(4*N+3 downto 4*N) - ); - end generate slayers_inv; - p1: pLayer_inv port map( - input => ciph, - output => P - ); - mixer: keyupd_inv port map( - key => keyfout, - num => keynum, - keyout => kupd - ); - SM: PresentDecStateMachine port map( - start => start, - reset => reset, - ready => ready_sig, - cnt_res => cnt_res, - ctrl_mux => mux_ctrl, - clk => clk, - num => keynum, - RegEn => RegEn - ); - count: counter_inv port map( - clk => clk, - reset => reset, - cnt_res => cnt_res, - num => keynum - ); - ciph <= toXor xor keyfout(79 downto 16); - ciphertext <= ciph; - ready <= ready_sig; -end Behavioral; Index: Decode/PresentStateMachine.vhd =================================================================== --- Decode/PresentStateMachine.vhd (revision 3) +++ Decode/PresentStateMachine.vhd (nonexistent) @@ -1,100 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:17:10 04/02/2011 --- Design Name: --- Module Name: PresentStateMachine - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.NUMERIC_STD.ALL; -use work.kody.ALL; - -entity PresentStateMachine is - generic ( - w_5 : integer := 5 - ); - port ( - clk, reset, start : in std_logic; - ready, cnt_res, ctrl_mux, RegEn: out std_logic; - num : in std_logic_vector (w_5-1 downto 0) - ); -end PresentStateMachine; - -architecture Behavioral of PresentStateMachine is - - signal state : stany; - signal next_state : stany; - - begin - States : process(state, start, num) - begin - case state is - when NOP => - ready <= '0'; - cnt_res <= '0'; - ctrl_mux <= '0'; - RegEn <= '0'; - if (start = '1') then - next_state <= SM_START; - else - next_state <= NOP; - end if; - when SM_START => - ready <= '0'; - RegEn <= '1'; - cnt_res <= '1'; - if (start = '1') then - if (num = "00000") then - ctrl_mux <= '0'; - next_state <= SM_START; - elsif (num = "11111") then - ctrl_mux <= '1'; - next_state <= SM_READY; - else - ctrl_mux <= '1'; - next_state <= SM_START; - end if; - else - ctrl_mux <= '0'; - next_state <= NOP; - end if; - when SM_READY => - cnt_res <= '0'; - RegEn <= '0'; - ready <= '1'; - if (start = '1') then - ctrl_mux <= '1'; - next_state <= SM_READY; - else - ctrl_mux <= '0'; - next_state <= NOP; - end if; - end case; - end process States; - - SM : process (clk, reset) - begin - if (reset = '1') then - state <= NOP; - elsif (clk'Event and clk = '1') then - state <= next_state; - end if; - end process SM; - - end Behavioral; - Index: Decode/slayer.vhd =================================================================== --- Decode/slayer.vhd (revision 3) +++ Decode/slayer.vhd (nonexistent) @@ -1,55 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 13:48:15 05/13/2010 --- Design Name: --- Module Name: permutation - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity slayer is - generic ( - w_4 : integer := 4 - ); - port ( - input : in std_logic_vector(w_4-1 downto 0); - output : out std_logic_vector(w_4-1 downto 0) - ); -end slayer; - -architecture Behavioral of slayer is - - begin - output <= x"C" when input = x"0" else - x"5" when input = x"1" else - x"6" when input = x"2" else - x"B" when input = x"3" else - x"9" when input = x"4" else - x"0" when input = x"5" else - x"A" when input = x"6" else - x"D" when input = x"7" else - x"3" when input = x"8" else - x"E" when input = x"9" else - x"F" when input = x"A" else - x"8" when input = x"B" else - x"4" when input = x"C" else - x"7" when input = x"D" else - x"1" when input = x"E" else - x"2" when input = x"F" else - "ZZZZ"; - end Behavioral; \ No newline at end of file Index: Decode/counter.vhd =================================================================== --- Decode/counter.vhd (revision 3) +++ Decode/counter.vhd (nonexistent) @@ -1,49 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 13:47:04 04/02/2011 --- Design Name: --- Module Name: counter - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity counter is - generic ( - w_5 : integer := 5 - ); - port ( - clk, reset, cnt_res : in std_logic; - num : out std_logic_vector (w_5-1 downto 0) - ); -end counter; - -architecture Behavioral of counter is - signal cnt : std_logic_vector(w_5-1 downto 0) := (others => '0'); - begin - licznik : process (clk, reset, cnt) - begin - if (reset = '1') then - cnt <= (others => '0'); - elsif (clk'Event and clk = '1') then - if (cnt_res = '1') then - cnt <= cnt + 1; - end if; - end if; - end process licznik; - num <= cnt; - end Behavioral; - Index: Decode/counter_inv.vhd =================================================================== --- Decode/counter_inv.vhd (revision 3) +++ Decode/counter_inv.vhd (nonexistent) @@ -1,49 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 13:47:04 04/02/2011 --- Design Name: --- Module Name: counter - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity counter_inv is - generic ( - w_5 : integer := 5 - ); - port ( - clk, reset, cnt_res : in std_logic; - num : out std_logic_vector (w_5-1 downto 0) - ); -end counter_inv; - -architecture Behavioral of counter_inv is - signal cnt : std_logic_vector(w_5-1 downto 0) := (others => '0'); - begin - licznik : process (clk, reset, cnt) - begin - if (reset = '1') then - cnt <= (others => '1'); - elsif (clk'Event and clk = '1') then - if (cnt_res = '1') then - cnt <= cnt - 1; - end if; - end if; - end process licznik; - num <= cnt; - end Behavioral; - Index: Decode/PresentFullDecoder.vhd =================================================================== --- Decode/PresentFullDecoder.vhd (revision 3) +++ Decode/PresentFullDecoder.vhd (nonexistent) @@ -1,141 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 22:14:34 07/14/2013 --- Design Name: --- Module Name: PresentFullDecoder - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity PresentFullDecoder is - generic ( - w_2: integer := 2; - w_4: integer := 4; - w_5: integer := 5; - w_32: integer := 32; - w_64: integer := 64; - w_80: integer := 80 - ); - port( - ciphertext : in std_logic_vector(w_64 - 1 downto 0); - key : in std_logic_vector(w_80 - 1 downto 0); - plaintext : out std_logic_vector(w_64 - 1 downto 0); - start, clk, reset : in std_logic; - ready : out std_logic - ); -end PresentFullDecoder; - -architecture Behavioral of PresentFullDecoder is - -component PresentEncKeyGen is - generic ( - w_2: integer := 2; - w_4: integer := 4; - w_5: integer := 5; - w_80: integer := 80 - ); - port( - key : in std_logic_vector(w_80 - 1 downto 0); - key_end : out std_logic_vector(w_80 - 1 downto 0); - start, clk, reset : in std_logic; - ready : out std_logic - ); -end component PresentEncKeyGen; - -component PresentDec is - generic ( - w_2: integer := 2; - w_4: integer := 4; - w_5: integer := 5; - w_32: integer := 32; - w_64: integer := 64; - w_80: integer := 80 - ); - port( - plaintext : in std_logic_vector(w_64 - 1 downto 0); - key : in std_logic_vector(w_80 - 1 downto 0); - ciphertext : out std_logic_vector(w_64 - 1 downto 0); - start, clk, reset : in std_logic; - ready : out std_logic - ); -end component PresentDec; - -component FullDecoderSM is - port( - key_gen_start : out std_logic; - key_gen_ready : in std_logic; - decode_start : out std_logic; - decode_ready : in std_logic; - full_decoder_start :in std_logic; - full_decoder_ready : out std_logic; - clk, reset :in std_logic - ); -end component FullDecoderSM; - -signal key_gen_output : std_logic_vector(w_80 - 1 downto 0); - -signal key_gen_start : std_logic; -signal key_gen_ready : std_logic; - -signal decode_start : std_logic; -signal decode_ready : std_logic; - -begin - - keyGen : PresentEncKeyGen - port map( - key => key, - key_end => key_gen_output, - start => key_gen_start, - clk => clk, - reset => reset, - ready => key_gen_ready - ); - - decoder : PresentDec - port map( - plaintext => ciphertext, - key => key_gen_output, - ciphertext => plaintext, - start => decode_start, - clk => clk, - reset => reset, - ready => decode_ready - ); - - SM : FullDecoderSM - port map( - key_gen_start => key_gen_start, - key_gen_ready => key_gen_ready, - decode_start => decode_start, - decode_ready => decode_ready, - full_decoder_start => start, - full_decoder_ready => ready, - clk => clk, - reset => reset - ); - -end Behavioral; ---- TODO -- Modyfikacja SM w zwi�zku ze start i licznikiem (jak w czasie liczenia start = 0!!!) Index: Decode/sLayer_invTB.vhd =================================================================== --- Decode/sLayer_invTB.vhd (revision 3) +++ Decode/sLayer_invTB.vhd (nonexistent) @@ -1,95 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:11:33 05/16/2010 --- Design Name: --- Module Name: C:/Users/gajos/Desktop/Polibuda/vhdl/projekt/szyfrator/sLayerTB.vhd --- Project Name: szyfrator --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: slayer --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.all; -USE ieee.numeric_std.ALL; - -ENTITY sLayerTB IS -END sLayerTB; - -ARCHITECTURE behavior OF sLayer_invTB IS - - -- Component Declaration for the Unit Under Test (UUT) - - COMPONENT slayer_inv - PORT( - input : IN std_logic_vector(3 downto 0); - output : OUT std_logic_vector(3 downto 0) - ); - END COMPONENT; - - - --Inputs - signal clk : std_logic := '0'; - signal reset : std_logic := '0'; - - --BiDirs - signal input : std_logic_vector(3 downto 0); - signal output : std_logic_vector(3 downto 0); - - -- Clock period definitions - constant clk_period : time := 1ns; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: slayer_inv PORT MAP ( - input => input, - output => output - ); - - -- Clock process definitions - clk_process :process - begin - clk <= '0'; - wait for clk_period/2; - clk <= '1'; - wait for clk_period/2; - end process; - - - -- Stimulus process - stim_proc: process - begin - -- hold reset state for 100ms. - reset <= '1'; - wait for 100ns; - reset <= '0'; - wait for clk_period; - input <= x"0"; - wait for clk_period; - input <= x"A"; - wait for clk_period; - input <= x"F"; - wait for clk_period; - -- insert stimulus here - assert false severity failure; - end process; - -END; \ No newline at end of file Index: Decode/PresentDecTB.vhd =================================================================== --- Decode/PresentDecTB.vhd (revision 3) +++ Decode/PresentDecTB.vhd (nonexistent) @@ -1,135 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 22:21:14 06/25/2013 --- Design Name: --- Module Name: E:/spent i praca/OpenCores/present_opencores/trunk/Pure/PresentTB.vhd --- Project Name: Present_Pure --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: PresentEnc --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---USE ieee.numeric_std.ALL; - -ENTITY PresentDecTB IS -END PresentDecTB; - -ARCHITECTURE behavior OF PresentDecTB IS - - -- Component Declaration for the Unit Under Test (UUT) - - COMPONENT PresentDec - PORT( - plaintext : IN std_logic_vector(63 downto 0); - key : IN std_logic_vector(79 downto 0); - ciphertext : OUT std_logic_vector(63 downto 0); - start : IN std_logic; - clk : IN std_logic; - reset : IN std_logic; - ready : OUT std_logic - ); - END COMPONENT; - - - --Inputs - signal plaintext : std_logic_vector(63 downto 0) := (others => '0'); - signal key : std_logic_vector(79 downto 0) := (others => '0'); - signal start : std_logic := '0'; - signal clk : std_logic := '0'; - signal reset : std_logic := '0'; - - --Outputs - signal ciphertext : std_logic_vector(63 downto 0); - signal ready : std_logic; - - -- Clock period definitions - constant clk_period : time := 10 ns; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: PresentDec PORT MAP ( - plaintext => plaintext, - key => key, - ciphertext => ciphertext, - start => start, - clk => clk, - reset => reset, - ready => ready - ); - - -- Clock process definitions - clk_process :process - begin - clk <= '0'; - wait for clk_period/2; - clk <= '1'; - wait for clk_period/2; - end process; - - - -- Stimulus process - stim_proc: process - begin - - reset <= '1'; - start <= '0'; - plaintext <= x"5579c1387b228445"; - key <= x"6dab31744f41d7008759"; - wait for 100 ns; - reset <= '0'; - - plaintext <= x"5579c1387b228445"; - key <= x"6dab31744f41d7008759"; - start <= '1'; - wait for clk_period*40; - start <= '0'; - wait for clk_period; - - plaintext <= x"e72c46c0f5945049"; - key <= x"fe7a548fb60eb167c511"; - start <= '1'; - wait for clk_period*40; - start <= '0'; - wait for clk_period; - - plaintext <= x"a112ffc72f68417b"; - key <= x"6dab31744f41d7008759"; - start <= '1'; - wait for clk_period*40; - start <= '0'; - wait for clk_period; - - plaintext <= x"3333dcd3213210d2"; - key <= x"fe7a548fb60eb167c511"; - start <= '1'; - wait for clk_period*40; - start <= '0'; - wait for clk_period; - - assert false severity failure; - - end process; - -END; Index: Decode/keyupd_inv.vhd =================================================================== --- Decode/keyupd_inv.vhd (revision 3) +++ Decode/keyupd_inv.vhd (nonexistent) @@ -1,59 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 19:45:36 05/13/2010 --- Design Name: --- Module Name: keyupd - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity keyupd_inv is - generic( - w_80: integer := 80; - w_5 : integer := 5; - w_4 : integer := 4); - port( - key : in std_logic_vector(w_80-1 downto 0); - num : in std_logic_vector(w_5-1 downto 0); - keyout : out std_logic_vector(w_80-1 downto 0) - ); -end keyupd_inv; - -architecture Behavioral of keyupd_inv is - - component slayer_inv is - generic(w_4: integer := 4); - port( - input : in std_logic_vector(w_4-1 downto 0); - output : out std_logic_vector(w_4-1 downto 0) - ); - end component; - - signal changed : std_logic_vector(w_4-1 downto 0); - signal changin : std_logic_vector(w_4-1 downto 0); - signal keytemp : std_logic_vector(w_80-1 downto 0); - - begin - s1: slayer_inv port map(input => changin, output => changed); - changin <= key(79 downto 76); - keytemp(79 downto 76)<= changed; - keytemp(75 downto 20) <= key(75 downto 20); - keytemp(19 downto 15)<= key(19 downto 15) xor num; - keytemp(14 downto 0) <= key(14 downto 0); - keyout <= keytemp(60 downto 0) & keytemp(79 downto 61); - end Behavioral; \ No newline at end of file Index: Decode/PresentFullDecoderTB.vhd =================================================================== --- Decode/PresentFullDecoderTB.vhd (revision 3) +++ Decode/PresentFullDecoderTB.vhd (nonexistent) @@ -1,135 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 23:12:57 07/14/2013 --- Design Name: --- Module Name: E:/spent i praca/OpenCores/present_opencores/trunk/Decode/PresentFullDecoderTB.vhd --- Project Name: PresentDecode --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: PresentFullDecoder --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---USE ieee.numeric_std.ALL; - -ENTITY PresentFullDecoderTB IS -END PresentFullDecoderTB; - -ARCHITECTURE behavior OF PresentFullDecoderTB IS - - -- Component Declaration for the Unit Under Test (UUT) - - COMPONENT PresentFullDecoder - PORT( - ciphertext : IN std_logic_vector(63 downto 0); - key : IN std_logic_vector(79 downto 0); - plaintext : OUT std_logic_vector(63 downto 0); - start : IN std_logic; - clk : IN std_logic; - reset : IN std_logic; - ready : OUT std_logic - ); - END COMPONENT; - - - --Inputs - signal ciphertext : std_logic_vector(63 downto 0) := (others => '0'); - signal key : std_logic_vector(79 downto 0) := (others => '0'); - signal start : std_logic := '0'; - signal clk : std_logic := '0'; - signal reset : std_logic := '0'; - - --Outputs - signal plaintext : std_logic_vector(63 downto 0); - signal ready : std_logic; - - -- Clock period definitions - constant clk_period : time := 10 ns; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: PresentFullDecoder PORT MAP ( - ciphertext => ciphertext, - key => key, - plaintext => plaintext, - start => start, - clk => clk, - reset => reset, - ready => ready - ); - - -- Clock process definitions - clk_process :process - begin - clk <= '0'; - wait for clk_period/2; - clk <= '1'; - wait for clk_period/2; - end process; - - - -- Stimulus process - stim_proc: process - begin - - reset <= '1'; - start <= '0'; - ciphertext <= x"5579c1387b228445"; - key <= (others => '0'); - wait for 100 ns; - reset <= '0'; - - ciphertext <= x"5579c1387b228445"; - key <= (others => '0'); - start <= '1'; - wait for clk_period*80; - start <= '0'; - wait for clk_period; - - ciphertext <= x"e72c46c0f5945049"; - key <= (others => '1'); - start <= '1'; - wait for clk_period*80; - start <= '0'; - wait for clk_period; - - ciphertext <= x"a112ffc72f68417b"; - key <= (others => '0'); - start <= '1'; - wait for clk_period*80; - start <= '0'; - wait for clk_period; - - ciphertext <= x"3333dcd3213210d2"; - key <= (others => '1'); - start <= '1'; - wait for clk_period*80; - start <= '0'; - wait for clk_period; - - assert false severity failure; - - end process; - -END; Index: Decode/txt_util.vhd =================================================================== --- Decode/txt_util.vhd (revision 3) +++ Decode/txt_util.vhd (nonexistent) @@ -1,586 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use std.textio.all; - - -package txt_util is - - -- prints a message to the screen - procedure print(text: string); - - -- prints the message when active - -- useful for debug switches - procedure print(active: boolean; text: string); - - -- converts std_logic into a character - function chr(sl: std_logic) return character; - - -- converts std_logic into a string (1 to 1) - function str(sl: std_logic) return string; - - -- converts std_logic_vector into a string (binary base) - function str(slv: std_logic_vector) return string; - - -- converts boolean into a string - function str(b: boolean) return string; - - -- converts an integer into a single character - -- (can also be used for hex conversion and other bases) - function chr(int: integer) return character; - - -- converts integer into string using specified base - function str(int: integer; base: integer) return string; - - -- converts integer to string, using base 10 - function str(int: integer) return string; - - -- convert std_logic_vector into a string in hex format - function hstr(slv: std_logic_vector) return string; - - - -- functions to manipulate strings - ----------------------------------- - - -- convert a character to upper case - function to_upper(c: character) return character; - - -- convert a character to lower case - function to_lower(c: character) return character; - - -- convert a string to upper case - function to_upper(s: string) return string; - - -- convert a string to lower case - function to_lower(s: string) return string; - - - - -- functions to convert strings into other formats - -------------------------------------------------- - - -- converts a character into std_logic - function to_std_logic(c: character) return std_logic; - - -- converts a string into std_logic_vector - function to_std_logic_vector(s: string) return std_logic_vector; - - - - -- file I/O - ----------- - - -- read variable length string from input file - procedure str_read(file in_file: TEXT; - res_string: out string); - - -- print string to a file and start new line - procedure print(file out_file: TEXT; - new_string: in string); - - -- print character to a file and start new line - procedure print(file out_file: TEXT; - char: in character); - -end txt_util; - - - - -package body txt_util is - - - - - -- prints text to the screen - - procedure print(text: string) is - variable msg_line: line; - begin - write(msg_line, text); - writeline(output, msg_line); - end print; - - - - - -- prints text to the screen when active - - procedure print(active: boolean; text: string) is - begin - if active then - print(text); - end if; - end print; - - - -- converts std_logic into a character - - function chr(sl: std_logic) return character is - variable c: character; - begin - case sl is - when 'U' => c:= 'U'; - when 'X' => c:= 'X'; - when '0' => c:= '0'; - when '1' => c:= '1'; - when 'Z' => c:= 'Z'; - when 'W' => c:= 'W'; - when 'L' => c:= 'L'; - when 'H' => c:= 'H'; - when '-' => c:= '-'; - end case; - return c; - end chr; - - - - -- converts std_logic into a string (1 to 1) - - function str(sl: std_logic) return string is - variable s: string(1 to 1); - begin - s(1) := chr(sl); - return s; - end str; - - - - -- converts std_logic_vector into a string (binary base) - -- (this also takes care of the fact that the range of - -- a string is natural while a std_logic_vector may - -- have an integer range) - - function str(slv: std_logic_vector) return string is - variable result : string (1 to slv'length); - variable r : integer; - begin - r := 1; - for i in slv'range loop - result(r) := chr(slv(i)); - r := r + 1; - end loop; - return result; - end str; - - - function str(b: boolean) return string is - - begin - if b then - return "true"; - else - return "false"; - end if; - end str; - - - -- converts an integer into a character - -- for 0 to 9 the obvious mapping is used, higher - -- values are mapped to the characters A-Z - -- (this is usefull for systems with base > 10) - -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) - - function chr(int: integer) return character is - variable c: character; - begin - case int is - when 0 => c := '0'; - when 1 => c := '1'; - when 2 => c := '2'; - when 3 => c := '3'; - when 4 => c := '4'; - when 5 => c := '5'; - when 6 => c := '6'; - when 7 => c := '7'; - when 8 => c := '8'; - when 9 => c := '9'; - when 10 => c := 'A'; - when 11 => c := 'B'; - when 12 => c := 'C'; - when 13 => c := 'D'; - when 14 => c := 'E'; - when 15 => c := 'F'; - when 16 => c := 'G'; - when 17 => c := 'H'; - when 18 => c := 'I'; - when 19 => c := 'J'; - when 20 => c := 'K'; - when 21 => c := 'L'; - when 22 => c := 'M'; - when 23 => c := 'N'; - when 24 => c := 'O'; - when 25 => c := 'P'; - when 26 => c := 'Q'; - when 27 => c := 'R'; - when 28 => c := 'S'; - when 29 => c := 'T'; - when 30 => c := 'U'; - when 31 => c := 'V'; - when 32 => c := 'W'; - when 33 => c := 'X'; - when 34 => c := 'Y'; - when 35 => c := 'Z'; - when others => c := '?'; - end case; - return c; - end chr; - - - - -- convert integer to string using specified base - -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) - - function str(int: integer; base: integer) return string is - - variable temp: string(1 to 10); - variable num: integer; - variable abs_int: integer; - variable len: integer := 1; - variable power: integer := 1; - - begin - - -- bug fix for negative numbers - abs_int := abs(int); - - num := abs_int; - - while num >= base loop -- Determine how many - len := len + 1; -- characters required - num := num / base; -- to represent the - end loop ; -- number. - - for i in len downto 1 loop -- Convert the number to - temp(i) := chr(abs_int/power mod base); -- a string starting - power := power * base; -- with the right hand - end loop ; -- side. - - -- return result and add sign if required - if int < 0 then - return '-'& temp(1 to len); - else - return temp(1 to len); - end if; - - end str; - - - -- convert integer to string, using base 10 - function str(int: integer) return string is - - begin - - return str(int, 10) ; - - end str; - - - - -- converts a std_logic_vector into a hex string. - function hstr(slv: std_logic_vector) return string is - variable hexlen: integer; - variable longslv : std_logic_vector(67 downto 0) := (others => '0'); - variable hex : string(1 to 16); - variable fourbit : std_logic_vector(3 downto 0); - begin - hexlen := (slv'left+1)/4; - if (slv'left+1) mod 4 /= 0 then - hexlen := hexlen + 1; - end if; - longslv(slv'left downto 0) := slv; - for i in (hexlen -1) downto 0 loop - fourbit := longslv(((i*4)+3) downto (i*4)); - case fourbit is - when "0000" => hex(hexlen -I) := '0'; - when "0001" => hex(hexlen -I) := '1'; - when "0010" => hex(hexlen -I) := '2'; - when "0011" => hex(hexlen -I) := '3'; - when "0100" => hex(hexlen -I) := '4'; - when "0101" => hex(hexlen -I) := '5'; - when "0110" => hex(hexlen -I) := '6'; - when "0111" => hex(hexlen -I) := '7'; - when "1000" => hex(hexlen -I) := '8'; - when "1001" => hex(hexlen -I) := '9'; - when "1010" => hex(hexlen -I) := 'A'; - when "1011" => hex(hexlen -I) := 'B'; - when "1100" => hex(hexlen -I) := 'C'; - when "1101" => hex(hexlen -I) := 'D'; - when "1110" => hex(hexlen -I) := 'E'; - when "1111" => hex(hexlen -I) := 'F'; - when "ZZZZ" => hex(hexlen -I) := 'z'; - when "UUUU" => hex(hexlen -I) := 'u'; - when "XXXX" => hex(hexlen -I) := 'x'; - when others => hex(hexlen -I) := '?'; - end case; - end loop; - return hex(1 to hexlen); - end hstr; - - - - -- functions to manipulate strings - ----------------------------------- - - - -- convert a character to upper case - - function to_upper(c: character) return character is - - variable u: character; - - begin - - case c is - when 'a' => u := 'A'; - when 'b' => u := 'B'; - when 'c' => u := 'C'; - when 'd' => u := 'D'; - when 'e' => u := 'E'; - when 'f' => u := 'F'; - when 'g' => u := 'G'; - when 'h' => u := 'H'; - when 'i' => u := 'I'; - when 'j' => u := 'J'; - when 'k' => u := 'K'; - when 'l' => u := 'L'; - when 'm' => u := 'M'; - when 'n' => u := 'N'; - when 'o' => u := 'O'; - when 'p' => u := 'P'; - when 'q' => u := 'Q'; - when 'r' => u := 'R'; - when 's' => u := 'S'; - when 't' => u := 'T'; - when 'u' => u := 'U'; - when 'v' => u := 'V'; - when 'w' => u := 'W'; - when 'x' => u := 'X'; - when 'y' => u := 'Y'; - when 'z' => u := 'Z'; - when others => u := c; - end case; - - return u; - - end to_upper; - - - -- convert a character to lower case - - function to_lower(c: character) return character is - - variable l: character; - - begin - - case c is - when 'A' => l := 'a'; - when 'B' => l := 'b'; - when 'C' => l := 'c'; - when 'D' => l := 'd'; - when 'E' => l := 'e'; - when 'F' => l := 'f'; - when 'G' => l := 'g'; - when 'H' => l := 'h'; - when 'I' => l := 'i'; - when 'J' => l := 'j'; - when 'K' => l := 'k'; - when 'L' => l := 'l'; - when 'M' => l := 'm'; - when 'N' => l := 'n'; - when 'O' => l := 'o'; - when 'P' => l := 'p'; - when 'Q' => l := 'q'; - when 'R' => l := 'r'; - when 'S' => l := 's'; - when 'T' => l := 't'; - when 'U' => l := 'u'; - when 'V' => l := 'v'; - when 'W' => l := 'w'; - when 'X' => l := 'x'; - when 'Y' => l := 'y'; - when 'Z' => l := 'z'; - when others => l := c; - end case; - - return l; - - end to_lower; - - - - -- convert a string to upper case - - function to_upper(s: string) return string is - - variable uppercase: string (s'range); - - begin - - for i in s'range loop - uppercase(i):= to_upper(s(i)); - end loop; - return uppercase; - - end to_upper; - - - - -- convert a string to lower case - - function to_lower(s: string) return string is - - variable lowercase: string (s'range); - - begin - - for i in s'range loop - lowercase(i):= to_lower(s(i)); - end loop; - return lowercase; - - end to_lower; - - - --- functions to convert strings into other types - - --- converts a character into a std_logic - -function to_std_logic(c: character) return std_logic is - variable sl: std_logic; - begin - case c is - when 'U' => - sl := 'U'; - when 'X' => - sl := 'X'; - when '0' => - sl := '0'; - when '1' => - sl := '1'; - when 'Z' => - sl := 'Z'; - when 'W' => - sl := 'W'; - when 'L' => - sl := 'L'; - when 'H' => - sl := 'H'; - when '-' => - sl := '-'; - when others => - sl := 'X'; - end case; - return sl; - end to_std_logic; - - --- converts a string into std_logic_vector - -function to_std_logic_vector(s: string) return std_logic_vector is - variable slv: std_logic_vector(s'high-s'low downto 0); - variable k: integer; -begin - k := s'high-s'low; - for i in s'range loop - slv(k) := to_std_logic(s(i)); - k := k - 1; - end loop; - return slv; -end to_std_logic_vector; - - - - - - ----------------- --- file I/O -- ----------------- - - - --- read variable length string from input file - -procedure str_read(file in_file: TEXT; - res_string: out string) is - - variable l: line; - variable c: character; - variable is_string: boolean; - - begin - - readline(in_file, l); - -- clear the contents of the result string - for i in res_string'range loop - res_string(i) := ' '; - end loop; - -- read all characters of the line, up to the length - -- of the results string - for i in res_string'range loop - read(l, c, is_string); - res_string(i) := c; - if not is_string then -- found end of line - exit; - end if; - end loop; - -end str_read; - - --- print string to a file -procedure print(file out_file: TEXT; - new_string: in string) is - - variable l: line; - - begin - - write(l, new_string); - writeline(out_file, l); - -end print; - - --- print character to a file and start new line -procedure print(file out_file: TEXT; - char: in character) is - - variable l: line; - - begin - - write(l, char); - writeline(out_file, l); - -end print; - - - --- appends contents of a string to a file until line feed occurs --- (LF is considered to be the end of the string) - -procedure str_write(file out_file: TEXT; - new_string: in string) is - begin - - for i in new_string'range loop - print(out_file, new_string(i)); - if new_string(i) = LF then -- end of string - exit; - end if; - end loop; - -end str_write; - - - - -end txt_util; - - - - Index: Decode/keyupd.vhd =================================================================== --- Decode/keyupd.vhd (revision 3) +++ Decode/keyupd.vhd (nonexistent) @@ -1,59 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 19:45:36 05/13/2010 --- Design Name: --- Module Name: keyupd - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity keyupd is - generic( - w_80: integer := 80; - w_5 : integer := 5; - w_4 : integer := 4); - port( - key : in std_logic_vector(w_80-1 downto 0); - num : in std_logic_vector(w_5-1 downto 0); - keyout : out std_logic_vector(w_80-1 downto 0) - ); -end keyupd; - -architecture Behavioral of keyupd is - - component slayer is - generic(w_4: integer := 4); - port( - input : in std_logic_vector(w_4-1 downto 0); - output : out std_logic_vector(w_4-1 downto 0) - ); - end component; - - signal changed : std_logic_vector(w_4-1 downto 0); - signal changin : std_logic_vector(w_4-1 downto 0); - signal keytemp : std_logic_vector(w_80-1 downto 0); - - begin - s1: slayer port map(input => changin, output => changed); - changin <= keytemp(79 downto 76); - keytemp <= key(18 downto 0) & key(79 downto 19); - keyout(79 downto 76)<= changed; - keyout(75 downto 20) <= keytemp(75 downto 20); - keyout(19 downto 15)<= keytemp(19 downto 15) xor num; - keyout(14 downto 0) <= keytemp(14 downto 0); - end Behavioral; \ No newline at end of file Index: Decode/PresentKeyGenTB.vhd =================================================================== --- Decode/PresentKeyGenTB.vhd (revision 3) +++ Decode/PresentKeyGenTB.vhd (nonexistent) @@ -1,126 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 22:21:14 06/25/2013 --- Design Name: --- Module Name: E:/spent i praca/OpenCores/present_opencores/trunk/Pure/PresentTB.vhd --- Project Name: Present_Pure --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: PresentEnc --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---USE ieee.numeric_std.ALL; - -ENTITY PresentKeyGenTB IS -END PresentKeyGenTB; - -ARCHITECTURE behavior OF PresentKeyGenTB IS - - -- Component Declaration for the Unit Under Test (UUT) - - COMPONENT PresentEncKeyGen - PORT( - key : IN std_logic_vector(79 downto 0); - key_end : OUT std_logic_vector(79 downto 0); - start : IN std_logic; - clk : IN std_logic; - reset : IN std_logic; - ready : OUT std_logic - ); - END COMPONENT; - - - --Inputs - signal key : std_logic_vector(79 downto 0) := (others => '0'); - signal start : std_logic := '0'; - signal clk : std_logic := '0'; - signal reset : std_logic := '0'; - - --Outputs - signal key_end : std_logic_vector(79 downto 0); - signal ready : std_logic; - - -- Clock period definitions - constant clk_period : time := 10 ns; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: PresentEncKeyGen PORT MAP ( - key => key, - key_end => key_end, - start => start, - clk => clk, - reset => reset, - ready => ready - ); - - -- Clock process definitions - clk_process :process - begin - clk <= '0'; - wait for clk_period/2; - clk <= '1'; - wait for clk_period/2; - end process; - - - -- Stimulus process - stim_proc: process - begin - - reset <= '1'; - start <= '0'; - wait for 100 ns; - reset <= '0'; - - key <= (others => '0'); - start <= '1'; - wait for clk_period*40; - start <= '0'; - wait for clk_period; - - key <= (others => '1'); - start <= '1'; - wait for clk_period*40; - start <= '0'; - wait for clk_period; - - key <= (others => '0'); - start <= '1'; - wait for clk_period*40; - start <= '0'; - wait for clk_period; - - key <= (others => '1'); - start <= '1'; - wait for clk_period*40; - start <= '0'; - wait for clk_period; - - assert false severity failure; - - end process; - -END; Index: Decode/FullDecoderSM.vhd =================================================================== --- Decode/FullDecoderSM.vhd (revision 3) +++ Decode/FullDecoderSM.vhd (nonexistent) @@ -1,104 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 22:24:13 07/14/2013 --- Design Name: --- Module Name: FullDecoderSM - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use work.kody.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity FullDecoderSM is - port( - key_gen_start : out std_logic; - key_gen_ready : in std_logic; - decode_start : out std_logic; - decode_ready : in std_logic; - full_decoder_start :in std_logic; - full_decoder_ready : out std_logic; - clk, reset :in std_logic - ); -end FullDecoderSM; - -architecture Behavioral of FullDecoderSM is - - signal state : decode_states; - signal next_state : decode_states; - -begin - - states : process(state, full_decoder_start, key_gen_ready, decode_ready) - begin - case state is - when NOP => - key_gen_start <= '0'; - decode_start <= '0'; - full_decoder_ready <= '0'; - if (full_decoder_start = '1') then - next_state <= KG_START; - else - next_state <= NOP; - end if; - when KG_START => - key_gen_start <= '1'; - decode_start <= '0'; - full_decoder_ready <= '0'; - if (key_gen_ready = '1') then - next_state <= DEC_START; - else - next_state <= KG_START; - end if; - when DEC_START => - key_gen_start <= '1'; - decode_start <= '1'; - full_decoder_ready <= '0'; - if (decode_ready = '1') then - next_state <= DEC_READY; - else - next_state <= DEC_START; - end if; - when DEC_READY => - key_gen_start <= '1'; - decode_start <= '1'; - full_decoder_ready <= '1'; - if (full_decoder_start = '1') then - next_state <= DEC_READY; - else - next_state <= NOP; - end if; - end case; - end process states; - - SM : process (clk, reset) - begin - if (reset = '1') then - state <= NOP; - elsif (clk'Event and clk = '1') then - state <= next_state; - end if; - end process SM; - -end Behavioral; - Index: Decode/AsyncMux.vhd =================================================================== --- Decode/AsyncMux.vhd (revision 3) +++ Decode/AsyncMux.vhd (nonexistent) @@ -1,50 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 23:24:35 06/24/2013 --- Design Name: --- Module Name: AsyncMux - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity AsyncMux is - generic ( - width : integer := 64 - ); - port ( - input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); - input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); - ctrl : in STD_LOGIC; - output : out STD_LOGIC_VECTOR(width - 1 downto 0) - ); -end AsyncMux; - -architecture Behavioral of AsyncMux is - -begin - output <= input0 when (ctrl = '0') else - input1; -end Behavioral; - Index: Decode/kody.vhd =================================================================== --- Decode/kody.vhd (revision 3) +++ Decode/kody.vhd (nonexistent) @@ -1,35 +0,0 @@ --- Package File Template --- --- Purpose: This package defines supplemental types, subtypes, --- constants, and functions - - -library IEEE; -use IEEE.STD_LOGIC_1164.all; -package kody is - -- type for PresentStateMachine to control the datapath & circuit -- - type stany is (NOP, SM_START, SM_READY); - type decode_states is (NOP, KG_START, DEC_START, DEC_READY); - -- constant as control command from input -- - constant cnop : std_logic_vector(3 downto 0) := "0000"; --0 no operations - constant cdec : std_logic_vector(3 downto 0) := "0001"; --1 decode text - constant crdk1 : std_logic_vector(3 downto 0) := "0010"; --2 read key part 1 - constant crdk2 : std_logic_vector(3 downto 0) := "0011"; --3 read key part 2 - constant crdk3 : std_logic_vector(3 downto 0) := "0100"; --4 read key part 3 - constant cmkd : std_logic_vector(3 downto 0) := "0101"; --5 make decrypt key - constant ccod : std_logic_vector(3 downto 0) := "0110"; --6 code text - constant crdt1 : std_logic_vector(3 downto 0) := "0111"; --7 read text part 1 - constant crdt2 : std_logic_vector(3 downto 0) := "1000"; --8 read text part 2 - constant ccto1 : std_logic_vector(3 downto 0) := "1001"; --9 ciphertext output part 1 (LSW) - constant ccto2 : std_logic_vector(3 downto 0) := "1010"; --A ciphertext output part 2 (MSW) - -- For input registers (early version, now for mux's) -- - constant in_ld_reg_L : std_logic_vector(1 downto 0) := "00"; -- Load low part of the register (64 & 80 bit) - constant in_ld_reg_H : std_logic_vector(1 downto 0) := "01"; -- Load high part of the register (64 & 80 bit) - constant in_ld_reg_HH : std_logic_vector(1 downto 0) := "10"; -- Load highest part of the register (80 bit only) - constant in_reg_Z : std_logic_vector(1 downto 0) := "11"; -- High impedance on the line (unused - in this design only for block input) - -- For output register -- - constant out_ld_reg : std_logic_vector(1 downto 0) := "00"; -- Load the output register - constant out_reg_L : std_logic_vector(1 downto 0) := "01"; -- send low part of the register to the output - constant out_reg_H : std_logic_vector(1 downto 0) := "10"; -- senf high part of the register to the output - constant out_reg_Z : std_logic_vector(1 downto 0) := "11"; -- High impedance on the line (unused - in this design only for block input) -end kody; \ No newline at end of file Index: Decode/bench/vhdl/PresentFullDecoderTB.vhd =================================================================== --- Decode/bench/vhdl/PresentFullDecoderTB.vhd (nonexistent) +++ Decode/bench/vhdl/PresentFullDecoderTB.vhd (revision 4) @@ -0,0 +1,152 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Present full decoder test bench. Test signals were taken ---- +---- from 'pure' Presnet encoder simulation (it is proper work, ---- +---- because it was good implementation). ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY PresentFullDecoderTB IS +END PresentFullDecoderTB; + +ARCHITECTURE behavior OF PresentFullDecoderTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT PresentFullDecoder + PORT( + ciphertext : IN std_logic_vector(63 downto 0); + key : IN std_logic_vector(79 downto 0); + plaintext : OUT std_logic_vector(63 downto 0); + start : IN std_logic; + clk : IN std_logic; + reset : IN std_logic; + ready : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal ciphertext : std_logic_vector(63 downto 0) := (others => '0'); + signal key : std_logic_vector(79 downto 0) := (others => '0'); + signal start : std_logic := '0'; + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --Outputs + signal plaintext : std_logic_vector(63 downto 0); + signal ready : std_logic; + + -- Clock period definitions + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: PresentFullDecoder PORT MAP ( + ciphertext => ciphertext, + key => key, + plaintext => plaintext, + start => start, + clk => clk, + reset => reset, + ready => ready + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + + reset <= '1'; + start <= '0'; + ciphertext <= x"5579c1387b228445"; + key <= (others => '0'); + wait for 100 ns; + reset <= '0'; + + ciphertext <= x"5579c1387b228445"; + key <= (others => '0'); + start <= '1'; + wait for clk_period*80; + start <= '0'; + wait for clk_period; + + ciphertext <= x"e72c46c0f5945049"; + key <= (others => '1'); + start <= '1'; + wait for clk_period*80; + start <= '0'; + wait for clk_period; + + ciphertext <= x"a112ffc72f68417b"; + key <= (others => '0'); + start <= '1'; + wait for clk_period*80; + start <= '0'; + wait for clk_period; + + ciphertext <= x"3333dcd3213210d2"; + key <= (others => '1'); + start <= '1'; + wait for clk_period*80; + start <= '0'; + wait for clk_period; + + assert false severity failure; + + end process; + +END; Index: Decode/bench/vhdl/sLayer_invTB.vhd =================================================================== --- Decode/bench/vhdl/sLayer_invTB.vhd (nonexistent) +++ Decode/bench/vhdl/sLayer_invTB.vhd (revision 4) @@ -0,0 +1,111 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Inverse substitution layer test bench of Present decoder. ---- +---- Nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + +ENTITY sLayerTB IS +END sLayerTB; + +ARCHITECTURE behavior OF sLayer_invTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT slayer_inv + PORT( + input : IN std_logic_vector(3 downto 0); + output : OUT std_logic_vector(3 downto 0) + ); + END COMPONENT; + + + --Inputs + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --BiDirs + signal input : std_logic_vector(3 downto 0); + signal output : std_logic_vector(3 downto 0); + + -- Clock period definitions + constant clk_period : time := 1ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: slayer_inv PORT MAP ( + input => input, + output => output + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + reset <= '1'; + wait for 100ns; + reset <= '0'; + wait for clk_period; + input <= x"0"; + wait for clk_period; + input <= x"A"; + wait for clk_period; + input <= x"F"; + wait for clk_period; + -- insert stimulus here + assert false severity failure; + end process; + +END; \ No newline at end of file Index: Decode/bench/vhdl/PresentDecTB.vhd =================================================================== --- Decode/bench/vhdl/PresentDecTB.vhd (nonexistent) +++ Decode/bench/vhdl/PresentDecTB.vhd (revision 4) @@ -0,0 +1,152 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Present decoder test bench. Test signals were taken from ---- +---- 'pure' Presnet encoder simulation (it is proper work, because ---- +---- it was good implementation). ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY PresentDecTB IS +END PresentDecTB; + +ARCHITECTURE behavior OF PresentDecTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT PresentDec + PORT( + plaintext : IN std_logic_vector(63 downto 0); + key : IN std_logic_vector(79 downto 0); + ciphertext : OUT std_logic_vector(63 downto 0); + start : IN std_logic; + clk : IN std_logic; + reset : IN std_logic; + ready : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal plaintext : std_logic_vector(63 downto 0) := (others => '0'); + signal key : std_logic_vector(79 downto 0) := (others => '0'); + signal start : std_logic := '0'; + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --Outputs + signal ciphertext : std_logic_vector(63 downto 0); + signal ready : std_logic; + + -- Clock period definitions + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: PresentDec PORT MAP ( + plaintext => plaintext, + key => key, + ciphertext => ciphertext, + start => start, + clk => clk, + reset => reset, + ready => ready + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + + reset <= '1'; + start <= '0'; + plaintext <= x"5579c1387b228445"; + key <= x"6dab31744f41d7008759"; + wait for 100 ns; + reset <= '0'; + + plaintext <= x"5579c1387b228445"; + key <= x"6dab31744f41d7008759"; + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + plaintext <= x"e72c46c0f5945049"; + key <= x"fe7a548fb60eb167c511"; + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + plaintext <= x"a112ffc72f68417b"; + key <= x"6dab31744f41d7008759"; + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + plaintext <= x"3333dcd3213210d2"; + key <= x"fe7a548fb60eb167c511"; + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + assert false severity failure; + + end process; + +END; Index: Decode/bench/vhdl/keyupd_invTB.vhd =================================================================== --- Decode/bench/vhdl/keyupd_invTB.vhd (nonexistent) +++ Decode/bench/vhdl/keyupd_invTB.vhd (revision 4) @@ -0,0 +1,123 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Inverse Key update test bench to be sure that it was ---- +---- properly written. As input data, "generated data" by ISE ---- +---- simulator present cipher was used. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + +ENTITY keyupd_invTB IS +END keyupd_invTB; + +ARCHITECTURE behavior OF keyupd_invTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT keyupd_inv + PORT( + key : IN std_logic_vector(79 downto 0); + num : IN std_logic_vector(4 downto 0); + keyout : OUT std_logic_vector(79 downto 0)--; + --clk, reset : std_logic + ); + END COMPONENT; + + + --Inputs + signal key : std_logic_vector(79 downto 0) := (others => '0'); + signal num : std_logic_vector(4 downto 0) := (others => '0'); + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --Outputs + signal keyout : std_logic_vector(79 downto 0); + + constant clk_period : time := 1ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: keyupd_inv PORT MAP ( + key => key, + num => num, + keyout => keyout--, + --clk => clk, + --reset => reset + ); + + -- No clocks detected in port list. Replace clk below with + -- appropriate port name + + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + reset <= '1'; + wait for 100ns; + reset <='0'; + wait for clk_period; + key <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + num <= "00001"; + wait for clk_period; + key <= x"c0000000000000008000"; + num <= "00010"; + wait for clk_period; + key <= x"50001800000000010000"; + num <= "00011"; + wait for clk_period; + key <= x"8ba27a0eb8783ac96d59"; + num <= "11111"; + wait for clk_period; + assert false severity failure; + end process; +END; \ No newline at end of file Index: Decode/bench/vhdl/PresentKeyGenTB.vhd =================================================================== --- Decode/bench/vhdl/PresentKeyGenTB.vhd (nonexistent) +++ Decode/bench/vhdl/PresentKeyGenTB.vhd (revision 4) @@ -0,0 +1,141 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Present key gen test bench - nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY PresentKeyGenTB IS +END PresentKeyGenTB; + +ARCHITECTURE behavior OF PresentKeyGenTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT PresentEncKeyGen + PORT( + key : IN std_logic_vector(79 downto 0); + key_end : OUT std_logic_vector(79 downto 0); + start : IN std_logic; + clk : IN std_logic; + reset : IN std_logic; + ready : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal key : std_logic_vector(79 downto 0) := (others => '0'); + signal start : std_logic := '0'; + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --Outputs + signal key_end : std_logic_vector(79 downto 0); + signal ready : std_logic; + + -- Clock period definitions + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: PresentEncKeyGen PORT MAP ( + key => key, + key_end => key_end, + start => start, + clk => clk, + reset => reset, + ready => ready + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + + reset <= '1'; + start <= '0'; + wait for 100 ns; + reset <= '0'; + + key <= (others => '0'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + key <= (others => '1'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + key <= (others => '0'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + key <= (others => '1'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + assert false severity failure; + + end process; + +END; Index: Decode/bench/vhdl/txt_util.vhd =================================================================== --- Decode/bench/vhdl/txt_util.vhd (nonexistent) +++ Decode/bench/vhdl/txt_util.vhd (revision 4) @@ -0,0 +1,586 @@ +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; + + +package txt_util is + + -- prints a message to the screen + procedure print(text: string); + + -- prints the message when active + -- useful for debug switches + procedure print(active: boolean; text: string); + + -- converts std_logic into a character + function chr(sl: std_logic) return character; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string; + + -- converts std_logic_vector into a string (binary base) + function str(slv: std_logic_vector) return string; + + -- converts boolean into a string + function str(b: boolean) return string; + + -- converts an integer into a single character + -- (can also be used for hex conversion and other bases) + function chr(int: integer) return character; + + -- converts integer into string using specified base + function str(int: integer; base: integer) return string; + + -- converts integer to string, using base 10 + function str(int: integer) return string; + + -- convert std_logic_vector into a string in hex format + function hstr(slv: std_logic_vector) return string; + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c: character) return character; + + -- convert a character to lower case + function to_lower(c: character) return character; + + -- convert a string to upper case + function to_upper(s: string) return string; + + -- convert a string to lower case + function to_lower(s: string) return string; + + + + -- functions to convert strings into other formats + -------------------------------------------------- + + -- converts a character into std_logic + function to_std_logic(c: character) return std_logic; + + -- converts a string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector; + + + + -- file I/O + ----------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string); + + -- print string to a file and start new line + procedure print(file out_file: TEXT; + new_string: in string); + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character); + +end txt_util; + + + + +package body txt_util is + + + + + -- prints text to the screen + + procedure print(text: string) is + variable msg_line: line; + begin + write(msg_line, text); + writeline(output, msg_line); + end print; + + + + + -- prints text to the screen when active + + procedure print(active: boolean; text: string) is + begin + if active then + print(text); + end if; + end print; + + + -- converts std_logic into a character + + function chr(sl: std_logic) return character is + variable c: character; + begin + case sl is + when 'U' => c:= 'U'; + when 'X' => c:= 'X'; + when '0' => c:= '0'; + when '1' => c:= '1'; + when 'Z' => c:= 'Z'; + when 'W' => c:= 'W'; + when 'L' => c:= 'L'; + when 'H' => c:= 'H'; + when '-' => c:= '-'; + end case; + return c; + end chr; + + + + -- converts std_logic into a string (1 to 1) + + function str(sl: std_logic) return string is + variable s: string(1 to 1); + begin + s(1) := chr(sl); + return s; + end str; + + + + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + + function str(slv: std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r := 1; + for i in slv'range loop + result(r) := chr(slv(i)); + r := r + 1; + end loop; + return result; + end str; + + + function str(b: boolean) return string is + + begin + if b then + return "true"; + else + return "false"; + end if; + end str; + + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function chr(int: integer) return character is + variable c: character; + begin + case int is + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; + end case; + return c; + end chr; + + + + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function str(int: integer; base: integer) return string is + + variable temp: string(1 to 10); + variable num: integer; + variable abs_int: integer; + variable len: integer := 1; + variable power: integer := 1; + + begin + + -- bug fix for negative numbers + abs_int := abs(int); + + num := abs_int; + + while num >= base loop -- Determine how many + len := len + 1; -- characters required + num := num / base; -- to represent the + end loop ; -- number. + + for i in len downto 1 loop -- Convert the number to + temp(i) := chr(abs_int/power mod base); -- a string starting + power := power * base; -- with the right hand + end loop ; -- side. + + -- return result and add sign if required + if int < 0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; + + end str; + + + -- convert integer to string, using base 10 + function str(int: integer) return string is + + begin + + return str(int, 10) ; + + end str; + + + + -- converts a std_logic_vector into a hex string. + function hstr(slv: std_logic_vector) return string is + variable hexlen: integer; + variable longslv : std_logic_vector(67 downto 0) := (others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen := (slv'left+1)/4; + if (slv'left+1) mod 4 /= 0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen -1) downto 0 loop + fourbit := longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen -I) := '0'; + when "0001" => hex(hexlen -I) := '1'; + when "0010" => hex(hexlen -I) := '2'; + when "0011" => hex(hexlen -I) := '3'; + when "0100" => hex(hexlen -I) := '4'; + when "0101" => hex(hexlen -I) := '5'; + when "0110" => hex(hexlen -I) := '6'; + when "0111" => hex(hexlen -I) := '7'; + when "1000" => hex(hexlen -I) := '8'; + when "1001" => hex(hexlen -I) := '9'; + when "1010" => hex(hexlen -I) := 'A'; + when "1011" => hex(hexlen -I) := 'B'; + when "1100" => hex(hexlen -I) := 'C'; + when "1101" => hex(hexlen -I) := 'D'; + when "1110" => hex(hexlen -I) := 'E'; + when "1111" => hex(hexlen -I) := 'F'; + when "ZZZZ" => hex(hexlen -I) := 'z'; + when "UUUU" => hex(hexlen -I) := 'u'; + when "XXXX" => hex(hexlen -I) := 'x'; + when others => hex(hexlen -I) := '?'; + end case; + end loop; + return hex(1 to hexlen); + end hstr; + + + + -- functions to manipulate strings + ----------------------------------- + + + -- convert a character to upper case + + function to_upper(c: character) return character is + + variable u: character; + + begin + + case c is + when 'a' => u := 'A'; + when 'b' => u := 'B'; + when 'c' => u := 'C'; + when 'd' => u := 'D'; + when 'e' => u := 'E'; + when 'f' => u := 'F'; + when 'g' => u := 'G'; + when 'h' => u := 'H'; + when 'i' => u := 'I'; + when 'j' => u := 'J'; + when 'k' => u := 'K'; + when 'l' => u := 'L'; + when 'm' => u := 'M'; + when 'n' => u := 'N'; + when 'o' => u := 'O'; + when 'p' => u := 'P'; + when 'q' => u := 'Q'; + when 'r' => u := 'R'; + when 's' => u := 'S'; + when 't' => u := 'T'; + when 'u' => u := 'U'; + when 'v' => u := 'V'; + when 'w' => u := 'W'; + when 'x' => u := 'X'; + when 'y' => u := 'Y'; + when 'z' => u := 'Z'; + when others => u := c; + end case; + + return u; + + end to_upper; + + + -- convert a character to lower case + + function to_lower(c: character) return character is + + variable l: character; + + begin + + case c is + when 'A' => l := 'a'; + when 'B' => l := 'b'; + when 'C' => l := 'c'; + when 'D' => l := 'd'; + when 'E' => l := 'e'; + when 'F' => l := 'f'; + when 'G' => l := 'g'; + when 'H' => l := 'h'; + when 'I' => l := 'i'; + when 'J' => l := 'j'; + when 'K' => l := 'k'; + when 'L' => l := 'l'; + when 'M' => l := 'm'; + when 'N' => l := 'n'; + when 'O' => l := 'o'; + when 'P' => l := 'p'; + when 'Q' => l := 'q'; + when 'R' => l := 'r'; + when 'S' => l := 's'; + when 'T' => l := 't'; + when 'U' => l := 'u'; + when 'V' => l := 'v'; + when 'W' => l := 'w'; + when 'X' => l := 'x'; + when 'Y' => l := 'y'; + when 'Z' => l := 'z'; + when others => l := c; + end case; + + return l; + + end to_lower; + + + + -- convert a string to upper case + + function to_upper(s: string) return string is + + variable uppercase: string (s'range); + + begin + + for i in s'range loop + uppercase(i):= to_upper(s(i)); + end loop; + return uppercase; + + end to_upper; + + + + -- convert a string to lower case + + function to_lower(s: string) return string is + + variable lowercase: string (s'range); + + begin + + for i in s'range loop + lowercase(i):= to_lower(s(i)); + end loop; + return lowercase; + + end to_lower; + + + +-- functions to convert strings into other types + + +-- converts a character into a std_logic + +function to_std_logic(c: character) return std_logic is + variable sl: std_logic; + begin + case c is + when 'U' => + sl := 'U'; + when 'X' => + sl := 'X'; + when '0' => + sl := '0'; + when '1' => + sl := '1'; + when 'Z' => + sl := 'Z'; + when 'W' => + sl := 'W'; + when 'L' => + sl := 'L'; + when 'H' => + sl := 'H'; + when '-' => + sl := '-'; + when others => + sl := 'X'; + end case; + return sl; + end to_std_logic; + + +-- converts a string into std_logic_vector + +function to_std_logic_vector(s: string) return std_logic_vector is + variable slv: std_logic_vector(s'high-s'low downto 0); + variable k: integer; +begin + k := s'high-s'low; + for i in s'range loop + slv(k) := to_std_logic(s(i)); + k := k - 1; + end loop; + return slv; +end to_std_logic_vector; + + + + + + +---------------- +-- file I/O -- +---------------- + + + +-- read variable length string from input file + +procedure str_read(file in_file: TEXT; + res_string: out string) is + + variable l: line; + variable c: character; + variable is_string: boolean; + + begin + + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i) := ' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + read(l, c, is_string); + res_string(i) := c; + if not is_string then -- found end of line + exit; + end if; + end loop; + +end str_read; + + +-- print string to a file +procedure print(file out_file: TEXT; + new_string: in string) is + + variable l: line; + + begin + + write(l, new_string); + writeline(out_file, l); + +end print; + + +-- print character to a file and start new line +procedure print(file out_file: TEXT; + char: in character) is + + variable l: line; + + begin + + write(l, char); + writeline(out_file, l); + +end print; + + + +-- appends contents of a string to a file until line feed occurs +-- (LF is considered to be the end of the string) + +procedure str_write(file out_file: TEXT; + new_string: in string) is + begin + + for i in new_string'range loop + print(out_file, new_string(i)); + if new_string(i) = LF then -- end of string + exit; + end if; + end loop; + +end str_write; + + + + +end txt_util; + + + + Index: Decode/bench/vhdl =================================================================== --- Decode/bench/vhdl (nonexistent) +++ Decode/bench/vhdl (revision 4)

Decode/bench/vhdl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Decode/bench =================================================================== --- Decode/bench (nonexistent) +++ Decode/bench (revision 4)

Decode/bench Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Decode/rtl/vhdl/slayer.vhd =================================================================== --- Decode/rtl/vhdl/slayer.vhd (nonexistent) +++ Decode/rtl/vhdl/slayer.vhd (revision 4) @@ -0,0 +1,81 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Substitution layer of Present cipher. Simple logic. ---- +---- For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity slayer is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); +end slayer; + +architecture Behavioral of slayer is + + begin + output <= x"C" when input = x"0" else + x"5" when input = x"1" else + x"6" when input = x"2" else + x"B" when input = x"3" else + x"9" when input = x"4" else + x"0" when input = x"5" else + x"A" when input = x"6" else + x"D" when input = x"7" else + x"3" when input = x"8" else + x"E" when input = x"9" else + x"F" when input = x"A" else + x"8" when input = x"B" else + x"4" when input = x"C" else + x"7" when input = x"D" else + x"1" when input = x"E" else + x"2" when input = x"F" else + "ZZZZ"; + end Behavioral; \ No newline at end of file Index: Decode/rtl/vhdl/keyupd.vhd =================================================================== --- Decode/rtl/vhdl/keyupd.vhd (nonexistent) +++ Decode/rtl/vhdl/keyupd.vhd (revision 4) @@ -0,0 +1,86 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Key update module for present cipher it is 'signal ---- +---- mixing' made by rotation left by 61 bits, using one s-box, ---- +---- and output of the counter. For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity keyupd is + generic( + w_80: integer := 80; + w_5 : integer := 5; + w_4 : integer := 4); + port( + key : in std_logic_vector(w_80-1 downto 0); + num : in std_logic_vector(w_5-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); +end keyupd; + +architecture Behavioral of keyupd is + + component slayer is + generic(w_4: integer := 4); + port( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + signal changed : std_logic_vector(w_4-1 downto 0); + signal changin : std_logic_vector(w_4-1 downto 0); + signal keytemp : std_logic_vector(w_80-1 downto 0); + + begin + s1: slayer port map(input => changin, output => changed); + changin <= keytemp(79 downto 76); + keytemp <= key(18 downto 0) & key(79 downto 19); + keyout(79 downto 76)<= changed; + keyout(75 downto 20) <= keytemp(75 downto 20); + keyout(19 downto 15)<= keytemp(19 downto 15) xor num; + keyout(14 downto 0) <= keytemp(14 downto 0); + end Behavioral; \ No newline at end of file Index: Decode/rtl/vhdl/PresentStateMachine.vhd =================================================================== --- Decode/rtl/vhdl/PresentStateMachine.vhd (nonexistent) +++ Decode/rtl/vhdl/PresentStateMachine.vhd (revision 4) @@ -0,0 +1,130 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- State machine for Present encoder. For more informations ---- +---- see below. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.kody.ALL; + +entity PresentStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); +end PresentStateMachine; + +architecture Behavioral of PresentStateMachine is + + signal state : stany; + signal next_state : stany; + + begin + States : process(state, start, num) + begin + case state is + ---- Waiting for start + when NOP => + ready <= '0'; + cnt_res <= '0'; + ctrl_mux <= '0'; + RegEn <= '0'; + if (start = '1') then + next_state <= SM_START; + else + next_state <= NOP; + end if; + -- Decoding + when SM_START => + ready <= '0'; + RegEn <= '1'; + cnt_res <= '1'; + if (start = '1') then + -- control during first start + if (num = "00000") then + ctrl_mux <= '0'; + next_state <= SM_START; + -- last iteration + elsif (num = "11111") then + ctrl_mux <= '1'; + next_state <= SM_READY; + -- rest iterations + else + ctrl_mux <= '1'; + next_state <= SM_START; + end if; + else + ctrl_mux <= '0'; + next_state <= NOP; + end if; + -- Decoding end + when SM_READY => + cnt_res <= '0'; + RegEn <= '0'; + ready <= '1'; + if (start = '1') then + ctrl_mux <= '1'; + next_state <= SM_READY; + else + ctrl_mux <= '0'; + next_state <= NOP; + end if; + end case; + end process States; + + SM : process (clk, reset) + begin + if (reset = '1') then + state <= NOP; + elsif (clk'Event and clk = '1') then + state <= next_state; + end if; + end process SM; + + end Behavioral; + Index: Decode/rtl/vhdl/kody.vhd =================================================================== --- Decode/rtl/vhdl/kody.vhd (nonexistent) +++ Decode/rtl/vhdl/kody.vhd (revision 4) @@ -0,0 +1,56 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- This file contains types and constant used by this ---- +---- implementation of Present project ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +package kody is + -- type for PresentStateMachine to control the datapath & circuit -- + type stany is (NOP, SM_START, SM_READY); + type decode_states is (NOP, KG_START, DEC_START, DEC_READY); +end kody; \ No newline at end of file Index: Decode/rtl/vhdl/AsyncMux.vhd =================================================================== --- Decode/rtl/vhdl/AsyncMux.vhd (nonexistent) +++ Decode/rtl/vhdl/AsyncMux.vhd (revision 4) @@ -0,0 +1,73 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Simple construction of multiplexer. Nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity AsyncMux is + generic ( + width : integer := 64 + ); + port ( + input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); + input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(width - 1 downto 0) + ); +end AsyncMux; + +architecture Behavioral of AsyncMux is + +begin + output <= input0 when (ctrl = '0') else + input1; +end Behavioral; + Index: Decode/rtl/vhdl/pLayer_inv.vhd =================================================================== --- Decode/rtl/vhdl/pLayer_inv.vhd (nonexistent) +++ Decode/rtl/vhdl/pLayer_inv.vhd (revision 4) @@ -0,0 +1,125 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Permutation layer of Present decoder. Simple signal ---- +---- mixing, but in inverse way as cipher. For more information see---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity pLayer_inv is + generic(w_64 : integer := 64); + port ( + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_64-1 downto 0) + ); +end pLayer_inv; + +architecture Behavioral of pLayer_inv is +begin + output(0) <= input(0); + output(1) <= input(16); + output(2) <= input(32); + output(3) <= input(48); + output(4) <= input(1); + output(5) <= input(17); + output(6) <= input(33); + output(7) <= input(49); + output(8) <= input(2); + output(9) <= input(18); + output(10) <= input(34); + output(11) <= input(50); + output(12) <= input(3); + output(13) <= input(19); + output(14) <= input(35); + output(15) <= input(51); + output(16) <= input(4); + output(17) <= input(20); + output(18) <= input(36); + output(19) <= input(52); + output(20) <= input(5); + output(21) <= input(21); + output(22) <= input(37); + output(23) <= input(53); + output(24) <= input(6); + output(25) <= input(22); + output(26) <= input(38); + output(27) <= input(54); + output(28) <= input(7); + output(29) <= input(23); + output(30) <= input(39); + output(31) <= input(55); + output(32) <= input(8); + output(33) <= input(24); + output(34) <= input(40); + output(35) <= input(56); + output(36) <= input(9); + output(37) <= input(25); + output(38) <= input(41); + output(39) <= input(57); + output(40) <= input(10); + output(41) <= input(26); + output(42) <= input(42); + output(43) <= input(58); + output(44) <= input(11); + output(45) <= input(27); + output(46) <= input(43); + output(47) <= input(59); + output(48) <= input(12); + output(49) <= input(28); + output(50) <= input(44); + output(51) <= input(60); + output(52) <= input(13); + output(53) <= input(29); + output(54) <= input(45); + output(55) <= input(61); + output(56) <= input(14); + output(57) <= input(30); + output(58) <= input(46); + output(59) <= input(62); + output(60) <= input(15); + output(61) <= input(31); + output(62) <= input(47); + output(63) <= input(63); +end Behavioral; \ No newline at end of file Index: Decode/rtl/vhdl/PresentEncKeyGen.vhd =================================================================== --- Decode/rtl/vhdl/PresentEncKeyGen.vhd (nonexistent) +++ Decode/rtl/vhdl/PresentEncKeyGen.vhd (revision 4) @@ -0,0 +1,170 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Key generator of Present encoder. It is only those part ---- +---- which is needed for key and cipher decoding by Present ---- +---- decoder. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity PresentEncKeyGen is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_80: integer := 80 + ); + port( + key : in std_logic_vector(w_80 - 1 downto 0); + key_end : out std_logic_vector(w_80 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end PresentEncKeyGen; + +architecture Behavioral of PresentEncKeyGen is + + component Reg is + generic(width : integer := w_80); + port( + input : in STD_LOGIC_VECTOR(width - 1 downto 0); + output : out STD_LOGIC_VECTOR(width - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); + end component Reg; + + component AsyncMux is + generic ( + width : integer := 80 + ); + port ( + input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); + input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(width - 1 downto 0) + ); + end component AsyncMux; + + component PresentStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); + end component; + + component keyupd is + generic( + w_5 : integer := 5; + w_80: integer := 80 + ); + port( + num : in std_logic_vector(w_5-1 downto 0); + key : in std_logic_vector(w_80-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); + end component; + + component counter is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); + end component; + + -- signals + + signal keynum : std_logic_vector (w_5-1 downto 0); + signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0); + signal ready_sig, mux_ctrl, cnt_res, RegEn : std_logic; + + begin + + -- connections + + mux_80: AsyncMux generic map(width => w_80) port map( + input0 => key, + input1 => kupd, + ctrl => mux_ctrl, + output => keyToReg + ); + regKey : Reg generic map(width => w_80) port map( + input => keyToReg, + output => keyfout, + enable => RegEn, + clk => clk, + reset => reset + ); + mixer: keyupd port map( + key => keyfout, + num => keynum, + keyout => kupd + ); + SM: PresentStateMachine port map( + start => start, + reset => reset, + ready => ready_sig, + cnt_res => cnt_res, + ctrl_mux => mux_ctrl, + clk => clk, + num => keynum, + RegEn => RegEn + ); + count: counter port map( + clk => clk, + reset => reset, + cnt_res => cnt_res, + num => keynum + ); + key_end <= keyfout; + ready <= ready_sig; +end Behavioral; Index: Decode/rtl/vhdl/slayer_inv.vhd =================================================================== --- Decode/rtl/vhdl/slayer_inv.vhd (nonexistent) +++ Decode/rtl/vhdl/slayer_inv.vhd (revision 4) @@ -0,0 +1,81 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Inverse substitution layer of Present decoder. Simple ---- +---- logic. For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity slayer_inv is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); +end slayer_inv; + +architecture Behavioral of slayer_inv is + + begin + output <= x"0" when input = x"C" else + x"1" when input = x"5" else + x"2" when input = x"6" else + x"3" when input = x"B" else + x"4" when input = x"9" else + x"5" when input = x"0" else + x"6" when input = x"A" else + x"7" when input = x"D" else + x"8" when input = x"3" else + x"9" when input = x"E" else + x"A" when input = x"F" else + x"B" when input = x"8" else + x"C" when input = x"4" else + x"D" when input = x"7" else + x"E" when input = x"1" else + x"F" when input = x"2" else + "ZZZZ"; + end Behavioral; \ No newline at end of file Index: Decode/rtl/vhdl/Reg.vhd =================================================================== --- Decode/rtl/vhdl/Reg.vhd (nonexistent) +++ Decode/rtl/vhdl/Reg.vhd (revision 4) @@ -0,0 +1,83 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Register - nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Reg is + generic(width : integer := 64); + port( + input : in STD_LOGIC_VECTOR(width - 1 downto 0); + output : out STD_LOGIC_VECTOR(width - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); +end Reg; + +architecture Behavioral of Reg is + +signal reg : STD_LOGIC_VECTOR(width - 1 downto 0); + +begin + clock : process(clk, reset) + begin + if (reset = '1') then + reg <= (others => '0'); + elsif (clk = '1' and clk'Event) then + if (enable = '1') then + reg <= input; + end if; + end if; + end process clock; + output <= reg; +end Behavioral; + Index: Decode/rtl/vhdl/keyupd_inv.vhd =================================================================== --- Decode/rtl/vhdl/keyupd_inv.vhd (nonexistent) +++ Decode/rtl/vhdl/keyupd_inv.vhd (revision 4) @@ -0,0 +1,88 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Inverse Key update module for present cipher decoding ---- +---- it is 'signal mixing' made by rotation right by 61 bits, ---- +---- using one s-box, and output of the counter. Note, that order ---- +---- of this operatins must be inverse in comparison with key_upd. ---- +---- For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity keyupd_inv is + generic( + w_80: integer := 80; + w_5 : integer := 5; + w_4 : integer := 4); + port( + key : in std_logic_vector(w_80-1 downto 0); + num : in std_logic_vector(w_5-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); +end keyupd_inv; + +architecture Behavioral of keyupd_inv is + + component slayer_inv is + generic(w_4: integer := 4); + port( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + signal changed : std_logic_vector(w_4-1 downto 0); + signal changin : std_logic_vector(w_4-1 downto 0); + signal keytemp : std_logic_vector(w_80-1 downto 0); + + begin + s1: slayer_inv port map(input => changin, output => changed); + changin <= key(79 downto 76); + keytemp(79 downto 76)<= changed; + keytemp(75 downto 20) <= key(75 downto 20); + keytemp(19 downto 15)<= key(19 downto 15) xor num; + keytemp(14 downto 0) <= key(14 downto 0); + keyout <= keytemp(60 downto 0) & keytemp(79 downto 61); + end Behavioral; \ No newline at end of file Index: Decode/rtl/vhdl/counter.vhd =================================================================== --- Decode/rtl/vhdl/counter.vhd (nonexistent) +++ Decode/rtl/vhdl/counter.vhd (revision 4) @@ -0,0 +1,73 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Typical construction of 5bit counter. It is counting up. ---- +---- Nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity counter is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); +end counter; + +architecture Behavioral of counter is + signal cnt : std_logic_vector(w_5-1 downto 0) := (others => '0'); + begin + licznik : process (clk, reset, cnt) + begin + if (reset = '1') then + cnt <= (others => '0'); + elsif (clk'Event and clk = '1') then + if (cnt_res = '1') then + cnt <= cnt + 1; + end if; + end if; + end process licznik; + num <= cnt; + end Behavioral; + Index: Decode/rtl/vhdl/PresentDecStateMachine.vhd =================================================================== --- Decode/rtl/vhdl/PresentDecStateMachine.vhd (nonexistent) +++ Decode/rtl/vhdl/PresentDecStateMachine.vhd (revision 4) @@ -0,0 +1,135 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- State machine for Present decoder. It is only part of ---- +---- "inverse Present", not key gen. For more informations see ---- +---- below. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.kody.ALL; + +entity PresentDecStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); +end PresentDecStateMachine; + +architecture Behavioral of PresentDecStateMachine is + + signal state : stany; + signal next_state : stany; + + begin + States : process(state, start, num) + begin + case state is + ---- Waiting for start + when NOP => + ready <= '0'; + cnt_res <= '0'; + ctrl_mux <= '0'; + if (start = '1') then + RegEn <= '1'; + next_state <= SM_START; + else + RegEn <= '0'; + next_state <= NOP; + end if; + -- Decoding + when SM_START => + ready <= '0'; + cnt_res <= '1'; + if (start = '1') then + -- control during first start + if (num = "11111") then + RegEn <= '1'; + ctrl_mux <= '1'; + next_state <= SM_START; + -- last iteration + elsif (num = "00000") then + RegEn <= '0'; + ctrl_mux <= '1'; + next_state <= SM_READY; + -- rest iterations + else + RegEn <= '1'; + ctrl_mux <= '1'; + next_state <= SM_START; + end if; + else + RegEn <= '0'; + ctrl_mux <= '0'; + next_state <= NOP; + end if; + -- Decoding end + when SM_READY => + cnt_res <= '0'; + RegEn <= '0'; + ready <= '1'; + if (start = '1') then + ctrl_mux <= '1'; + next_state <= SM_READY; + else + ctrl_mux <= '0'; + next_state <= NOP; + end if; + end case; + end process States; + + SM : process (clk, reset) + begin + if (reset = '1') then + state <= NOP; + elsif (clk'Event and clk = '1') then + state <= next_state; + end if; + end process SM; + + end Behavioral; + Index: Decode/rtl/vhdl/FullDecoderSM.vhd =================================================================== --- Decode/rtl/vhdl/FullDecoderSM.vhd (nonexistent) +++ Decode/rtl/vhdl/FullDecoderSM.vhd (revision 4) @@ -0,0 +1,134 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- State machine for Present decoder. It controls entire ---- +---- environment for decoding. We can feature 2 'steady states' ---- +---- and 2 'running states'. For more informations see below ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.kody.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FullDecoderSM is + port( + key_gen_start : out std_logic; + key_gen_ready : in std_logic; + decode_start : out std_logic; + decode_ready : in std_logic; + full_decoder_start :in std_logic; + full_decoder_ready : out std_logic; + clk, reset :in std_logic + ); +end FullDecoderSM; + +architecture Behavioral of FullDecoderSM is + + signal state : decode_states; + signal next_state : decode_states; + +begin + + states : process(state, full_decoder_start, key_gen_ready, decode_ready) + begin + case state is + ---- It is No operation - waiting for proper data in the input ---- + when NOP => + key_gen_start <= '0'; + decode_start <= '0'; + full_decoder_ready <= '0'; + if (full_decoder_start = '1') then + next_state <= KG_START; + else + next_state <= NOP; + end if; + ---- It is running key generator for decoding + when KG_START => + key_gen_start <= '1'; + decode_start <= '0'; + full_decoder_ready <= '0'; + if (key_gen_ready = '1') then + next_state <= DEC_START; + else + next_state <= KG_START; + end if; + ---- enerated key for decoding is ready. Now we are decoding ---- + when DEC_START => + key_gen_start <= '1'; + decode_start <= '1'; + full_decoder_ready <= '0'; + if (decode_ready = '1') then + next_state <= DEC_READY; + else + next_state <= DEC_START; + end if; + ---- Decoding was ended. Waiting for user retrieving data ---- + ---- and give information about new operation ---- + when DEC_READY => + key_gen_start <= '1'; + decode_start <= '1'; + full_decoder_ready <= '1'; + if (full_decoder_start = '1') then + next_state <= DEC_READY; + else + next_state <= NOP; + end if; + end case; + end process states; + + SM : process (clk, reset) + begin + if (reset = '1') then + state <= NOP; + elsif (clk'Event and clk = '1') then + state <= next_state; + end if; + end process SM; + +end Behavioral; + Index: Decode/rtl/vhdl/PresentFullDecoder.vhd =================================================================== --- Decode/rtl/vhdl/PresentFullDecoder.vhd (nonexistent) +++ Decode/rtl/vhdl/PresentFullDecoder.vhd (revision 4) @@ -0,0 +1,170 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Present decoder with suitable key generator for decoding ---- +---- (basing on given encode key). ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity PresentFullDecoder is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port( + ciphertext : in std_logic_vector(w_64 - 1 downto 0); + key : in std_logic_vector(w_80 - 1 downto 0); + plaintext : out std_logic_vector(w_64 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end PresentFullDecoder; + +architecture Behavioral of PresentFullDecoder is + +-- Key generator component +component PresentEncKeyGen is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_80: integer := 80 + ); + port( + key : in std_logic_vector(w_80 - 1 downto 0); + key_end : out std_logic_vector(w_80 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end component PresentEncKeyGen; + +-- 'pure' Present decoder +component PresentDec is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port( + plaintext : in std_logic_vector(w_64 - 1 downto 0); + key : in std_logic_vector(w_80 - 1 downto 0); + ciphertext : out std_logic_vector(w_64 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end component PresentDec; + +component FullDecoderSM is + port( + key_gen_start : out std_logic; + key_gen_ready : in std_logic; + decode_start : out std_logic; + decode_ready : in std_logic; + full_decoder_start :in std_logic; + full_decoder_ready : out std_logic; + clk, reset :in std_logic + ); +end component FullDecoderSM; + +-- signals + +signal key_gen_output : std_logic_vector(w_80 - 1 downto 0); + +signal key_gen_start : std_logic; +signal key_gen_ready : std_logic; + +signal decode_start : std_logic; +signal decode_ready : std_logic; + +begin + + -- connections + + keyGen : PresentEncKeyGen + port map( + key => key, + key_end => key_gen_output, + start => key_gen_start, + clk => clk, + reset => reset, + ready => key_gen_ready + ); + + decoder : PresentDec + port map( + plaintext => ciphertext, + key => key_gen_output, + ciphertext => plaintext, + start => decode_start, + clk => clk, + reset => reset, + ready => decode_ready + ); + + SM : FullDecoderSM + port map( + key_gen_start => key_gen_start, + key_gen_ready => key_gen_ready, + decode_start => decode_start, + decode_ready => decode_ready, + full_decoder_start => start, + full_decoder_ready => ready, + clk => clk, + reset => reset + ); + +end Behavioral; Index: Decode/rtl/vhdl/counter_inv.vhd =================================================================== --- Decode/rtl/vhdl/counter_inv.vhd (nonexistent) +++ Decode/rtl/vhdl/counter_inv.vhd (revision 4) @@ -0,0 +1,73 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Typical construction of 5bit counter. It is counting ---- +---- down. Nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity counter_inv is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); +end counter_inv; + +architecture Behavioral of counter_inv is + signal cnt : std_logic_vector(w_5-1 downto 0) := (others => '0'); + begin + licznik : process (clk, reset, cnt) + begin + if (reset = '1') then + cnt <= (others => '1'); + elsif (clk'Event and clk = '1') then + if (cnt_res = '1') then + cnt <= cnt - 1; + end if; + end if; + end process licznik; + num <= cnt; + end Behavioral; + Index: Decode/rtl/vhdl/PresentDec.vhd =================================================================== --- Decode/rtl/vhdl/PresentDec.vhd (nonexistent) +++ Decode/rtl/vhdl/PresentDec.vhd (revision 4) @@ -0,0 +1,220 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Top level of present decoder. It contains 'Key generator' ---- +---- from encoder and 'inverse Present' for decoding the cipher. ---- +---- For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity PresentDec is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port( + plaintext : in std_logic_vector(w_64 - 1 downto 0); + key : in std_logic_vector(w_80 - 1 downto 0); + ciphertext : out std_logic_vector(w_64 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end PresentDec; + +architecture Behavioral of PresentDec is + + component Reg is + generic(width : integer := w_64); + port( + input : in STD_LOGIC_VECTOR(width - 1 downto 0); + output : out STD_LOGIC_VECTOR(width - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); + end component Reg; + + component AsyncMux is + generic ( + width : integer := 64 + ); + port ( + input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); + input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(width - 1 downto 0) + ); + end component AsyncMux; + + component PresentDecStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); + end component; + + -- INVERSE substitution layer for decoding + component slayer_inv is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + -- INVERSE permutation layer for decoding + component pLayer_inv is + generic(w_64 : integer := 64); + port( + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_64-1 downto 0) + ); + end component; + + -- INVERSE key update for decoding + component keyupd_inv is + generic( + w_5 : integer := 5; + w_80: integer := 80 + ); + port( + num : in std_logic_vector(w_5-1 downto 0); + key : in std_logic_vector(w_80-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); + end component; + + -- INVERSE counter for decoding. It is counting down!!! + component counter_inv is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); + end component; + + -- signals + signal keynum : std_logic_vector (w_5-1 downto 0); + signal toXor, ciph, P, Pout, textToReg : std_logic_vector (w_64-1 downto 0); + signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0); + signal ready_sig, mux_ctrl, cnt_res, RegEn : std_logic; + + begin + + -- connections + mux_64: AsyncMux generic map(width => w_64) port map( + input0 => plaintext, + input1 => Pout, + ctrl => mux_ctrl, + output => textToReg + ); + regText : Reg generic map(width => w_64) port map( + input => textToReg, + output => toXor, + enable => RegEn, + clk => clk, + reset => reset + ); + mux_80: AsyncMux generic map(width => w_80) port map( + input0 => key, + input1 => kupd, + ctrl => mux_ctrl, + output => keyToReg + ); + regKey : Reg generic map(width => w_80) port map( + input => keyToReg, + output => keyfout, + enable => RegEn, + clk => clk, + reset => reset + ); + slayers_inv : for N in 15 downto 0 generate + s_x: slayer_inv port map( + input => P(4*N+3 downto 4*N), + output => Pout(4*N+3 downto 4*N) + ); + end generate slayers_inv; + p1: pLayer_inv port map( + input => ciph, + output => P + ); + mixer: keyupd_inv port map( + key => keyfout, + num => keynum, + keyout => kupd + ); + SM: PresentDecStateMachine port map( + start => start, + reset => reset, + ready => ready_sig, + cnt_res => cnt_res, + ctrl_mux => mux_ctrl, + clk => clk, + num => keynum, + RegEn => RegEn + ); + count: counter_inv port map( + clk => clk, + reset => reset, + cnt_res => cnt_res, + num => keynum + ); + ciph <= toXor xor keyfout(79 downto 16); + ciphertext <= ciph; + ready <= ready_sig; +end Behavioral; Index: Decode/rtl/vhdl =================================================================== --- Decode/rtl/vhdl (nonexistent) +++ Decode/rtl/vhdl (revision 4)

Decode/rtl/vhdl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Decode/rtl =================================================================== --- Decode/rtl (nonexistent) +++ Decode/rtl (revision 4)

Decode/rtl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Decode/doc/src =================================================================== --- Decode/doc/src (nonexistent) +++ Decode/doc/src (revision 4)

Decode/doc/src Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Decode/doc =================================================================== --- Decode/doc (nonexistent) +++ Decode/doc (revision 4)

Decode/doc Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Decode/sim =================================================================== --- Decode/sim (nonexistent) +++ Decode/sim (revision 4)

Decode/sim Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Decode/sw =================================================================== --- Decode/sw (nonexistent) +++ Decode/sw (revision 4)

Decode/sw Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Decode/syn/XC3ES500 =================================================================== --- Decode/syn/XC3ES500 (nonexistent) +++ Decode/syn/XC3ES500 (revision 4)

Decode/syn/XC3ES500 Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Decode/syn =================================================================== --- Decode/syn (nonexistent) +++ Decode/syn (revision 4)

Decode/syn Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: PureTesting/PresentTB.vhd =================================================================== --- PureTesting/PresentTB.vhd (revision 3) +++ PureTesting/PresentTB.vhd (nonexistent) @@ -1,133 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 22:21:14 06/25/2013 --- Design Name: --- Module Name: E:/spent i praca/OpenCores/present_opencores/trunk/Pure/PresentTB.vhd --- Project Name: Present_Pure --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: PresentEnc --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---USE ieee.numeric_std.ALL; - -ENTITY PresentTB IS -END PresentTB; - -ARCHITECTURE behavior OF PresentTB IS - - -- Component Declaration for the Unit Under Test (UUT) - - COMPONENT PresentEnc - PORT( - plaintext : IN std_logic_vector(63 downto 0); - key : IN std_logic_vector(79 downto 0); - ciphertext : OUT std_logic_vector(63 downto 0); - start : IN std_logic; - clk : IN std_logic; - reset : IN std_logic; - ready : OUT std_logic - ); - END COMPONENT; - - - --Inputs - signal plaintext : std_logic_vector(63 downto 0) := (others => '0'); - signal key : std_logic_vector(79 downto 0) := (others => '0'); - signal start : std_logic := '0'; - signal clk : std_logic := '0'; - signal reset : std_logic := '0'; - - --Outputs - signal ciphertext : std_logic_vector(63 downto 0); - signal ready : std_logic; - - -- Clock period definitions - constant clk_period : time := 10 ns; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: PresentEnc PORT MAP ( - plaintext => plaintext, - key => key, - ciphertext => ciphertext, - start => start, - clk => clk, - reset => reset, - ready => ready - ); - - -- Clock process definitions - clk_process :process - begin - clk <= '0'; - wait for clk_period/2; - clk <= '1'; - wait for clk_period/2; - end process; - - - -- Stimulus process - stim_proc: process - begin - - reset <= '1'; - start <= '0'; - wait for 100 ns; - reset <= '0'; - - plaintext <= (others => '0'); - key <= (others => '0'); - start <= '1'; - wait for clk_period*40; - start <= '0'; - wait for clk_period; - - plaintext <= (others => '0'); - key <= (others => '1'); - start <= '1'; - wait for clk_period*40; - start <= '0'; - wait for clk_period; - - plaintext <= (others => '1'); - key <= (others => '0'); - start <= '1'; - wait for clk_period*40; - start <= '0'; - wait for clk_period; - - plaintext <= (others => '1'); - key <= (others => '1'); - start <= '1'; - wait for clk_period*40; - start <= '0'; - wait for clk_period; - - assert false severity failure; - - end process; - -END; Index: PureTesting/keyupdTB.vhd =================================================================== --- PureTesting/keyupdTB.vhd (revision 3) +++ PureTesting/keyupdTB.vhd (nonexistent) @@ -1,106 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:00:18 05/16/2010 --- Design Name: --- Module Name: C:/Users/gajos/Desktop/Polibuda/vhdl/projekt/szyfrator/keyupdTB.vhd --- Project Name: szyfrator --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: keyupd --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.all; -USE ieee.numeric_std.ALL; - -ENTITY keyupdTB IS -END keyupdTB; - -ARCHITECTURE behavior OF keyupdTB IS - - -- Component Declaration for the Unit Under Test (UUT) - - COMPONENT keyupd - PORT( - key : IN std_logic_vector(79 downto 0); - num : IN std_logic_vector(4 downto 0); - keyout : OUT std_logic_vector(79 downto 0)--; - --clk, reset : std_logic - ); - END COMPONENT; - - - --Inputs - signal key : std_logic_vector(79 downto 0) := (others => '0'); - signal num : std_logic_vector(4 downto 0) := (others => '0'); - signal clk : std_logic := '0'; - signal reset : std_logic := '0'; - - --Outputs - signal keyout : std_logic_vector(79 downto 0); - - constant clk_period : time := 1ns; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: keyupd PORT MAP ( - key => key, - num => num, - keyout => keyout--, - --clk => clk, - --reset => reset - ); - - -- No clocks detected in port list. Replace clk below with - -- appropriate port name - - clk_process :process - begin - clk <= '0'; - wait for clk_period/2; - clk <= '1'; - wait for clk_period/2; - end process; - - - -- Stimulus process - stim_proc: process - begin - -- hold reset state for 100ms. - reset <= '1'; - wait for 100ns; - reset <='0'; - wait for clk_period; - key <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - num <= "00001"; - wait for clk_period; - key <= x"c0000000000000008000"; - num <= "00010"; - wait for clk_period; - key <= x"50001800000000010000"; - num <= "00011"; - wait for clk_period; - key <= x"8ba27a0eb8783ac96d59"; - num <= "11111"; - wait for clk_period; - assert false severity failure; - end process; -END; \ No newline at end of file Index: PureTesting/ShiftRegTB.vhd =================================================================== --- PureTesting/ShiftRegTB.vhd (revision 3) +++ PureTesting/ShiftRegTB.vhd (nonexistent) @@ -1,119 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 22:11:18 10/08/2012 --- Design Name: --- Module Name: E:/spent i praca/OpenCores/mRSAKeyFinalizer/ShiftRegTB.vhd --- Project Name: mRSAKeyFinalizer --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: ShiftReg --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -use work.RSAFinalizerProperties.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---USE ieee.numeric_std.ALL; - -ENTITY ShiftRegTB IS -END ShiftRegTB; - -ARCHITECTURE behavior OF ShiftRegTB IS - - -- Component Declaration for the Unit Under Test (UUT) - - COMPONENT ShiftReg --- generic (length_1 : integer := WORD_LENGTH; --- length_2 : integer := BYTE - GENERIC ( - length_1 : integer := BYTE; - length_2 : integer := WORD_LENGTH - ); - PORT( - input : in STD_LOGIC_VECTOR(7 downto 0); - --input : IN std_logic_vector(63 downto 0); - output : out STD_LOGIC_VECTOR(63 downto 0); - --output : OUT std_logic_vector(7 downto 0); - en : in STD_LOGIC; - shift : in STD_LOGIC; - clk : in STD_LOGIC; - reset : in STD_LOGIC - ); - END COMPONENT; - - - --Inputs - signal input : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); - --signal input : std_logic_vector(63 downto 0) := (others => '0'); - signal en : STD_LOGIC := '0'; - signal shift : STD_LOGIC := '0'; - signal clk : STD_LOGIC := '0'; - signal reset : STD_LOGIC := '0'; - - --Outputs - signal output : STD_LOGIC_VECTOR(63 downto 0); - --signal output : std_logic_vector(7 downto 0); - - -- Clock period definitions - constant clk_period : time := 10 ns; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: ShiftReg PORT MAP ( - input => input, - output => output, - en => en, - shift => shift, - clk => clk, - reset => reset - ); - - -- Clock process definitions - clk_process :process - begin - clk <= '0'; - wait for clk_period/2; - clk <= '1'; - wait for clk_period/2; - end process; - - - -- Stimulus process - stim_proc: process - begin - reset <= '0'; - shift <= '0'; - input <= "10101010"; - --input <= "1111000011110000111100001111000011110000111100001111000011110000"; - wait for 100 ns; - reset <= '1'; - wait for clk_period*10; - en <= '1'; - wait for clk_period*1; - en <= '0'; - wait for clk_period*1; - shift <= '1'; - wait for clk_period*10; - assert false severity failure; - end process; - -END; Index: PureTesting/Reg.vhd =================================================================== --- PureTesting/Reg.vhd (revision 3) +++ PureTesting/Reg.vhd (nonexistent) @@ -1,60 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 23:41:41 06/24/2013 --- Design Name: --- Module Name: Reg - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity Reg is - generic(width : integer := 64); - port( - input : in STD_LOGIC_VECTOR(width - 1 downto 0); - output : out STD_LOGIC_VECTOR(width - 1 downto 0); - enable : in STD_LOGIC; - clk : in STD_LOGIC; - reset : in STD_LOGIC - ); -end Reg; - -architecture Behavioral of Reg is - -signal reg : STD_LOGIC_VECTOR(width - 1 downto 0); - -begin - clock : process(clk, reset) - begin - if (reset = '1') then - reg <= (others => '0'); - elsif (clk = '1' and clk'Event) then - if (enable = '1') then - reg <= input; - end if; - end if; - end process clock; - output <= reg; -end Behavioral; - Index: PureTesting/PresentCommTB.vhd =================================================================== --- PureTesting/PresentCommTB.vhd (revision 3) +++ PureTesting/PresentCommTB.vhd (nonexistent) @@ -1,346 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 22:26:35 07/05/2013 --- Design Name: --- Module Name: E:/spent i praca/OpenCores/present_opencores/trunk/Testing/VHDL/PresentCommTB.vhd --- Project Name: PresentComm --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: PresentComm --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE std.textio.all; -USE work.txt_util.all; -USE ieee.std_logic_textio.all; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---USE ieee.numeric_std.ALL; - -ENTITY PresentCommTB IS -END PresentCommTB; - -ARCHITECTURE behavior OF PresentCommTB IS - - -- Component Declaration for the Unit Under Test (UUT) - - COMPONENT PresentComm - PORT( - DATA_RXD : IN std_logic; - CLK : IN std_logic; - RESET : IN std_logic; - DATA_TXD : OUT std_logic - ); - END COMPONENT; - - - --Inputs - signal DATA_RXD : std_logic := '0'; - signal CLK : std_logic := '0'; - signal RESET : std_logic := '0'; - - --Outputs - signal DATA_TXD : std_logic; - - -- Clock period definitions - constant CLK_period : time := 20 ns; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: PresentComm PORT MAP ( - DATA_RXD => DATA_RXD, - CLK => CLK, - RESET => RESET, - DATA_TXD => DATA_TXD - ); - - -- Clock process definitions - CLK_process :process - begin - CLK <= '0'; - wait for CLK_period/2; - CLK <= '1'; - wait for CLK_period/2; - end process; - - - -- Stimulus process - stim_proc: process - - file txt :text is in "test/data.txt"; - file key :text is in "test/key.txt"; - file txt2 :text is in "test/data2.txt"; - file key2 :text is in "test/key2.txt"; - - variable line_in : line; - variable line_content : string(1 to 8); - variable data : STD_LOGIC; - - begin - - DATA_RXD <= '1'; - RESET <= '1'; - wait for 1000 ns; - RESET <= '0'; - - wait for CLK_period*10; - - while not (endfile(txt)) loop - readline(txt, line_in); -- info line - read(line_in, line_content); - report line_content; - - DATA_RXD <= '0'; -- start bit - wait for 8.75 us; - - readline(txt, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(txt, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(txt, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(txt, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(txt, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(txt, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(txt, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(txt, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(txt, line_in); - read(line_in, data); - DATA_RXD <= data; -- parity bit - wait for 8.75 us; - - report "Koniec bajtu"; - DATA_RXD <= '1'; -- stop bit - wait for 100 us; - end loop; - - while not (endfile(key)) loop - readline(key, line_in); -- info line - read(line_in, line_content); - report line_content; - - DATA_RXD <= '0'; -- start bit - wait for 8.75 us; - - readline(key, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(key, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(key, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(key, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(key, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(key, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(key, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(key, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(key, line_in); - read(line_in, data); - DATA_RXD <= data; -- parity bit - wait for 8.75 us; - - report "Koniec bajtu"; - DATA_RXD <= '1'; -- stop bit - wait for 100 us; - end loop; - - wait for 2000 us; - - while not (endfile(txt2)) loop - readline(txt2, line_in); -- info line - read(line_in, line_content); - report line_content; - - DATA_RXD <= '0'; -- start bit - wait for 8.75 us; - - readline(txt2, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(txt2, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(txt2, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(txt2, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(txt2, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(txt2, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(txt2, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(txt2, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(txt2, line_in); - read(line_in, data); - DATA_RXD <= data; -- parity bit - wait for 8.75 us; - - report "Koniec bajtu"; - DATA_RXD <= '1'; -- stop bit - wait for 100 us; - end loop; - - while not (endfile(key2)) loop - readline(key2, line_in); -- info line - read(line_in, line_content); - report line_content; - - DATA_RXD <= '0'; -- start bit - wait for 8.75 us; - - readline(key2, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(key2, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(key2, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(key2, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(key2, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(key2, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(key2, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(key2, line_in); - read(line_in, data); - DATA_RXD <= data; - wait for 8.75 us; - - readline(key2, line_in); - read(line_in, data); - DATA_RXD <= data; -- parity bit - wait for 8.75 us; - - report "Koniec bajtu"; - DATA_RXD <= '1'; -- stop bit - wait for 100 us; - end loop; - - wait for 2000 us; - - assert false severity failure; - end process; - -END; Index: PureTesting/PresentCommImpl.ucf =================================================================== --- PureTesting/PresentCommImpl.ucf (revision 3) +++ PureTesting/PresentCommImpl.ucf (nonexistent) @@ -1,7 +0,0 @@ -NET "DATA_RXD" LOC= "R7" | IOSTANDARD= LVTTL | SLEW= FAST ; -NET "DATA_TXD" LOC= "M14" | IOSTANDARD= LVTTL | DRIVE= 8 | SLEW= FAST ; -NET "CLK" LOC= "C9" | IOSTANDARD= LVCMOS33 | SLEW= FAST ; -NET "CLK" TNM_NET = "clk_group"; -TIMESPEC "TS_CLK" = PERIOD "clk_group" 20 ns HIGH 40%; -NET "RESET" LOC= "K17" | IOSTANDARD= LVTTL | PULLDOWN; -SYSTEM_JITTER = 1 ns; \ No newline at end of file Index: PureTesting/PresentComm.vhd =================================================================== --- PureTesting/PresentComm.vhd (revision 3) +++ PureTesting/PresentComm.vhd (nonexistent) @@ -1,236 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 22:01:00 06/26/2013 --- Design Name: --- Module Name: PresentComm - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity PresentComm is - generic ( - w_2: integer := 2; - w_4: integer := 4; - w_5: integer := 5; - w_64: integer := 64; - w_80: integer := 80 - ); - port ( - DATA_RXD : in STD_LOGIC; - CLK : in STD_LOGIC; - RESET : in STD_LOGIC; - DATA_TXD : out STD_LOGIC - ); -end PresentComm; - -architecture Behavioral of PresentComm is - -component ShiftReg is - generic ( - length_1 : integer := 8; - length_2 : integer := w_64; - internal_data : integer := w_64 - ); - port ( - input : in STD_LOGIC_VECTOR(length_1 - 1 downto 0); - output : out STD_LOGIC_VECTOR(length_2 - 1 downto 0); - en : in STD_LOGIC; - shift : in STD_LOGIC; - clk : in STD_LOGIC; - reset : in STD_LOGIC - ); -end component ShiftReg; - -component Rs232RefComp is - Port ( - TXD : out std_logic := '1'; - RXD : in std_logic; - CLK : in std_logic; --Master Clock - DBIN : in std_logic_vector (7 downto 0); --Data Bus in - DBOUT : out std_logic_vector (7 downto 0); --Data Bus out - RDA : inout std_logic; --Read Data Available - TBE : inout std_logic := '1'; --Transfer Bus Empty - RD : in std_logic; --Read Strobe - WR : in std_logic; --Write Strobe - PE : out std_logic; --Parity Error Flag - FE : out std_logic; --Frame Error Flag - OE : out std_logic; --Overwrite Error Flag - RST : in std_logic := '0'); --Master Reset -end component Rs232RefComp; - -component PresentEnc is - generic ( - w_64: integer := 64; - w_80: integer := 80 - ); - port( - plaintext : in std_logic_vector(w_64 - 1 downto 0); - key : in std_logic_vector(w_80 - 1 downto 0); - ciphertext : out std_logic_vector(w_64 - 1 downto 0); - start, clk, reset : in std_logic; - ready : out std_logic - ); -end component PresentEnc; - -component PresentCommSM is - port ( - clk : in STD_LOGIC; - reset : in STD_LOGIC; - RDAsig : in STD_LOGIC; - TBEsig : in STD_LOGIC; - RDsig : out STD_LOGIC; - WRsig : out STD_LOGIC; - textDataEn : out STD_LOGIC; - textDataShift : out STD_LOGIC; - keyDataEn : out STD_LOGIC; - keyDataShift : out STD_LOGIC; - ciphDataEn : out STD_LOGIC; - ciphDataShift : out STD_LOGIC; - startSig : out STD_LOGIC; - readySig : in STD_LOGIC - ); -end component PresentCommSM; - -signal keyText : STD_LOGIC_VECTOR(w_80 - 1 downto 0); -signal plaintext : STD_LOGIC_VECTOR(w_64 - 1 downto 0); -signal ciphertext : STD_LOGIC_VECTOR(w_64 - 1 downto 0); - -signal dataTXD : STD_LOGIC_VECTOR(7 downto 0); -signal dataRXD : STD_LOGIC_VECTOR(7 downto 0); -signal RDAsig : STD_LOGIC; -signal TBEsig : STD_LOGIC; -signal RDsig : STD_LOGIC; -signal WRsig : STD_LOGIC; -signal PEsig : STD_LOGIC; -signal FEsig : STD_LOGIC; -signal OEsig : STD_LOGIC; - -signal keyDataEn : STD_LOGIC; -signal keyDataShift : STD_LOGIC; - -signal textDataEn : STD_LOGIC; -signal textDataShift : STD_LOGIC; - -signal ciphDataEn : STD_LOGIC; -signal ciphDataShift : STD_LOGIC; - -signal startSig : STD_LOGIC; -signal readySig : STD_LOGIC; - -begin - - RS232 : Rs232RefComp - Port map( - TXD => DATA_TXD, - RXD => DATA_RXD, - CLK => clk, - DBIN => dataTXD, - DBOUT => dataRXD, - RDA => RDAsig, - TBE => TBEsig, - RD => RDsig, - WR => WRsig, - PE => PEsig, - FE => FEsig, - OE => OEsig, - RST => reset - ); - - textReg : ShiftReg - generic map( - length_1 => 8, - length_2 => w_64, - internal_data => w_64 - ) - port map( - input => dataRXD, - output => plaintext, - en => textDataEn, - shift => textDataShift, - clk => clk, - reset => reset - ); - - keyReg : ShiftReg - generic map( - length_1 => 8, - length_2 => w_80, - internal_data => w_80 - ) - port map( - input => dataRXD, - output => keyText, - en => keyDataEn, - shift => keyDataShift, - clk => clk, - reset => reset - ); - - present :PresentEnc - port map( - plaintext => plaintext, - key => keyText, - ciphertext => ciphertext, - start => startSig, - clk => clk, - reset => reset, - ready => readySig - ); - - outReg : ShiftReg - generic map( - length_1 => w_64, - length_2 => 8, - internal_data => w_64 - ) - port map( - input => ciphertext, - output => dataTXD, - en => ciphDataEn, - shift => ciphDataShift, - clk => clk, - reset => reset - ); - - SM : PresentCommSM - port map( - clk => clk, - reset => reset, - RDAsig => RDAsig, - TBEsig => TBEsig, - RDsig => RDsig, - WRsig => WRsig, - textDataEn => textDataEn, - textDataShift => textDataShift, - keyDataEn => keyDataEn, - keyDataShift => keyDataShift, - ciphDataEn => ciphDataEn, - ciphDataShift => ciphDataShift, - startSig => startSig, - readySig => readySig - ); - -end Behavioral; - Index: PureTesting/pLayer.vhd =================================================================== --- PureTesting/pLayer.vhd (revision 3) +++ PureTesting/pLayer.vhd (nonexistent) @@ -1,99 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 16:06:24 05/13/2010 --- Design Name: --- Module Name: pLayer - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity pLayer is - generic(w_64 : integer := 64); - port ( - input : in std_logic_vector(w_64-1 downto 0); - output : out std_logic_vector(w_64-1 downto 0) - ); -end pLayer; - -architecture Behavioral of pLayer is -begin - output(0) <= input(0); - output(16) <= input(1); - output(32) <= input(2); - output(48) <= input(3); - output(1) <= input(4); - output(17) <= input(5); - output(33) <= input(6); - output(49) <= input(7); - output(2) <= input(8); - output(18) <= input(9); - output(34) <= input(10); - output(50) <= input(11); - output(3) <= input(12); - output(19) <= input(13); - output(35) <= input(14); - output(51) <= input(15); - output(4) <= input(16); - output(20) <= input(17); - output(36) <= input(18); - output(52) <= input(19); - output(5) <= input(20); - output(21) <= input(21); - output(37) <= input(22); - output(53) <= input(23); - output(6) <= input(24); - output(22) <= input(25); - output(38) <= input(26); - output(54) <= input(27); - output(7) <= input(28); - output(23) <= input(29); - output(39) <= input(30); - output(55) <= input(31); - output(8) <= input(32); - output(24) <= input(33); - output(40) <= input(34); - output(56) <= input(35); - output(9) <= input(36); - output(25) <= input(37); - output(41) <= input(38); - output(57) <= input(39); - output(10) <= input(40); - output(26) <= input(41); - output(42) <= input(42); - output(58) <= input(43); - output(11) <= input(44); - output(27) <= input(45); - output(43) <= input(46); - output(59) <= input(47); - output(12) <= input(48); - output(28) <= input(49); - output(44) <= input(50); - output(60) <= input(51); - output(13) <= input(52); - output(29) <= input(53); - output(45) <= input(54); - output(61) <= input(55); - output(14) <= input(56); - output(30) <= input(57); - output(46) <= input(58); - output(62) <= input(59); - output(15) <= input(60); - output(31) <= input(61); - output(47) <= input(62); - output(63) <= input(63); -end Behavioral; \ No newline at end of file Index: PureTesting/RS232RefComp.vhd =================================================================== --- PureTesting/RS232RefComp.vhd (revision 3) +++ PureTesting/RS232RefComp.vhd (nonexistent) @@ -1,406 +0,0 @@ ------------------------------------------------------------------------- --- RS232RefCom.vhd ------------------------------------------------------------------------- --- Author: Dan Pederson --- Copyright 2004 Digilent, Inc. ------------------------------------------------------------------------- --- Description: This file defines a UART which tranfers data from --- serial form to parallel form and vice versa. ------------------------------------------------------------------------- --- Revision History: --- 07/15/04 (Created) DanP --- 02/25/08 (Created) ClaudiaG: made use of the baudDivide constant --- in the Clock Dividing Processes ------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - --- Uncomment the following lines to use the declarations that are --- provided for instantiating Xilinx primitive components. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity Rs232RefComp is - Port ( - TXD : out std_logic := '1'; - RXD : in std_logic; - CLK : in std_logic; --Master Clock - DBIN : in std_logic_vector (7 downto 0); --Data Bus in - DBOUT : out std_logic_vector (7 downto 0); --Data Bus out - RDA : inout std_logic; --Read Data Available - TBE : inout std_logic := '1'; --Transfer Bus Empty - RD : in std_logic; --Read Strobe - WR : in std_logic; --Write Strobe - PE : out std_logic; --Parity Error Flag - FE : out std_logic; --Frame Error Flag - OE : out std_logic; --Overwrite Error Flag - RST : in std_logic := '0'); --Master Reset -end Rs232RefComp; - -architecture Behavioral of Rs232RefComp is ------------------------------------------------------------------------- --- Component Declarations ------------------------------------------------------------------------- - ------------------------------------------------------------------------- --- Local Type Declarations ------------------------------------------------------------------------- - --Receive state machine - type rstate is ( - strIdle, --Idle state - strEightDelay, --Delays for 8 clock cycles - strGetData, --Shifts in the 8 data bits, and checks parity - strCheckStop --Sets framing error flag if Stop bit is wrong - ); - - type tstate is ( - sttIdle, --Idle state - sttTransfer, --Move data into shift register - sttShift --Shift out data - ); - - type TBEstate is ( - stbeIdle, - stbeSetTBE, - stbeWaitLoad, - stbeWaitWrite - ); - - ------------------------------------------------------------------------- --- Signal Declarations ------------------------------------------------------------------------- - constant baudDivide : std_logic_vector(7 downto 0) := "00001101"; --Baud Rate dividor, set now for a rate of 9600. - --Found by dividing 50MHz by 9600 and 16. - signal rdReg : std_logic_vector(7 downto 0) := "00000000"; --Receive holding register - signal rdSReg : std_logic_vector(9 downto 0) := "1111111111"; --Receive shift register - signal tfReg : std_logic_vector(7 downto 0); --Transfer holding register - signal tfSReg : std_logic_vector(10 downto 0) := "11111111111"; --Transfer shift register - signal clkDiv : std_logic_vector(8 downto 0) := "000000000"; --used for rClk - signal rClkDiv : std_logic_vector(3 downto 0) := "0000"; --used for tClk - signal ctr : std_logic_vector(3 downto 0) := "0000"; --used for delay times - signal tfCtr : std_logic_vector(3 downto 0) := "0000"; --used to delay in transfer - signal rClk : std_logic := '0'; --Receiving Clock - signal tClk : std_logic; --Transfering Clock - signal dataCtr : std_logic_vector(3 downto 0) := "0000"; --Counts the number of read data bits - signal parError: std_logic; --Parity error bit - signal frameError: std_logic; --Frame error bit - signal CE : std_logic; --Clock enable for the latch - signal ctRst : std_logic := '0'; - signal load : std_logic := '0'; - signal shift : std_logic := '0'; - signal par : std_logic; - signal tClkRST : std_logic := '0'; - signal rShift : std_logic := '0'; - signal dataRST : std_logic := '0'; - signal dataIncr: std_logic := '0'; - - signal strCur : rstate := strIdle; --Current state in the Receive state machine - signal strNext : rstate; --Next state in the Receive state machine - signal sttCur : tstate := sttIdle; --Current state in the Transfer state machine - signal sttNext : tstate; --Next state in the Transfer staet machine - signal stbeCur : TBEstate := stbeIdle; - signal stbeNext: TBEstate; - ------------------------------------------------------------------------- --- Module Implementation ------------------------------------------------------------------------- - -begin - frameError <= not rdSReg(9); - parError <= not ( rdSReg(8) xor (((rdSReg(0) xor rdSReg(1)) xor (rdSReg(2) xor rdSReg(3))) xor ((rdSReg(4) xor rdSReg(5)) xor (rdSReg(6) xor rdSReg(7)))) ); - DBOUT <= rdReg; - tfReg <= DBIN; - par <= not ( ((tfReg(0) xor tfReg(1)) xor (tfReg(2) xor tfReg(3))) xor ((tfReg(4) xor tfReg(5)) xor (tfReg(6) xor tfReg(7))) ); - ---Clock Dividing Functions-- - - process (CLK, clkDiv) --set up clock divide for rClk - begin - if (Clk = '1' and Clk'event) then - if (clkDiv = baudDivide) then - clkDiv <= "000000000"; - else - clkDiv <= clkDiv +1; - end if; - end if; - end process; - - process (clkDiv, rClk, CLK) --Define rClk - begin - if CLK = '1' and CLK'Event then - if clkDiv = baudDivide then - rClk <= not rClk; - else - rClk <= rClk; - end if; - end if; - end process; - - process (rClk) --set up clock divide for tClk - begin - if (rClk = '1' and rClk'event) then - rClkDiv <= rClkDiv +1; - end if; - end process; - - tClk <= rClkDiv(3); --define tClk - - process (rClk, ctRst) --set up a counter based on rClk - begin - if rClk = '1' and rClk'Event then - if ctRst = '1' then - ctr <= "0000"; - else - ctr <= ctr +1; - end if; - end if; - end process; - - process (tClk, tClkRST) --set up a counter based on tClk - begin - if (tClk = '1' and tClk'event) then - if tClkRST = '1' then - tfCtr <= "0000"; - else - tfCtr <= tfCtr +1; - end if; - end if; - end process; - - --This process controls the error flags-- - process (rClk, RST, RD, CE) - begin - if RD = '1' or RST = '1' then - FE <= '0'; - OE <= '0'; - RDA <= '0'; - PE <= '0'; - elsif rClk = '1' and rClk'event then - if CE = '1' then - FE <= frameError; - OE <= RDA; - RDA <= '1'; - PE <= parError; - rdReg(7 downto 0) <= rdSReg (7 downto 0); - end if; - end if; - end process; - - --This process controls the receiving shift register-- - process (rClk, rShift) - begin - if rClk = '1' and rClk'Event then - if rShift = '1' then - rdSReg <= (RXD & rdSReg(9 downto 1)); - end if; - end if; - end process; - - --This process controls the dataCtr to keep track of shifted values-- - process (rClk, dataRST) - begin - if (rClk = '1' and rClk'event) then - if dataRST = '1' then - dataCtr <= "0000"; - elsif dataIncr = '1' then - dataCtr <= dataCtr +1; - end if; - end if; - end process; - - --Receiving State Machine-- - process (rClk, RST) - begin - if rClk = '1' and rClk'Event then - if RST = '1' then - strCur <= strIdle; - else - strCur <= strNext; - end if; - end if; - end process; - - --This process generates the sequence of steps needed receive the data - - process (strCur, ctr, RXD, dataCtr, rdSReg, rdReg, RDA) - begin - case strCur is - - when strIdle => - dataIncr <= '0'; - rShift <= '0'; - dataRst <= '0'; - - CE <= '0'; - if RXD = '0' then - ctRst <= '1'; - strNext <= strEightDelay; - else - ctRst <= '0'; - strNext <= strIdle; - end if; - - when strEightDelay => - dataIncr <= '0'; - rShift <= '0'; - CE <= '0'; - - if ctr(2 downto 0) = "111" then - ctRst <= '1'; - dataRST <= '1'; - strNext <= strGetData; - else - ctRst <= '0'; - dataRST <= '0'; - strNext <= strEightDelay; - end if; - - when strGetData => - CE <= '0'; - dataRst <= '0'; - if ctr(3 downto 0) = "1111" then - ctRst <= '1'; - dataIncr <= '1'; - rShift <= '1'; - else - ctRst <= '0'; - dataIncr <= '0'; - rShift <= '0'; - end if; - - if dataCtr = "1010" then - strNext <= strCheckStop; - else - strNext <= strGetData; - end if; - - when strCheckStop => - dataIncr <= '0'; - rShift <= '0'; - dataRst <= '0'; - ctRst <= '0'; - - CE <= '1'; - strNext <= strIdle; - - end case; - - end process; - - --TBE State Machine-- - process (CLK, RST) - begin - if CLK = '1' and CLK'Event then - if RST = '1' then - stbeCur <= stbeIdle; - else - stbeCur <= stbeNext; - end if; - end if; - end process; - - --This process gererates the sequence of events needed to control the TBE flag-- - process (stbeCur, CLK, WR, DBIN, load) - begin - - case stbeCur is - - when stbeIdle => - TBE <= '1'; - if WR = '1' then - stbeNext <= stbeSetTBE; - else - stbeNext <= stbeIdle; - end if; - - when stbeSetTBE => - TBE <= '0'; - if load = '1' then - stbeNext <= stbeWaitLoad; - else - stbeNext <= stbeSetTBE; - end if; - - when stbeWaitLoad => - if load = '0' then - stbeNext <= stbeWaitWrite; - else - stbeNext <= stbeWaitLoad; - end if; - - when stbeWaitWrite => - if WR = '0' then - stbeNext <= stbeIdle; - else - stbeNext <= stbeWaitWrite; - end if; - end case; - end process; - - --This process loads and shifts out the transfer shift register-- - process (load, shift, tClk, tfSReg) - begin - TXD <= tfsReg(0); - if tClk = '1' and tClk'Event then - if load = '1' then - tfSReg (10 downto 0) <= ('1' & par & tfReg(7 downto 0) &'0'); - end if; - if shift = '1' then - - tfSReg (10 downto 0) <= ('1' & tfSReg(10 downto 1)); - end if; - end if; - end process; - - -- Transfer State Machine-- - process (tClk, RST) - begin - if (tClk = '1' and tClk'Event) then - if RST = '1' then - sttCur <= sttIdle; - else - sttCur <= sttNext; - end if; - end if; - end process; - - -- This process generates the sequence of steps needed transfer the data-- - process (sttCur, tfCtr, tfReg, TBE, tclk) - begin - - case sttCur is - - when sttIdle => - tClkRST <= '0'; - shift <= '0'; - load <= '0'; - if TBE = '1' then - sttNext <= sttIdle; - else - sttNext <= sttTransfer; - end if; - - when sttTransfer => - shift <= '0'; - load <= '1'; - tClkRST <= '1'; - sttNext <= sttShift; - - - when sttShift => - shift <= '1'; - load <= '0'; - tClkRST <= '0'; - if tfCtr = "1100" then - sttNext <= sttIdle; - else - sttNext <= sttShift; - end if; - end case; - end process; - -end Behavioral; \ No newline at end of file Index: PureTesting/PresentStateMachine.vhd =================================================================== --- PureTesting/PresentStateMachine.vhd (revision 3) +++ PureTesting/PresentStateMachine.vhd (nonexistent) @@ -1,100 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:17:10 04/02/2011 --- Design Name: --- Module Name: PresentStateMachine - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.NUMERIC_STD.ALL; -use work.kody.ALL; - -entity PresentStateMachine is - generic ( - w_5 : integer := 5 - ); - port ( - clk, reset, start : in std_logic; - ready, cnt_res, ctrl_mux, RegEn: out std_logic; - num : in std_logic_vector (w_5-1 downto 0) - ); -end PresentStateMachine; - -architecture Behavioral of PresentStateMachine is - - signal state : stany; - signal next_state : stany; - - begin - States : process(state, start, num) - begin - case state is - when NOP => - ready <= '0'; - cnt_res <= '0'; - ctrl_mux <= '0'; - RegEn <= '0'; - if (start = '1') then - next_state <= SM_START; - else - next_state <= NOP; - end if; - when SM_START => - ready <= '0'; - RegEn <= '1'; - cnt_res <= '1'; - if (start = '1') then - if (num = "00000") then - ctrl_mux <= '0'; - next_state <= SM_START; - elsif (num = "11111") then - ctrl_mux <= '1'; - next_state <= SM_READY; - else - ctrl_mux <= '1'; - next_state <= SM_START; - end if; - else - ctrl_mux <= '0'; - next_state <= NOP; - end if; - when SM_READY => - cnt_res <= '0'; - RegEn <= '0'; - ready <= '1'; - if (start = '1') then - ctrl_mux <= '1'; - next_state <= SM_READY; - else - ctrl_mux <= '0'; - next_state <= NOP; - end if; - end case; - end process States; - - SM : process (clk, reset) - begin - if (reset = '1') then - state <= NOP; - elsif (clk'Event and clk = '1') then - state <= next_state; - end if; - end process SM; - - end Behavioral; - Index: PureTesting/slayer.vhd =================================================================== --- PureTesting/slayer.vhd (revision 3) +++ PureTesting/slayer.vhd (nonexistent) @@ -1,55 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 13:48:15 05/13/2010 --- Design Name: --- Module Name: permutation - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity slayer is - generic ( - w_4 : integer := 4 - ); - port ( - input : in std_logic_vector(w_4-1 downto 0); - output : out std_logic_vector(w_4-1 downto 0) - ); -end slayer; - -architecture Behavioral of slayer is - - begin - output <= x"C" when input = x"0" else - x"5" when input = x"1" else - x"6" when input = x"2" else - x"B" when input = x"3" else - x"9" when input = x"4" else - x"0" when input = x"5" else - x"A" when input = x"6" else - x"D" when input = x"7" else - x"3" when input = x"8" else - x"E" when input = x"9" else - x"F" when input = x"A" else - x"8" when input = x"B" else - x"4" when input = x"C" else - x"7" when input = x"D" else - x"1" when input = x"E" else - x"2" when input = x"F" else - "ZZZZ"; - end Behavioral; \ No newline at end of file Index: PureTesting/counter.vhd =================================================================== --- PureTesting/counter.vhd (revision 3) +++ PureTesting/counter.vhd (nonexistent) @@ -1,49 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 13:47:04 04/02/2011 --- Design Name: --- Module Name: counter - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity counter is - generic ( - w_5 : integer := 5 - ); - port ( - clk, reset, cnt_res : in std_logic; - num : out std_logic_vector (w_5-1 downto 0) - ); -end counter; - -architecture Behavioral of counter is - signal cnt : std_logic_vector(w_5-1 downto 0) := (others => '0'); - begin - licznik : process (clk, reset, cnt) - begin - if (reset = '1') then - cnt <= (others => '0'); - elsif (clk'Event and clk = '1') then - if (cnt_res = '1') then - cnt <= cnt + 1; - end if; - end if; - end process licznik; - num <= cnt; - end Behavioral; - Index: PureTesting/ShiftReg.vhd =================================================================== --- PureTesting/ShiftReg.vhd (revision 3) +++ PureTesting/ShiftReg.vhd (nonexistent) @@ -1,70 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 21:39:23 10/08/2012 --- Design Name: --- Module Name: ShiftReg - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity ShiftReg is - generic ( - length_1 : integer := 8; - length_2 : integer := 64; - internal_data : integer := 64 - ); - port ( - input : in STD_LOGIC_VECTOR(length_1 - 1 downto 0); - output : out STD_LOGIC_VECTOR(length_2 - 1 downto 0); - en : in STD_LOGIC; - shift : in STD_LOGIC; - clk : in STD_LOGIC; - reset : in STD_LOGIC - ); -end ShiftReg; - -architecture Behavioral of ShiftReg is - -signal data : STD_LOGIC_VECTOR(internal_data - 1 downto 0); - -begin - reg : process (clk, reset, data) - begin - if (clk'event and clk = '1') then - if (reset = '1') then - data <= (others => '0'); - elsif (en = '1') then - data(internal_data - 1 downto internal_data - length_1) <= input; - else - if (shift = '1') then - data <= '0' & data(internal_data - 1 downto 1); - end if; - end if; - end if; - output <= data(length_2 - 1 downto 0); - end process reg; - -end Behavioral; - Index: PureTesting/PresentEnc.vhd =================================================================== --- PureTesting/PresentEnc.vhd (revision 3) +++ PureTesting/PresentEnc.vhd (nonexistent) @@ -1,186 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 18:02:34 05/15/2010 --- Design Name: --- Module Name: PresentEnc - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: - --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity PresentEnc is - generic ( - w_2: integer := 2; - w_4: integer := 4; - w_5: integer := 5; - w_32: integer := 32; - w_64: integer := 64; - w_80: integer := 80 - ); - port( - plaintext : in std_logic_vector(w_64 - 1 downto 0); - key : in std_logic_vector(w_80 - 1 downto 0); - ciphertext : out std_logic_vector(w_64 - 1 downto 0); - start, clk, reset : in std_logic; - ready : out std_logic - ); -end PresentEnc; - -architecture Behavioral of PresentEnc is - - component Reg is - generic(width : integer := w_64); - port( - input : in STD_LOGIC_VECTOR(width - 1 downto 0); - output : out STD_LOGIC_VECTOR(width - 1 downto 0); - enable : in STD_LOGIC; - clk : in STD_LOGIC; - reset : in STD_LOGIC - ); - end component Reg; - - component AsyncMux is - generic ( - width : integer := 64 - ); - port ( - input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); - input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); - ctrl : in STD_LOGIC; - output : out STD_LOGIC_VECTOR(width - 1 downto 0) - ); - end component AsyncMux; - - component PresentStateMachine is - generic ( - w_5 : integer := 5 - ); - port ( - clk, reset, start : in std_logic; - ready, cnt_res, ctrl_mux, RegEn: out std_logic; - num : in std_logic_vector (w_5-1 downto 0) - ); - end component; - - component slayer is - generic ( - w_4 : integer := 4 - ); - port ( - input : in std_logic_vector(w_4-1 downto 0); - output : out std_logic_vector(w_4-1 downto 0) - ); - end component; - - component pLayer is - generic(w_64 : integer := 64); - port( - input : in std_logic_vector(w_64-1 downto 0); - output : out std_logic_vector(w_64-1 downto 0) - ); - end component; - - component keyupd is - generic( - w_5 : integer := 5; - w_80: integer := 80 - ); - port( - num : in std_logic_vector(w_5-1 downto 0); - key : in std_logic_vector(w_80-1 downto 0); - keyout : out std_logic_vector(w_80-1 downto 0) - ); - end component; - - component counter is - generic ( - w_5 : integer := 5 - ); - port ( - clk, reset, cnt_res : in std_logic; - num : out std_logic_vector (w_5-1 downto 0) - ); - end component; - - signal keynum : std_logic_vector (w_5-1 downto 0); - signal toXor, ciph, P, Pout, textToReg : std_logic_vector (w_64-1 downto 0); - signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0); - signal ready_sig, mux_ctrl, cnt_res, RegEn : std_logic; - - begin - mux_64: AsyncMux generic map(width => w_64) port map( - input0 => plaintext, - input1 => Pout, - ctrl => mux_ctrl, - output => textToReg - ); - regText : Reg generic map(width => w_64) port map( - input => textToReg, - output => toXor, - enable => RegEn, - clk => clk, - reset => reset - ); - mux_80: AsyncMux generic map(width => w_80) port map( - input0 => key, - input1 => kupd, - ctrl => mux_ctrl, - output => keyToReg - ); - regKey : Reg generic map(width => w_80) port map( - input => keyToReg, - output => keyfout, - enable => RegEn, - clk => clk, - reset => reset - ); - slayers : for N in 15 downto 0 generate - s_x: slayer port map( - input => ciph(4*N+3 downto 4*N), - output => P(4*N+3 downto 4*N) - ); - end generate slayers; - p1: pLayer port map( - input => P, - output => Pout - ); - mixer: keyupd port map( - key => keyfout, - num => keynum, - keyout => kupd - ); - SM: PresentStateMachine port map( - start => start, - reset => reset, - ready => ready_sig, - cnt_res => cnt_res, - ctrl_mux => mux_ctrl, - clk => clk, - num => keynum, - RegEn => RegEn - ); - count: counter port map( - clk => clk, - reset => reset, - cnt_res => cnt_res, - num => keynum - ); - ciph <= toXor xor keyfout(79 downto 16); - ciphertext <= ciph; - ready <= ready_sig; -end Behavioral; Index: PureTesting/PresentCommSM.vhd =================================================================== --- PureTesting/PresentCommSM.vhd (revision 3) +++ PureTesting/PresentCommSM.vhd (nonexistent) @@ -1,367 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 22:49:35 06/26/2013 --- Design Name: --- Module Name: PresentCommSM - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use work.kody.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity PresentCommSM is - port ( - clk : in STD_LOGIC; - reset : in STD_LOGIC; - RDAsig : in STD_LOGIC; - TBEsig : in STD_LOGIC; - RDsig : out STD_LOGIC; - WRsig : out STD_LOGIC; - textDataEn : out STD_LOGIC; - textDataShift : out STD_LOGIC; - keyDataEn : out STD_LOGIC; - keyDataShift : out STD_LOGIC; - ciphDataEn : out STD_LOGIC; - ciphDataShift : out STD_LOGIC; - startSig : out STD_LOGIC; - readySig : in STD_LOGIC - ); -end PresentCommSM; - -architecture Behavioral of PresentCommSM is - -component counter is - generic ( - w_5 : integer := 5 - ); - port ( - clk, reset, cnt_res : in std_logic; - num : out std_logic_vector (w_5-1 downto 0) - ); -end component counter; - -signal state : stany_comm := NOP; -signal next_state : stany_comm := NOP; - --- modify for variable key size -signal serialDataCtrCt : STD_LOGIC; -signal serialDataCtrOut : STD_LOGIC_VECTOR(3 downto 0); -signal serialDataCtrReset : STD_LOGIC; -signal ctrReset : STD_LOGIC; --- DO NOT MODIFY!!! -signal shiftDataCtrCt : STD_LOGIC; -signal shiftDataCtrOut : STD_LOGIC_VECTOR(2 downto 0); - -begin - ctrReset <= serialDataCtrReset or reset; - SM : process(state, RDAsig, TBEsig, shiftDataCtrOut, serialDataCtrOut, readySig) - begin - case state is - when NOP => - RDsig <= '0'; - WRsig <= '0'; - textDataEn <= '0'; - textDataShift <= '0'; - keyDataEn <= '0'; - keyDataShift <= '0'; - ciphDataEn <= '0'; - ciphDataShift <= '0'; - startSig <= '0'; - serialDataCtrCt <= '0'; - shiftDataCtrCt <= '0'; - serialDataCtrReset <= '0'; - if (RDAsig = '1') then - next_state <= READ_DATA_TEXT; - else - next_state <= NOP; - end if; - when READ_DATA_TEXT => - RDsig <= '1'; - WRsig <= '0'; - textDataEn <= '1'; - textDataShift <= '0'; - keyDataEn <= '0'; - keyDataShift <= '0'; - ciphDataEn <= '0'; - ciphDataShift <= '0'; - startSig <= '0'; - serialDataCtrCt <= '1'; - shiftDataCtrCt <= '0'; - serialDataCtrReset <= '0'; - next_state <= DECODE_READ_TEXT; - when DECODE_READ_TEXT => - RDsig <= '0'; - WRsig <= '0'; - textDataEn <= '0'; - textDataShift <= '0'; - keyDataEn <= '0'; - keyDataShift <= '0'; - ciphDataEn <= '0'; - ciphDataShift <= '0'; - startSig <= '0'; - serialDataCtrCt <= '0'; - shiftDataCtrCt <= '0'; - if (serialDataCtrOut(3 downto 0) = "1000") then - next_state <= TEMP_STATE; - else - next_state <= MOVE_TEXT; - end if; - when TEMP_STATE => - RDsig <= '0'; - WRsig <= '0'; - textDataEn <= '0'; - textDataShift <= '0'; - keyDataEn <= '0'; - keyDataShift <= '0'; - ciphDataEn <= '0'; - ciphDataShift <= '0'; - startSig <= '0'; - serialDataCtrCt <= '0'; - shiftDataCtrCt <= '0'; - serialDataCtrReset <= '1'; - next_state <= NOP_FOR_KEY; - when MOVE_TEXT => - RDsig <= '0'; - WRsig <= '0'; - textDataEn <= '0'; - textDataShift <= '1'; - keyDataEn <= '0'; - keyDataShift <= '0'; - ciphDataEn <= '0'; - ciphDataShift <= '0'; - startSig <= '0'; - serialDataCtrCt <= '0'; - shiftDataCtrCt <= '1'; - serialDataCtrReset <= '0'; - if (shiftDataCtrOut(2 downto 0) = "111") then - next_state <= NOP; - else - next_state <= MOVE_TEXT; - end if; - when NOP_FOR_KEY => - RDsig <= '0'; - WRsig <= '0'; - textDataEn <= '0'; - textDataShift <= '0'; - keyDataEn <= '0'; - keyDataShift <= '0'; - ciphDataEn <= '0'; - ciphDataShift <= '0'; - startSig <= '0'; - serialDataCtrCt <= '0'; - shiftDataCtrCt <= '0'; - serialDataCtrReset <= '0'; - if (RDAsig = '1') then - next_state <= READ_DATA_KEY; - else - next_state <= NOP_FOR_KEY; - end if; - when READ_DATA_KEY => - RDsig <= '1'; - WRsig <= '0'; - textDataEn <= '0'; - textDataShift <= '0'; - keyDataEn <= '1'; - keyDataShift <= '0'; - ciphDataEn <= '0'; - ciphDataShift <= '0'; - startSig <= '0'; - serialDataCtrCt <= '1'; - shiftDataCtrCt <= '0'; - serialDataCtrReset <= '0'; - next_state <= DECODE_READ_KEY; - when DECODE_READ_KEY => - RDsig <= '0'; - WRsig <= '0'; - textDataEn <= '0'; - textDataShift <= '0'; - keyDataEn <= '0'; - keyDataShift <= '0'; - ciphDataEn <= '0'; - ciphDataShift <= '0'; - startSig <= '0'; - serialDataCtrCt <= '0'; - shiftDataCtrCt <= '0'; - serialDataCtrReset <= '0'; - if (serialDataCtrOut(3 downto 0) = "1010") then - next_state <= TEMP2_STATE; - else - next_state <= MOVE_KEY; - end if; - when TEMP2_STATE => - RDsig <= '0'; - WRsig <= '0'; - textDataEn <= '0'; - textDataShift <= '0'; - keyDataEn <= '0'; - keyDataShift <= '0'; - ciphDataEn <= '0'; - ciphDataShift <= '0'; - startSig <= '0'; - serialDataCtrCt <= '0'; - shiftDataCtrCt <= '0'; - serialDataCtrReset <= '1'; - next_state <= PRESENT_ENCODE; - when MOVE_KEY => - RDsig <= '0'; - WRsig <= '0'; - textDataEn <= '0'; - textDataShift <= '0'; - keyDataEn <= '0'; - keyDataShift <= '1'; - ciphDataEn <= '0'; - ciphDataShift <= '0'; - startSig <= '0'; - serialDataCtrCt <= '0'; - shiftDataCtrCt <= '1'; - serialDataCtrReset <= '0'; - if (shiftDataCtrOut(2 downto 0) = "111") then - next_state <= NOP_FOR_KEY; - else - next_state <= MOVE_KEY; - end if; - when PRESENT_ENCODE => - RDsig <= '0'; - WRsig <= '0'; - textDataEn <= '0'; - textDataShift <= '0'; - keyDataEn <= '0'; - keyDataShift <= '0'; - ciphDataShift <= '0'; - startSig <= '1'; - serialDataCtrCt <= '0'; - shiftDataCtrCt <= '0'; - serialDataCtrReset <= '0'; - if (readySig = '1') then - ciphDataEn <= '1'; - next_state <= WRITE_OUT; - else - ciphDataEn <= '0'; - next_state <= PRESENT_ENCODE; - end if; - when WRITE_OUT => - RDsig <= '0'; - textDataEn <= '0'; - textDataShift <= '0'; - keyDataEn <= '0'; - keyDataShift <= '0'; - ciphDataEn <= '0'; - ciphDataShift <= '0'; - startSig <= '1'; - serialDataCtrCt <= '1'; - shiftDataCtrCt <= '0'; - serialDataCtrReset <= '0'; - if (serialDataCtrOut = "1000") then - WRsig <= '0'; - next_state <= TEMP_OUT; - else - WRsig <= '1'; - next_state <= MOVE_OUT; - end if; - when TEMP_OUT => - RDsig <= '0'; - WRsig <= '0'; - textDataEn <= '0'; - textDataShift <= '0'; - keyDataEn <= '0'; - keyDataShift <= '0'; - ciphDataEn <= '0'; - ciphDataShift <= '0'; - startSig <= '1'; - serialDataCtrCt <= '0'; - shiftDataCtrCt <= '0'; - serialDataCtrReset <= '1'; - next_state <= NOP; - when MOVE_OUT => - if (TBEsig = '0') then - RDsig <= '0'; - WRsig <= '0'; - textDataEn <= '0'; - textDataShift <= '0'; - keyDataEn <= '0'; - keyDataShift <= '0'; - ciphDataEn <= '0'; - ciphDataShift <= '0'; - startSig <= '1'; - serialDataCtrCt <= '0'; - shiftDataCtrCt <= '0'; - serialDataCtrReset <= '0'; - next_state <= MOVE_OUT; - else - RDsig <= '0'; - WRsig <= '0'; - textDataEn <= '0'; - textDataShift <= '0'; - keyDataEn <= '0'; - keyDataShift <= '0'; - ciphDataEn <= '0'; - ciphDataShift <= '1'; - startSig <= '1'; - serialDataCtrCt <= '0'; - shiftDataCtrCt <= '1'; - serialDataCtrReset <= '0'; - if (shiftDataCtrOut = "111") then - next_state <= WRITE_OUT; - else - next_state <= MOVE_OUT; - end if; - end if; - end case; - end process SM; - - state_modifier : process (clk, reset) - begin - if (clk = '1' and clk'Event) then - if (reset = '1') then - state <= NOP; - else - state <= next_state; - end if; - end if; - end process state_modifier; - - dataCounter : counter - generic map( - w_5 => 4 - ) - port map ( - cnt_res => serialDataCtrCt, - num => serialDataCtrOut, - clk => clk, - reset => ctrReset - ); - - shiftCounter : counter - generic map( - w_5 => 3 - ) - port map ( - cnt_res => shiftDataCtrCt, - num => shiftDataCtrOut, - clk => clk, - reset => reset - ); - -end Behavioral; - Index: PureTesting/sLayerTB.vhd =================================================================== --- PureTesting/sLayerTB.vhd (revision 3) +++ PureTesting/sLayerTB.vhd (nonexistent) @@ -1,95 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:11:33 05/16/2010 --- Design Name: --- Module Name: C:/Users/gajos/Desktop/Polibuda/vhdl/projekt/szyfrator/sLayerTB.vhd --- Project Name: szyfrator --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: slayer --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.all; -USE ieee.numeric_std.ALL; - -ENTITY sLayerTB IS -END sLayerTB; - -ARCHITECTURE behavior OF sLayerTB IS - - -- Component Declaration for the Unit Under Test (UUT) - - COMPONENT slayer - PORT( - input : IN std_logic_vector(3 downto 0); - output : OUT std_logic_vector(3 downto 0) - ); - END COMPONENT; - - - --Inputs - signal clk : std_logic := '0'; - signal reset : std_logic := '0'; - - --BiDirs - signal input : std_logic_vector(3 downto 0); - signal output : std_logic_vector(3 downto 0); - - -- Clock period definitions - constant clk_period : time := 1ns; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: slayer PORT MAP ( - input => input, - output => output - ); - - -- Clock process definitions - clk_process :process - begin - clk <= '0'; - wait for clk_period/2; - clk <= '1'; - wait for clk_period/2; - end process; - - - -- Stimulus process - stim_proc: process - begin - -- hold reset state for 100ms. - reset <= '1'; - wait for 100ns; - reset <= '0'; - wait for clk_period; - input <= x"0"; - wait for clk_period; - input <= x"A"; - wait for clk_period; - input <= x"F"; - wait for clk_period; - -- insert stimulus here - assert false severity failure; - end process; - -END; \ No newline at end of file Index: PureTesting/txt_util.vhd =================================================================== --- PureTesting/txt_util.vhd (revision 3) +++ PureTesting/txt_util.vhd (nonexistent) @@ -1,586 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use std.textio.all; - - -package txt_util is - - -- prints a message to the screen - procedure print(text: string); - - -- prints the message when active - -- useful for debug switches - procedure print(active: boolean; text: string); - - -- converts std_logic into a character - function chr(sl: std_logic) return character; - - -- converts std_logic into a string (1 to 1) - function str(sl: std_logic) return string; - - -- converts std_logic_vector into a string (binary base) - function str(slv: std_logic_vector) return string; - - -- converts boolean into a string - function str(b: boolean) return string; - - -- converts an integer into a single character - -- (can also be used for hex conversion and other bases) - function chr(int: integer) return character; - - -- converts integer into string using specified base - function str(int: integer; base: integer) return string; - - -- converts integer to string, using base 10 - function str(int: integer) return string; - - -- convert std_logic_vector into a string in hex format - function hstr(slv: std_logic_vector) return string; - - - -- functions to manipulate strings - ----------------------------------- - - -- convert a character to upper case - function to_upper(c: character) return character; - - -- convert a character to lower case - function to_lower(c: character) return character; - - -- convert a string to upper case - function to_upper(s: string) return string; - - -- convert a string to lower case - function to_lower(s: string) return string; - - - - -- functions to convert strings into other formats - -------------------------------------------------- - - -- converts a character into std_logic - function to_std_logic(c: character) return std_logic; - - -- converts a string into std_logic_vector - function to_std_logic_vector(s: string) return std_logic_vector; - - - - -- file I/O - ----------- - - -- read variable length string from input file - procedure str_read(file in_file: TEXT; - res_string: out string); - - -- print string to a file and start new line - procedure print(file out_file: TEXT; - new_string: in string); - - -- print character to a file and start new line - procedure print(file out_file: TEXT; - char: in character); - -end txt_util; - - - - -package body txt_util is - - - - - -- prints text to the screen - - procedure print(text: string) is - variable msg_line: line; - begin - write(msg_line, text); - writeline(output, msg_line); - end print; - - - - - -- prints text to the screen when active - - procedure print(active: boolean; text: string) is - begin - if active then - print(text); - end if; - end print; - - - -- converts std_logic into a character - - function chr(sl: std_logic) return character is - variable c: character; - begin - case sl is - when 'U' => c:= 'U'; - when 'X' => c:= 'X'; - when '0' => c:= '0'; - when '1' => c:= '1'; - when 'Z' => c:= 'Z'; - when 'W' => c:= 'W'; - when 'L' => c:= 'L'; - when 'H' => c:= 'H'; - when '-' => c:= '-'; - end case; - return c; - end chr; - - - - -- converts std_logic into a string (1 to 1) - - function str(sl: std_logic) return string is - variable s: string(1 to 1); - begin - s(1) := chr(sl); - return s; - end str; - - - - -- converts std_logic_vector into a string (binary base) - -- (this also takes care of the fact that the range of - -- a string is natural while a std_logic_vector may - -- have an integer range) - - function str(slv: std_logic_vector) return string is - variable result : string (1 to slv'length); - variable r : integer; - begin - r := 1; - for i in slv'range loop - result(r) := chr(slv(i)); - r := r + 1; - end loop; - return result; - end str; - - - function str(b: boolean) return string is - - begin - if b then - return "true"; - else - return "false"; - end if; - end str; - - - -- converts an integer into a character - -- for 0 to 9 the obvious mapping is used, higher - -- values are mapped to the characters A-Z - -- (this is usefull for systems with base > 10) - -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) - - function chr(int: integer) return character is - variable c: character; - begin - case int is - when 0 => c := '0'; - when 1 => c := '1'; - when 2 => c := '2'; - when 3 => c := '3'; - when 4 => c := '4'; - when 5 => c := '5'; - when 6 => c := '6'; - when 7 => c := '7'; - when 8 => c := '8'; - when 9 => c := '9'; - when 10 => c := 'A'; - when 11 => c := 'B'; - when 12 => c := 'C'; - when 13 => c := 'D'; - when 14 => c := 'E'; - when 15 => c := 'F'; - when 16 => c := 'G'; - when 17 => c := 'H'; - when 18 => c := 'I'; - when 19 => c := 'J'; - when 20 => c := 'K'; - when 21 => c := 'L'; - when 22 => c := 'M'; - when 23 => c := 'N'; - when 24 => c := 'O'; - when 25 => c := 'P'; - when 26 => c := 'Q'; - when 27 => c := 'R'; - when 28 => c := 'S'; - when 29 => c := 'T'; - when 30 => c := 'U'; - when 31 => c := 'V'; - when 32 => c := 'W'; - when 33 => c := 'X'; - when 34 => c := 'Y'; - when 35 => c := 'Z'; - when others => c := '?'; - end case; - return c; - end chr; - - - - -- convert integer to string using specified base - -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) - - function str(int: integer; base: integer) return string is - - variable temp: string(1 to 10); - variable num: integer; - variable abs_int: integer; - variable len: integer := 1; - variable power: integer := 1; - - begin - - -- bug fix for negative numbers - abs_int := abs(int); - - num := abs_int; - - while num >= base loop -- Determine how many - len := len + 1; -- characters required - num := num / base; -- to represent the - end loop ; -- number. - - for i in len downto 1 loop -- Convert the number to - temp(i) := chr(abs_int/power mod base); -- a string starting - power := power * base; -- with the right hand - end loop ; -- side. - - -- return result and add sign if required - if int < 0 then - return '-'& temp(1 to len); - else - return temp(1 to len); - end if; - - end str; - - - -- convert integer to string, using base 10 - function str(int: integer) return string is - - begin - - return str(int, 10) ; - - end str; - - - - -- converts a std_logic_vector into a hex string. - function hstr(slv: std_logic_vector) return string is - variable hexlen: integer; - variable longslv : std_logic_vector(67 downto 0) := (others => '0'); - variable hex : string(1 to 16); - variable fourbit : std_logic_vector(3 downto 0); - begin - hexlen := (slv'left+1)/4; - if (slv'left+1) mod 4 /= 0 then - hexlen := hexlen + 1; - end if; - longslv(slv'left downto 0) := slv; - for i in (hexlen -1) downto 0 loop - fourbit := longslv(((i*4)+3) downto (i*4)); - case fourbit is - when "0000" => hex(hexlen -I) := '0'; - when "0001" => hex(hexlen -I) := '1'; - when "0010" => hex(hexlen -I) := '2'; - when "0011" => hex(hexlen -I) := '3'; - when "0100" => hex(hexlen -I) := '4'; - when "0101" => hex(hexlen -I) := '5'; - when "0110" => hex(hexlen -I) := '6'; - when "0111" => hex(hexlen -I) := '7'; - when "1000" => hex(hexlen -I) := '8'; - when "1001" => hex(hexlen -I) := '9'; - when "1010" => hex(hexlen -I) := 'A'; - when "1011" => hex(hexlen -I) := 'B'; - when "1100" => hex(hexlen -I) := 'C'; - when "1101" => hex(hexlen -I) := 'D'; - when "1110" => hex(hexlen -I) := 'E'; - when "1111" => hex(hexlen -I) := 'F'; - when "ZZZZ" => hex(hexlen -I) := 'z'; - when "UUUU" => hex(hexlen -I) := 'u'; - when "XXXX" => hex(hexlen -I) := 'x'; - when others => hex(hexlen -I) := '?'; - end case; - end loop; - return hex(1 to hexlen); - end hstr; - - - - -- functions to manipulate strings - ----------------------------------- - - - -- convert a character to upper case - - function to_upper(c: character) return character is - - variable u: character; - - begin - - case c is - when 'a' => u := 'A'; - when 'b' => u := 'B'; - when 'c' => u := 'C'; - when 'd' => u := 'D'; - when 'e' => u := 'E'; - when 'f' => u := 'F'; - when 'g' => u := 'G'; - when 'h' => u := 'H'; - when 'i' => u := 'I'; - when 'j' => u := 'J'; - when 'k' => u := 'K'; - when 'l' => u := 'L'; - when 'm' => u := 'M'; - when 'n' => u := 'N'; - when 'o' => u := 'O'; - when 'p' => u := 'P'; - when 'q' => u := 'Q'; - when 'r' => u := 'R'; - when 's' => u := 'S'; - when 't' => u := 'T'; - when 'u' => u := 'U'; - when 'v' => u := 'V'; - when 'w' => u := 'W'; - when 'x' => u := 'X'; - when 'y' => u := 'Y'; - when 'z' => u := 'Z'; - when others => u := c; - end case; - - return u; - - end to_upper; - - - -- convert a character to lower case - - function to_lower(c: character) return character is - - variable l: character; - - begin - - case c is - when 'A' => l := 'a'; - when 'B' => l := 'b'; - when 'C' => l := 'c'; - when 'D' => l := 'd'; - when 'E' => l := 'e'; - when 'F' => l := 'f'; - when 'G' => l := 'g'; - when 'H' => l := 'h'; - when 'I' => l := 'i'; - when 'J' => l := 'j'; - when 'K' => l := 'k'; - when 'L' => l := 'l'; - when 'M' => l := 'm'; - when 'N' => l := 'n'; - when 'O' => l := 'o'; - when 'P' => l := 'p'; - when 'Q' => l := 'q'; - when 'R' => l := 'r'; - when 'S' => l := 's'; - when 'T' => l := 't'; - when 'U' => l := 'u'; - when 'V' => l := 'v'; - when 'W' => l := 'w'; - when 'X' => l := 'x'; - when 'Y' => l := 'y'; - when 'Z' => l := 'z'; - when others => l := c; - end case; - - return l; - - end to_lower; - - - - -- convert a string to upper case - - function to_upper(s: string) return string is - - variable uppercase: string (s'range); - - begin - - for i in s'range loop - uppercase(i):= to_upper(s(i)); - end loop; - return uppercase; - - end to_upper; - - - - -- convert a string to lower case - - function to_lower(s: string) return string is - - variable lowercase: string (s'range); - - begin - - for i in s'range loop - lowercase(i):= to_lower(s(i)); - end loop; - return lowercase; - - end to_lower; - - - --- functions to convert strings into other types - - --- converts a character into a std_logic - -function to_std_logic(c: character) return std_logic is - variable sl: std_logic; - begin - case c is - when 'U' => - sl := 'U'; - when 'X' => - sl := 'X'; - when '0' => - sl := '0'; - when '1' => - sl := '1'; - when 'Z' => - sl := 'Z'; - when 'W' => - sl := 'W'; - when 'L' => - sl := 'L'; - when 'H' => - sl := 'H'; - when '-' => - sl := '-'; - when others => - sl := 'X'; - end case; - return sl; - end to_std_logic; - - --- converts a string into std_logic_vector - -function to_std_logic_vector(s: string) return std_logic_vector is - variable slv: std_logic_vector(s'high-s'low downto 0); - variable k: integer; -begin - k := s'high-s'low; - for i in s'range loop - slv(k) := to_std_logic(s(i)); - k := k - 1; - end loop; - return slv; -end to_std_logic_vector; - - - - - - ----------------- --- file I/O -- ----------------- - - - --- read variable length string from input file - -procedure str_read(file in_file: TEXT; - res_string: out string) is - - variable l: line; - variable c: character; - variable is_string: boolean; - - begin - - readline(in_file, l); - -- clear the contents of the result string - for i in res_string'range loop - res_string(i) := ' '; - end loop; - -- read all characters of the line, up to the length - -- of the results string - for i in res_string'range loop - read(l, c, is_string); - res_string(i) := c; - if not is_string then -- found end of line - exit; - end if; - end loop; - -end str_read; - - --- print string to a file -procedure print(file out_file: TEXT; - new_string: in string) is - - variable l: line; - - begin - - write(l, new_string); - writeline(out_file, l); - -end print; - - --- print character to a file and start new line -procedure print(file out_file: TEXT; - char: in character) is - - variable l: line; - - begin - - write(l, char); - writeline(out_file, l); - -end print; - - - --- appends contents of a string to a file until line feed occurs --- (LF is considered to be the end of the string) - -procedure str_write(file out_file: TEXT; - new_string: in string) is - begin - - for i in new_string'range loop - print(out_file, new_string(i)); - if new_string(i) = LF then -- end of string - exit; - end if; - end loop; - -end str_write; - - - - -end txt_util; - - - - Index: PureTesting/keyupd.vhd =================================================================== --- PureTesting/keyupd.vhd (revision 3) +++ PureTesting/keyupd.vhd (nonexistent) @@ -1,59 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 19:45:36 05/13/2010 --- Design Name: --- Module Name: keyupd - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity keyupd is - generic( - w_80: integer := 80; - w_5 : integer := 5; - w_4 : integer := 4); - port( - key : in std_logic_vector(w_80-1 downto 0); - num : in std_logic_vector(w_5-1 downto 0); - keyout : out std_logic_vector(w_80-1 downto 0) - ); -end keyupd; - -architecture Behavioral of keyupd is - - component slayer is - generic(w_4: integer := 4); - port( - input : in std_logic_vector(w_4-1 downto 0); - output : out std_logic_vector(w_4-1 downto 0) - ); - end component; - - signal changed : std_logic_vector(w_4-1 downto 0); - signal changin : std_logic_vector(w_4-1 downto 0); - signal keytemp : std_logic_vector(w_80-1 downto 0); - - begin - s1: slayer port map(input => changin, output => changed); - changin <= keytemp(79 downto 76); - keytemp <= key(18 downto 0) & key(79 downto 19); - keyout(79 downto 76)<= changed; - keyout(75 downto 20) <= keytemp(75 downto 20); - keyout(19 downto 15)<= keytemp(19 downto 15) xor num; - keyout(14 downto 0) <= keytemp(14 downto 0); - end Behavioral; \ No newline at end of file Index: PureTesting/AsyncMux.vhd =================================================================== --- PureTesting/AsyncMux.vhd (revision 3) +++ PureTesting/AsyncMux.vhd (nonexistent) @@ -1,50 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 23:24:35 06/24/2013 --- Design Name: --- Module Name: AsyncMux - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity AsyncMux is - generic ( - width : integer := 64 - ); - port ( - input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); - input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); - ctrl : in STD_LOGIC; - output : out STD_LOGIC_VECTOR(width - 1 downto 0) - ); -end AsyncMux; - -architecture Behavioral of AsyncMux is - -begin - output <= input0 when (ctrl = '0') else - input1; -end Behavioral; - Index: PureTesting/kody.vhd =================================================================== --- PureTesting/kody.vhd (revision 3) +++ PureTesting/kody.vhd (nonexistent) @@ -1,15 +0,0 @@ --- Package File Template --- --- Purpose: This package defines supplemental types, subtypes, --- constants, and functions - - -library IEEE; -use IEEE.STD_LOGIC_1164.all; -package kody is - -- type for PresentStateMachine to control the datapath & circuit -- - type stany is (NOP, SM_START, SM_READY); - type stany_comm is (NOP, READ_DATA_KEY, DECODE_READ_KEY, MOVE_KEY, TEMP_STATE, TEMP2_STATE, TEMP_OUT, - NOP_FOR_KEY, READ_DATA_TEXT, DECODE_READ_TEXT, MOVE_TEXT, - PRESENT_ENCODE, WRITE_OUT, MOVE_OUT); -end kody; \ No newline at end of file Index: PureTesting/bench/vhdl/ShiftRegTB.vhd =================================================================== --- PureTesting/bench/vhdl/ShiftRegTB.vhd (nonexistent) +++ PureTesting/bench/vhdl/ShiftRegTB.vhd (revision 4) @@ -0,0 +1,134 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Test bench of shift register - nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +use work.RSAFinalizerProperties.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY ShiftRegTB IS +END ShiftRegTB; + +ARCHITECTURE behavior OF ShiftRegTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT ShiftReg +-- generic (length_1 : integer := WORD_LENGTH; +-- length_2 : integer := BYTE + GENERIC ( + length_1 : integer := BYTE; + length_2 : integer := WORD_LENGTH + ); + PORT( + input : in STD_LOGIC_VECTOR(7 downto 0); + --input : IN std_logic_vector(63 downto 0); + output : out STD_LOGIC_VECTOR(63 downto 0); + --output : OUT std_logic_vector(7 downto 0); + en : in STD_LOGIC; + shift : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); + END COMPONENT; + + + --Inputs + signal input : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); + --signal input : std_logic_vector(63 downto 0) := (others => '0'); + signal en : STD_LOGIC := '0'; + signal shift : STD_LOGIC := '0'; + signal clk : STD_LOGIC := '0'; + signal reset : STD_LOGIC := '0'; + + --Outputs + signal output : STD_LOGIC_VECTOR(63 downto 0); + --signal output : std_logic_vector(7 downto 0); + + -- Clock period definitions + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: ShiftReg PORT MAP ( + input => input, + output => output, + en => en, + shift => shift, + clk => clk, + reset => reset + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + reset <= '0'; + shift <= '0'; + input <= "10101010"; + --input <= "1111000011110000111100001111000011110000111100001111000011110000"; + wait for 100 ns; + reset <= '1'; + wait for clk_period*10; + en <= '1'; + wait for clk_period*1; + en <= '0'; + wait for clk_period*1; + shift <= '1'; + wait for clk_period*10; + assert false severity failure; + end process; + +END; Index: PureTesting/bench/vhdl/PresentCommTB.vhd =================================================================== --- PureTesting/bench/vhdl/PresentCommTB.vhd (nonexistent) +++ PureTesting/bench/vhdl/PresentCommTB.vhd (revision 4) @@ -0,0 +1,374 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- This test bench simulate data transfer between PC and ---- +---- PresentComm core. All test data were generated in another ---- +---- program and textio was used for processing. Test bench is for ---- +---- to distinct data sets. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE std.textio.all; +USE work.txt_util.all; +USE ieee.std_logic_textio.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY PresentCommTB IS +END PresentCommTB; + +ARCHITECTURE behavior OF PresentCommTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT PresentComm + PORT( + DATA_RXD : IN std_logic; + CLK : IN std_logic; + RESET : IN std_logic; + DATA_TXD : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal DATA_RXD : std_logic := '0'; + signal CLK : std_logic := '0'; + signal RESET : std_logic := '0'; + + --Outputs + signal DATA_TXD : std_logic; + + -- Clock period definitions + -- speed of DIGILENT board and RS-232 core + constant CLK_period : time := 20 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: PresentComm PORT MAP ( + DATA_RXD => DATA_RXD, + CLK => CLK, + RESET => RESET, + DATA_TXD => DATA_TXD + ); + + -- Clock process definitions + CLK_process :process + begin + CLK <= '0'; + wait for CLK_period/2; + CLK <= '1'; + wait for CLK_period/2; + end process; + + + -- Stimulus process + stim_proc: process + + -- Variables + file txt :text is in "test/data.txt"; + file key :text is in "test/key.txt"; + file txt2 :text is in "test/data2.txt"; + file key2 :text is in "test/key2.txt"; + + variable line_in : line; + variable line_content : string(1 to 8); + variable data : STD_LOGIC; + + begin + + DATA_RXD <= '1'; + RESET <= '1'; + wait for 1000 ns; + RESET <= '0'; + + wait for CLK_period*10; + + -- Reading first 'data' file each "segment" is one bit of serial data + while not (endfile(txt)) loop + readline(txt, line_in); -- info line + read(line_in, line_content); + report line_content; + + DATA_RXD <= '0'; -- start bit + -- this amount is due to estimation of period of time needed for sending + -- one bit in RS-232 with 115 200 bps bandwith + wait for 8.75 us; + + readline(txt, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt, line_in); + read(line_in, data); + DATA_RXD <= data; -- parity bit + wait for 8.75 us; + + report "End of byte"; + DATA_RXD <= '1'; -- stop bit + wait for 100 us; + end loop; + + -- Reading first 'key' file each "segment" is one bit of serial data + while not (endfile(key)) loop + readline(key, line_in); -- info line + read(line_in, line_content); + report line_content; + + DATA_RXD <= '0'; -- start bit + wait for 8.75 us; + + readline(key, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key, line_in); + read(line_in, data); + DATA_RXD <= data; -- parity bit + wait for 8.75 us; + + report "End of byte"; + DATA_RXD <= '1'; -- stop bit + wait for 100 us; + end loop; + + -- Cipher counting and sending result + wait for 2000 us; + + -- Reading second 'data2' file each "segment" is one bit of serial data + while not (endfile(txt2)) loop + readline(txt2, line_in); -- info line + read(line_in, line_content); + report line_content; + + DATA_RXD <= '0'; -- start bit + wait for 8.75 us; + + readline(txt2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(txt2, line_in); + read(line_in, data); + DATA_RXD <= data; -- parity bit + wait for 8.75 us; + + report "Koniec bajtu"; + DATA_RXD <= '1'; -- stop bit + wait for 100 us; + end loop; + + -- Reading second 'key2' file each "segment" is one bit of serial data + while not (endfile(key2)) loop + readline(key2, line_in); -- info line + read(line_in, line_content); + report line_content; + + DATA_RXD <= '0'; -- start bit + wait for 8.75 us; + + readline(key2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key2, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(key2, line_in); + read(line_in, data); + DATA_RXD <= data; -- parity bit + wait for 8.75 us; + + report "Koniec bajtu"; + DATA_RXD <= '1'; -- stop bit + wait for 100 us; + end loop; + + -- Cipher counting and sending result + wait for 2000 us; + + assert false severity failure; + end process; + +END; Index: PureTesting/bench/vhdl/sLayerTB.vhd =================================================================== --- PureTesting/bench/vhdl/sLayerTB.vhd (nonexistent) +++ PureTesting/bench/vhdl/sLayerTB.vhd (revision 4) @@ -0,0 +1,111 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Substitution layer test bench of Present encoder. ---- +---- Nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + +ENTITY sLayerTB IS +END sLayerTB; + +ARCHITECTURE behavior OF sLayerTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT slayer + PORT( + input : IN std_logic_vector(3 downto 0); + output : OUT std_logic_vector(3 downto 0) + ); + END COMPONENT; + + + --Inputs + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --BiDirs + signal input : std_logic_vector(3 downto 0); + signal output : std_logic_vector(3 downto 0); + + -- Clock period definitions + constant clk_period : time := 1ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: slayer PORT MAP ( + input => input, + output => output + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + reset <= '1'; + wait for 100ns; + reset <= '0'; + wait for clk_period; + input <= x"0"; + wait for clk_period; + input <= x"A"; + wait for clk_period; + input <= x"F"; + wait for clk_period; + -- insert stimulus here + assert false severity failure; + end process; + +END; \ No newline at end of file Index: PureTesting/bench/vhdl/PresentTB.vhd =================================================================== --- PureTesting/bench/vhdl/PresentTB.vhd (nonexistent) +++ PureTesting/bench/vhdl/PresentTB.vhd (revision 4) @@ -0,0 +1,150 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Test bench of Present encoder. Nothing special. Data taken---- +---- from http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY PresentTB IS +END PresentTB; + +ARCHITECTURE behavior OF PresentTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT PresentEnc + PORT( + plaintext : IN std_logic_vector(63 downto 0); + key : IN std_logic_vector(79 downto 0); + ciphertext : OUT std_logic_vector(63 downto 0); + start : IN std_logic; + clk : IN std_logic; + reset : IN std_logic; + ready : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal plaintext : std_logic_vector(63 downto 0) := (others => '0'); + signal key : std_logic_vector(79 downto 0) := (others => '0'); + signal start : std_logic := '0'; + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --Outputs + signal ciphertext : std_logic_vector(63 downto 0); + signal ready : std_logic; + + -- Clock period definitions + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: PresentEnc PORT MAP ( + plaintext => plaintext, + key => key, + ciphertext => ciphertext, + start => start, + clk => clk, + reset => reset, + ready => ready + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + + reset <= '1'; + start <= '0'; + wait for 100 ns; + reset <= '0'; + + plaintext <= (others => '0'); + key <= (others => '0'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + plaintext <= (others => '0'); + key <= (others => '1'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + plaintext <= (others => '1'); + key <= (others => '0'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + plaintext <= (others => '1'); + key <= (others => '1'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + assert false severity failure; + + end process; + +END; Index: PureTesting/bench/vhdl/keyupdTB.vhd =================================================================== --- PureTesting/bench/vhdl/keyupdTB.vhd (nonexistent) +++ PureTesting/bench/vhdl/keyupdTB.vhd (revision 4) @@ -0,0 +1,122 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Key update test bench. It was much more used during ---- +---- inverse so data below are the same. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + +ENTITY keyupdTB IS +END keyupdTB; + +ARCHITECTURE behavior OF keyupdTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT keyupd + PORT( + key : IN std_logic_vector(79 downto 0); + num : IN std_logic_vector(4 downto 0); + keyout : OUT std_logic_vector(79 downto 0)--; + --clk, reset : std_logic + ); + END COMPONENT; + + + --Inputs + signal key : std_logic_vector(79 downto 0) := (others => '0'); + signal num : std_logic_vector(4 downto 0) := (others => '0'); + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --Outputs + signal keyout : std_logic_vector(79 downto 0); + + constant clk_period : time := 1ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: keyupd PORT MAP ( + key => key, + num => num, + keyout => keyout--, + --clk => clk, + --reset => reset + ); + + -- No clocks detected in port list. Replace clk below with + -- appropriate port name + + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + reset <= '1'; + wait for 100ns; + reset <='0'; + wait for clk_period; + key <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + num <= "00001"; + wait for clk_period; + key <= x"c0000000000000008000"; + num <= "00010"; + wait for clk_period; + key <= x"50001800000000010000"; + num <= "00011"; + wait for clk_period; + key <= x"8ba27a0eb8783ac96d59"; + num <= "11111"; + wait for clk_period; + assert false severity failure; + end process; +END; \ No newline at end of file Index: PureTesting/bench/vhdl/txt_util.vhd =================================================================== --- PureTesting/bench/vhdl/txt_util.vhd (nonexistent) +++ PureTesting/bench/vhdl/txt_util.vhd (revision 4) @@ -0,0 +1,586 @@ +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; + + +package txt_util is + + -- prints a message to the screen + procedure print(text: string); + + -- prints the message when active + -- useful for debug switches + procedure print(active: boolean; text: string); + + -- converts std_logic into a character + function chr(sl: std_logic) return character; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string; + + -- converts std_logic_vector into a string (binary base) + function str(slv: std_logic_vector) return string; + + -- converts boolean into a string + function str(b: boolean) return string; + + -- converts an integer into a single character + -- (can also be used for hex conversion and other bases) + function chr(int: integer) return character; + + -- converts integer into string using specified base + function str(int: integer; base: integer) return string; + + -- converts integer to string, using base 10 + function str(int: integer) return string; + + -- convert std_logic_vector into a string in hex format + function hstr(slv: std_logic_vector) return string; + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c: character) return character; + + -- convert a character to lower case + function to_lower(c: character) return character; + + -- convert a string to upper case + function to_upper(s: string) return string; + + -- convert a string to lower case + function to_lower(s: string) return string; + + + + -- functions to convert strings into other formats + -------------------------------------------------- + + -- converts a character into std_logic + function to_std_logic(c: character) return std_logic; + + -- converts a string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector; + + + + -- file I/O + ----------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string); + + -- print string to a file and start new line + procedure print(file out_file: TEXT; + new_string: in string); + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character); + +end txt_util; + + + + +package body txt_util is + + + + + -- prints text to the screen + + procedure print(text: string) is + variable msg_line: line; + begin + write(msg_line, text); + writeline(output, msg_line); + end print; + + + + + -- prints text to the screen when active + + procedure print(active: boolean; text: string) is + begin + if active then + print(text); + end if; + end print; + + + -- converts std_logic into a character + + function chr(sl: std_logic) return character is + variable c: character; + begin + case sl is + when 'U' => c:= 'U'; + when 'X' => c:= 'X'; + when '0' => c:= '0'; + when '1' => c:= '1'; + when 'Z' => c:= 'Z'; + when 'W' => c:= 'W'; + when 'L' => c:= 'L'; + when 'H' => c:= 'H'; + when '-' => c:= '-'; + end case; + return c; + end chr; + + + + -- converts std_logic into a string (1 to 1) + + function str(sl: std_logic) return string is + variable s: string(1 to 1); + begin + s(1) := chr(sl); + return s; + end str; + + + + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + + function str(slv: std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r := 1; + for i in slv'range loop + result(r) := chr(slv(i)); + r := r + 1; + end loop; + return result; + end str; + + + function str(b: boolean) return string is + + begin + if b then + return "true"; + else + return "false"; + end if; + end str; + + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function chr(int: integer) return character is + variable c: character; + begin + case int is + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; + end case; + return c; + end chr; + + + + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function str(int: integer; base: integer) return string is + + variable temp: string(1 to 10); + variable num: integer; + variable abs_int: integer; + variable len: integer := 1; + variable power: integer := 1; + + begin + + -- bug fix for negative numbers + abs_int := abs(int); + + num := abs_int; + + while num >= base loop -- Determine how many + len := len + 1; -- characters required + num := num / base; -- to represent the + end loop ; -- number. + + for i in len downto 1 loop -- Convert the number to + temp(i) := chr(abs_int/power mod base); -- a string starting + power := power * base; -- with the right hand + end loop ; -- side. + + -- return result and add sign if required + if int < 0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; + + end str; + + + -- convert integer to string, using base 10 + function str(int: integer) return string is + + begin + + return str(int, 10) ; + + end str; + + + + -- converts a std_logic_vector into a hex string. + function hstr(slv: std_logic_vector) return string is + variable hexlen: integer; + variable longslv : std_logic_vector(67 downto 0) := (others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen := (slv'left+1)/4; + if (slv'left+1) mod 4 /= 0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen -1) downto 0 loop + fourbit := longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen -I) := '0'; + when "0001" => hex(hexlen -I) := '1'; + when "0010" => hex(hexlen -I) := '2'; + when "0011" => hex(hexlen -I) := '3'; + when "0100" => hex(hexlen -I) := '4'; + when "0101" => hex(hexlen -I) := '5'; + when "0110" => hex(hexlen -I) := '6'; + when "0111" => hex(hexlen -I) := '7'; + when "1000" => hex(hexlen -I) := '8'; + when "1001" => hex(hexlen -I) := '9'; + when "1010" => hex(hexlen -I) := 'A'; + when "1011" => hex(hexlen -I) := 'B'; + when "1100" => hex(hexlen -I) := 'C'; + when "1101" => hex(hexlen -I) := 'D'; + when "1110" => hex(hexlen -I) := 'E'; + when "1111" => hex(hexlen -I) := 'F'; + when "ZZZZ" => hex(hexlen -I) := 'z'; + when "UUUU" => hex(hexlen -I) := 'u'; + when "XXXX" => hex(hexlen -I) := 'x'; + when others => hex(hexlen -I) := '?'; + end case; + end loop; + return hex(1 to hexlen); + end hstr; + + + + -- functions to manipulate strings + ----------------------------------- + + + -- convert a character to upper case + + function to_upper(c: character) return character is + + variable u: character; + + begin + + case c is + when 'a' => u := 'A'; + when 'b' => u := 'B'; + when 'c' => u := 'C'; + when 'd' => u := 'D'; + when 'e' => u := 'E'; + when 'f' => u := 'F'; + when 'g' => u := 'G'; + when 'h' => u := 'H'; + when 'i' => u := 'I'; + when 'j' => u := 'J'; + when 'k' => u := 'K'; + when 'l' => u := 'L'; + when 'm' => u := 'M'; + when 'n' => u := 'N'; + when 'o' => u := 'O'; + when 'p' => u := 'P'; + when 'q' => u := 'Q'; + when 'r' => u := 'R'; + when 's' => u := 'S'; + when 't' => u := 'T'; + when 'u' => u := 'U'; + when 'v' => u := 'V'; + when 'w' => u := 'W'; + when 'x' => u := 'X'; + when 'y' => u := 'Y'; + when 'z' => u := 'Z'; + when others => u := c; + end case; + + return u; + + end to_upper; + + + -- convert a character to lower case + + function to_lower(c: character) return character is + + variable l: character; + + begin + + case c is + when 'A' => l := 'a'; + when 'B' => l := 'b'; + when 'C' => l := 'c'; + when 'D' => l := 'd'; + when 'E' => l := 'e'; + when 'F' => l := 'f'; + when 'G' => l := 'g'; + when 'H' => l := 'h'; + when 'I' => l := 'i'; + when 'J' => l := 'j'; + when 'K' => l := 'k'; + when 'L' => l := 'l'; + when 'M' => l := 'm'; + when 'N' => l := 'n'; + when 'O' => l := 'o'; + when 'P' => l := 'p'; + when 'Q' => l := 'q'; + when 'R' => l := 'r'; + when 'S' => l := 's'; + when 'T' => l := 't'; + when 'U' => l := 'u'; + when 'V' => l := 'v'; + when 'W' => l := 'w'; + when 'X' => l := 'x'; + when 'Y' => l := 'y'; + when 'Z' => l := 'z'; + when others => l := c; + end case; + + return l; + + end to_lower; + + + + -- convert a string to upper case + + function to_upper(s: string) return string is + + variable uppercase: string (s'range); + + begin + + for i in s'range loop + uppercase(i):= to_upper(s(i)); + end loop; + return uppercase; + + end to_upper; + + + + -- convert a string to lower case + + function to_lower(s: string) return string is + + variable lowercase: string (s'range); + + begin + + for i in s'range loop + lowercase(i):= to_lower(s(i)); + end loop; + return lowercase; + + end to_lower; + + + +-- functions to convert strings into other types + + +-- converts a character into a std_logic + +function to_std_logic(c: character) return std_logic is + variable sl: std_logic; + begin + case c is + when 'U' => + sl := 'U'; + when 'X' => + sl := 'X'; + when '0' => + sl := '0'; + when '1' => + sl := '1'; + when 'Z' => + sl := 'Z'; + when 'W' => + sl := 'W'; + when 'L' => + sl := 'L'; + when 'H' => + sl := 'H'; + when '-' => + sl := '-'; + when others => + sl := 'X'; + end case; + return sl; + end to_std_logic; + + +-- converts a string into std_logic_vector + +function to_std_logic_vector(s: string) return std_logic_vector is + variable slv: std_logic_vector(s'high-s'low downto 0); + variable k: integer; +begin + k := s'high-s'low; + for i in s'range loop + slv(k) := to_std_logic(s(i)); + k := k - 1; + end loop; + return slv; +end to_std_logic_vector; + + + + + + +---------------- +-- file I/O -- +---------------- + + + +-- read variable length string from input file + +procedure str_read(file in_file: TEXT; + res_string: out string) is + + variable l: line; + variable c: character; + variable is_string: boolean; + + begin + + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i) := ' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + read(l, c, is_string); + res_string(i) := c; + if not is_string then -- found end of line + exit; + end if; + end loop; + +end str_read; + + +-- print string to a file +procedure print(file out_file: TEXT; + new_string: in string) is + + variable l: line; + + begin + + write(l, new_string); + writeline(out_file, l); + +end print; + + +-- print character to a file and start new line +procedure print(file out_file: TEXT; + char: in character) is + + variable l: line; + + begin + + write(l, char); + writeline(out_file, l); + +end print; + + + +-- appends contents of a string to a file until line feed occurs +-- (LF is considered to be the end of the string) + +procedure str_write(file out_file: TEXT; + new_string: in string) is + begin + + for i in new_string'range loop + print(out_file, new_string(i)); + if new_string(i) = LF then -- end of string + exit; + end if; + end loop; + +end str_write; + + + + +end txt_util; + + + + Index: PureTesting/bench/vhdl =================================================================== --- PureTesting/bench/vhdl (nonexistent) +++ PureTesting/bench/vhdl (revision 4)

PureTesting/bench/vhdl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: PureTesting/bench =================================================================== --- PureTesting/bench (nonexistent) +++ PureTesting/bench (revision 4)

PureTesting/bench Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: PureTesting/rtl/vhdl/counter.vhd =================================================================== --- PureTesting/rtl/vhdl/counter.vhd (nonexistent) +++ PureTesting/rtl/vhdl/counter.vhd (revision 4) @@ -0,0 +1,73 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Typical construction of 5bit counter. It is counting up. ---- +---- Nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity counter is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); +end counter; + +architecture Behavioral of counter is + signal cnt : std_logic_vector(w_5-1 downto 0) := (others => '0'); + begin + licznik : process (clk, reset, cnt) + begin + if (reset = '1') then + cnt <= (others => '0'); + elsif (clk'Event and clk = '1') then + if (cnt_res = '1') then + cnt <= cnt + 1; + end if; + end if; + end process licznik; + num <= cnt; + end Behavioral; + Index: PureTesting/rtl/vhdl/slayer.vhd =================================================================== --- PureTesting/rtl/vhdl/slayer.vhd (nonexistent) +++ PureTesting/rtl/vhdl/slayer.vhd (revision 4) @@ -0,0 +1,81 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Substitution layer of Present cipher. Simple logic. ---- +---- For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity slayer is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); +end slayer; + +architecture Behavioral of slayer is + + begin + output <= x"C" when input = x"0" else + x"5" when input = x"1" else + x"6" when input = x"2" else + x"B" when input = x"3" else + x"9" when input = x"4" else + x"0" when input = x"5" else + x"A" when input = x"6" else + x"D" when input = x"7" else + x"3" when input = x"8" else + x"E" when input = x"9" else + x"F" when input = x"A" else + x"8" when input = x"B" else + x"4" when input = x"C" else + x"7" when input = x"D" else + x"1" when input = x"E" else + x"2" when input = x"F" else + "ZZZZ"; + end Behavioral; \ No newline at end of file Index: PureTesting/rtl/vhdl/keyupd.vhd =================================================================== --- PureTesting/rtl/vhdl/keyupd.vhd (nonexistent) +++ PureTesting/rtl/vhdl/keyupd.vhd (revision 4) @@ -0,0 +1,86 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Key update module for present cipher it is 'signal ---- +---- mixing' made by rotation left by 61 bits, using one s-box, ---- +---- and output of the counter. For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity keyupd is + generic( + w_80: integer := 80; + w_5 : integer := 5; + w_4 : integer := 4); + port( + key : in std_logic_vector(w_80-1 downto 0); + num : in std_logic_vector(w_5-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); +end keyupd; + +architecture Behavioral of keyupd is + + component slayer is + generic(w_4: integer := 4); + port( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + signal changed : std_logic_vector(w_4-1 downto 0); + signal changin : std_logic_vector(w_4-1 downto 0); + signal keytemp : std_logic_vector(w_80-1 downto 0); + + begin + s1: slayer port map(input => changin, output => changed); + changin <= keytemp(79 downto 76); + keytemp <= key(18 downto 0) & key(79 downto 19); + keyout(79 downto 76)<= changed; + keyout(75 downto 20) <= keytemp(75 downto 20); + keyout(19 downto 15)<= keytemp(19 downto 15) xor num; + keyout(14 downto 0) <= keytemp(14 downto 0); + end Behavioral; \ No newline at end of file Index: PureTesting/rtl/vhdl/PresentEnc.vhd =================================================================== --- PureTesting/rtl/vhdl/PresentEnc.vhd (nonexistent) +++ PureTesting/rtl/vhdl/PresentEnc.vhd (revision 4) @@ -0,0 +1,220 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Top level of present encoder. For more information see ---- +---- below and http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity PresentEnc is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port( + plaintext : in std_logic_vector(w_64 - 1 downto 0); + key : in std_logic_vector(w_80 - 1 downto 0); + ciphertext : out std_logic_vector(w_64 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end PresentEnc; + +architecture Behavioral of PresentEnc is + + component Reg is + generic(width : integer := w_64); + port( + input : in STD_LOGIC_VECTOR(width - 1 downto 0); + output : out STD_LOGIC_VECTOR(width - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); + end component Reg; + + component AsyncMux is + generic ( + width : integer := 64 + ); + port ( + input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); + input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(width - 1 downto 0) + ); + end component AsyncMux; + + component PresentStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); + end component; + + -- substitution layer for decoding + component slayer is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + -- permutation layer for decoding + component pLayer is + generic(w_64 : integer := 64); + port( + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_64-1 downto 0) + ); + end component; + + -- key update for decoding + component keyupd is + generic( + w_5 : integer := 5; + w_80: integer := 80 + ); + port( + num : in std_logic_vector(w_5-1 downto 0); + key : in std_logic_vector(w_80-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); + end component; + + -- counter for decoding. It is counting up!!! + component counter is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); + end component; + + -- signals + + signal keynum : std_logic_vector (w_5-1 downto 0); + signal toXor, ciph, P, Pout, textToReg : std_logic_vector (w_64-1 downto 0); + signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0); + signal ready_sig, mux_ctrl, cnt_res, RegEn : std_logic; + + begin + + -- connections + + mux_64: AsyncMux generic map(width => w_64) port map( + input0 => plaintext, + input1 => Pout, + ctrl => mux_ctrl, + output => textToReg + ); + regText : Reg generic map(width => w_64) port map( + input => textToReg, + output => toXor, + enable => RegEn, + clk => clk, + reset => reset + ); + mux_80: AsyncMux generic map(width => w_80) port map( + input0 => key, + input1 => kupd, + ctrl => mux_ctrl, + output => keyToReg + ); + regKey : Reg generic map(width => w_80) port map( + input => keyToReg, + output => keyfout, + enable => RegEn, + clk => clk, + reset => reset + ); + slayers : for N in 15 downto 0 generate + s_x: slayer port map( + input => ciph(4*N+3 downto 4*N), + output => P(4*N+3 downto 4*N) + ); + end generate slayers; + p1: pLayer port map( + input => P, + output => Pout + ); + mixer: keyupd port map( + key => keyfout, + num => keynum, + keyout => kupd + ); + SM: PresentStateMachine port map( + start => start, + reset => reset, + ready => ready_sig, + cnt_res => cnt_res, + ctrl_mux => mux_ctrl, + clk => clk, + num => keynum, + RegEn => RegEn + ); + count: counter port map( + clk => clk, + reset => reset, + cnt_res => cnt_res, + num => keynum + ); + ciph <= toXor xor keyfout(79 downto 16); + ciphertext <= ciph; + ready <= ready_sig; +end Behavioral; Index: PureTesting/rtl/vhdl/PresentStateMachine.vhd =================================================================== --- PureTesting/rtl/vhdl/PresentStateMachine.vhd (nonexistent) +++ PureTesting/rtl/vhdl/PresentStateMachine.vhd (revision 4) @@ -0,0 +1,130 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- State machine for Present encoder. For more informations ---- +---- see below. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.kody.ALL; + +entity PresentStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); +end PresentStateMachine; + +architecture Behavioral of PresentStateMachine is + + signal state : stany; + signal next_state : stany; + + begin + States : process(state, start, num) + begin + case state is + ---- Waiting for start + when NOP => + ready <= '0'; + cnt_res <= '0'; + ctrl_mux <= '0'; + RegEn <= '0'; + if (start = '1') then + next_state <= SM_START; + else + next_state <= NOP; + end if; + -- Decoding + when SM_START => + ready <= '0'; + RegEn <= '1'; + cnt_res <= '1'; + if (start = '1') then + -- control during first start + if (num = "00000") then + ctrl_mux <= '0'; + next_state <= SM_START; + -- last iteration + elsif (num = "11111") then + ctrl_mux <= '1'; + next_state <= SM_READY; + -- rest iterations + else + ctrl_mux <= '1'; + next_state <= SM_START; + end if; + else + ctrl_mux <= '0'; + next_state <= NOP; + end if; + -- Decoding end + when SM_READY => + cnt_res <= '0'; + RegEn <= '0'; + ready <= '1'; + if (start = '1') then + ctrl_mux <= '1'; + next_state <= SM_READY; + else + ctrl_mux <= '0'; + next_state <= NOP; + end if; + end case; + end process States; + + SM : process (clk, reset) + begin + if (reset = '1') then + state <= NOP; + elsif (clk'Event and clk = '1') then + state <= next_state; + end if; + end process SM; + + end Behavioral; + Index: PureTesting/rtl/vhdl/kody.vhd =================================================================== --- PureTesting/rtl/vhdl/kody.vhd (nonexistent) +++ PureTesting/rtl/vhdl/kody.vhd (revision 4) @@ -0,0 +1,58 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- This file contains types and constant used by this ---- +---- implementation of Present project ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +package kody is + -- type for PresentStateMachine to control the datapath & circuit -- + type stany is (NOP, SM_START, SM_READY); + type stany_comm is (NOP, READ_DATA_KEY, DECODE_READ_KEY, MOVE_KEY, TEMP_STATE, TEMP2_STATE, TEMP_OUT, + NOP_FOR_KEY, READ_DATA_TEXT, DECODE_READ_TEXT, MOVE_TEXT, + PRESENT_ENCODE, WRITE_OUT, MOVE_OUT); +end kody; \ No newline at end of file Index: PureTesting/rtl/vhdl/AsyncMux.vhd =================================================================== --- PureTesting/rtl/vhdl/AsyncMux.vhd (nonexistent) +++ PureTesting/rtl/vhdl/AsyncMux.vhd (revision 4) @@ -0,0 +1,73 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Simple construction of multiplexer. Nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity AsyncMux is + generic ( + width : integer := 64 + ); + port ( + input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); + input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(width - 1 downto 0) + ); +end AsyncMux; + +architecture Behavioral of AsyncMux is + +begin + output <= input0 when (ctrl = '0') else + input1; +end Behavioral; + Index: PureTesting/rtl/vhdl/RS232RefComp.vhd =================================================================== --- PureTesting/rtl/vhdl/RS232RefComp.vhd (nonexistent) +++ PureTesting/rtl/vhdl/RS232RefComp.vhd (revision 4) @@ -0,0 +1,406 @@ +------------------------------------------------------------------------ +-- RS232RefCom.vhd +------------------------------------------------------------------------ +-- Author: Dan Pederson +-- Copyright 2004 Digilent, Inc. +------------------------------------------------------------------------ +-- Description: This file defines a UART which tranfers data from +-- serial form to parallel form and vice versa. +------------------------------------------------------------------------ +-- Revision History: +-- 07/15/04 (Created) DanP +-- 02/25/08 (Created) ClaudiaG: made use of the baudDivide constant +-- in the Clock Dividing Processes +------------------------------------------------------------------------ + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Rs232RefComp is + Port ( + TXD : out std_logic := '1'; + RXD : in std_logic; + CLK : in std_logic; --Master Clock + DBIN : in std_logic_vector (7 downto 0); --Data Bus in + DBOUT : out std_logic_vector (7 downto 0); --Data Bus out + RDA : inout std_logic; --Read Data Available + TBE : inout std_logic := '1'; --Transfer Bus Empty + RD : in std_logic; --Read Strobe + WR : in std_logic; --Write Strobe + PE : out std_logic; --Parity Error Flag + FE : out std_logic; --Frame Error Flag + OE : out std_logic; --Overwrite Error Flag + RST : in std_logic := '0'); --Master Reset +end Rs232RefComp; + +architecture Behavioral of Rs232RefComp is +------------------------------------------------------------------------ +-- Component Declarations +------------------------------------------------------------------------ + +------------------------------------------------------------------------ +-- Local Type Declarations +------------------------------------------------------------------------ + --Receive state machine + type rstate is ( + strIdle, --Idle state + strEightDelay, --Delays for 8 clock cycles + strGetData, --Shifts in the 8 data bits, and checks parity + strCheckStop --Sets framing error flag if Stop bit is wrong + ); + + type tstate is ( + sttIdle, --Idle state + sttTransfer, --Move data into shift register + sttShift --Shift out data + ); + + type TBEstate is ( + stbeIdle, + stbeSetTBE, + stbeWaitLoad, + stbeWaitWrite + ); + + +------------------------------------------------------------------------ +-- Signal Declarations +------------------------------------------------------------------------ + constant baudDivide : std_logic_vector(7 downto 0) := "00001101"; --Baud Rate dividor, set now for a rate of 9600. + --Found by dividing 50MHz by 9600 and 16. + signal rdReg : std_logic_vector(7 downto 0) := "00000000"; --Receive holding register + signal rdSReg : std_logic_vector(9 downto 0) := "1111111111"; --Receive shift register + signal tfReg : std_logic_vector(7 downto 0); --Transfer holding register + signal tfSReg : std_logic_vector(10 downto 0) := "11111111111"; --Transfer shift register + signal clkDiv : std_logic_vector(8 downto 0) := "000000000"; --used for rClk + signal rClkDiv : std_logic_vector(3 downto 0) := "0000"; --used for tClk + signal ctr : std_logic_vector(3 downto 0) := "0000"; --used for delay times + signal tfCtr : std_logic_vector(3 downto 0) := "0000"; --used to delay in transfer + signal rClk : std_logic := '0'; --Receiving Clock + signal tClk : std_logic; --Transfering Clock + signal dataCtr : std_logic_vector(3 downto 0) := "0000"; --Counts the number of read data bits + signal parError: std_logic; --Parity error bit + signal frameError: std_logic; --Frame error bit + signal CE : std_logic; --Clock enable for the latch + signal ctRst : std_logic := '0'; + signal load : std_logic := '0'; + signal shift : std_logic := '0'; + signal par : std_logic; + signal tClkRST : std_logic := '0'; + signal rShift : std_logic := '0'; + signal dataRST : std_logic := '0'; + signal dataIncr: std_logic := '0'; + + signal strCur : rstate := strIdle; --Current state in the Receive state machine + signal strNext : rstate; --Next state in the Receive state machine + signal sttCur : tstate := sttIdle; --Current state in the Transfer state machine + signal sttNext : tstate; --Next state in the Transfer staet machine + signal stbeCur : TBEstate := stbeIdle; + signal stbeNext: TBEstate; + +------------------------------------------------------------------------ +-- Module Implementation +------------------------------------------------------------------------ + +begin + frameError <= not rdSReg(9); + parError <= not ( rdSReg(8) xor (((rdSReg(0) xor rdSReg(1)) xor (rdSReg(2) xor rdSReg(3))) xor ((rdSReg(4) xor rdSReg(5)) xor (rdSReg(6) xor rdSReg(7)))) ); + DBOUT <= rdReg; + tfReg <= DBIN; + par <= not ( ((tfReg(0) xor tfReg(1)) xor (tfReg(2) xor tfReg(3))) xor ((tfReg(4) xor tfReg(5)) xor (tfReg(6) xor tfReg(7))) ); + +--Clock Dividing Functions-- + + process (CLK, clkDiv) --set up clock divide for rClk + begin + if (Clk = '1' and Clk'event) then + if (clkDiv = baudDivide) then + clkDiv <= "000000000"; + else + clkDiv <= clkDiv +1; + end if; + end if; + end process; + + process (clkDiv, rClk, CLK) --Define rClk + begin + if CLK = '1' and CLK'Event then + if clkDiv = baudDivide then + rClk <= not rClk; + else + rClk <= rClk; + end if; + end if; + end process; + + process (rClk) --set up clock divide for tClk + begin + if (rClk = '1' and rClk'event) then + rClkDiv <= rClkDiv +1; + end if; + end process; + + tClk <= rClkDiv(3); --define tClk + + process (rClk, ctRst) --set up a counter based on rClk + begin + if rClk = '1' and rClk'Event then + if ctRst = '1' then + ctr <= "0000"; + else + ctr <= ctr +1; + end if; + end if; + end process; + + process (tClk, tClkRST) --set up a counter based on tClk + begin + if (tClk = '1' and tClk'event) then + if tClkRST = '1' then + tfCtr <= "0000"; + else + tfCtr <= tfCtr +1; + end if; + end if; + end process; + + --This process controls the error flags-- + process (rClk, RST, RD, CE) + begin + if RD = '1' or RST = '1' then + FE <= '0'; + OE <= '0'; + RDA <= '0'; + PE <= '0'; + elsif rClk = '1' and rClk'event then + if CE = '1' then + FE <= frameError; + OE <= RDA; + RDA <= '1'; + PE <= parError; + rdReg(7 downto 0) <= rdSReg (7 downto 0); + end if; + end if; + end process; + + --This process controls the receiving shift register-- + process (rClk, rShift) + begin + if rClk = '1' and rClk'Event then + if rShift = '1' then + rdSReg <= (RXD & rdSReg(9 downto 1)); + end if; + end if; + end process; + + --This process controls the dataCtr to keep track of shifted values-- + process (rClk, dataRST) + begin + if (rClk = '1' and rClk'event) then + if dataRST = '1' then + dataCtr <= "0000"; + elsif dataIncr = '1' then + dataCtr <= dataCtr +1; + end if; + end if; + end process; + + --Receiving State Machine-- + process (rClk, RST) + begin + if rClk = '1' and rClk'Event then + if RST = '1' then + strCur <= strIdle; + else + strCur <= strNext; + end if; + end if; + end process; + + --This process generates the sequence of steps needed receive the data + + process (strCur, ctr, RXD, dataCtr, rdSReg, rdReg, RDA) + begin + case strCur is + + when strIdle => + dataIncr <= '0'; + rShift <= '0'; + dataRst <= '0'; + + CE <= '0'; + if RXD = '0' then + ctRst <= '1'; + strNext <= strEightDelay; + else + ctRst <= '0'; + strNext <= strIdle; + end if; + + when strEightDelay => + dataIncr <= '0'; + rShift <= '0'; + CE <= '0'; + + if ctr(2 downto 0) = "111" then + ctRst <= '1'; + dataRST <= '1'; + strNext <= strGetData; + else + ctRst <= '0'; + dataRST <= '0'; + strNext <= strEightDelay; + end if; + + when strGetData => + CE <= '0'; + dataRst <= '0'; + if ctr(3 downto 0) = "1111" then + ctRst <= '1'; + dataIncr <= '1'; + rShift <= '1'; + else + ctRst <= '0'; + dataIncr <= '0'; + rShift <= '0'; + end if; + + if dataCtr = "1010" then + strNext <= strCheckStop; + else + strNext <= strGetData; + end if; + + when strCheckStop => + dataIncr <= '0'; + rShift <= '0'; + dataRst <= '0'; + ctRst <= '0'; + + CE <= '1'; + strNext <= strIdle; + + end case; + + end process; + + --TBE State Machine-- + process (CLK, RST) + begin + if CLK = '1' and CLK'Event then + if RST = '1' then + stbeCur <= stbeIdle; + else + stbeCur <= stbeNext; + end if; + end if; + end process; + + --This process gererates the sequence of events needed to control the TBE flag-- + process (stbeCur, CLK, WR, DBIN, load) + begin + + case stbeCur is + + when stbeIdle => + TBE <= '1'; + if WR = '1' then + stbeNext <= stbeSetTBE; + else + stbeNext <= stbeIdle; + end if; + + when stbeSetTBE => + TBE <= '0'; + if load = '1' then + stbeNext <= stbeWaitLoad; + else + stbeNext <= stbeSetTBE; + end if; + + when stbeWaitLoad => + if load = '0' then + stbeNext <= stbeWaitWrite; + else + stbeNext <= stbeWaitLoad; + end if; + + when stbeWaitWrite => + if WR = '0' then + stbeNext <= stbeIdle; + else + stbeNext <= stbeWaitWrite; + end if; + end case; + end process; + + --This process loads and shifts out the transfer shift register-- + process (load, shift, tClk, tfSReg) + begin + TXD <= tfsReg(0); + if tClk = '1' and tClk'Event then + if load = '1' then + tfSReg (10 downto 0) <= ('1' & par & tfReg(7 downto 0) &'0'); + end if; + if shift = '1' then + + tfSReg (10 downto 0) <= ('1' & tfSReg(10 downto 1)); + end if; + end if; + end process; + + -- Transfer State Machine-- + process (tClk, RST) + begin + if (tClk = '1' and tClk'Event) then + if RST = '1' then + sttCur <= sttIdle; + else + sttCur <= sttNext; + end if; + end if; + end process; + + -- This process generates the sequence of steps needed transfer the data-- + process (sttCur, tfCtr, tfReg, TBE, tclk) + begin + + case sttCur is + + when sttIdle => + tClkRST <= '0'; + shift <= '0'; + load <= '0'; + if TBE = '1' then + sttNext <= sttIdle; + else + sttNext <= sttTransfer; + end if; + + when sttTransfer => + shift <= '0'; + load <= '1'; + tClkRST <= '1'; + sttNext <= sttShift; + + + when sttShift => + shift <= '1'; + load <= '0'; + tClkRST <= '0'; + if tfCtr = "1100" then + sttNext <= sttIdle; + else + sttNext <= sttShift; + end if; + end case; + end process; + +end Behavioral; \ No newline at end of file Index: PureTesting/rtl/vhdl/PresentCommImpl.ucf =================================================================== --- PureTesting/rtl/vhdl/PresentCommImpl.ucf (nonexistent) +++ PureTesting/rtl/vhdl/PresentCommImpl.ucf (revision 4) @@ -0,0 +1,7 @@ +NET "DATA_RXD" LOC= "R7" | IOSTANDARD= LVTTL | SLEW= FAST ; +NET "DATA_TXD" LOC= "M14" | IOSTANDARD= LVTTL | DRIVE= 8 | SLEW= FAST ; +NET "CLK" LOC= "C9" | IOSTANDARD= LVCMOS33 | SLEW= FAST ; +NET "CLK" TNM_NET = "clk_group"; +TIMESPEC "TS_CLK" = PERIOD "clk_group" 20 ns HIGH 40%; +NET "RESET" LOC= "K17" | IOSTANDARD= LVTTL | PULLDOWN; +SYSTEM_JITTER = 1 ns; \ No newline at end of file Index: PureTesting/rtl/vhdl/ShiftReg.vhd =================================================================== --- PureTesting/rtl/vhdl/ShiftReg.vhd (nonexistent) +++ PureTesting/rtl/vhdl/ShiftReg.vhd (revision 4) @@ -0,0 +1,95 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Shift register with parallel input/output. Nothing special---- +---- except configuration - it enables wider input than output and ---- +---- inverse config. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ShiftReg is + generic ( + length_1 : integer := 8; + length_2 : integer := 64; + internal_data : integer := 64 + ); + port ( + input : in STD_LOGIC_VECTOR(length_1 - 1 downto 0); + output : out STD_LOGIC_VECTOR(length_2 - 1 downto 0); + en : in STD_LOGIC; + shift : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); +end ShiftReg; + +architecture Behavioral of ShiftReg is + +signal data : STD_LOGIC_VECTOR(internal_data - 1 downto 0); + +begin + reg : process (clk, reset, data) + begin + if (clk'event and clk = '1') then + if (reset = '1') then + data <= (others => '0'); + elsif (en = '1') then + data(internal_data - 1 downto internal_data - length_1) <= input; + else + if (shift = '1') then + data <= '0' & data(internal_data - 1 downto 1); + end if; + end if; + end if; + output <= data(length_2 - 1 downto 0); + end process reg; + +end Behavioral; + Index: PureTesting/rtl/vhdl/PresentComm.vhd =================================================================== --- PureTesting/rtl/vhdl/PresentComm.vhd (nonexistent) +++ PureTesting/rtl/vhdl/PresentComm.vhd (revision 4) @@ -0,0 +1,273 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Top level part of 'pure' Present cipher with RS-232 ---- +---- communication with PC. It contains all suitable components ---- +---- with links between each others. For more informations see ---- +---- below and http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity PresentComm is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_64: integer := 64; + w_80: integer := 80 + ); + port ( + DATA_RXD : in STD_LOGIC; + CLK : in STD_LOGIC; + RESET : in STD_LOGIC; + DATA_TXD : out STD_LOGIC + ); +end PresentComm; + +architecture Behavioral of PresentComm is + +-- Shift register is used for translation 8 bit input of RS-232 data (both RXD and TXD) +-- 64 bit and 80 bit data in dependence of the data type (key, text, result). SM ocntrols it +-- If data are not fully retrieved, last received data are shifted by 8 bits. This is repeated +-- 8 times for text and output value (8 x 8 bits) or 10 times (10 x 8 bits) for key. +-- Width of the word is fully configurable. +component ShiftReg is + generic ( + length_1 : integer := 8; + length_2 : integer := w_64; + internal_data : integer := w_64 + ); + port ( + input : in STD_LOGIC_VECTOR(length_1 - 1 downto 0); + output : out STD_LOGIC_VECTOR(length_2 - 1 downto 0); + en : in STD_LOGIC; + shift : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); +end component ShiftReg; + +-- Component given by Digilent in Eval board for RS-232 communication +component Rs232RefComp is + Port ( + TXD : out std_logic := '1'; + RXD : in std_logic; + CLK : in std_logic; --Master Clock + DBIN : in std_logic_vector (7 downto 0); --Data Bus in + DBOUT : out std_logic_vector (7 downto 0); --Data Bus out + RDA : inout std_logic; --Read Data Available + TBE : inout std_logic := '1'; --Transfer Bus Empty + RD : in std_logic; --Read Strobe + WR : in std_logic; --Write Strobe + PE : out std_logic; --Parity Error Flag + FE : out std_logic; --Frame Error Flag + OE : out std_logic; --Overwrite Error Flag + RST : in std_logic := '0'); --Master Reset +end component Rs232RefComp; + +-- Present cipher - nothing special +component PresentEnc is + generic ( + w_64: integer := 64; + w_80: integer := 80 + ); + port( + plaintext : in std_logic_vector(w_64 - 1 downto 0); + key : in std_logic_vector(w_80 - 1 downto 0); + ciphertext : out std_logic_vector(w_64 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end component PresentEnc; + +-- State machine +component PresentCommSM is + port ( + clk : in STD_LOGIC; + reset : in STD_LOGIC; + RDAsig : in STD_LOGIC; + TBEsig : in STD_LOGIC; + RDsig : out STD_LOGIC; + WRsig : out STD_LOGIC; + textDataEn : out STD_LOGIC; + textDataShift : out STD_LOGIC; + keyDataEn : out STD_LOGIC; + keyDataShift : out STD_LOGIC; + ciphDataEn : out STD_LOGIC; + ciphDataShift : out STD_LOGIC; + startSig : out STD_LOGIC; + readySig : in STD_LOGIC + ); +end component PresentCommSM; + +--Signals +signal keyText : STD_LOGIC_VECTOR(w_80 - 1 downto 0); +signal plaintext : STD_LOGIC_VECTOR(w_64 - 1 downto 0); +signal ciphertext : STD_LOGIC_VECTOR(w_64 - 1 downto 0); + +signal dataTXD : STD_LOGIC_VECTOR(7 downto 0); +signal dataRXD : STD_LOGIC_VECTOR(7 downto 0); +signal RDAsig : STD_LOGIC; +signal TBEsig : STD_LOGIC; +signal RDsig : STD_LOGIC; +signal WRsig : STD_LOGIC; +signal PEsig : STD_LOGIC; +signal FEsig : STD_LOGIC; +signal OEsig : STD_LOGIC; + +signal keyDataEn : STD_LOGIC; +signal keyDataShift : STD_LOGIC; + +signal textDataEn : STD_LOGIC; +signal textDataShift : STD_LOGIC; + +signal ciphDataEn : STD_LOGIC; +signal ciphDataShift : STD_LOGIC; + +signal startSig : STD_LOGIC; +signal readySig : STD_LOGIC; + +begin + -- Connections + + RS232 : Rs232RefComp + Port map( + TXD => DATA_TXD, + RXD => DATA_RXD, + CLK => clk, + DBIN => dataTXD, + DBOUT => dataRXD, + RDA => RDAsig, + TBE => TBEsig, + RD => RDsig, + WR => WRsig, + PE => PEsig, + FE => FEsig, + OE => OEsig, + RST => reset + ); + + textReg : ShiftReg + generic map( + length_1 => 8, + length_2 => w_64, + internal_data => w_64 + ) + port map( + input => dataRXD, + output => plaintext, + en => textDataEn, + shift => textDataShift, + clk => clk, + reset => reset + ); + + keyReg : ShiftReg + generic map( + length_1 => 8, + length_2 => w_80, + internal_data => w_80 + ) + port map( + input => dataRXD, + output => keyText, + en => keyDataEn, + shift => keyDataShift, + clk => clk, + reset => reset + ); + + present :PresentEnc + port map( + plaintext => plaintext, + key => keyText, + ciphertext => ciphertext, + start => startSig, + clk => clk, + reset => reset, + ready => readySig + ); + + outReg : ShiftReg + generic map( + length_1 => w_64, + length_2 => 8, + internal_data => w_64 + ) + port map( + input => ciphertext, + output => dataTXD, + en => ciphDataEn, + shift => ciphDataShift, + clk => clk, + reset => reset + ); + + SM : PresentCommSM + port map( + clk => clk, + reset => reset, + RDAsig => RDAsig, + TBEsig => TBEsig, + RDsig => RDsig, + WRsig => WRsig, + textDataEn => textDataEn, + textDataShift => textDataShift, + keyDataEn => keyDataEn, + keyDataShift => keyDataShift, + ciphDataEn => ciphDataEn, + ciphDataShift => ciphDataShift, + startSig => startSig, + readySig => readySig + ); + +end Behavioral; + Index: PureTesting/rtl/vhdl/PresentCommSM.vhd =================================================================== --- PureTesting/rtl/vhdl/PresentCommSM.vhd (nonexistent) +++ PureTesting/rtl/vhdl/PresentCommSM.vhd (revision 4) @@ -0,0 +1,427 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- State machine of 'pure' Present cipher with RS-232 ---- +---- communication with PC. For more informations see below. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.kody.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity PresentCommSM is + port ( + clk : in STD_LOGIC; + reset : in STD_LOGIC; + RDAsig : in STD_LOGIC; + TBEsig : in STD_LOGIC; + RDsig : out STD_LOGIC; + WRsig : out STD_LOGIC; + textDataEn : out STD_LOGIC; + textDataShift : out STD_LOGIC; + keyDataEn : out STD_LOGIC; + keyDataShift : out STD_LOGIC; + ciphDataEn : out STD_LOGIC; + ciphDataShift : out STD_LOGIC; + startSig : out STD_LOGIC; + readySig : in STD_LOGIC + ); +end PresentCommSM; + +architecture Behavioral of PresentCommSM is + +-- counter used for determine number of readed/sended data (key, text, result) +component counter is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); +end component counter; + +-- signals + +signal state : stany_comm := NOP; +signal next_state : stany_comm := NOP; + +-- modify for variable key size +signal serialDataCtrCt : STD_LOGIC; +signal serialDataCtrOut : STD_LOGIC_VECTOR(3 downto 0); +signal serialDataCtrReset : STD_LOGIC; +signal ctrReset : STD_LOGIC; +-- DO NOT MODIFY!!! +signal shiftDataCtrCt : STD_LOGIC; +signal shiftDataCtrOut : STD_LOGIC_VECTOR(2 downto 0); + +begin + -- In this state machine is determined, that firs data should be 64 bit text + -- after text, key should appear. After receiving last byte of key, ciphertext + -- is counted. And later it is sended back to PC. + ctrReset <= serialDataCtrReset or reset; + SM : process(state, RDAsig, TBEsig, shiftDataCtrOut, serialDataCtrOut, readySig) + begin + case state is + -- No operation - waiting for incoming data + when NOP => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + -- data has come + if (RDAsig = '1') then + next_state <= READ_DATA_TEXT; + else + next_state <= NOP; + end if; + -- Text data enable and read data + when READ_DATA_TEXT => + RDsig <= '1'; + WRsig <= '0'; + textDataEn <= '1'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + -- counter of retrieved bytes + serialDataCtrCt <= '1'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + next_state <= DECODE_READ_TEXT; + -- Data readed, stop counter and check if proper number of byte + -- was readed + when DECODE_READ_TEXT => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + -- 8 bytes should be readed + if (serialDataCtrOut(3 downto 0) = "1000") then + -- 8 bytes was readed + next_state <= TEMP_STATE; + else + -- 8 bytes was not readed + next_state <= MOVE_TEXT; + end if; + -- Reset counter for next reading + when TEMP_STATE => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '1'; + next_state <= NOP_FOR_KEY; + -- Here data are shfted in shift register - another shift counter are used + when MOVE_TEXT => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '1'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '1'; + serialDataCtrReset <= '0'; + if (shiftDataCtrOut(2 downto 0) = "111") then + next_state <= NOP; + else + next_state <= MOVE_TEXT; + end if; + -- "No operation 2" waiting for data - it could be optimized in way, + -- that waiting for key and text could be the same state, but it was + -- intentionally separated. + when NOP_FOR_KEY => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + if (RDAsig = '1') then + -- data has come + next_state <= READ_DATA_KEY; + else + next_state <= NOP_FOR_KEY; + end if; + -- Key data enable and read data + when READ_DATA_KEY => + RDsig <= '1'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '1'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + -- counter of retrieved bytes + serialDataCtrCt <= '1'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + next_state <= DECODE_READ_KEY; + -- Data readed, stop counter and check if proper number of byte + -- was readed + when DECODE_READ_KEY => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + -- 10 bytes should be readed + if (serialDataCtrOut(3 downto 0) = "1010") then + -- 10 bytes was readed + next_state <= TEMP2_STATE; + else + -- 10 bytes was not readed + next_state <= MOVE_KEY; + end if; + -- Reset counter for next reading + when TEMP2_STATE => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '1'; + next_state <= PRESENT_ENCODE; + -- Here data are shfted in shift register - another shift counter are used + when MOVE_KEY => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '1'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '0'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '1'; + serialDataCtrReset <= '0'; + if (shiftDataCtrOut(2 downto 0) = "111") then + next_state <= NOP_FOR_KEY; + else + next_state <= MOVE_KEY; + end if; + -- All suitable data was readed Present encode start + when PRESENT_ENCODE => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataShift <= '0'; + startSig <= '1'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + -- change state if Present result ready + if (readySig = '1') then + ciphDataEn <= '1'; + next_state <= WRITE_OUT; + else + ciphDataEn <= '0'; + next_state <= PRESENT_ENCODE; + end if; + -- similar control of writing result as during reading + when WRITE_OUT => + RDsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '1'; + serialDataCtrCt <= '1'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + if (serialDataCtrOut = "1000") then + WRsig <= '0'; + next_state <= TEMP_OUT; + else + WRsig <= '1'; + next_state <= MOVE_OUT; + end if; + -- all data was sended - start new Present encode cycle + when TEMP_OUT => + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '1'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '1'; + next_state <= NOP; + when MOVE_OUT => + if (TBEsig = '0') then + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '0'; + startSig <= '1'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '0'; + serialDataCtrReset <= '0'; + next_state <= MOVE_OUT; + else + RDsig <= '0'; + WRsig <= '0'; + textDataEn <= '0'; + textDataShift <= '0'; + keyDataEn <= '0'; + keyDataShift <= '0'; + ciphDataEn <= '0'; + ciphDataShift <= '1'; + startSig <= '1'; + serialDataCtrCt <= '0'; + shiftDataCtrCt <= '1'; + serialDataCtrReset <= '0'; + if (shiftDataCtrOut = "111") then + next_state <= WRITE_OUT; + else + next_state <= MOVE_OUT; + end if; + end if; + end case; + end process SM; + + state_modifier : process (clk, reset) + begin + if (clk = '1' and clk'Event) then + if (reset = '1') then + state <= NOP; + else + state <= next_state; + end if; + end if; + end process state_modifier; + + -- counter for controling number of bytes of readed data + dataCounter : counter + generic map( + w_5 => 4 + ) + port map ( + cnt_res => serialDataCtrCt, + num => serialDataCtrOut, + clk => clk, + reset => ctrReset + ); + + -- counter for controling number of shifted bits of readed data + shiftCounter : counter + generic map( + w_5 => 3 + ) + port map ( + cnt_res => shiftDataCtrCt, + num => shiftDataCtrOut, + clk => clk, + reset => reset + ); + +end Behavioral; + Index: PureTesting/rtl/vhdl/pLayer.vhd =================================================================== --- PureTesting/rtl/vhdl/pLayer.vhd (nonexistent) +++ PureTesting/rtl/vhdl/pLayer.vhd (revision 4) @@ -0,0 +1,125 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- Permutation layer of Present cipher. Simple signal mixing.---- +---- For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- Description: ---- +---- ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity pLayer is + generic(w_64 : integer := 64); + port ( + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_64-1 downto 0) + ); +end pLayer; + +architecture Behavioral of pLayer is +begin + output(0) <= input(0); + output(16) <= input(1); + output(32) <= input(2); + output(48) <= input(3); + output(1) <= input(4); + output(17) <= input(5); + output(33) <= input(6); + output(49) <= input(7); + output(2) <= input(8); + output(18) <= input(9); + output(34) <= input(10); + output(50) <= input(11); + output(3) <= input(12); + output(19) <= input(13); + output(35) <= input(14); + output(51) <= input(15); + output(4) <= input(16); + output(20) <= input(17); + output(36) <= input(18); + output(52) <= input(19); + output(5) <= input(20); + output(21) <= input(21); + output(37) <= input(22); + output(53) <= input(23); + output(6) <= input(24); + output(22) <= input(25); + output(38) <= input(26); + output(54) <= input(27); + output(7) <= input(28); + output(23) <= input(29); + output(39) <= input(30); + output(55) <= input(31); + output(8) <= input(32); + output(24) <= input(33); + output(40) <= input(34); + output(56) <= input(35); + output(9) <= input(36); + output(25) <= input(37); + output(41) <= input(38); + output(57) <= input(39); + output(10) <= input(40); + output(26) <= input(41); + output(42) <= input(42); + output(58) <= input(43); + output(11) <= input(44); + output(27) <= input(45); + output(43) <= input(46); + output(59) <= input(47); + output(12) <= input(48); + output(28) <= input(49); + output(44) <= input(50); + output(60) <= input(51); + output(13) <= input(52); + output(29) <= input(53); + output(45) <= input(54); + output(61) <= input(55); + output(14) <= input(56); + output(30) <= input(57); + output(46) <= input(58); + output(62) <= input(59); + output(15) <= input(60); + output(31) <= input(61); + output(47) <= input(62); + output(63) <= input(63); +end Behavioral; \ No newline at end of file Index: PureTesting/rtl/vhdl/Reg.vhd =================================================================== --- PureTesting/rtl/vhdl/Reg.vhd (nonexistent) +++ PureTesting/rtl/vhdl/Reg.vhd (revision 4) @@ -0,0 +1,83 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Register - nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Reg is + generic(width : integer := 64); + port( + input : in STD_LOGIC_VECTOR(width - 1 downto 0); + output : out STD_LOGIC_VECTOR(width - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); +end Reg; + +architecture Behavioral of Reg is + +signal reg : STD_LOGIC_VECTOR(width - 1 downto 0); + +begin + clock : process(clk, reset) + begin + if (reset = '1') then + reg <= (others => '0'); + elsif (clk = '1' and clk'Event) then + if (enable = '1') then + reg <= input; + end if; + end if; + end process clock; + output <= reg; +end Behavioral; + Index: PureTesting/rtl/vhdl =================================================================== --- PureTesting/rtl/vhdl (nonexistent) +++ PureTesting/rtl/vhdl (revision 4)

PureTesting/rtl/vhdl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: PureTesting/rtl =================================================================== --- PureTesting/rtl (nonexistent) +++ PureTesting/rtl (revision 4)

PureTesting/rtl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: PureTesting/doc/src =================================================================== --- PureTesting/doc/src (nonexistent) +++ PureTesting/doc/src (revision 4)

PureTesting/doc/src Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: PureTesting/doc =================================================================== --- PureTesting/doc (nonexistent) +++ PureTesting/doc (revision 4)

PureTesting/doc Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: PureTesting/sim =================================================================== --- PureTesting/sim (nonexistent) +++ PureTesting/sim (revision 4)

PureTesting/sim Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: PureTesting/sw/JavaTests/PresentCommTesting/rxtxSerial.dll =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: PureTesting/sw/JavaTests/PresentCommTesting/rxtxSerial.dll =================================================================== --- PureTesting/sw/JavaTests/PresentCommTesting/rxtxSerial.dll (nonexistent) +++ PureTesting/sw/JavaTests/PresentCommTesting/rxtxSerial.dll (revision 4)

PureTesting/sw/JavaTests/PresentCommTesting/rxtxSerial.dll Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: PureTesting/sw/JavaTests/PresentCommTesting/.classpath =================================================================== --- PureTesting/sw/JavaTests/PresentCommTesting/.classpath (nonexistent) +++ PureTesting/sw/JavaTests/PresentCommTesting/.classpath (revision 4) @@ -0,0 +1,9 @@ + + + + + + + + + Index: PureTesting/sw/JavaTests/PresentCommTesting/.project =================================================================== --- PureTesting/sw/JavaTests/PresentCommTesting/.project (nonexistent) +++ PureTesting/sw/JavaTests/PresentCommTesting/.project (revision 4) @@ -0,0 +1,17 @@ + + + PresentCommTesting + + + + + + org.eclipse.jdt.core.javabuilder + + + + + + org.eclipse.jdt.core.javanature + + Index: PureTesting/sw/JavaTests/PresentCommTesting/lib/commons-lang3-3.1.jar =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: PureTesting/sw/JavaTests/PresentCommTesting/lib/commons-lang3-3.1.jar =================================================================== --- PureTesting/sw/JavaTests/PresentCommTesting/lib/commons-lang3-3.1.jar (nonexistent) +++ PureTesting/sw/JavaTests/PresentCommTesting/lib/commons-lang3-3.1.jar (revision 4)

PureTesting/sw/JavaTests/PresentCommTesting/lib/commons-lang3-3.1.jar Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: PureTesting/sw/JavaTests/PresentCommTesting/lib/RXTXcomm.jar =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: PureTesting/sw/JavaTests/PresentCommTesting/lib/RXTXcomm.jar =================================================================== --- PureTesting/sw/JavaTests/PresentCommTesting/lib/RXTXcomm.jar (nonexistent) +++ PureTesting/sw/JavaTests/PresentCommTesting/lib/RXTXcomm.jar (revision 4)

PureTesting/sw/JavaTests/PresentCommTesting/lib/RXTXcomm.jar Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: PureTesting/sw/JavaTests/PresentCommTesting/lib =================================================================== --- PureTesting/sw/JavaTests/PresentCommTesting/lib (nonexistent) +++ PureTesting/sw/JavaTests/PresentCommTesting/lib (revision 4)

PureTesting/sw/JavaTests/PresentCommTesting/lib Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen/PresentDataGenerator.java =================================================================== --- PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen/PresentDataGenerator.java (nonexistent) +++ PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen/PresentDataGenerator.java (revision 4) @@ -0,0 +1,90 @@ +package pl.com.kgajewski.serialcomm.datagen; +import java.io.BufferedWriter; +import java.io.File; +import java.io.FileWriter; +import java.io.IOException; + +import org.apache.commons.lang3.StringUtils; + + +public class PresentDataGenerator { + public static void main(String[] args) { + String drive = "e:\\"; + String data = "a112ffc72f68417b"; + String key = "00000000000000000000"; + + String data2 = "3333dcd3213210d2"; + String key2 = "ffffffffffffffffffff"; + + try { + System.out.println("key"); + File f1 = new File(drive + "key.txt"); + f1.createNewFile(); + formatDataFromHex(key, f1); + + System.out.println("data"); + File f2 = new File(drive + "data.txt"); + f1.createNewFile(); + formatDataFromHex(data, f2); + + System.out.println("key2"); + File f3 = new File(drive + "key2.txt"); + f3.createNewFile(); + formatDataFromHex(key2, f3); + + System.out.println("data2"); + File f4 = new File(drive + "data2.txt"); + f4.createNewFile(); + formatDataFromHex(data2, f4); + + } catch (IOException e1) { + // TODO Auto-generated catch block + e1.printStackTrace(); + } + + } + + private static void formatDataFromHex(String str, File f) throws IOException { + BufferedWriter bfw = new BufferedWriter(new FileWriter(f)); + for (int i = str.length(); i > 0; i -= 2) { + String substr = str.substring(i - 2, i); + + parseByteStringHex(bfw, substr); + } + bfw.close(); + } + + private static void parseByteStringHex(BufferedWriter bfw, String str) + throws IOException { + Integer i = Integer.valueOf(str, 16); + String s = Integer.toString(i, 2); + String tmp = ""; + for (int j = 8 - s.length(); j > 0; j--) { + tmp = tmp.concat("0"); + } + parseByteString(bfw, tmp + s); + } + + private static void parseByteString(BufferedWriter bfw, String str) + throws IOException { + int ones = 0; + bfw.write(str); + bfw.write("\n"); + str = StringUtils.reverse(str); + + for (int j = 0; j < str.length(); j++) { + bfw.write(str.charAt(j)); + bfw.write("\n"); + if (str.charAt(j) == '1') { + ones++; + } + } + if (ones % 2 == 1) { + bfw.write("0"); + } else { + bfw.write("1"); + } + bfw.write("\n"); + } + +} Index: PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen =================================================================== --- PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen (nonexistent) +++ PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen (revision 4)

PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/datagen Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Communication.java =================================================================== --- PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Communication.java (nonexistent) +++ PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Communication.java (revision 4) @@ -0,0 +1,261 @@ +package pl.com.kgajewski.serialcomm.gui; + +import gnu.io.CommPort; +import gnu.io.CommPortIdentifier; +import gnu.io.PortInUseException; +import gnu.io.SerialPort; +import gnu.io.SerialPortEvent; +import gnu.io.SerialPortEventListener; + +import java.io.IOException; +import java.io.InputStream; +import java.io.OutputStream; +import java.math.BigInteger; +import java.util.Enumeration; +import java.util.HashMap; +import java.util.TooManyListenersException; + +import org.apache.commons.lang3.ArrayUtils; +import org.apache.commons.lang3.StringUtils; +import org.eclipse.swt.graphics.Color; + +public class Communication implements SerialPortEventListener { + + //passed from main GUI + Window window = null; + + // just a boolean flag that i use for enabling + // and disabling buttons depending on whether the program + // is connected to a serial port or not + private boolean bConnected = false; + + // the timeout value for connecting with the port + final static int TIMEOUT = 2000; + + // for containing the ports that will be found + private Enumeration ports = null; + // map the port names to CommPortIdentifiers + private HashMap portMap = new HashMap(); + + // this is the object that contains the opened port + private CommPortIdentifier selectedPortIdentifier = null; + private SerialPort serialPort = null; + + // input and output streams for sending and receiving data + private InputStream input = null; + private OutputStream output = null; + + public Communication(Window window) { + this.window = window; + } + + // a string for recording what goes on in the program + // this string is written to the GUI + String logText = ""; + + // search for all the serial ports + // pre style="font-size: 11px;": none + // post: adds all the found ports to a combo box on the GUI + public void searchForPorts() { + ports = CommPortIdentifier.getPortIdentifiers(); + + while (ports.hasMoreElements()) { + CommPortIdentifier curPort = (CommPortIdentifier) ports + .nextElement(); + + // get only serial ports + if (curPort.getPortType() == CommPortIdentifier.PORT_SERIAL) { + window.combo.add(curPort.getName()); + portMap.put(curPort.getName(), curPort); + } + } + } + + // connect to the selected port in the combo box + // pre style="font-size: 11px;": ports are already found by using the + // searchForPorts + // method + // post: the connected comm port is stored in commPort, otherwise, + // an exception is generated + public void connect() { + if (window.combo.getSelectionIndex() >= 0) { + String selectedPort = (String) window.combo.getItem(window.combo.getSelectionIndex()); + selectedPortIdentifier = (CommPortIdentifier) portMap + .get(selectedPort); + + CommPort commPort = null; + + try { + // the method below returns an object of type CommPort + commPort = selectedPortIdentifier.open("pl.com.kgajewski.cerialcomm", + TIMEOUT); + // the CommPort object can be casted to a SerialPort object + serialPort = (SerialPort) commPort; + serialPort.setSerialPortParams(115200,SerialPort.DATABITS_8,SerialPort.STOPBITS_1,SerialPort.PARITY_ODD); + + // for controlling GUI elements + setConnected(true); + + // logging + logText = selectedPort + " opened successfully."; + window.text.setForeground(new Color(window.shell.getDisplay(), 0, 0, 0)); + window.appendText(logText + "\n"); + + // CODE ON SETTING BAUD RATE ETC OMITTED + // XBEE PAIR ASSUMED TO HAVE SAME SETTINGS ALREADY + + // enables the controls on the GUI if a successful connection is + // made + window.toggleControls(); + + } catch (PortInUseException e) { + logText = selectedPort + " is in use. (" + e.toString() + ")"; + + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } catch (Exception e) { + logText = "Failed to open " + selectedPort + "(" + e.toString() + + ")"; + window.appendText(logText + "\n"); + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + } + } + } + // open the input and output streams + // pre style="font-size: 11px;": an open port + // post: initialized input and output streams for use to communicate data + public boolean initIOStream() { + // return value for whether opening the streams is successful or not + boolean successful = false; + + try { + // + input = serialPort.getInputStream(); + output = serialPort.getOutputStream(); + + successful = true; + return successful; + } catch (IOException e) { + logText = "I/O Streams failed to open. (" + e.toString() + ")"; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + return successful; + } + } + + // starts the event listener that knows whenever data is available to be + // read + // pre style="font-size: 11px;": an open serial port + // post: an event listener for the serial port that knows when data is + // received + public void initListener() { + try { + serialPort.addEventListener(this); + serialPort.notifyOnDataAvailable(true); + } catch (TooManyListenersException e) { + logText = "Too many listeners. (" + e.toString() + ")"; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } + } + + //disconnect the serial port + //pre style="font-size: 11px;": an open serial port + //post: closed serial port + public void disconnect() + { + //close the serial port + try + { + serialPort.removeEventListener(); + serialPort.close(); + input.close(); + output.close(); + setConnected(false); + window.toggleControls(); + + logText = "Disconnected."; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } + catch (Exception e) + { + logText = "Failed to close " + serialPort.getName() + + "(" + e.toString() + ")"; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } + } + + //what happens when data is received + //pre style="font-size: 11px;": serial event is triggered + //post: processing on the data it reads + public void serialEvent(SerialPortEvent evt) { + if (evt.getEventType() == SerialPortEvent.DATA_AVAILABLE) + { + try + { + byte [] buffer = new byte[10]; + int n = input.read(buffer); + if (n > 0) + { + if (n == 1) { + BigInteger command = new BigInteger(new byte []{0, buffer[0]}); + final String s = "Command = " + command.toString(16) + "\n"; + window.appendText(s); + } else { + buffer = ArrayUtils.subarray(buffer, 0, buffer.length - 2); + buffer = ArrayUtils.add(buffer, (byte)0); + ArrayUtils.reverse(buffer); + BigInteger data = new BigInteger(buffer); + window.appendText(data.toString(16) + "\n"); + } + } + else + { + window.appendText("\n"); + } + } + catch (Exception e) + { + logText = "Failed to read data. (" + e.toString() + ")"; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } + } + } + + //method that can be called to send data + //pre style="font-size: 11px;": open serial port + //post: data sent to the other device + public void writeData(String str) + { + try + { + for (int i = str.length()-1; i > 0; i -= 2) { + String s = str.substring(i-1, i+1); + byte b = (byte)(Integer.parseInt(s, 16) & 0xFF); + output.write(b); + Thread.sleep(1); + } + } + catch (Exception e) + { + logText = "Failed to write data. (" + e.toString() + ")"; + window.text.setForeground(new Color(window.shell.getDisplay(), 255, 0, 0)); + window.appendText(logText + "\n"); + } + } + + final public boolean getConnected() + { + return bConnected; + } + + public void setConnected(boolean bConnected) + { + this.bConnected = bConnected; + } + + +} Index: PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Window.java =================================================================== --- PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Window.java (nonexistent) +++ PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui/Window.java (revision 4) @@ -0,0 +1,159 @@ +package pl.com.kgajewski.serialcomm.gui; + +import org.eclipse.swt.SWT; +import org.eclipse.swt.events.MouseAdapter; +import org.eclipse.swt.events.MouseEvent; +import org.eclipse.swt.widgets.Button; +import org.eclipse.swt.widgets.Combo; +import org.eclipse.swt.widgets.Composite; +import org.eclipse.swt.widgets.Display; +import org.eclipse.swt.widgets.Label; +import org.eclipse.swt.widgets.Shell; +import org.eclipse.swt.widgets.Text; + +public class Window { + + //Communicator object + Communication communication = null; + public Display display; + protected Shell shell; + public Text text; + private Text data; + private Text key; + public Combo combo; + private Button btnConnect; + private Button btnDisconnect; + private Button btnSendData; + + public void toggleControls() + { + if (communication.getConnected() == true) + { + btnDisconnect.setEnabled(true); + btnConnect.setEnabled(false); + btnSendData.setEnabled(true); + } + else + { + btnDisconnect.setEnabled(false); + btnConnect.setEnabled(true); + btnSendData.setEnabled(false); + } + } + + /** + * Launch the application. + * + * @param args + */ + public static void main(String[] args) { + try { + Window window = new Window(); + window.open(); + } catch (Exception e) { + e.printStackTrace(); + } + } + + /** + * Open the window. + */ + public void open() { + display = Display.getDefault(); + createContents(); + communication = new Communication(this); + communication.searchForPorts(); + toggleControls(); + shell.open(); + shell.layout(); + while (!shell.isDisposed()) { + if (!display.readAndDispatch()) { + display.sleep(); + } + } + } + + /** + * Create contents of the window. + */ + protected void createContents() { + shell = new Shell(); + shell.setSize(470, 274); + shell.setText("SWT Application"); + shell.setLayout(null); + + Composite composite = new Composite(shell, SWT.NONE); + composite.setBounds(0, 0, 444, 236); + + text = new Text(composite, SWT.BORDER | SWT.MULTI); + this.text.setBounds(107, 126, 327, 105); + + combo = new Combo(composite, SWT.NONE); + combo.setBounds(10, 10, 91, 23); + + btnConnect = new Button(composite, SWT.NONE); + btnConnect.addMouseListener(new MouseAdapter() { + @Override + public void mouseUp(MouseEvent arg0) { + communication.connect(); + if (communication.getConnected() == true) + { + if (communication.initIOStream() == true) + { + communication.initListener(); + } + } + } + }); + btnConnect.setBounds(107, 10, 75, 25); + btnConnect.setText("Connect"); + + btnDisconnect = new Button(composite, SWT.NONE); + btnDisconnect.addMouseListener(new MouseAdapter() { + @Override + public void mouseUp(MouseEvent arg0) { + communication.disconnect(); + } + }); + btnDisconnect.setBounds(188, 10, 75, 25); + btnDisconnect.setText("Disconnect"); + + Label lblLog = new Label(composite, SWT.NONE); + lblLog.setBounds(107, 105, 186, 15); + lblLog.setText("Log"); + + data = new Text(composite, SWT.BORDER); + data.setBounds(45, 39, 248, 21); + + key = new Text(composite, SWT.BORDER); + key.setBounds(45, 66, 248, 21); + + btnSendData = new Button(composite, SWT.NONE); + btnSendData.addMouseListener(new MouseAdapter() { + @Override + public void mouseUp(MouseEvent arg0) { + communication.writeData(data.getText()); + communication.writeData(key.getText()); + } + }); + btnSendData.setBounds(10, 100, 75, 25); + btnSendData.setText("Send"); + + Label lblData = new Label(composite, SWT.NONE); + lblData.setBounds(10, 39, 29, 15); + lblData.setText("Data"); + + Label lblKey = new Label(composite, SWT.NONE); + lblKey.setBounds(10, 66, 55, 15); + lblKey.setText("Key"); + } + + public void appendText(final String s) { + display.syncExec(new Runnable() { + public void run() { + text.append(s); + } + }); + + } +} Index: PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui =================================================================== --- PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui (nonexistent) +++ PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui (revision 4)

PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm/gui Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm =================================================================== --- PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm (nonexistent) +++ PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm (revision 4)

PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski/serialcomm Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski =================================================================== --- PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski (nonexistent) +++ PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski (revision 4)

PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com/kgajewski Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com =================================================================== --- PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com (nonexistent) +++ PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com (revision 4)

PureTesting/sw/JavaTests/PresentCommTesting/src/pl/com Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: PureTesting/sw/JavaTests/PresentCommTesting/src/pl =================================================================== --- PureTesting/sw/JavaTests/PresentCommTesting/src/pl (nonexistent) +++ PureTesting/sw/JavaTests/PresentCommTesting/src/pl (revision 4)

PureTesting/sw/JavaTests/PresentCommTesting/src/pl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: PureTesting/sw/JavaTests/PresentCommTesting/src =================================================================== --- PureTesting/sw/JavaTests/PresentCommTesting/src (nonexistent) +++ PureTesting/sw/JavaTests/PresentCommTesting/src (revision 4)

PureTesting/sw/JavaTests/PresentCommTesting/src Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: PureTesting/sw/JavaTests/PresentCommTesting/bin =================================================================== --- PureTesting/sw/JavaTests/PresentCommTesting/bin (nonexistent) +++ PureTesting/sw/JavaTests/PresentCommTesting/bin (revision 4)

PureTesting/sw/JavaTests/PresentCommTesting/bin Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: PureTesting/sw/JavaTests/PresentCommTesting/rxtxParallel.dll =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: PureTesting/sw/JavaTests/PresentCommTesting/rxtxParallel.dll =================================================================== --- PureTesting/sw/JavaTests/PresentCommTesting/rxtxParallel.dll (nonexistent) +++ PureTesting/sw/JavaTests/PresentCommTesting/rxtxParallel.dll (revision 4)

PureTesting/sw/JavaTests/PresentCommTesting/rxtxParallel.dll Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: PureTesting/sw/JavaTests/PresentCommTesting/.settings/org.eclipse.jdt.core.prefs =================================================================== --- PureTesting/sw/JavaTests/PresentCommTesting/.settings/org.eclipse.jdt.core.prefs (nonexistent) +++ PureTesting/sw/JavaTests/PresentCommTesting/.settings/org.eclipse.jdt.core.prefs (revision 4) @@ -0,0 +1,11 @@ +eclipse.preferences.version=1 +org.eclipse.jdt.core.compiler.codegen.inlineJsrBytecode=enabled +org.eclipse.jdt.core.compiler.codegen.targetPlatform=1.6 +org.eclipse.jdt.core.compiler.codegen.unusedLocal=preserve +org.eclipse.jdt.core.compiler.compliance=1.6 +org.eclipse.jdt.core.compiler.debug.lineNumber=generate +org.eclipse.jdt.core.compiler.debug.localVariable=generate +org.eclipse.jdt.core.compiler.debug.sourceFile=generate +org.eclipse.jdt.core.compiler.problem.assertIdentifier=error +org.eclipse.jdt.core.compiler.problem.enumIdentifier=error +org.eclipse.jdt.core.compiler.source=1.6 Index: PureTesting/sw/JavaTests/PresentCommTesting/.settings =================================================================== --- PureTesting/sw/JavaTests/PresentCommTesting/.settings (nonexistent) +++ PureTesting/sw/JavaTests/PresentCommTesting/.settings (revision 4)

PureTesting/sw/JavaTests/PresentCommTesting/.settings Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: PureTesting/sw/JavaTests/PresentCommTesting =================================================================== --- PureTesting/sw/JavaTests/PresentCommTesting (nonexistent) +++ PureTesting/sw/JavaTests/PresentCommTesting (revision 4)

PureTesting/sw/JavaTests/PresentCommTesting Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: PureTesting/sw/JavaTests =================================================================== --- PureTesting/sw/JavaTests (nonexistent) +++ PureTesting/sw/JavaTests (revision 4)

PureTesting/sw/JavaTests Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: PureTesting/sw =================================================================== --- PureTesting/sw (nonexistent) +++ PureTesting/sw (revision 4)

PureTesting/sw Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: PureTesting/syn/XC3ES500 =================================================================== --- PureTesting/syn/XC3ES500 (nonexistent) +++ PureTesting/syn/XC3ES500 (revision 4)

PureTesting/syn/XC3ES500 Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: PureTesting/syn =================================================================== --- PureTesting/syn (nonexistent) +++ PureTesting/syn (revision 4)

PureTesting/syn Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: 32BitIO/PresentEnc.vhd =================================================================== --- 32BitIO/PresentEnc.vhd (revision 3) +++ 32BitIO/PresentEnc.vhd (nonexistent) @@ -1,189 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 18:02:34 05/15/2010 --- Design Name: --- Module Name: PresentEnc - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: - --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity PresentEnc is - generic ( - w_2: integer := 2; - w_4: integer := 4; - w_5: integer := 5; - w_32: integer := 32; - w_64: integer := 64; - w_80: integer := 80 - ); - port( - ctrl : in std_logic_vector(w_4-1 downto 0); - input : in std_logic_vector(w_32-1 downto 0); - output : out std_logic_vector(w_32-1 downto 0); - clk, reset : in std_logic; - ready : out std_logic - ); -end PresentEnc; - -architecture Behavioral of PresentEnc is - - component PresentStateMachine is - generic ( - w_2: integer := 2; - w_4: integer := 4; - w_5: integer := 5; - w_32: integer := 32; - w_64: integer := 64; - w_80: integer := 80 - ); - port ( - info : in std_logic_vector (w_2-1 downto 0); - ctrl : in std_logic_vector (w_4-1 downto 0); - key_ctrl: out std_logic_vector (w_2-1 downto 0); - plain_ctrl: out std_logic_vector (w_2-1 downto 0); - outReg : out std_logic_vector (w_2-1 downto 0); - reset, clk : in std_logic; - ready, cnt_res, ctrl_mux64, ctrl_mux80 : out std_logic - ); - end component; - - component slayer is - generic ( - w_4 : integer := 4 - ); - port ( - input : in std_logic_vector(w_4-1 downto 0); - output : out std_logic_vector(w_4-1 downto 0) - ); - end component; - - component pLayer is - generic(w_64 : integer := 64); - port( - input : in std_logic_vector(w_64-1 downto 0); - output : out std_logic_vector(w_64-1 downto 0) - ); - end component; - - component keyupd is - generic( - w_5 : integer := 5; - w_80: integer := 80 - ); - port( - num : in std_logic_vector(w_5-1 downto 0); - key : in std_logic_vector(w_80-1 downto 0); - keyout : out std_logic_vector(w_80-1 downto 0) - ); - end component; - - component outputRegister is - generic ( - w_2 : integer := 2; - w_32: integer := 32; - w_64: integer := 64 - ); - port( - ctrl : in std_logic_vector(w_2-1 downto 0); - input : in std_logic_vector(w_64-1 downto 0); - output : out std_logic_vector(w_32-1 downto 0); - rst, clk, rd : in std_logic; - ready : out std_logic - ); - end component; - - component counter is - generic ( - w_2 : integer := 2; - w_5 : integer := 5 - ); - port ( - clk, reset, cnt_res : in std_logic; - info : out std_logic_vector(w_2-1 downto 0); - num : out std_logic_vector (w_5-1 downto 0) - ); - end component; - - component mux64 is - generic ( - w_2 : integer := 2; - w_32 : integer := 32; - w_64 : integer := 64 - ); - port( - i0ctrl : in std_logic_vector (w_2-1 downto 0); - input0 : in std_logic_vector(w_32-1 downto 0); - input1 : in std_logic_vector(w_64-1 downto 0); - output : inout std_logic_vector(w_64-1 downto 0); - ctrl, clk, reset : in std_logic - ); - end component; - - component mux80 is - generic ( - w_2 : integer := 2; - w_32 : integer := 32; - w_80 : integer := 80 - ); - port( - i0ctrl : in std_logic_vector (w_2-1 downto 0); - input0 : in std_logic_vector(w_32-1 downto 0); - input1 : in std_logic_vector(w_80-1 downto 0); - output : inout std_logic_vector(w_80-1 downto 0); - ctrl, clk, reset : in std_logic - ); - end component; - - component xorModule is - generic( - w : positive - ); - port( - inputA, inputB : in std_logic_vector( w-1 downto 0 ); - output : out std_logic_vector ( w-1 downto 0 ) - ); - end component; - - signal ro32ctrl, key_ctrl, plain_ctrl, info : std_logic_vector(w_2-1 downto 0); - signal keynum : std_logic_vector (w_5-1 downto 0); - signal toXor, ciphertext, P, Pout : std_logic_vector (w_64-1 downto 0); - signal keyfout, kupd : std_logic_vector (w_80-1 downto 0); - signal ready_sig, mux64ctrl, mux80ctrl, cnt_res : std_logic; - - begin - mux_64: mux64 port map( - input0 => input, input1 => Pout, output => toXor, ctrl => mux64ctrl, - i0ctrl => plain_ctrl, clk => clk, reset => reset); - mux_80: mux80 port map( - input0 => input, input1 => kupd, output => keyfout, ctrl => mux80ctrl, - i0ctrl => key_ctrl, clk => clk, reset => reset); - slayers : for N in 15 downto 0 generate - s_x: slayer port map(input => ciphertext(4*N+3 downto 4*N), output => P(4*N+3 downto 4*N)); - end generate slayers; - p1: pLayer port map(input => P, output => Pout); - mixer: keyupd port map(key => keyfout, num => keynum, keyout => kupd); - output_reg: outputRegister port map(rst => reset, clk => clk, rd => ready_sig, ctrl => ro32ctrl, - input => ciphertext, output => output, ready => ready); - SM: PresentStateMachine port map(ctrl => ctrl, outReg => ro32ctrl, reset => reset, - ready => ready_sig, cnt_res => cnt_res, ctrl_mux64 => mux64ctrl, ctrl_mux80 => mux80ctrl, - clk => clk, key_ctrl => key_ctrl, plain_ctrl => plain_ctrl, info => info - ); - count: counter port map( clk => clk, reset => reset, cnt_res => cnt_res, info => info, num => keynum); - ciphertext <= toXor xor keyfout(79 downto 16); -end Behavioral; Index: 32BitIO/keyupdTB.vhd =================================================================== --- 32BitIO/keyupdTB.vhd (revision 3) +++ 32BitIO/keyupdTB.vhd (nonexistent) @@ -1,106 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:00:18 05/16/2010 --- Design Name: --- Module Name: C:/Users/gajos/Desktop/Polibuda/vhdl/projekt/szyfrator/keyupdTB.vhd --- Project Name: szyfrator --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: keyupd --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.all; -USE ieee.numeric_std.ALL; - -ENTITY keyupdTB IS -END keyupdTB; - -ARCHITECTURE behavior OF keyupdTB IS - - -- Component Declaration for the Unit Under Test (UUT) - - COMPONENT keyupd - PORT( - key : IN std_logic_vector(79 downto 0); - num : IN std_logic_vector(4 downto 0); - keyout : OUT std_logic_vector(79 downto 0)--; - --clk, reset : std_logic - ); - END COMPONENT; - - - --Inputs - signal key : std_logic_vector(79 downto 0) := (others => '0'); - signal num : std_logic_vector(4 downto 0) := (others => '0'); - signal clk : std_logic := '0'; - signal reset : std_logic := '0'; - - --Outputs - signal keyout : std_logic_vector(79 downto 0); - - constant clk_period : time := 1ns; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: keyupd PORT MAP ( - key => key, - num => num, - keyout => keyout--, - --clk => clk, - --reset => reset - ); - - -- No clocks detected in port list. Replace clk below with - -- appropriate port name - - clk_process :process - begin - clk <= '0'; - wait for clk_period/2; - clk <= '1'; - wait for clk_period/2; - end process; - - - -- Stimulus process - stim_proc: process - begin - -- hold reset state for 100ms. - reset <= '1'; - wait for 100ns; - reset <='0'; - wait for clk_period; - key <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - num <= "00001"; - wait for clk_period; - key <= x"c0000000000000008000"; - num <= "00010"; - wait for clk_period; - key <= x"50001800000000010000"; - num <= "00011"; - wait for clk_period; - key <= x"8ba27a0eb8783ac96d59"; - num <= "11111"; - wait for clk_period; - assert false severity failure; - end process; -END; \ No newline at end of file Index: 32BitIO/sLayerTB.vhd =================================================================== --- 32BitIO/sLayerTB.vhd (revision 3) +++ 32BitIO/sLayerTB.vhd (nonexistent) @@ -1,95 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:11:33 05/16/2010 --- Design Name: --- Module Name: C:/Users/gajos/Desktop/Polibuda/vhdl/projekt/szyfrator/sLayerTB.vhd --- Project Name: szyfrator --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: slayer --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.all; -USE ieee.numeric_std.ALL; - -ENTITY sLayerTB IS -END sLayerTB; - -ARCHITECTURE behavior OF sLayerTB IS - - -- Component Declaration for the Unit Under Test (UUT) - - COMPONENT slayer - PORT( - input : IN std_logic_vector(3 downto 0); - output : OUT std_logic_vector(3 downto 0) - ); - END COMPONENT; - - - --Inputs - signal clk : std_logic := '0'; - signal reset : std_logic := '0'; - - --BiDirs - signal input : std_logic_vector(3 downto 0); - signal output : std_logic_vector(3 downto 0); - - -- Clock period definitions - constant clk_period : time := 1ns; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: slayer PORT MAP ( - input => input, - output => output - ); - - -- Clock process definitions - clk_process :process - begin - clk <= '0'; - wait for clk_period/2; - clk <= '1'; - wait for clk_period/2; - end process; - - - -- Stimulus process - stim_proc: process - begin - -- hold reset state for 100ms. - reset <= '1'; - wait for 100ns; - reset <= '0'; - wait for clk_period; - input <= x"0"; - wait for clk_period; - input <= x"A"; - wait for clk_period; - input <= x"F"; - wait for clk_period; - -- insert stimulus here - assert false severity failure; - end process; - -END; \ No newline at end of file Index: 32BitIO/mux80.vhd =================================================================== --- 32BitIO/mux80.vhd (revision 3) +++ 32BitIO/mux80.vhd (nonexistent) @@ -1,72 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 20:59:34 04/03/2011 --- Design Name: --- Module Name: mux - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use work.kody.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity mux80 is - generic ( - w_2 : integer := 2; - w_32 : integer := 32; - w_80 : integer := 80 - ); - port( - i0ctrl : in std_logic_vector (w_2-1 downto 0); - input0 : in std_logic_vector(w_32-1 downto 0); - input1 : in std_logic_vector(w_80-1 downto 0); - output : inout std_logic_vector(w_80-1 downto 0); - ctrl, clk, reset : in std_logic - ); -end mux80; - -architecture Behavioral of mux80 is - -begin - inne : process (clk, reset) - begin - if (reset = '1') then - output <= (others => '0'); - elsif (clk'Event and clk = '1') then - if ctrl = '0' then - if (i0ctrl = in_ld_reg_L ) then - output <= output(80-1 downto 32) & input0; - elsif (i0ctrl = in_ld_reg_H) then - output <= output(79 downto 64) & input0 & output(31 downto 0); - elsif (i0ctrl = in_ld_reg_HH) then - output <= input0(15 downto 0) & output(63 downto 0); - else - output <= output; - end if; - else - output <= input1; - end if; - end if; - end process inne; -end Behavioral; - Index: 32BitIO/pLayer.vhd =================================================================== --- 32BitIO/pLayer.vhd (revision 3) +++ 32BitIO/pLayer.vhd (nonexistent) @@ -1,99 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 16:06:24 05/13/2010 --- Design Name: --- Module Name: pLayer - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity pLayer is - generic(w_64 : integer := 64); - port ( - input : in std_logic_vector(w_64-1 downto 0); - output : out std_logic_vector(w_64-1 downto 0) - ); -end pLayer; - -architecture Behavioral of pLayer is -begin - output(0) <= input(0); - output(16) <= input(1); - output(32) <= input(2); - output(48) <= input(3); - output(1) <= input(4); - output(17) <= input(5); - output(33) <= input(6); - output(49) <= input(7); - output(2) <= input(8); - output(18) <= input(9); - output(34) <= input(10); - output(50) <= input(11); - output(3) <= input(12); - output(19) <= input(13); - output(35) <= input(14); - output(51) <= input(15); - output(4) <= input(16); - output(20) <= input(17); - output(36) <= input(18); - output(52) <= input(19); - output(5) <= input(20); - output(21) <= input(21); - output(37) <= input(22); - output(53) <= input(23); - output(6) <= input(24); - output(22) <= input(25); - output(38) <= input(26); - output(54) <= input(27); - output(7) <= input(28); - output(23) <= input(29); - output(39) <= input(30); - output(55) <= input(31); - output(8) <= input(32); - output(24) <= input(33); - output(40) <= input(34); - output(56) <= input(35); - output(9) <= input(36); - output(25) <= input(37); - output(41) <= input(38); - output(57) <= input(39); - output(10) <= input(40); - output(26) <= input(41); - output(42) <= input(42); - output(58) <= input(43); - output(11) <= input(44); - output(27) <= input(45); - output(43) <= input(46); - output(59) <= input(47); - output(12) <= input(48); - output(28) <= input(49); - output(44) <= input(50); - output(60) <= input(51); - output(13) <= input(52); - output(29) <= input(53); - output(45) <= input(54); - output(61) <= input(55); - output(14) <= input(56); - output(30) <= input(57); - output(46) <= input(58); - output(62) <= input(59); - output(15) <= input(60); - output(31) <= input(61); - output(47) <= input(62); - output(63) <= input(63); -end Behavioral; \ No newline at end of file Index: 32BitIO/txt_util.vhd =================================================================== --- 32BitIO/txt_util.vhd (revision 3) +++ 32BitIO/txt_util.vhd (nonexistent) @@ -1,586 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use std.textio.all; - - -package txt_util is - - -- prints a message to the screen - procedure print(text: string); - - -- prints the message when active - -- useful for debug switches - procedure print(active: boolean; text: string); - - -- converts std_logic into a character - function chr(sl: std_logic) return character; - - -- converts std_logic into a string (1 to 1) - function str(sl: std_logic) return string; - - -- converts std_logic_vector into a string (binary base) - function str(slv: std_logic_vector) return string; - - -- converts boolean into a string - function str(b: boolean) return string; - - -- converts an integer into a single character - -- (can also be used for hex conversion and other bases) - function chr(int: integer) return character; - - -- converts integer into string using specified base - function str(int: integer; base: integer) return string; - - -- converts integer to string, using base 10 - function str(int: integer) return string; - - -- convert std_logic_vector into a string in hex format - function hstr(slv: std_logic_vector) return string; - - - -- functions to manipulate strings - ----------------------------------- - - -- convert a character to upper case - function to_upper(c: character) return character; - - -- convert a character to lower case - function to_lower(c: character) return character; - - -- convert a string to upper case - function to_upper(s: string) return string; - - -- convert a string to lower case - function to_lower(s: string) return string; - - - - -- functions to convert strings into other formats - -------------------------------------------------- - - -- converts a character into std_logic - function to_std_logic(c: character) return std_logic; - - -- converts a string into std_logic_vector - function to_std_logic_vector(s: string) return std_logic_vector; - - - - -- file I/O - ----------- - - -- read variable length string from input file - procedure str_read(file in_file: TEXT; - res_string: out string); - - -- print string to a file and start new line - procedure print(file out_file: TEXT; - new_string: in string); - - -- print character to a file and start new line - procedure print(file out_file: TEXT; - char: in character); - -end txt_util; - - - - -package body txt_util is - - - - - -- prints text to the screen - - procedure print(text: string) is - variable msg_line: line; - begin - write(msg_line, text); - writeline(output, msg_line); - end print; - - - - - -- prints text to the screen when active - - procedure print(active: boolean; text: string) is - begin - if active then - print(text); - end if; - end print; - - - -- converts std_logic into a character - - function chr(sl: std_logic) return character is - variable c: character; - begin - case sl is - when 'U' => c:= 'U'; - when 'X' => c:= 'X'; - when '0' => c:= '0'; - when '1' => c:= '1'; - when 'Z' => c:= 'Z'; - when 'W' => c:= 'W'; - when 'L' => c:= 'L'; - when 'H' => c:= 'H'; - when '-' => c:= '-'; - end case; - return c; - end chr; - - - - -- converts std_logic into a string (1 to 1) - - function str(sl: std_logic) return string is - variable s: string(1 to 1); - begin - s(1) := chr(sl); - return s; - end str; - - - - -- converts std_logic_vector into a string (binary base) - -- (this also takes care of the fact that the range of - -- a string is natural while a std_logic_vector may - -- have an integer range) - - function str(slv: std_logic_vector) return string is - variable result : string (1 to slv'length); - variable r : integer; - begin - r := 1; - for i in slv'range loop - result(r) := chr(slv(i)); - r := r + 1; - end loop; - return result; - end str; - - - function str(b: boolean) return string is - - begin - if b then - return "true"; - else - return "false"; - end if; - end str; - - - -- converts an integer into a character - -- for 0 to 9 the obvious mapping is used, higher - -- values are mapped to the characters A-Z - -- (this is usefull for systems with base > 10) - -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) - - function chr(int: integer) return character is - variable c: character; - begin - case int is - when 0 => c := '0'; - when 1 => c := '1'; - when 2 => c := '2'; - when 3 => c := '3'; - when 4 => c := '4'; - when 5 => c := '5'; - when 6 => c := '6'; - when 7 => c := '7'; - when 8 => c := '8'; - when 9 => c := '9'; - when 10 => c := 'A'; - when 11 => c := 'B'; - when 12 => c := 'C'; - when 13 => c := 'D'; - when 14 => c := 'E'; - when 15 => c := 'F'; - when 16 => c := 'G'; - when 17 => c := 'H'; - when 18 => c := 'I'; - when 19 => c := 'J'; - when 20 => c := 'K'; - when 21 => c := 'L'; - when 22 => c := 'M'; - when 23 => c := 'N'; - when 24 => c := 'O'; - when 25 => c := 'P'; - when 26 => c := 'Q'; - when 27 => c := 'R'; - when 28 => c := 'S'; - when 29 => c := 'T'; - when 30 => c := 'U'; - when 31 => c := 'V'; - when 32 => c := 'W'; - when 33 => c := 'X'; - when 34 => c := 'Y'; - when 35 => c := 'Z'; - when others => c := '?'; - end case; - return c; - end chr; - - - - -- convert integer to string using specified base - -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) - - function str(int: integer; base: integer) return string is - - variable temp: string(1 to 10); - variable num: integer; - variable abs_int: integer; - variable len: integer := 1; - variable power: integer := 1; - - begin - - -- bug fix for negative numbers - abs_int := abs(int); - - num := abs_int; - - while num >= base loop -- Determine how many - len := len + 1; -- characters required - num := num / base; -- to represent the - end loop ; -- number. - - for i in len downto 1 loop -- Convert the number to - temp(i) := chr(abs_int/power mod base); -- a string starting - power := power * base; -- with the right hand - end loop ; -- side. - - -- return result and add sign if required - if int < 0 then - return '-'& temp(1 to len); - else - return temp(1 to len); - end if; - - end str; - - - -- convert integer to string, using base 10 - function str(int: integer) return string is - - begin - - return str(int, 10) ; - - end str; - - - - -- converts a std_logic_vector into a hex string. - function hstr(slv: std_logic_vector) return string is - variable hexlen: integer; - variable longslv : std_logic_vector(67 downto 0) := (others => '0'); - variable hex : string(1 to 16); - variable fourbit : std_logic_vector(3 downto 0); - begin - hexlen := (slv'left+1)/4; - if (slv'left+1) mod 4 /= 0 then - hexlen := hexlen + 1; - end if; - longslv(slv'left downto 0) := slv; - for i in (hexlen -1) downto 0 loop - fourbit := longslv(((i*4)+3) downto (i*4)); - case fourbit is - when "0000" => hex(hexlen -I) := '0'; - when "0001" => hex(hexlen -I) := '1'; - when "0010" => hex(hexlen -I) := '2'; - when "0011" => hex(hexlen -I) := '3'; - when "0100" => hex(hexlen -I) := '4'; - when "0101" => hex(hexlen -I) := '5'; - when "0110" => hex(hexlen -I) := '6'; - when "0111" => hex(hexlen -I) := '7'; - when "1000" => hex(hexlen -I) := '8'; - when "1001" => hex(hexlen -I) := '9'; - when "1010" => hex(hexlen -I) := 'A'; - when "1011" => hex(hexlen -I) := 'B'; - when "1100" => hex(hexlen -I) := 'C'; - when "1101" => hex(hexlen -I) := 'D'; - when "1110" => hex(hexlen -I) := 'E'; - when "1111" => hex(hexlen -I) := 'F'; - when "ZZZZ" => hex(hexlen -I) := 'z'; - when "UUUU" => hex(hexlen -I) := 'u'; - when "XXXX" => hex(hexlen -I) := 'x'; - when others => hex(hexlen -I) := '?'; - end case; - end loop; - return hex(1 to hexlen); - end hstr; - - - - -- functions to manipulate strings - ----------------------------------- - - - -- convert a character to upper case - - function to_upper(c: character) return character is - - variable u: character; - - begin - - case c is - when 'a' => u := 'A'; - when 'b' => u := 'B'; - when 'c' => u := 'C'; - when 'd' => u := 'D'; - when 'e' => u := 'E'; - when 'f' => u := 'F'; - when 'g' => u := 'G'; - when 'h' => u := 'H'; - when 'i' => u := 'I'; - when 'j' => u := 'J'; - when 'k' => u := 'K'; - when 'l' => u := 'L'; - when 'm' => u := 'M'; - when 'n' => u := 'N'; - when 'o' => u := 'O'; - when 'p' => u := 'P'; - when 'q' => u := 'Q'; - when 'r' => u := 'R'; - when 's' => u := 'S'; - when 't' => u := 'T'; - when 'u' => u := 'U'; - when 'v' => u := 'V'; - when 'w' => u := 'W'; - when 'x' => u := 'X'; - when 'y' => u := 'Y'; - when 'z' => u := 'Z'; - when others => u := c; - end case; - - return u; - - end to_upper; - - - -- convert a character to lower case - - function to_lower(c: character) return character is - - variable l: character; - - begin - - case c is - when 'A' => l := 'a'; - when 'B' => l := 'b'; - when 'C' => l := 'c'; - when 'D' => l := 'd'; - when 'E' => l := 'e'; - when 'F' => l := 'f'; - when 'G' => l := 'g'; - when 'H' => l := 'h'; - when 'I' => l := 'i'; - when 'J' => l := 'j'; - when 'K' => l := 'k'; - when 'L' => l := 'l'; - when 'M' => l := 'm'; - when 'N' => l := 'n'; - when 'O' => l := 'o'; - when 'P' => l := 'p'; - when 'Q' => l := 'q'; - when 'R' => l := 'r'; - when 'S' => l := 's'; - when 'T' => l := 't'; - when 'U' => l := 'u'; - when 'V' => l := 'v'; - when 'W' => l := 'w'; - when 'X' => l := 'x'; - when 'Y' => l := 'y'; - when 'Z' => l := 'z'; - when others => l := c; - end case; - - return l; - - end to_lower; - - - - -- convert a string to upper case - - function to_upper(s: string) return string is - - variable uppercase: string (s'range); - - begin - - for i in s'range loop - uppercase(i):= to_upper(s(i)); - end loop; - return uppercase; - - end to_upper; - - - - -- convert a string to lower case - - function to_lower(s: string) return string is - - variable lowercase: string (s'range); - - begin - - for i in s'range loop - lowercase(i):= to_lower(s(i)); - end loop; - return lowercase; - - end to_lower; - - - --- functions to convert strings into other types - - --- converts a character into a std_logic - -function to_std_logic(c: character) return std_logic is - variable sl: std_logic; - begin - case c is - when 'U' => - sl := 'U'; - when 'X' => - sl := 'X'; - when '0' => - sl := '0'; - when '1' => - sl := '1'; - when 'Z' => - sl := 'Z'; - when 'W' => - sl := 'W'; - when 'L' => - sl := 'L'; - when 'H' => - sl := 'H'; - when '-' => - sl := '-'; - when others => - sl := 'X'; - end case; - return sl; - end to_std_logic; - - --- converts a string into std_logic_vector - -function to_std_logic_vector(s: string) return std_logic_vector is - variable slv: std_logic_vector(s'high-s'low downto 0); - variable k: integer; -begin - k := s'high-s'low; - for i in s'range loop - slv(k) := to_std_logic(s(i)); - k := k - 1; - end loop; - return slv; -end to_std_logic_vector; - - - - - - ----------------- --- file I/O -- ----------------- - - - --- read variable length string from input file - -procedure str_read(file in_file: TEXT; - res_string: out string) is - - variable l: line; - variable c: character; - variable is_string: boolean; - - begin - - readline(in_file, l); - -- clear the contents of the result string - for i in res_string'range loop - res_string(i) := ' '; - end loop; - -- read all characters of the line, up to the length - -- of the results string - for i in res_string'range loop - read(l, c, is_string); - res_string(i) := c; - if not is_string then -- found end of line - exit; - end if; - end loop; - -end str_read; - - --- print string to a file -procedure print(file out_file: TEXT; - new_string: in string) is - - variable l: line; - - begin - - write(l, new_string); - writeline(out_file, l); - -end print; - - --- print character to a file and start new line -procedure print(file out_file: TEXT; - char: in character) is - - variable l: line; - - begin - - write(l, char); - writeline(out_file, l); - -end print; - - - --- appends contents of a string to a file until line feed occurs --- (LF is considered to be the end of the string) - -procedure str_write(file out_file: TEXT; - new_string: in string) is - begin - - for i in new_string'range loop - print(out_file, new_string(i)); - if new_string(i) = LF then -- end of string - exit; - end if; - end loop; - -end str_write; - - - - -end txt_util; - - - - Index: 32BitIO/PresentStateMachine.vhd =================================================================== --- 32BitIO/PresentStateMachine.vhd (revision 3) +++ 32BitIO/PresentStateMachine.vhd (nonexistent) @@ -1,160 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:17:10 04/02/2011 --- Design Name: --- Module Name: PresentStateMachine - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.NUMERIC_STD.ALL; -use work.kody.ALL; - -entity PresentStateMachine is - generic ( - w_2 : integer := 2; - w_4 : integer := 4; - w_5 : integer := 5; - w_32: integer := 32; - w_64: integer := 64; - w_80: integer := 80 - ); - port ( - clk, reset : in std_logic; - info : in std_logic_vector (w_2-1 downto 0); - ctrl : in std_logic_vector (w_4-1 downto 0); - key_ctrl: out std_logic_vector (w_2-1 downto 0); - plain_ctrl: out std_logic_vector (w_2-1 downto 0); - outReg : out std_logic_vector (w_2-1 downto 0); - ready, cnt_res, ctrl_mux64, ctrl_mux80: out std_logic - ); -end PresentStateMachine; - -architecture Behavioral of PresentStateMachine is - - signal stan : stany; - signal stan_nast : stany; - - begin - States : process(stan, ctrl, info) - begin - stan_nast<= stan; - case stan is - when NOP => - ready <= '0'; - outReg <= out_reg_Z; - cnt_res <= '0'; - ctrl_mux64 <= '0'; - ctrl_mux80 <= '0'; - if (ctrl = crdk1) then - key_ctrl <= in_ld_reg_L; - stan_nast <= RDK1; - else - stan_nast <= NOP; - end if; - when RDK1 => - if (ctrl = crdk2) then - key_ctrl <= in_ld_reg_H; - stan_nast <= RDK2; - elsif (ctrl = crdk1) then - key_ctrl <= in_ld_reg_L; - else - stan_nast <= NOP; - end if; - when RDK2 => - if (ctrl = crdk3) then - key_ctrl <= in_ld_reg_HH; - stan_nast <= RDK3; - elsif (ctrl = crdk2) then - key_ctrl <= in_ld_reg_H; - else - stan_nast <= NOP; - end if; - when RDK3 => - if (ctrl = crdt1) then - key_ctrl <= in_reg_Z; - plain_ctrl <= in_ld_reg_L; - stan_nast <= RDT1; - elsif (ctrl = crdk3) then - key_ctrl <= in_ld_reg_HH; - else - stan_nast <= NOP; - end if; - when RDT1 => - if (ctrl = crdt2) then - plain_ctrl <= in_ld_reg_H; - stan_nast <= RDT2; - elsif (ctrl = crdt1) then - plain_ctrl <= in_ld_reg_L; - else - stan_nast <= NOP; - end if; - when RDT2 => - if (ctrl = ccod) then - plain_ctrl <= in_reg_Z; - stan_nast <= COD; - cnt_res <= '1'; - elsif (ctrl = crdt2) then - plain_ctrl <= in_ld_reg_H; - else - stan_nast <= NOP; - end if; - when COD => - if (ctrl = ccod) then - if (info = "00") then - stan_nast <= CTO1; - outReg <= out_ld_reg; - ready <= '1'; - cnt_res <= '0'; - ready <= '1'; - elsif (info = "01") then - ctrl_mux64 <= '1'; - ctrl_mux80 <= '1'; - end if; - else - stan_nast <= NOP; - end if; - when CTO1 => - if (ctrl = ccto2) then - stan_nast <= CTO2; - outReg <= out_reg_L; - elsif ((ctrl = ccto1) or (ctrl = ccod)) then - outReg <= out_reg_L; - else - stan_nast <= NOP; - end if; - when CTO2 => - if (ctrl = ccto2) then - stan_nast <= CTO2; - outReg <= out_reg_H; - else - stan_nast <= NOP; - end if; - end case; - end process States; - - inne : process (clk, reset) - begin - if (reset = '1') then - stan <= NOP; - elsif (clk'Event and clk = '1') then - stan <= stan_nast; - end if; - end process inne; - - end Behavioral; - Index: 32BitIO/keyupd.vhd =================================================================== --- 32BitIO/keyupd.vhd (revision 3) +++ 32BitIO/keyupd.vhd (nonexistent) @@ -1,59 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 19:45:36 05/13/2010 --- Design Name: --- Module Name: keyupd - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity keyupd is - generic( - w_80: integer := 80; - w_5 : integer := 5; - w_4 : integer := 4); - port( - key : in std_logic_vector(w_80-1 downto 0); - num : in std_logic_vector(w_5-1 downto 0); - keyout : out std_logic_vector(w_80-1 downto 0) - ); -end keyupd; - -architecture Behavioral of keyupd is - - component slayer is - generic(w_4: integer := 4); - port( - input : in std_logic_vector(w_4-1 downto 0); - output : out std_logic_vector(w_4-1 downto 0) - ); - end component; - - signal changed : std_logic_vector(w_4-1 downto 0); - signal changin : std_logic_vector(w_4-1 downto 0); - signal keytemp : std_logic_vector(w_80-1 downto 0); - - begin - s1: slayer port map(input => changin, output => changed); - changin <= keytemp(79 downto 76); - keytemp <= key(18 downto 0) & key(79 downto 19); - keyout(79 downto 76)<= changed; - keyout(75 downto 20) <= keytemp(75 downto 20); - keyout(19 downto 15)<= keytemp(19 downto 15) xor num; - keyout(14 downto 0) <= keytemp(14 downto 0); - end Behavioral; \ No newline at end of file Index: 32BitIO/PresentEncTB.vhd =================================================================== --- 32BitIO/PresentEncTB.vhd (revision 3) +++ 32BitIO/PresentEncTB.vhd (nonexistent) @@ -1,260 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 10:29:45 05/16/2010 --- Design Name: --- Module Name: C:/Users/gajos/Desktop/Polibuda/vhdl/projekt/szyfrator/PresentEncTB.vhd --- Project Name: szyfrator --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: PresentEnc --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.all; -USE ieee.numeric_std.ALL; -USE std.textio.all; -USE work.txt_util.all; -USE ieee.std_logic_textio.all; -use work.kody.ALL; - -ENTITY PresentEncTB IS -END PresentEncTB; - -ARCHITECTURE behavior OF PresentEncTB IS - - -- Component Declaration for the Unit Under Test (UUT) - - COMPONENT PresentEnc - PORT( - input : IN std_logic_vector(31 downto 0); - output : OUT std_logic_vector(31 downto 0); - ctrl : IN std_logic_vector(3 downto 0); - clk : IN std_logic; - reset : IN std_logic; - ready : out std_logic - ); - END COMPONENT; - - -- Clock period definitions - constant clk_period : time := 1ns; - constant p10 : time := clk_period/10; - constant edge : time := clk_period-p10; - - --Inputs - signal input : std_logic_vector(31 downto 0) := (others => '0'); - signal ctrl : std_logic_vector(3 downto 0) := (others => '0'); - signal clk : std_logic := '0'; - signal reset : std_logic := '0'; - signal strobe : std_logic; - - --Outputs - signal output : std_logic_vector(31 downto 0); - signal ready : std_logic := '0'; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: PresentEnc PORT MAP ( - input => input, - output => output, - ctrl => ctrl, - clk => clk, - reset => reset, - ready => ready - ); - - -- Clock process definitions - clk_process :process - begin - clk <= '0'; - wait for clk_period/2; - clk <= '1'; - wait for clk_period/2; - end process; - - - -- Stimulus process - stim_proc: process - - file infile :text is in "wejscie.txt"; - variable line_in :line; - variable bytes : std_logic_vector(32 downto 0); - variable bytes2 : std_logic_vector(3 downto 0); - variable xbit : std_logic; - - - begin - -- hold reset state for 100ms. - wait for 100ns; - reset <= '1'; - wait for 10ns; - reset <= '0'; - wait for 10ns; - -- insert stimulus here - while not (endfile(infile)) loop - readline(infile, line_in); --2 - hread(line_in, bytes2); - ctrl <= bytes2; - wait for clk_period; - readline(infile, line_in); -- 1 - hread(line_in, bytes2); - ctrl <= bytes2; - readline(infile, line_in); - read(line_in, xbit); - input <= (others => xbit); - wait for clk_period; - readline(infile, line_in); - hread(line_in, bytes2); - ctrl <= bytes2; - readline(infile, line_in); - read(line_in, xbit); - input <= (others => xbit); - wait for clk_period; - readline(infile, line_in); - hread(line_in, bytes2); - ctrl <= bytes2; - readline(infile, line_in); - read(line_in, xbit); - input <= (others => xbit); - wait for clk_period; - readline(infile, line_in); - hread(line_in, bytes2); - ctrl <= bytes2; - readline(infile, line_in); - read(line_in, xbit); - input <= (others => xbit); - wait for clk_period; - readline(infile, line_in); - hread(line_in, bytes2); - ctrl <= bytes2; - readline(infile, line_in); - read(line_in, xbit); - input <= (others => xbit); - wait for clk_period; - readline(infile, line_in); - hread(line_in, bytes2); - ctrl <= bytes2; - wait for clk_period*33; - readline(infile, line_in); - hread(line_in, bytes2); - ctrl <= bytes2; - wait for clk_period; - readline(infile, line_in); - hread(line_in, bytes2); - ctrl <= bytes2; - wait for clk_period*2; - end loop; - assert false severity failure; - end process; - - strobe <= TRANSPORT clk AFTER edge; - - outs: PROCESS (strobe) - variable str :string(1 to 29); - variable lineout :line; - variable init_file :std_logic := '1'; - file outfile :text is out "wyjscie.txt"; - - -------- funkcja konwersji: std_logic_vector => character -------- - function conv_to_hex_char (sig: std_logic_vector(3 downto 0)) RETURN character IS - begin - case sig is - when "0000" => return '0'; - when "0001" => return '1'; - when "0010" => return '2'; - when "0011" => return '3'; - when "0100" => return '4'; - when "0101" => return '5'; - when "0110" => return '6'; - when "0111" => return '7'; - when "1000" => return '8'; - when "1001" => return '9'; - when "1010" => return 'A'; - when "1011" => return 'B'; - when "1100" => return 'C'; - when "1101" => return 'D'; - when "1110" => return 'E'; - when others => return 'F'; - end case; - end conv_to_hex_char; - - -------- funkcja konwersji: std_logic => character -------- - function conv_to_char (sig: std_logic) RETURN character IS - begin - case sig is - when '1' => return '1'; - when '0' => return '0'; - when 'Z' => return 'Z'; - when others => return 'X'; - end case; - end conv_to_char; - - -------- funkcja konwersji: std_logic_vector => string -------- - function conv_to_string (inp: std_logic_vector; length: integer) RETURN string IS - variable x : integer := length/4; - variable s : string(1 to x); - begin - for i in 0 to (x-1) loop - s(x-i) := conv_to_hex_char(inp(4*i+3 downto 4*i)); - end loop; - return s; - end conv_to_string; - - ------------------------------------- - begin - -------- nag��wek pliku wyj�ciowego (podzia� kolumn) -------- - if init_file = '1' then - str:="clk "; - write(lineout,str); writeline(outfile,lineout); - str:="| reset "; - write(lineout,str); writeline(outfile,lineout); - str:="| | ready "; - write(lineout,str); writeline(outfile,lineout); - str:="| | | ctrl "; - write(lineout,str); writeline(outfile,lineout); - str:="| | | | input "; - write(lineout,str); writeline(outfile,lineout); - str:="| | | | | output "; - write(lineout,str); writeline(outfile,lineout); - str:="| | | | | | "; - write(lineout,str); writeline(outfile,lineout); - init_file := '0'; - end if; - - -------- zapis danych do pliku wyjsciowego �wyjscie� -------- - if (strobe'EVENT and strobe='0') then - str := (others => ' '); - str(1) := conv_to_char(clk); - str(2) := '|'; - str(3) := conv_to_char(reset); - str(4) := '|'; - str(5) := conv_to_char(ready); - str(6) := '|'; - str(7) := conv_to_hex_char(ctrl); - str(8) := '|'; - str(9 to 16) := conv_to_string(input,32); - str(17) := '|'; - str(18 to 25) := conv_to_string(output,32); - str(26) := '|'; - write(lineout,str); - writeline(outfile,lineout); - end if; - end process outs; -end; \ No newline at end of file Index: 32BitIO/slayer.vhd =================================================================== --- 32BitIO/slayer.vhd (revision 3) +++ 32BitIO/slayer.vhd (nonexistent) @@ -1,55 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 13:48:15 05/13/2010 --- Design Name: --- Module Name: permutation - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity slayer is - generic ( - w_4 : integer := 4 - ); - port ( - input : in std_logic_vector(w_4-1 downto 0); - output : out std_logic_vector(w_4-1 downto 0) - ); -end slayer; - -architecture Behavioral of slayer is - - begin - output <= x"C" when input = x"0" else - x"5" when input = x"1" else - x"6" when input = x"2" else - x"B" when input = x"3" else - x"9" when input = x"4" else - x"0" when input = x"5" else - x"A" when input = x"6" else - x"D" when input = x"7" else - x"3" when input = x"8" else - x"E" when input = x"9" else - x"F" when input = x"A" else - x"8" when input = x"B" else - x"4" when input = x"C" else - x"7" when input = x"D" else - x"1" when input = x"E" else - x"2" when input = x"F" else - "ZZZZ"; - end Behavioral; \ No newline at end of file Index: 32BitIO/counter.vhd =================================================================== --- 32BitIO/counter.vhd (revision 3) +++ 32BitIO/counter.vhd (nonexistent) @@ -1,61 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 13:47:04 04/02/2011 --- Design Name: --- Module Name: counter - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity counter is - generic ( - w_2 : integer := 2; - w_5 : integer := 5 - ); - port ( - clk, reset, cnt_res : in std_logic; - info : out std_logic_vector (w_2-1 downto 0); - num : out std_logic_vector (w_5-1 downto 0) - ); -end counter; - -architecture Behavioral of counter is - begin - licznik : process (clk, reset) - variable cnt : unsigned(w_5-1 downto 0); - begin - if (reset = '1') then - cnt := (others => '0'); - elsif (clk'Event and clk = '1') then - if (cnt_res = '1') then - cnt := cnt + 1; - if (std_logic_vector(cnt) = "00001") then - info <= "01"; - elsif (std_logic_vector(cnt) = "00000") then - info <= "00"; - else - info <= "11"; - end if; - else - cnt := (others => '0'); - end if; - end if; - num <= std_logic_vector(cnt); - end process licznik; - end Behavioral; - Index: 32BitIO/mux64.vhd =================================================================== --- 32BitIO/mux64.vhd (revision 3) +++ 32BitIO/mux64.vhd (nonexistent) @@ -1,70 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 20:59:34 04/03/2011 --- Design Name: --- Module Name: mux - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use work.kody.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity mux64 is - generic ( - w_2 : integer := 2; - w_32 : integer := 32; - w_64 : integer := 64 - ); - port( - i0ctrl : in std_logic_vector (w_2-1 downto 0); - input0 : in std_logic_vector(w_32-1 downto 0); - input1 : in std_logic_vector(w_64-1 downto 0); - ctrl, clk, reset : in std_logic; - output : inout std_logic_vector(w_64-1 downto 0) - ); -end mux64; - -architecture Behavioral of mux64 is - -begin - inne : process (clk, reset) - begin - if (reset = '1') then - output <= (others => '0'); - elsif (clk'Event and clk = '1') then - if ctrl = '0' then - if (i0ctrl = in_ld_reg_L ) then - output <= output(w_64-1 downto 32) & input0; - elsif (i0ctrl = in_ld_reg_H) then - output <= input0 & output(31 downto 0); - else - output <= output; - end if; - else - output <= input1; - end if; - end if; - end process inne; -end Behavioral; - Index: 32BitIO/kody.vhd =================================================================== --- 32BitIO/kody.vhd (revision 3) +++ 32BitIO/kody.vhd (nonexistent) @@ -1,34 +0,0 @@ --- Package File Template --- --- Purpose: This package defines supplemental types, subtypes, --- constants, and functions - - -library IEEE; -use IEEE.STD_LOGIC_1164.all; -package kody is - -- type for PresentStateMachine to control the datapath & circuit -- - type stany is (NOP, RDK1, RDK2, RDK3, RDT1, RDT2, COD, CTO1, CTO2); - -- constant as control command from input -- - constant cnop : std_logic_vector(3 downto 0) := "0000"; --0 no operations - constant cdec : std_logic_vector(3 downto 0) := "0001"; --1 decode text - constant crdk1 : std_logic_vector(3 downto 0) := "0010"; --2 read key part 1 - constant crdk2 : std_logic_vector(3 downto 0) := "0011"; --3 read key part 2 - constant crdk3 : std_logic_vector(3 downto 0) := "0100"; --4 read key part 3 - constant cmkd : std_logic_vector(3 downto 0) := "0101"; --5 make decrypt key - constant ccod : std_logic_vector(3 downto 0) := "0110"; --6 code text - constant crdt1 : std_logic_vector(3 downto 0) := "0111"; --7 read text part 1 - constant crdt2 : std_logic_vector(3 downto 0) := "1000"; --8 read text part 2 - constant ccto1 : std_logic_vector(3 downto 0) := "1001"; --9 ciphertext output part 1 (LSW) - constant ccto2 : std_logic_vector(3 downto 0) := "1010"; --A ciphertext output part 2 (MSW) - -- For input registers (early version, now for mux's) -- - constant in_ld_reg_L : std_logic_vector(1 downto 0) := "00"; -- Load low part of the register (64 & 80 bit) - constant in_ld_reg_H : std_logic_vector(1 downto 0) := "01"; -- Load high part of the register (64 & 80 bit) - constant in_ld_reg_HH : std_logic_vector(1 downto 0) := "10"; -- Load highest part of the register (80 bit only) - constant in_reg_Z : std_logic_vector(1 downto 0) := "11"; -- High impedance on the line (unused - in this design only for block input) - -- For output register -- - constant out_ld_reg : std_logic_vector(1 downto 0) := "00"; -- Load the output register - constant out_reg_L : std_logic_vector(1 downto 0) := "01"; -- send low part of the register to the output - constant out_reg_H : std_logic_vector(1 downto 0) := "10"; -- senf high part of the register to the output - constant out_reg_Z : std_logic_vector(1 downto 0) := "11"; -- High impedance on the line (unused - in this design only for block input) -end kody; \ No newline at end of file Index: 32BitIO/outputRegister.vhd =================================================================== --- 32BitIO/outputRegister.vhd (revision 3) +++ 32BitIO/outputRegister.vhd (nonexistent) @@ -1,65 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:58:15 04/02/2011 --- Design Name: --- Module Name: outputRegister - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use work.kody.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - -entity outputRegister is - generic ( - w_2 : integer := 2; - w_32: integer := 32; - w_64: integer := 64 - ); - port( - rst, clk, rd : in std_logic; - ctrl : in std_logic_vector(w_2-1 downto 0); - input : in std_logic_vector(w_64-1 downto 0); - output : out std_logic_vector(w_32-1 downto 0); - ready : out std_logic - ); -end outputRegister; - -architecture Behavioral of outputRegister is - signal reg : std_logic_vector(w_64-1 downto 0); - begin - process( rst, clk, ctrl, input) - begin - if (rst = '1') then - output <= (others=>'Z'); - elsif(clk'event and clk = '1') then - if(ctrl = out_ld_reg) then - reg <= input; - output <= (others=>'Z'); - elsif (ctrl = out_reg_L) then - output <= reg(w_32-1 downto 0); - elsif (ctrl = out_reg_H) then - output <= reg(w_64-1 downto w_32); - else - output <= (others=>'Z'); - end if; - end if; - end process; - ready <= rd; - end Behavioral; - Index: 32BitIO/bench/vhdl/sLayerTB.vhd =================================================================== --- 32BitIO/bench/vhdl/sLayerTB.vhd (nonexistent) +++ 32BitIO/bench/vhdl/sLayerTB.vhd (revision 4) @@ -0,0 +1,111 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Substitution layer test bench of Present encoder. ---- +---- Nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + +ENTITY sLayerTB IS +END sLayerTB; + +ARCHITECTURE behavior OF sLayerTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT slayer + PORT( + input : IN std_logic_vector(3 downto 0); + output : OUT std_logic_vector(3 downto 0) + ); + END COMPONENT; + + + --Inputs + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --BiDirs + signal input : std_logic_vector(3 downto 0); + signal output : std_logic_vector(3 downto 0); + + -- Clock period definitions + constant clk_period : time := 1ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: slayer PORT MAP ( + input => input, + output => output + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + reset <= '1'; + wait for 100ns; + reset <= '0'; + wait for clk_period; + input <= x"0"; + wait for clk_period; + input <= x"A"; + wait for clk_period; + input <= x"F"; + wait for clk_period; + -- insert stimulus here + assert false severity failure; + end process; + +END; \ No newline at end of file Index: 32BitIO/bench/vhdl/keyupdTB.vhd =================================================================== --- 32BitIO/bench/vhdl/keyupdTB.vhd (nonexistent) +++ 32BitIO/bench/vhdl/keyupdTB.vhd (revision 4) @@ -0,0 +1,122 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Key update test bench. It was much more used during ---- +---- inverse so data below are the same. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + +ENTITY keyupdTB IS +END keyupdTB; + +ARCHITECTURE behavior OF keyupdTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT keyupd + PORT( + key : IN std_logic_vector(79 downto 0); + num : IN std_logic_vector(4 downto 0); + keyout : OUT std_logic_vector(79 downto 0)--; + --clk, reset : std_logic + ); + END COMPONENT; + + + --Inputs + signal key : std_logic_vector(79 downto 0) := (others => '0'); + signal num : std_logic_vector(4 downto 0) := (others => '0'); + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --Outputs + signal keyout : std_logic_vector(79 downto 0); + + constant clk_period : time := 1ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: keyupd PORT MAP ( + key => key, + num => num, + keyout => keyout--, + --clk => clk, + --reset => reset + ); + + -- No clocks detected in port list. Replace clk below with + -- appropriate port name + + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + reset <= '1'; + wait for 100ns; + reset <='0'; + wait for clk_period; + key <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + num <= "00001"; + wait for clk_period; + key <= x"c0000000000000008000"; + num <= "00010"; + wait for clk_period; + key <= x"50001800000000010000"; + num <= "00011"; + wait for clk_period; + key <= x"8ba27a0eb8783ac96d59"; + num <= "11111"; + wait for clk_period; + assert false severity failure; + end process; +END; \ No newline at end of file Index: 32BitIO/bench/vhdl/PresentEncTB.vhd =================================================================== --- 32BitIO/bench/vhdl/PresentEncTB.vhd (nonexistent) +++ 32BitIO/bench/vhdl/PresentEncTB.vhd (revision 4) @@ -0,0 +1,275 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Test bench of Present encoder with 32 bit IO. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; +USE std.textio.all; +USE work.txt_util.all; +USE ieee.std_logic_textio.all; +use work.kody.ALL; + +ENTITY PresentEncTB IS +END PresentEncTB; + +ARCHITECTURE behavior OF PresentEncTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT PresentEnc + PORT( + input : IN std_logic_vector(31 downto 0); + output : OUT std_logic_vector(31 downto 0); + ctrl : IN std_logic_vector(3 downto 0); + clk : IN std_logic; + reset : IN std_logic; + ready : out std_logic + ); + END COMPONENT; + + -- Clock period definitions + constant clk_period : time := 1ns; + constant p10 : time := clk_period/10; + constant edge : time := clk_period-p10; + + --Inputs + signal input : std_logic_vector(31 downto 0) := (others => '0'); + signal ctrl : std_logic_vector(3 downto 0) := (others => '0'); + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal strobe : std_logic; + + --Outputs + signal output : std_logic_vector(31 downto 0); + signal ready : std_logic := '0'; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: PresentEnc PORT MAP ( + input => input, + output => output, + ctrl => ctrl, + clk => clk, + reset => reset, + ready => ready + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + + file infile :text is in "wejscie.txt"; + variable line_in :line; + variable bytes : std_logic_vector(32 downto 0); + variable bytes2 : std_logic_vector(3 downto 0); + variable xbit : std_logic; + + + begin + -- hold reset state for 100ms. + wait for 100ns; + reset <= '1'; + wait for 10ns; + reset <= '0'; + wait for 10ns; + -- insert stimulus here + while not (endfile(infile)) loop + readline(infile, line_in); --2 + hread(line_in, bytes2); + ctrl <= bytes2; + wait for clk_period; + readline(infile, line_in); -- 1 + hread(line_in, bytes2); + ctrl <= bytes2; + readline(infile, line_in); + read(line_in, xbit); + input <= (others => xbit); + wait for clk_period; + readline(infile, line_in); + hread(line_in, bytes2); + ctrl <= bytes2; + readline(infile, line_in); + read(line_in, xbit); + input <= (others => xbit); + wait for clk_period; + readline(infile, line_in); + hread(line_in, bytes2); + ctrl <= bytes2; + readline(infile, line_in); + read(line_in, xbit); + input <= (others => xbit); + wait for clk_period; + readline(infile, line_in); + hread(line_in, bytes2); + ctrl <= bytes2; + readline(infile, line_in); + read(line_in, xbit); + input <= (others => xbit); + wait for clk_period; + readline(infile, line_in); + hread(line_in, bytes2); + ctrl <= bytes2; + readline(infile, line_in); + read(line_in, xbit); + input <= (others => xbit); + wait for clk_period; + readline(infile, line_in); + hread(line_in, bytes2); + ctrl <= bytes2; + wait for clk_period*33; + readline(infile, line_in); + hread(line_in, bytes2); + ctrl <= bytes2; + wait for clk_period; + readline(infile, line_in); + hread(line_in, bytes2); + ctrl <= bytes2; + wait for clk_period*2; + end loop; + assert false severity failure; + end process; + + strobe <= TRANSPORT clk AFTER edge; + + outs: PROCESS (strobe) + variable str :string(1 to 29); + variable lineout :line; + variable init_file :std_logic := '1'; + file outfile :text is out "wyjscie.txt"; + + -------- funkcja konwersji: std_logic_vector => character -------- + function conv_to_hex_char (sig: std_logic_vector(3 downto 0)) RETURN character IS + begin + case sig is + when "0000" => return '0'; + when "0001" => return '1'; + when "0010" => return '2'; + when "0011" => return '3'; + when "0100" => return '4'; + when "0101" => return '5'; + when "0110" => return '6'; + when "0111" => return '7'; + when "1000" => return '8'; + when "1001" => return '9'; + when "1010" => return 'A'; + when "1011" => return 'B'; + when "1100" => return 'C'; + when "1101" => return 'D'; + when "1110" => return 'E'; + when others => return 'F'; + end case; + end conv_to_hex_char; + + -------- funkcja konwersji: std_logic => character -------- + function conv_to_char (sig: std_logic) RETURN character IS + begin + case sig is + when '1' => return '1'; + when '0' => return '0'; + when 'Z' => return 'Z'; + when others => return 'X'; + end case; + end conv_to_char; + + -------- funkcja konwersji: std_logic_vector => string -------- + function conv_to_string (inp: std_logic_vector; length: integer) RETURN string IS + variable x : integer := length/4; + variable s : string(1 to x); + begin + for i in 0 to (x-1) loop + s(x-i) := conv_to_hex_char(inp(4*i+3 downto 4*i)); + end loop; + return s; + end conv_to_string; + + ------------------------------------- + begin + -------- nag��wek pliku wyj�ciowego (podzia� kolumn) -------- + if init_file = '1' then + str:="clk "; + write(lineout,str); writeline(outfile,lineout); + str:="| reset "; + write(lineout,str); writeline(outfile,lineout); + str:="| | ready "; + write(lineout,str); writeline(outfile,lineout); + str:="| | | ctrl "; + write(lineout,str); writeline(outfile,lineout); + str:="| | | | input "; + write(lineout,str); writeline(outfile,lineout); + str:="| | | | | output "; + write(lineout,str); writeline(outfile,lineout); + str:="| | | | | | "; + write(lineout,str); writeline(outfile,lineout); + init_file := '0'; + end if; + + -------- zapis danych do pliku wyjsciowego �wyjscie� -------- + if (strobe'EVENT and strobe='0') then + str := (others => ' '); + str(1) := conv_to_char(clk); + str(2) := '|'; + str(3) := conv_to_char(reset); + str(4) := '|'; + str(5) := conv_to_char(ready); + str(6) := '|'; + str(7) := conv_to_hex_char(ctrl); + str(8) := '|'; + str(9 to 16) := conv_to_string(input,32); + str(17) := '|'; + str(18 to 25) := conv_to_string(output,32); + str(26) := '|'; + write(lineout,str); + writeline(outfile,lineout); + end if; + end process outs; +end; \ No newline at end of file Index: 32BitIO/bench/vhdl/txt_util.vhd =================================================================== --- 32BitIO/bench/vhdl/txt_util.vhd (nonexistent) +++ 32BitIO/bench/vhdl/txt_util.vhd (revision 4) @@ -0,0 +1,586 @@ +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; + + +package txt_util is + + -- prints a message to the screen + procedure print(text: string); + + -- prints the message when active + -- useful for debug switches + procedure print(active: boolean; text: string); + + -- converts std_logic into a character + function chr(sl: std_logic) return character; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string; + + -- converts std_logic_vector into a string (binary base) + function str(slv: std_logic_vector) return string; + + -- converts boolean into a string + function str(b: boolean) return string; + + -- converts an integer into a single character + -- (can also be used for hex conversion and other bases) + function chr(int: integer) return character; + + -- converts integer into string using specified base + function str(int: integer; base: integer) return string; + + -- converts integer to string, using base 10 + function str(int: integer) return string; + + -- convert std_logic_vector into a string in hex format + function hstr(slv: std_logic_vector) return string; + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c: character) return character; + + -- convert a character to lower case + function to_lower(c: character) return character; + + -- convert a string to upper case + function to_upper(s: string) return string; + + -- convert a string to lower case + function to_lower(s: string) return string; + + + + -- functions to convert strings into other formats + -------------------------------------------------- + + -- converts a character into std_logic + function to_std_logic(c: character) return std_logic; + + -- converts a string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector; + + + + -- file I/O + ----------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string); + + -- print string to a file and start new line + procedure print(file out_file: TEXT; + new_string: in string); + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character); + +end txt_util; + + + + +package body txt_util is + + + + + -- prints text to the screen + + procedure print(text: string) is + variable msg_line: line; + begin + write(msg_line, text); + writeline(output, msg_line); + end print; + + + + + -- prints text to the screen when active + + procedure print(active: boolean; text: string) is + begin + if active then + print(text); + end if; + end print; + + + -- converts std_logic into a character + + function chr(sl: std_logic) return character is + variable c: character; + begin + case sl is + when 'U' => c:= 'U'; + when 'X' => c:= 'X'; + when '0' => c:= '0'; + when '1' => c:= '1'; + when 'Z' => c:= 'Z'; + when 'W' => c:= 'W'; + when 'L' => c:= 'L'; + when 'H' => c:= 'H'; + when '-' => c:= '-'; + end case; + return c; + end chr; + + + + -- converts std_logic into a string (1 to 1) + + function str(sl: std_logic) return string is + variable s: string(1 to 1); + begin + s(1) := chr(sl); + return s; + end str; + + + + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + + function str(slv: std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r := 1; + for i in slv'range loop + result(r) := chr(slv(i)); + r := r + 1; + end loop; + return result; + end str; + + + function str(b: boolean) return string is + + begin + if b then + return "true"; + else + return "false"; + end if; + end str; + + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function chr(int: integer) return character is + variable c: character; + begin + case int is + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; + end case; + return c; + end chr; + + + + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function str(int: integer; base: integer) return string is + + variable temp: string(1 to 10); + variable num: integer; + variable abs_int: integer; + variable len: integer := 1; + variable power: integer := 1; + + begin + + -- bug fix for negative numbers + abs_int := abs(int); + + num := abs_int; + + while num >= base loop -- Determine how many + len := len + 1; -- characters required + num := num / base; -- to represent the + end loop ; -- number. + + for i in len downto 1 loop -- Convert the number to + temp(i) := chr(abs_int/power mod base); -- a string starting + power := power * base; -- with the right hand + end loop ; -- side. + + -- return result and add sign if required + if int < 0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; + + end str; + + + -- convert integer to string, using base 10 + function str(int: integer) return string is + + begin + + return str(int, 10) ; + + end str; + + + + -- converts a std_logic_vector into a hex string. + function hstr(slv: std_logic_vector) return string is + variable hexlen: integer; + variable longslv : std_logic_vector(67 downto 0) := (others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen := (slv'left+1)/4; + if (slv'left+1) mod 4 /= 0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen -1) downto 0 loop + fourbit := longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen -I) := '0'; + when "0001" => hex(hexlen -I) := '1'; + when "0010" => hex(hexlen -I) := '2'; + when "0011" => hex(hexlen -I) := '3'; + when "0100" => hex(hexlen -I) := '4'; + when "0101" => hex(hexlen -I) := '5'; + when "0110" => hex(hexlen -I) := '6'; + when "0111" => hex(hexlen -I) := '7'; + when "1000" => hex(hexlen -I) := '8'; + when "1001" => hex(hexlen -I) := '9'; + when "1010" => hex(hexlen -I) := 'A'; + when "1011" => hex(hexlen -I) := 'B'; + when "1100" => hex(hexlen -I) := 'C'; + when "1101" => hex(hexlen -I) := 'D'; + when "1110" => hex(hexlen -I) := 'E'; + when "1111" => hex(hexlen -I) := 'F'; + when "ZZZZ" => hex(hexlen -I) := 'z'; + when "UUUU" => hex(hexlen -I) := 'u'; + when "XXXX" => hex(hexlen -I) := 'x'; + when others => hex(hexlen -I) := '?'; + end case; + end loop; + return hex(1 to hexlen); + end hstr; + + + + -- functions to manipulate strings + ----------------------------------- + + + -- convert a character to upper case + + function to_upper(c: character) return character is + + variable u: character; + + begin + + case c is + when 'a' => u := 'A'; + when 'b' => u := 'B'; + when 'c' => u := 'C'; + when 'd' => u := 'D'; + when 'e' => u := 'E'; + when 'f' => u := 'F'; + when 'g' => u := 'G'; + when 'h' => u := 'H'; + when 'i' => u := 'I'; + when 'j' => u := 'J'; + when 'k' => u := 'K'; + when 'l' => u := 'L'; + when 'm' => u := 'M'; + when 'n' => u := 'N'; + when 'o' => u := 'O'; + when 'p' => u := 'P'; + when 'q' => u := 'Q'; + when 'r' => u := 'R'; + when 's' => u := 'S'; + when 't' => u := 'T'; + when 'u' => u := 'U'; + when 'v' => u := 'V'; + when 'w' => u := 'W'; + when 'x' => u := 'X'; + when 'y' => u := 'Y'; + when 'z' => u := 'Z'; + when others => u := c; + end case; + + return u; + + end to_upper; + + + -- convert a character to lower case + + function to_lower(c: character) return character is + + variable l: character; + + begin + + case c is + when 'A' => l := 'a'; + when 'B' => l := 'b'; + when 'C' => l := 'c'; + when 'D' => l := 'd'; + when 'E' => l := 'e'; + when 'F' => l := 'f'; + when 'G' => l := 'g'; + when 'H' => l := 'h'; + when 'I' => l := 'i'; + when 'J' => l := 'j'; + when 'K' => l := 'k'; + when 'L' => l := 'l'; + when 'M' => l := 'm'; + when 'N' => l := 'n'; + when 'O' => l := 'o'; + when 'P' => l := 'p'; + when 'Q' => l := 'q'; + when 'R' => l := 'r'; + when 'S' => l := 's'; + when 'T' => l := 't'; + when 'U' => l := 'u'; + when 'V' => l := 'v'; + when 'W' => l := 'w'; + when 'X' => l := 'x'; + when 'Y' => l := 'y'; + when 'Z' => l := 'z'; + when others => l := c; + end case; + + return l; + + end to_lower; + + + + -- convert a string to upper case + + function to_upper(s: string) return string is + + variable uppercase: string (s'range); + + begin + + for i in s'range loop + uppercase(i):= to_upper(s(i)); + end loop; + return uppercase; + + end to_upper; + + + + -- convert a string to lower case + + function to_lower(s: string) return string is + + variable lowercase: string (s'range); + + begin + + for i in s'range loop + lowercase(i):= to_lower(s(i)); + end loop; + return lowercase; + + end to_lower; + + + +-- functions to convert strings into other types + + +-- converts a character into a std_logic + +function to_std_logic(c: character) return std_logic is + variable sl: std_logic; + begin + case c is + when 'U' => + sl := 'U'; + when 'X' => + sl := 'X'; + when '0' => + sl := '0'; + when '1' => + sl := '1'; + when 'Z' => + sl := 'Z'; + when 'W' => + sl := 'W'; + when 'L' => + sl := 'L'; + when 'H' => + sl := 'H'; + when '-' => + sl := '-'; + when others => + sl := 'X'; + end case; + return sl; + end to_std_logic; + + +-- converts a string into std_logic_vector + +function to_std_logic_vector(s: string) return std_logic_vector is + variable slv: std_logic_vector(s'high-s'low downto 0); + variable k: integer; +begin + k := s'high-s'low; + for i in s'range loop + slv(k) := to_std_logic(s(i)); + k := k - 1; + end loop; + return slv; +end to_std_logic_vector; + + + + + + +---------------- +-- file I/O -- +---------------- + + + +-- read variable length string from input file + +procedure str_read(file in_file: TEXT; + res_string: out string) is + + variable l: line; + variable c: character; + variable is_string: boolean; + + begin + + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i) := ' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + read(l, c, is_string); + res_string(i) := c; + if not is_string then -- found end of line + exit; + end if; + end loop; + +end str_read; + + +-- print string to a file +procedure print(file out_file: TEXT; + new_string: in string) is + + variable l: line; + + begin + + write(l, new_string); + writeline(out_file, l); + +end print; + + +-- print character to a file and start new line +procedure print(file out_file: TEXT; + char: in character) is + + variable l: line; + + begin + + write(l, char); + writeline(out_file, l); + +end print; + + + +-- appends contents of a string to a file until line feed occurs +-- (LF is considered to be the end of the string) + +procedure str_write(file out_file: TEXT; + new_string: in string) is + begin + + for i in new_string'range loop + print(out_file, new_string(i)); + if new_string(i) = LF then -- end of string + exit; + end if; + end loop; + +end str_write; + + + + +end txt_util; + + + + Index: 32BitIO/bench/vhdl =================================================================== --- 32BitIO/bench/vhdl (nonexistent) +++ 32BitIO/bench/vhdl (revision 4)

32BitIO/bench/vhdl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: 32BitIO/bench =================================================================== --- 32BitIO/bench (nonexistent) +++ 32BitIO/bench (revision 4)

32BitIO/bench Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: 32BitIO/rtl/vhdl/counter.vhd =================================================================== --- 32BitIO/rtl/vhdl/counter.vhd (nonexistent) +++ 32BitIO/rtl/vhdl/counter.vhd (revision 4) @@ -0,0 +1,86 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- A little modified counter construction - it additionally ---- +---- control another one signal. It contains "built-in" reset if ---- +---- it is not counting. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity counter is + generic ( + w_2 : integer := 2; + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + info : out std_logic_vector (w_2-1 downto 0); + num : out std_logic_vector (w_5-1 downto 0) + ); +end counter; + +architecture Behavioral of counter is + begin + licznik : process (clk, reset) + variable cnt : unsigned(w_5-1 downto 0); + begin + if (reset = '1') then + cnt := (others => '0'); + elsif (clk'Event and clk = '1') then + if (cnt_res = '1') then + cnt := cnt + 1; + if (std_logic_vector(cnt) = "00001") then + info <= "01"; + elsif (std_logic_vector(cnt) = "00000") then + info <= "00"; + else + info <= "11"; + end if; + else + cnt := (others => '0'); + end if; + end if; + num <= std_logic_vector(cnt); + end process licznik; + end Behavioral; + Index: 32BitIO/rtl/vhdl/slayer.vhd =================================================================== --- 32BitIO/rtl/vhdl/slayer.vhd (nonexistent) +++ 32BitIO/rtl/vhdl/slayer.vhd (revision 4) @@ -0,0 +1,81 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Substitution layer of Present cipher. Simple logic. ---- +---- For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity slayer is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); +end slayer; + +architecture Behavioral of slayer is + + begin + output <= x"C" when input = x"0" else + x"5" when input = x"1" else + x"6" when input = x"2" else + x"B" when input = x"3" else + x"9" when input = x"4" else + x"0" when input = x"5" else + x"A" when input = x"6" else + x"D" when input = x"7" else + x"3" when input = x"8" else + x"E" when input = x"9" else + x"F" when input = x"A" else + x"8" when input = x"B" else + x"4" when input = x"C" else + x"7" when input = x"D" else + x"1" when input = x"E" else + x"2" when input = x"F" else + "ZZZZ"; + end Behavioral; \ No newline at end of file Index: 32BitIO/rtl/vhdl/keyupd.vhd =================================================================== --- 32BitIO/rtl/vhdl/keyupd.vhd (nonexistent) +++ 32BitIO/rtl/vhdl/keyupd.vhd (revision 4) @@ -0,0 +1,86 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Key update module for present cipher it is 'signal ---- +---- mixing' made by rotation left by 61 bits, using one s-box, ---- +---- and output of the counter. For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity keyupd is + generic( + w_80: integer := 80; + w_5 : integer := 5; + w_4 : integer := 4); + port( + key : in std_logic_vector(w_80-1 downto 0); + num : in std_logic_vector(w_5-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); +end keyupd; + +architecture Behavioral of keyupd is + + component slayer is + generic(w_4: integer := 4); + port( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + signal changed : std_logic_vector(w_4-1 downto 0); + signal changin : std_logic_vector(w_4-1 downto 0); + signal keytemp : std_logic_vector(w_80-1 downto 0); + + begin + s1: slayer port map(input => changin, output => changed); + changin <= keytemp(79 downto 76); + keytemp <= key(18 downto 0) & key(79 downto 19); + keyout(79 downto 76)<= changed; + keyout(75 downto 20) <= keytemp(75 downto 20); + keyout(19 downto 15)<= keytemp(19 downto 15) xor num; + keyout(14 downto 0) <= keytemp(14 downto 0); + end Behavioral; \ No newline at end of file Index: 32BitIO/rtl/vhdl/mux80.vhd =================================================================== --- 32BitIO/rtl/vhdl/mux80.vhd (nonexistent) +++ 32BitIO/rtl/vhdl/mux80.vhd (revision 4) @@ -0,0 +1,103 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- This is not "strict" implementation of multiplexer but ---- +---- contains its functionality. There are two inputs. One - ---- +---- 32 bit input, and one 80 bit input - because of way, in which ---- +---- Present is working. For more information see below ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.kody.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity mux80 is + generic ( + w_2 : integer := 2; + w_32 : integer := 32; + w_80 : integer := 80 + ); + port( + i0ctrl : in std_logic_vector (w_2-1 downto 0); + input0 : in std_logic_vector(w_32-1 downto 0); + input1 : in std_logic_vector(w_80-1 downto 0); + output : inout std_logic_vector(w_80-1 downto 0); + ctrl, clk, reset : in std_logic + ); +end mux80; + +architecture Behavioral of mux80 is + +begin + inne : process (clk, reset) + begin + if (reset = '1') then + output <= (others => '0'); + elsif (clk'Event and clk = '1') then + if ctrl = '0' then + -- load least significant 32 bits of output from input0 (32 bit wide) + if (i0ctrl = in_ld_reg_L ) then + output <= output(80-1 downto 32) & input0; + -- load "middle" significant 32 bits of output from input0 (32 bit wide) + elsif (i0ctrl = in_ld_reg_H) then + output <= output(79 downto 64) & input0 & output(31 downto 0); + -- load most significant 16 bits of output from input0 (16 bit wide) + elsif (i0ctrl = in_ld_reg_HH) then + output <= input0(15 downto 0) & output(63 downto 0); + else + -- do nothing + output <= output; + end if; + -- on output goes data from 80 bit input + else + output <= input1; + end if; + end if; + end process inne; +end Behavioral; + Index: 32BitIO/rtl/vhdl/mux64.vhd =================================================================== --- 32BitIO/rtl/vhdl/mux64.vhd (nonexistent) +++ 32BitIO/rtl/vhdl/mux64.vhd (revision 4) @@ -0,0 +1,100 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- This is not "strict" implementation of multiplexer but ---- +---- contains its functionality. There are two inputs. One - ---- +---- 32 bit input, and one 64 bit input - because of way, in which ---- +---- Present is working. For more information see below ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.kody.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity mux64 is + generic ( + w_2 : integer := 2; + w_32 : integer := 32; + w_64 : integer := 64 + ); + port( + i0ctrl : in std_logic_vector (w_2-1 downto 0); + input0 : in std_logic_vector(w_32-1 downto 0); + input1 : in std_logic_vector(w_64-1 downto 0); + ctrl, clk, reset : in std_logic; + output : inout std_logic_vector(w_64-1 downto 0) + ); +end mux64; + +architecture Behavioral of mux64 is + +begin + inne : process (clk, reset) + begin + if (reset = '1') then + output <= (others => '0'); + elsif (clk'Event and clk = '1') then + if ctrl = '0' then + -- load least significant 32 bits of output from input0 (32 bit wide) + if (i0ctrl = in_ld_reg_L ) then + output <= output(w_64-1 downto 32) & input0; + -- load most significant 32 bits of output from input0 (32 bit wide) + elsif (i0ctrl = in_ld_reg_H) then + output <= input0 & output(31 downto 0); + else + -- do nothing + output <= output; + end if; + -- on output goes data from 64 bit input + else + output <= input1; + end if; + end if; + end process inne; +end Behavioral; + Index: 32BitIO/rtl/vhdl/outputRegister.vhd =================================================================== --- 32BitIO/rtl/vhdl/outputRegister.vhd (nonexistent) +++ 32BitIO/rtl/vhdl/outputRegister.vhd (revision 4) @@ -0,0 +1,93 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Not "pure" registers. Main function of this component is ---- +---- to convert 64 bit input to 32 bit output. For more see below. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.kody.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +entity outputRegister is + generic ( + w_2 : integer := 2; + w_32: integer := 32; + w_64: integer := 64 + ); + port( + rst, clk, rd : in std_logic; + ctrl : in std_logic_vector(w_2-1 downto 0); + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_32-1 downto 0); + ready : out std_logic + ); +end outputRegister; + +architecture Behavioral of outputRegister is + signal reg : std_logic_vector(w_64-1 downto 0); + begin + process( rst, clk, ctrl, input) + begin + if (rst = '1') then + output <= (others=>'Z'); + elsif(clk'event and clk = '1') then + -- loading internal signal + if(ctrl = out_ld_reg) then + reg <= input; + output <= (others=>'Z'); + ---- leas significant 32 bits to output + elsif (ctrl = out_reg_L) then + output <= reg(w_32-1 downto 0); + ---- most significant 32 bits to output + elsif (ctrl = out_reg_H) then + output <= reg(w_64-1 downto w_32); + ---- this should not happen + else + output <= (others=>'Z'); + end if; + end if; + end process; + ready <= rd; + end Behavioral; + Index: 32BitIO/rtl/vhdl/PresentEnc.vhd =================================================================== --- 32BitIO/rtl/vhdl/PresentEnc.vhd (nonexistent) +++ 32BitIO/rtl/vhdl/PresentEnc.vhd (revision 4) @@ -0,0 +1,224 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Top level of present encoder with 32 bit IO. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity PresentEnc is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port( + ctrl : in std_logic_vector(w_4-1 downto 0); + input : in std_logic_vector(w_32-1 downto 0); + output : out std_logic_vector(w_32-1 downto 0); + clk, reset : in std_logic; + ready : out std_logic + ); +end PresentEnc; + +architecture Behavioral of PresentEnc is + + component PresentStateMachine is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port ( + info : in std_logic_vector (w_2-1 downto 0); + ctrl : in std_logic_vector (w_4-1 downto 0); + key_ctrl: out std_logic_vector (w_2-1 downto 0); + plain_ctrl: out std_logic_vector (w_2-1 downto 0); + outReg : out std_logic_vector (w_2-1 downto 0); + reset, clk : in std_logic; + ready, cnt_res, ctrl_mux64, ctrl_mux80 : out std_logic + ); + end component; + + -- substitution layer for decoding + component slayer is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + -- permutation layer for decoding + component pLayer is + generic(w_64 : integer := 64); + port( + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_64-1 downto 0) + ); + end component; + + -- key update for decoding + component keyupd is + generic( + w_5 : integer := 5; + w_80: integer := 80 + ); + port( + num : in std_logic_vector(w_5-1 downto 0); + key : in std_logic_vector(w_80-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); + end component; + + -- 'register' for 32 bit output and 64 bit input + component outputRegister is + generic ( + w_2 : integer := 2; + w_32: integer := 32; + w_64: integer := 64 + ); + port( + ctrl : in std_logic_vector(w_2-1 downto 0); + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_32-1 downto 0); + rst, clk, rd : in std_logic; + ready : out std_logic + ); + end component; + + -- counter for decoding. It is counting up!!! + component counter is + generic ( + w_2 : integer := 2; + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + info : out std_logic_vector(w_2-1 downto 0); + num : out std_logic_vector (w_5-1 downto 0) + ); + end component; + + -- 'multiplexer' for 32/64 bit input and 64 bit output + component mux64 is + generic ( + w_2 : integer := 2; + w_32 : integer := 32; + w_64 : integer := 64 + ); + port( + i0ctrl : in std_logic_vector (w_2-1 downto 0); + input0 : in std_logic_vector(w_32-1 downto 0); + input1 : in std_logic_vector(w_64-1 downto 0); + output : inout std_logic_vector(w_64-1 downto 0); + ctrl, clk, reset : in std_logic + ); + end component; + + -- 'multiplexer' for 32/80 bit input and 80 bit output + component mux80 is + generic ( + w_2 : integer := 2; + w_32 : integer := 32; + w_80 : integer := 80 + ); + port( + i0ctrl : in std_logic_vector (w_2-1 downto 0); + input0 : in std_logic_vector(w_32-1 downto 0); + input1 : in std_logic_vector(w_80-1 downto 0); + output : inout std_logic_vector(w_80-1 downto 0); + ctrl, clk, reset : in std_logic + ); + end component; + + component xorModule is + generic( + w : positive + ); + port( + inputA, inputB : in std_logic_vector( w-1 downto 0 ); + output : out std_logic_vector ( w-1 downto 0 ) + ); + end component; + + -- signals + + signal ro32ctrl, key_ctrl, plain_ctrl, info : std_logic_vector(w_2-1 downto 0); + signal keynum : std_logic_vector (w_5-1 downto 0); + signal toXor, ciphertext, P, Pout : std_logic_vector (w_64-1 downto 0); + signal keyfout, kupd : std_logic_vector (w_80-1 downto 0); + signal ready_sig, mux64ctrl, mux80ctrl, cnt_res : std_logic; + + begin + + -- connections + + mux_64: mux64 port map( + input0 => input, input1 => Pout, output => toXor, ctrl => mux64ctrl, + i0ctrl => plain_ctrl, clk => clk, reset => reset); + mux_80: mux80 port map( + input0 => input, input1 => kupd, output => keyfout, ctrl => mux80ctrl, + i0ctrl => key_ctrl, clk => clk, reset => reset); + slayers : for N in 15 downto 0 generate + s_x: slayer port map(input => ciphertext(4*N+3 downto 4*N), output => P(4*N+3 downto 4*N)); + end generate slayers; + p1: pLayer port map(input => P, output => Pout); + mixer: keyupd port map(key => keyfout, num => keynum, keyout => kupd); + output_reg: outputRegister port map(rst => reset, clk => clk, rd => ready_sig, ctrl => ro32ctrl, + input => ciphertext, output => output, ready => ready); + SM: PresentStateMachine port map(ctrl => ctrl, outReg => ro32ctrl, reset => reset, + ready => ready_sig, cnt_res => cnt_res, ctrl_mux64 => mux64ctrl, ctrl_mux80 => mux80ctrl, + clk => clk, key_ctrl => key_ctrl, plain_ctrl => plain_ctrl, info => info + ); + count: counter port map( clk => clk, reset => reset, cnt_res => cnt_res, info => info, num => keynum); + ciphertext <= toXor xor keyfout(79 downto 16); +end Behavioral; Index: 32BitIO/rtl/vhdl/PresentStateMachine.vhd =================================================================== --- 32BitIO/rtl/vhdl/PresentStateMachine.vhd (nonexistent) +++ 32BitIO/rtl/vhdl/PresentStateMachine.vhd (revision 4) @@ -0,0 +1,203 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- State machine for Present encoder with 32 bit IO. For more---- +---- informations ---- +---- see below. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.kody.ALL; + +entity PresentStateMachine is + generic ( + w_2 : integer := 2; + w_4 : integer := 4; + w_5 : integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port ( + clk, reset : in std_logic; + info : in std_logic_vector (w_2-1 downto 0); + ctrl : in std_logic_vector (w_4-1 downto 0); + key_ctrl: out std_logic_vector (w_2-1 downto 0); + plain_ctrl: out std_logic_vector (w_2-1 downto 0); + outReg : out std_logic_vector (w_2-1 downto 0); + ready, cnt_res, ctrl_mux64, ctrl_mux80: out std_logic + ); +end PresentStateMachine; + +architecture Behavioral of PresentStateMachine is + + signal stan : stany; + signal stan_nast : stany; + + begin + States : process(stan, ctrl, info) + begin + stan_nast<= stan; + case stan is + -- waiting for start + when NOP => + ready <= '0'; + outReg <= out_reg_Z; + cnt_res <= '0'; + ctrl_mux64 <= '0'; + ctrl_mux80 <= '0'; + -- read first 32 bits of key + if (ctrl = crdk1) then + key_ctrl <= in_ld_reg_L; + stan_nast <= RDK1; + else + stan_nast <= NOP; + end if; + when RDK1 => + -- read second 32 bits of key + if (ctrl = crdk2) then + key_ctrl <= in_ld_reg_H; + stan_nast <= RDK2; + -- wait for next 32 bits of key + elsif (ctrl = crdk1) then + key_ctrl <= in_ld_reg_L; + else + stan_nast <= NOP; + end if; + when RDK2 => + -- read last 16 bits of key + if (ctrl = crdk3) then + key_ctrl <= in_ld_reg_HH; + stan_nast <= RDK3; + -- wait for next 16 bits of key + elsif (ctrl = crdk2) then + key_ctrl <= in_ld_reg_H; + else + stan_nast <= NOP; + end if; + when RDK3 => + -- read first 32 bits of text + if (ctrl = crdt1) then + key_ctrl <= in_reg_Z; + plain_ctrl <= in_ld_reg_L; + stan_nast <= RDT1; + -- wait for first 32 bits of text + elsif (ctrl = crdk3) then + key_ctrl <= in_ld_reg_HH; + else + stan_nast <= NOP; + end if; + when RDT1 => + -- read second 32 bits of text + if (ctrl = crdt2) then + plain_ctrl <= in_ld_reg_H; + stan_nast <= RDT2; + -- wait for second 32 bits of text + elsif (ctrl = crdt1) then + plain_ctrl <= in_ld_reg_L; + else + stan_nast <= NOP; + end if; + when RDT2 => + --- Encode data + if (ctrl = ccod) then + plain_ctrl <= in_reg_Z; + stan_nast <= COD; + cnt_res <= '1'; + -- Wait for encode + elsif (ctrl = crdt2) then + plain_ctrl <= in_ld_reg_H; + else + stan_nast <= NOP; + end if; + when COD => + -- Encode data + if (ctrl = ccod) then + -- Ready + if (info = "00") then + stan_nast <= CTO1; + outReg <= out_ld_reg; + ready <= '1'; + cnt_res <= '0'; + ready <= '1'; + -- encoding + elsif (info = "01") then + ctrl_mux64 <= '1'; + ctrl_mux80 <= '1'; + end if; + else + stan_nast <= NOP; + end if; + when CTO1 => + -- send first 32 bits of data + if (ctrl = ccto2) then + stan_nast <= CTO2; + outReg <= out_reg_L; + -- wait for sending second 32 bits of data + elsif ((ctrl = ccto1) or (ctrl = ccod)) then + outReg <= out_reg_L; + else + stan_nast <= NOP; + end if; + when CTO2 => + -- send second 32 bits of data + if (ctrl = ccto2) then + stan_nast <= CTO2; + outReg <= out_reg_H; + else + stan_nast <= NOP; + end if; + end case; + end process States; + + inne : process (clk, reset) + begin + if (reset = '1') then + stan <= NOP; + elsif (clk'Event and clk = '1') then + stan <= stan_nast; + end if; + end process inne; + + end Behavioral; + Index: 32BitIO/rtl/vhdl/kody.vhd =================================================================== --- 32BitIO/rtl/vhdl/kody.vhd (nonexistent) +++ 32BitIO/rtl/vhdl/kody.vhd (revision 4) @@ -0,0 +1,77 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- This file contains types and constant used by this ---- +---- implementation of Present project ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +package kody is + -- type for PresentStateMachine to control the datapath & circuit -- + type stany is (NOP, RDK1, RDK2, RDK3, RDT1, RDT2, COD, CTO1, CTO2); + -- constant as control command from input -- + constant cnop : std_logic_vector(3 downto 0) := "0000"; --0 no operations + constant cdec : std_logic_vector(3 downto 0) := "0001"; --1 decode text + constant crdk1 : std_logic_vector(3 downto 0) := "0010"; --2 read key part 1 + constant crdk2 : std_logic_vector(3 downto 0) := "0011"; --3 read key part 2 + constant crdk3 : std_logic_vector(3 downto 0) := "0100"; --4 read key part 3 + constant cmkd : std_logic_vector(3 downto 0) := "0101"; --5 make decrypt key + constant ccod : std_logic_vector(3 downto 0) := "0110"; --6 code text + constant crdt1 : std_logic_vector(3 downto 0) := "0111"; --7 read text part 1 + constant crdt2 : std_logic_vector(3 downto 0) := "1000"; --8 read text part 2 + constant ccto1 : std_logic_vector(3 downto 0) := "1001"; --9 ciphertext output part 1 (LSW) + constant ccto2 : std_logic_vector(3 downto 0) := "1010"; --A ciphertext output part 2 (MSW) + -- For input registers (early version, now for mux's) -- + constant in_ld_reg_L : std_logic_vector(1 downto 0) := "00"; -- Load low part of the register (64 & 80 bit) + constant in_ld_reg_H : std_logic_vector(1 downto 0) := "01"; -- Load high part of the register (64 & 80 bit) + constant in_ld_reg_HH : std_logic_vector(1 downto 0) := "10"; -- Load highest part of the register (80 bit only) + constant in_reg_Z : std_logic_vector(1 downto 0) := "11"; -- High impedance on the line (unused - in this design only for block input) + -- For output register -- + constant out_ld_reg : std_logic_vector(1 downto 0) := "00"; -- Load the output register + constant out_reg_L : std_logic_vector(1 downto 0) := "01"; -- send low part of the register to the output + constant out_reg_H : std_logic_vector(1 downto 0) := "10"; -- senf high part of the register to the output + constant out_reg_Z : std_logic_vector(1 downto 0) := "11"; -- High impedance on the line (unused - in this design only for block input) +end kody; \ No newline at end of file Index: 32BitIO/rtl/vhdl/pLayer.vhd =================================================================== --- 32BitIO/rtl/vhdl/pLayer.vhd (nonexistent) +++ 32BitIO/rtl/vhdl/pLayer.vhd (revision 4) @@ -0,0 +1,125 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Permutation layer of Present cipher. Simple signal mixing.---- +---- For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity pLayer is + generic(w_64 : integer := 64); + port ( + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_64-1 downto 0) + ); +end pLayer; + +architecture Behavioral of pLayer is +begin + output(0) <= input(0); + output(16) <= input(1); + output(32) <= input(2); + output(48) <= input(3); + output(1) <= input(4); + output(17) <= input(5); + output(33) <= input(6); + output(49) <= input(7); + output(2) <= input(8); + output(18) <= input(9); + output(34) <= input(10); + output(50) <= input(11); + output(3) <= input(12); + output(19) <= input(13); + output(35) <= input(14); + output(51) <= input(15); + output(4) <= input(16); + output(20) <= input(17); + output(36) <= input(18); + output(52) <= input(19); + output(5) <= input(20); + output(21) <= input(21); + output(37) <= input(22); + output(53) <= input(23); + output(6) <= input(24); + output(22) <= input(25); + output(38) <= input(26); + output(54) <= input(27); + output(7) <= input(28); + output(23) <= input(29); + output(39) <= input(30); + output(55) <= input(31); + output(8) <= input(32); + output(24) <= input(33); + output(40) <= input(34); + output(56) <= input(35); + output(9) <= input(36); + output(25) <= input(37); + output(41) <= input(38); + output(57) <= input(39); + output(10) <= input(40); + output(26) <= input(41); + output(42) <= input(42); + output(58) <= input(43); + output(11) <= input(44); + output(27) <= input(45); + output(43) <= input(46); + output(59) <= input(47); + output(12) <= input(48); + output(28) <= input(49); + output(44) <= input(50); + output(60) <= input(51); + output(13) <= input(52); + output(29) <= input(53); + output(45) <= input(54); + output(61) <= input(55); + output(14) <= input(56); + output(30) <= input(57); + output(46) <= input(58); + output(62) <= input(59); + output(15) <= input(60); + output(31) <= input(61); + output(47) <= input(62); + output(63) <= input(63); +end Behavioral; \ No newline at end of file Index: 32BitIO/rtl/vhdl =================================================================== --- 32BitIO/rtl/vhdl (nonexistent) +++ 32BitIO/rtl/vhdl (revision 4)

32BitIO/rtl/vhdl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: 32BitIO/rtl =================================================================== --- 32BitIO/rtl (nonexistent) +++ 32BitIO/rtl (revision 4)

32BitIO/rtl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: 32BitIO/doc/src =================================================================== --- 32BitIO/doc/src (nonexistent) +++ 32BitIO/doc/src (revision 4)

32BitIO/doc/src Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: 32BitIO/doc =================================================================== --- 32BitIO/doc (nonexistent) +++ 32BitIO/doc (revision 4)

32BitIO/doc Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: 32BitIO/sim =================================================================== --- 32BitIO/sim (nonexistent) +++ 32BitIO/sim (revision 4)

32BitIO/sim Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: 32BitIO/sw =================================================================== --- 32BitIO/sw (nonexistent) +++ 32BitIO/sw (revision 4)

32BitIO/sw Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: 32BitIO/syn/XC3ES500 =================================================================== --- 32BitIO/syn/XC3ES500 (nonexistent) +++ 32BitIO/syn/XC3ES500 (revision 4)

32BitIO/syn/XC3ES500 Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: 32BitIO/syn =================================================================== --- 32BitIO/syn (nonexistent) +++ 32BitIO/syn (revision 4)

32BitIO/syn Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Pure/PresentEnc.vhd =================================================================== --- Pure/PresentEnc.vhd (revision 3) +++ Pure/PresentEnc.vhd (nonexistent) @@ -1,186 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 18:02:34 05/15/2010 --- Design Name: --- Module Name: PresentEnc - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: - --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity PresentEnc is - generic ( - w_2: integer := 2; - w_4: integer := 4; - w_5: integer := 5; - w_32: integer := 32; - w_64: integer := 64; - w_80: integer := 80 - ); - port( - plaintext : in std_logic_vector(w_64 - 1 downto 0); - key : in std_logic_vector(w_80 - 1 downto 0); - ciphertext : out std_logic_vector(w_64 - 1 downto 0); - start, clk, reset : in std_logic; - ready : out std_logic - ); -end PresentEnc; - -architecture Behavioral of PresentEnc is - - component Reg is - generic(width : integer := w_64); - port( - input : in STD_LOGIC_VECTOR(width - 1 downto 0); - output : out STD_LOGIC_VECTOR(width - 1 downto 0); - enable : in STD_LOGIC; - clk : in STD_LOGIC; - reset : in STD_LOGIC - ); - end component Reg; - - component AsyncMux is - generic ( - width : integer := 64 - ); - port ( - input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); - input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); - ctrl : in STD_LOGIC; - output : out STD_LOGIC_VECTOR(width - 1 downto 0) - ); - end component AsyncMux; - - component PresentStateMachine is - generic ( - w_5 : integer := 5 - ); - port ( - clk, reset, start : in std_logic; - ready, cnt_res, ctrl_mux, RegEn: out std_logic; - num : in std_logic_vector (w_5-1 downto 0) - ); - end component; - - component slayer is - generic ( - w_4 : integer := 4 - ); - port ( - input : in std_logic_vector(w_4-1 downto 0); - output : out std_logic_vector(w_4-1 downto 0) - ); - end component; - - component pLayer is - generic(w_64 : integer := 64); - port( - input : in std_logic_vector(w_64-1 downto 0); - output : out std_logic_vector(w_64-1 downto 0) - ); - end component; - - component keyupd is - generic( - w_5 : integer := 5; - w_80: integer := 80 - ); - port( - num : in std_logic_vector(w_5-1 downto 0); - key : in std_logic_vector(w_80-1 downto 0); - keyout : out std_logic_vector(w_80-1 downto 0) - ); - end component; - - component counter is - generic ( - w_5 : integer := 5 - ); - port ( - clk, reset, cnt_res : in std_logic; - num : out std_logic_vector (w_5-1 downto 0) - ); - end component; - - signal keynum : std_logic_vector (w_5-1 downto 0); - signal toXor, ciph, P, Pout, textToReg : std_logic_vector (w_64-1 downto 0); - signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0); - signal ready_sig, mux_ctrl, cnt_res, RegEn : std_logic; - - begin - mux_64: AsyncMux generic map(width => w_64) port map( - input0 => plaintext, - input1 => Pout, - ctrl => mux_ctrl, - output => textToReg - ); - regText : Reg generic map(width => w_64) port map( - input => textToReg, - output => toXor, - enable => RegEn, - clk => clk, - reset => reset - ); - mux_80: AsyncMux generic map(width => w_80) port map( - input0 => key, - input1 => kupd, - ctrl => mux_ctrl, - output => keyToReg - ); - regKey : Reg generic map(width => w_80) port map( - input => keyToReg, - output => keyfout, - enable => RegEn, - clk => clk, - reset => reset - ); - slayers : for N in 15 downto 0 generate - s_x: slayer port map( - input => ciph(4*N+3 downto 4*N), - output => P(4*N+3 downto 4*N) - ); - end generate slayers; - p1: pLayer port map( - input => P, - output => Pout - ); - mixer: keyupd port map( - key => keyfout, - num => keynum, - keyout => kupd - ); - SM: PresentStateMachine port map( - start => start, - reset => reset, - ready => ready_sig, - cnt_res => cnt_res, - ctrl_mux => mux_ctrl, - clk => clk, - num => keynum, - RegEn => RegEn - ); - count: counter port map( - clk => clk, - reset => reset, - cnt_res => cnt_res, - num => keynum - ); - ciph <= toXor xor keyfout(79 downto 16); - ciphertext <= ciph; - ready <= ready_sig; -end Behavioral; Index: Pure/PresentTB.vhd =================================================================== --- Pure/PresentTB.vhd (revision 3) +++ Pure/PresentTB.vhd (nonexistent) @@ -1,133 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 22:21:14 06/25/2013 --- Design Name: --- Module Name: E:/spent i praca/OpenCores/present_opencores/trunk/Pure/PresentTB.vhd --- Project Name: Present_Pure --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: PresentEnc --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---USE ieee.numeric_std.ALL; - -ENTITY PresentTB IS -END PresentTB; - -ARCHITECTURE behavior OF PresentTB IS - - -- Component Declaration for the Unit Under Test (UUT) - - COMPONENT PresentEnc - PORT( - plaintext : IN std_logic_vector(63 downto 0); - key : IN std_logic_vector(79 downto 0); - ciphertext : OUT std_logic_vector(63 downto 0); - start : IN std_logic; - clk : IN std_logic; - reset : IN std_logic; - ready : OUT std_logic - ); - END COMPONENT; - - - --Inputs - signal plaintext : std_logic_vector(63 downto 0) := (others => '0'); - signal key : std_logic_vector(79 downto 0) := (others => '0'); - signal start : std_logic := '0'; - signal clk : std_logic := '0'; - signal reset : std_logic := '0'; - - --Outputs - signal ciphertext : std_logic_vector(63 downto 0); - signal ready : std_logic; - - -- Clock period definitions - constant clk_period : time := 10 ns; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: PresentEnc PORT MAP ( - plaintext => plaintext, - key => key, - ciphertext => ciphertext, - start => start, - clk => clk, - reset => reset, - ready => ready - ); - - -- Clock process definitions - clk_process :process - begin - clk <= '0'; - wait for clk_period/2; - clk <= '1'; - wait for clk_period/2; - end process; - - - -- Stimulus process - stim_proc: process - begin - - reset <= '1'; - start <= '0'; - wait for 100 ns; - reset <= '0'; - - plaintext <= (others => '0'); - key <= (others => '0'); - start <= '1'; - wait for clk_period*40; - start <= '0'; - wait for clk_period; - - plaintext <= (others => '0'); - key <= (others => '1'); - start <= '1'; - wait for clk_period*40; - start <= '0'; - wait for clk_period; - - plaintext <= (others => '1'); - key <= (others => '0'); - start <= '1'; - wait for clk_period*40; - start <= '0'; - wait for clk_period; - - plaintext <= (others => '1'); - key <= (others => '1'); - start <= '1'; - wait for clk_period*40; - start <= '0'; - wait for clk_period; - - assert false severity failure; - - end process; - -END; Index: Pure/keyupdTB.vhd =================================================================== --- Pure/keyupdTB.vhd (revision 3) +++ Pure/keyupdTB.vhd (nonexistent) @@ -1,106 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:00:18 05/16/2010 --- Design Name: --- Module Name: C:/Users/gajos/Desktop/Polibuda/vhdl/projekt/szyfrator/keyupdTB.vhd --- Project Name: szyfrator --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: keyupd --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.all; -USE ieee.numeric_std.ALL; - -ENTITY keyupdTB IS -END keyupdTB; - -ARCHITECTURE behavior OF keyupdTB IS - - -- Component Declaration for the Unit Under Test (UUT) - - COMPONENT keyupd - PORT( - key : IN std_logic_vector(79 downto 0); - num : IN std_logic_vector(4 downto 0); - keyout : OUT std_logic_vector(79 downto 0)--; - --clk, reset : std_logic - ); - END COMPONENT; - - - --Inputs - signal key : std_logic_vector(79 downto 0) := (others => '0'); - signal num : std_logic_vector(4 downto 0) := (others => '0'); - signal clk : std_logic := '0'; - signal reset : std_logic := '0'; - - --Outputs - signal keyout : std_logic_vector(79 downto 0); - - constant clk_period : time := 1ns; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: keyupd PORT MAP ( - key => key, - num => num, - keyout => keyout--, - --clk => clk, - --reset => reset - ); - - -- No clocks detected in port list. Replace clk below with - -- appropriate port name - - clk_process :process - begin - clk <= '0'; - wait for clk_period/2; - clk <= '1'; - wait for clk_period/2; - end process; - - - -- Stimulus process - stim_proc: process - begin - -- hold reset state for 100ms. - reset <= '1'; - wait for 100ns; - reset <='0'; - wait for clk_period; - key <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - num <= "00001"; - wait for clk_period; - key <= x"c0000000000000008000"; - num <= "00010"; - wait for clk_period; - key <= x"50001800000000010000"; - num <= "00011"; - wait for clk_period; - key <= x"8ba27a0eb8783ac96d59"; - num <= "11111"; - wait for clk_period; - assert false severity failure; - end process; -END; \ No newline at end of file Index: Pure/sLayerTB.vhd =================================================================== --- Pure/sLayerTB.vhd (revision 3) +++ Pure/sLayerTB.vhd (nonexistent) @@ -1,95 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:11:33 05/16/2010 --- Design Name: --- Module Name: C:/Users/gajos/Desktop/Polibuda/vhdl/projekt/szyfrator/sLayerTB.vhd --- Project Name: szyfrator --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: slayer --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.all; -USE ieee.numeric_std.ALL; - -ENTITY sLayerTB IS -END sLayerTB; - -ARCHITECTURE behavior OF sLayerTB IS - - -- Component Declaration for the Unit Under Test (UUT) - - COMPONENT slayer - PORT( - input : IN std_logic_vector(3 downto 0); - output : OUT std_logic_vector(3 downto 0) - ); - END COMPONENT; - - - --Inputs - signal clk : std_logic := '0'; - signal reset : std_logic := '0'; - - --BiDirs - signal input : std_logic_vector(3 downto 0); - signal output : std_logic_vector(3 downto 0); - - -- Clock period definitions - constant clk_period : time := 1ns; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: slayer PORT MAP ( - input => input, - output => output - ); - - -- Clock process definitions - clk_process :process - begin - clk <= '0'; - wait for clk_period/2; - clk <= '1'; - wait for clk_period/2; - end process; - - - -- Stimulus process - stim_proc: process - begin - -- hold reset state for 100ms. - reset <= '1'; - wait for 100ns; - reset <= '0'; - wait for clk_period; - input <= x"0"; - wait for clk_period; - input <= x"A"; - wait for clk_period; - input <= x"F"; - wait for clk_period; - -- insert stimulus here - assert false severity failure; - end process; - -END; \ No newline at end of file Index: Pure/Reg.vhd =================================================================== --- Pure/Reg.vhd (revision 3) +++ Pure/Reg.vhd (nonexistent) @@ -1,60 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 23:41:41 06/24/2013 --- Design Name: --- Module Name: Reg - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity Reg is - generic(width : integer := 64); - port( - input : in STD_LOGIC_VECTOR(width - 1 downto 0); - output : out STD_LOGIC_VECTOR(width - 1 downto 0); - enable : in STD_LOGIC; - clk : in STD_LOGIC; - reset : in STD_LOGIC - ); -end Reg; - -architecture Behavioral of Reg is - -signal reg : STD_LOGIC_VECTOR(width - 1 downto 0); - -begin - clock : process(clk, reset) - begin - if (reset = '1') then - reg <= (others => '0'); - elsif (clk = '1' and clk'Event) then - if (enable = '1') then - reg <= input; - end if; - end if; - end process clock; - output <= reg; -end Behavioral; - Index: Pure/pLayer.vhd =================================================================== --- Pure/pLayer.vhd (revision 3) +++ Pure/pLayer.vhd (nonexistent) @@ -1,99 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 16:06:24 05/13/2010 --- Design Name: --- Module Name: pLayer - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity pLayer is - generic(w_64 : integer := 64); - port ( - input : in std_logic_vector(w_64-1 downto 0); - output : out std_logic_vector(w_64-1 downto 0) - ); -end pLayer; - -architecture Behavioral of pLayer is -begin - output(0) <= input(0); - output(16) <= input(1); - output(32) <= input(2); - output(48) <= input(3); - output(1) <= input(4); - output(17) <= input(5); - output(33) <= input(6); - output(49) <= input(7); - output(2) <= input(8); - output(18) <= input(9); - output(34) <= input(10); - output(50) <= input(11); - output(3) <= input(12); - output(19) <= input(13); - output(35) <= input(14); - output(51) <= input(15); - output(4) <= input(16); - output(20) <= input(17); - output(36) <= input(18); - output(52) <= input(19); - output(5) <= input(20); - output(21) <= input(21); - output(37) <= input(22); - output(53) <= input(23); - output(6) <= input(24); - output(22) <= input(25); - output(38) <= input(26); - output(54) <= input(27); - output(7) <= input(28); - output(23) <= input(29); - output(39) <= input(30); - output(55) <= input(31); - output(8) <= input(32); - output(24) <= input(33); - output(40) <= input(34); - output(56) <= input(35); - output(9) <= input(36); - output(25) <= input(37); - output(41) <= input(38); - output(57) <= input(39); - output(10) <= input(40); - output(26) <= input(41); - output(42) <= input(42); - output(58) <= input(43); - output(11) <= input(44); - output(27) <= input(45); - output(43) <= input(46); - output(59) <= input(47); - output(12) <= input(48); - output(28) <= input(49); - output(44) <= input(50); - output(60) <= input(51); - output(13) <= input(52); - output(29) <= input(53); - output(45) <= input(54); - output(61) <= input(55); - output(14) <= input(56); - output(30) <= input(57); - output(46) <= input(58); - output(62) <= input(59); - output(15) <= input(60); - output(31) <= input(61); - output(47) <= input(62); - output(63) <= input(63); -end Behavioral; \ No newline at end of file Index: Pure/txt_util.vhd =================================================================== --- Pure/txt_util.vhd (revision 3) +++ Pure/txt_util.vhd (nonexistent) @@ -1,586 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use std.textio.all; - - -package txt_util is - - -- prints a message to the screen - procedure print(text: string); - - -- prints the message when active - -- useful for debug switches - procedure print(active: boolean; text: string); - - -- converts std_logic into a character - function chr(sl: std_logic) return character; - - -- converts std_logic into a string (1 to 1) - function str(sl: std_logic) return string; - - -- converts std_logic_vector into a string (binary base) - function str(slv: std_logic_vector) return string; - - -- converts boolean into a string - function str(b: boolean) return string; - - -- converts an integer into a single character - -- (can also be used for hex conversion and other bases) - function chr(int: integer) return character; - - -- converts integer into string using specified base - function str(int: integer; base: integer) return string; - - -- converts integer to string, using base 10 - function str(int: integer) return string; - - -- convert std_logic_vector into a string in hex format - function hstr(slv: std_logic_vector) return string; - - - -- functions to manipulate strings - ----------------------------------- - - -- convert a character to upper case - function to_upper(c: character) return character; - - -- convert a character to lower case - function to_lower(c: character) return character; - - -- convert a string to upper case - function to_upper(s: string) return string; - - -- convert a string to lower case - function to_lower(s: string) return string; - - - - -- functions to convert strings into other formats - -------------------------------------------------- - - -- converts a character into std_logic - function to_std_logic(c: character) return std_logic; - - -- converts a string into std_logic_vector - function to_std_logic_vector(s: string) return std_logic_vector; - - - - -- file I/O - ----------- - - -- read variable length string from input file - procedure str_read(file in_file: TEXT; - res_string: out string); - - -- print string to a file and start new line - procedure print(file out_file: TEXT; - new_string: in string); - - -- print character to a file and start new line - procedure print(file out_file: TEXT; - char: in character); - -end txt_util; - - - - -package body txt_util is - - - - - -- prints text to the screen - - procedure print(text: string) is - variable msg_line: line; - begin - write(msg_line, text); - writeline(output, msg_line); - end print; - - - - - -- prints text to the screen when active - - procedure print(active: boolean; text: string) is - begin - if active then - print(text); - end if; - end print; - - - -- converts std_logic into a character - - function chr(sl: std_logic) return character is - variable c: character; - begin - case sl is - when 'U' => c:= 'U'; - when 'X' => c:= 'X'; - when '0' => c:= '0'; - when '1' => c:= '1'; - when 'Z' => c:= 'Z'; - when 'W' => c:= 'W'; - when 'L' => c:= 'L'; - when 'H' => c:= 'H'; - when '-' => c:= '-'; - end case; - return c; - end chr; - - - - -- converts std_logic into a string (1 to 1) - - function str(sl: std_logic) return string is - variable s: string(1 to 1); - begin - s(1) := chr(sl); - return s; - end str; - - - - -- converts std_logic_vector into a string (binary base) - -- (this also takes care of the fact that the range of - -- a string is natural while a std_logic_vector may - -- have an integer range) - - function str(slv: std_logic_vector) return string is - variable result : string (1 to slv'length); - variable r : integer; - begin - r := 1; - for i in slv'range loop - result(r) := chr(slv(i)); - r := r + 1; - end loop; - return result; - end str; - - - function str(b: boolean) return string is - - begin - if b then - return "true"; - else - return "false"; - end if; - end str; - - - -- converts an integer into a character - -- for 0 to 9 the obvious mapping is used, higher - -- values are mapped to the characters A-Z - -- (this is usefull for systems with base > 10) - -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) - - function chr(int: integer) return character is - variable c: character; - begin - case int is - when 0 => c := '0'; - when 1 => c := '1'; - when 2 => c := '2'; - when 3 => c := '3'; - when 4 => c := '4'; - when 5 => c := '5'; - when 6 => c := '6'; - when 7 => c := '7'; - when 8 => c := '8'; - when 9 => c := '9'; - when 10 => c := 'A'; - when 11 => c := 'B'; - when 12 => c := 'C'; - when 13 => c := 'D'; - when 14 => c := 'E'; - when 15 => c := 'F'; - when 16 => c := 'G'; - when 17 => c := 'H'; - when 18 => c := 'I'; - when 19 => c := 'J'; - when 20 => c := 'K'; - when 21 => c := 'L'; - when 22 => c := 'M'; - when 23 => c := 'N'; - when 24 => c := 'O'; - when 25 => c := 'P'; - when 26 => c := 'Q'; - when 27 => c := 'R'; - when 28 => c := 'S'; - when 29 => c := 'T'; - when 30 => c := 'U'; - when 31 => c := 'V'; - when 32 => c := 'W'; - when 33 => c := 'X'; - when 34 => c := 'Y'; - when 35 => c := 'Z'; - when others => c := '?'; - end case; - return c; - end chr; - - - - -- convert integer to string using specified base - -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) - - function str(int: integer; base: integer) return string is - - variable temp: string(1 to 10); - variable num: integer; - variable abs_int: integer; - variable len: integer := 1; - variable power: integer := 1; - - begin - - -- bug fix for negative numbers - abs_int := abs(int); - - num := abs_int; - - while num >= base loop -- Determine how many - len := len + 1; -- characters required - num := num / base; -- to represent the - end loop ; -- number. - - for i in len downto 1 loop -- Convert the number to - temp(i) := chr(abs_int/power mod base); -- a string starting - power := power * base; -- with the right hand - end loop ; -- side. - - -- return result and add sign if required - if int < 0 then - return '-'& temp(1 to len); - else - return temp(1 to len); - end if; - - end str; - - - -- convert integer to string, using base 10 - function str(int: integer) return string is - - begin - - return str(int, 10) ; - - end str; - - - - -- converts a std_logic_vector into a hex string. - function hstr(slv: std_logic_vector) return string is - variable hexlen: integer; - variable longslv : std_logic_vector(67 downto 0) := (others => '0'); - variable hex : string(1 to 16); - variable fourbit : std_logic_vector(3 downto 0); - begin - hexlen := (slv'left+1)/4; - if (slv'left+1) mod 4 /= 0 then - hexlen := hexlen + 1; - end if; - longslv(slv'left downto 0) := slv; - for i in (hexlen -1) downto 0 loop - fourbit := longslv(((i*4)+3) downto (i*4)); - case fourbit is - when "0000" => hex(hexlen -I) := '0'; - when "0001" => hex(hexlen -I) := '1'; - when "0010" => hex(hexlen -I) := '2'; - when "0011" => hex(hexlen -I) := '3'; - when "0100" => hex(hexlen -I) := '4'; - when "0101" => hex(hexlen -I) := '5'; - when "0110" => hex(hexlen -I) := '6'; - when "0111" => hex(hexlen -I) := '7'; - when "1000" => hex(hexlen -I) := '8'; - when "1001" => hex(hexlen -I) := '9'; - when "1010" => hex(hexlen -I) := 'A'; - when "1011" => hex(hexlen -I) := 'B'; - when "1100" => hex(hexlen -I) := 'C'; - when "1101" => hex(hexlen -I) := 'D'; - when "1110" => hex(hexlen -I) := 'E'; - when "1111" => hex(hexlen -I) := 'F'; - when "ZZZZ" => hex(hexlen -I) := 'z'; - when "UUUU" => hex(hexlen -I) := 'u'; - when "XXXX" => hex(hexlen -I) := 'x'; - when others => hex(hexlen -I) := '?'; - end case; - end loop; - return hex(1 to hexlen); - end hstr; - - - - -- functions to manipulate strings - ----------------------------------- - - - -- convert a character to upper case - - function to_upper(c: character) return character is - - variable u: character; - - begin - - case c is - when 'a' => u := 'A'; - when 'b' => u := 'B'; - when 'c' => u := 'C'; - when 'd' => u := 'D'; - when 'e' => u := 'E'; - when 'f' => u := 'F'; - when 'g' => u := 'G'; - when 'h' => u := 'H'; - when 'i' => u := 'I'; - when 'j' => u := 'J'; - when 'k' => u := 'K'; - when 'l' => u := 'L'; - when 'm' => u := 'M'; - when 'n' => u := 'N'; - when 'o' => u := 'O'; - when 'p' => u := 'P'; - when 'q' => u := 'Q'; - when 'r' => u := 'R'; - when 's' => u := 'S'; - when 't' => u := 'T'; - when 'u' => u := 'U'; - when 'v' => u := 'V'; - when 'w' => u := 'W'; - when 'x' => u := 'X'; - when 'y' => u := 'Y'; - when 'z' => u := 'Z'; - when others => u := c; - end case; - - return u; - - end to_upper; - - - -- convert a character to lower case - - function to_lower(c: character) return character is - - variable l: character; - - begin - - case c is - when 'A' => l := 'a'; - when 'B' => l := 'b'; - when 'C' => l := 'c'; - when 'D' => l := 'd'; - when 'E' => l := 'e'; - when 'F' => l := 'f'; - when 'G' => l := 'g'; - when 'H' => l := 'h'; - when 'I' => l := 'i'; - when 'J' => l := 'j'; - when 'K' => l := 'k'; - when 'L' => l := 'l'; - when 'M' => l := 'm'; - when 'N' => l := 'n'; - when 'O' => l := 'o'; - when 'P' => l := 'p'; - when 'Q' => l := 'q'; - when 'R' => l := 'r'; - when 'S' => l := 's'; - when 'T' => l := 't'; - when 'U' => l := 'u'; - when 'V' => l := 'v'; - when 'W' => l := 'w'; - when 'X' => l := 'x'; - when 'Y' => l := 'y'; - when 'Z' => l := 'z'; - when others => l := c; - end case; - - return l; - - end to_lower; - - - - -- convert a string to upper case - - function to_upper(s: string) return string is - - variable uppercase: string (s'range); - - begin - - for i in s'range loop - uppercase(i):= to_upper(s(i)); - end loop; - return uppercase; - - end to_upper; - - - - -- convert a string to lower case - - function to_lower(s: string) return string is - - variable lowercase: string (s'range); - - begin - - for i in s'range loop - lowercase(i):= to_lower(s(i)); - end loop; - return lowercase; - - end to_lower; - - - --- functions to convert strings into other types - - --- converts a character into a std_logic - -function to_std_logic(c: character) return std_logic is - variable sl: std_logic; - begin - case c is - when 'U' => - sl := 'U'; - when 'X' => - sl := 'X'; - when '0' => - sl := '0'; - when '1' => - sl := '1'; - when 'Z' => - sl := 'Z'; - when 'W' => - sl := 'W'; - when 'L' => - sl := 'L'; - when 'H' => - sl := 'H'; - when '-' => - sl := '-'; - when others => - sl := 'X'; - end case; - return sl; - end to_std_logic; - - --- converts a string into std_logic_vector - -function to_std_logic_vector(s: string) return std_logic_vector is - variable slv: std_logic_vector(s'high-s'low downto 0); - variable k: integer; -begin - k := s'high-s'low; - for i in s'range loop - slv(k) := to_std_logic(s(i)); - k := k - 1; - end loop; - return slv; -end to_std_logic_vector; - - - - - - ----------------- --- file I/O -- ----------------- - - - --- read variable length string from input file - -procedure str_read(file in_file: TEXT; - res_string: out string) is - - variable l: line; - variable c: character; - variable is_string: boolean; - - begin - - readline(in_file, l); - -- clear the contents of the result string - for i in res_string'range loop - res_string(i) := ' '; - end loop; - -- read all characters of the line, up to the length - -- of the results string - for i in res_string'range loop - read(l, c, is_string); - res_string(i) := c; - if not is_string then -- found end of line - exit; - end if; - end loop; - -end str_read; - - --- print string to a file -procedure print(file out_file: TEXT; - new_string: in string) is - - variable l: line; - - begin - - write(l, new_string); - writeline(out_file, l); - -end print; - - --- print character to a file and start new line -procedure print(file out_file: TEXT; - char: in character) is - - variable l: line; - - begin - - write(l, char); - writeline(out_file, l); - -end print; - - - --- appends contents of a string to a file until line feed occurs --- (LF is considered to be the end of the string) - -procedure str_write(file out_file: TEXT; - new_string: in string) is - begin - - for i in new_string'range loop - print(out_file, new_string(i)); - if new_string(i) = LF then -- end of string - exit; - end if; - end loop; - -end str_write; - - - - -end txt_util; - - - - Index: Pure/PresentStateMachine.vhd =================================================================== --- Pure/PresentStateMachine.vhd (revision 3) +++ Pure/PresentStateMachine.vhd (nonexistent) @@ -1,100 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:17:10 04/02/2011 --- Design Name: --- Module Name: PresentStateMachine - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.NUMERIC_STD.ALL; -use work.kody.ALL; - -entity PresentStateMachine is - generic ( - w_5 : integer := 5 - ); - port ( - clk, reset, start : in std_logic; - ready, cnt_res, ctrl_mux, RegEn: out std_logic; - num : in std_logic_vector (w_5-1 downto 0) - ); -end PresentStateMachine; - -architecture Behavioral of PresentStateMachine is - - signal state : stany; - signal next_state : stany; - - begin - States : process(state, start, num) - begin - case state is - when NOP => - ready <= '0'; - cnt_res <= '0'; - ctrl_mux <= '0'; - RegEn <= '0'; - if (start = '1') then - next_state <= SM_START; - else - next_state <= NOP; - end if; - when SM_START => - ready <= '0'; - RegEn <= '1'; - cnt_res <= '1'; - if (start = '1') then - if (num = "00000") then - ctrl_mux <= '0'; - next_state <= SM_START; - elsif (num = "11111") then - ctrl_mux <= '1'; - next_state <= SM_READY; - else - ctrl_mux <= '1'; - next_state <= SM_START; - end if; - else - ctrl_mux <= '0'; - next_state <= NOP; - end if; - when SM_READY => - cnt_res <= '0'; - RegEn <= '0'; - ready <= '1'; - if (start = '1') then - ctrl_mux <= '1'; - next_state <= SM_READY; - else - ctrl_mux <= '0'; - next_state <= NOP; - end if; - end case; - end process States; - - SM : process (clk, reset) - begin - if (reset = '1') then - state <= NOP; - elsif (clk'Event and clk = '1') then - state <= next_state; - end if; - end process SM; - - end Behavioral; - Index: Pure/keyupd.vhd =================================================================== --- Pure/keyupd.vhd (revision 3) +++ Pure/keyupd.vhd (nonexistent) @@ -1,59 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 19:45:36 05/13/2010 --- Design Name: --- Module Name: keyupd - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity keyupd is - generic( - w_80: integer := 80; - w_5 : integer := 5; - w_4 : integer := 4); - port( - key : in std_logic_vector(w_80-1 downto 0); - num : in std_logic_vector(w_5-1 downto 0); - keyout : out std_logic_vector(w_80-1 downto 0) - ); -end keyupd; - -architecture Behavioral of keyupd is - - component slayer is - generic(w_4: integer := 4); - port( - input : in std_logic_vector(w_4-1 downto 0); - output : out std_logic_vector(w_4-1 downto 0) - ); - end component; - - signal changed : std_logic_vector(w_4-1 downto 0); - signal changin : std_logic_vector(w_4-1 downto 0); - signal keytemp : std_logic_vector(w_80-1 downto 0); - - begin - s1: slayer port map(input => changin, output => changed); - changin <= keytemp(79 downto 76); - keytemp <= key(18 downto 0) & key(79 downto 19); - keyout(79 downto 76)<= changed; - keyout(75 downto 20) <= keytemp(75 downto 20); - keyout(19 downto 15)<= keytemp(19 downto 15) xor num; - keyout(14 downto 0) <= keytemp(14 downto 0); - end Behavioral; \ No newline at end of file Index: Pure/slayer.vhd =================================================================== --- Pure/slayer.vhd (revision 3) +++ Pure/slayer.vhd (nonexistent) @@ -1,55 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 13:48:15 05/13/2010 --- Design Name: --- Module Name: permutation - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity slayer is - generic ( - w_4 : integer := 4 - ); - port ( - input : in std_logic_vector(w_4-1 downto 0); - output : out std_logic_vector(w_4-1 downto 0) - ); -end slayer; - -architecture Behavioral of slayer is - - begin - output <= x"C" when input = x"0" else - x"5" when input = x"1" else - x"6" when input = x"2" else - x"B" when input = x"3" else - x"9" when input = x"4" else - x"0" when input = x"5" else - x"A" when input = x"6" else - x"D" when input = x"7" else - x"3" when input = x"8" else - x"E" when input = x"9" else - x"F" when input = x"A" else - x"8" when input = x"B" else - x"4" when input = x"C" else - x"7" when input = x"D" else - x"1" when input = x"E" else - x"2" when input = x"F" else - "ZZZZ"; - end Behavioral; \ No newline at end of file Index: Pure/AsyncMux.vhd =================================================================== --- Pure/AsyncMux.vhd (revision 3) +++ Pure/AsyncMux.vhd (nonexistent) @@ -1,50 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 23:24:35 06/24/2013 --- Design Name: --- Module Name: AsyncMux - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity AsyncMux is - generic ( - width : integer := 64 - ); - port ( - input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); - input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); - ctrl : in STD_LOGIC; - output : out STD_LOGIC_VECTOR(width - 1 downto 0) - ); -end AsyncMux; - -architecture Behavioral of AsyncMux is - -begin - output <= input0 when (ctrl = '0') else - input1; -end Behavioral; - Index: Pure/counter.vhd =================================================================== --- Pure/counter.vhd (revision 3) +++ Pure/counter.vhd (nonexistent) @@ -1,49 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 13:47:04 04/02/2011 --- Design Name: --- Module Name: counter - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity counter is - generic ( - w_5 : integer := 5 - ); - port ( - clk, reset, cnt_res : in std_logic; - num : out std_logic_vector (w_5-1 downto 0) - ); -end counter; - -architecture Behavioral of counter is - signal cnt : std_logic_vector(w_5-1 downto 0) := (others => '0'); - begin - licznik : process (clk, reset, cnt) - begin - if (reset = '1') then - cnt <= (others => '0'); - elsif (clk'Event and clk = '1') then - if (cnt_res = '1') then - cnt <= cnt + 1; - end if; - end if; - end process licznik; - num <= cnt; - end Behavioral; - Index: Pure/kody.vhd =================================================================== --- Pure/kody.vhd (revision 3) +++ Pure/kody.vhd (nonexistent) @@ -1,34 +0,0 @@ --- Package File Template --- --- Purpose: This package defines supplemental types, subtypes, --- constants, and functions - - -library IEEE; -use IEEE.STD_LOGIC_1164.all; -package kody is - -- type for PresentStateMachine to control the datapath & circuit -- - type stany is (NOP, SM_START, SM_READY); - -- constant as control command from input -- - constant cnop : std_logic_vector(3 downto 0) := "0000"; --0 no operations - constant cdec : std_logic_vector(3 downto 0) := "0001"; --1 decode text - constant crdk1 : std_logic_vector(3 downto 0) := "0010"; --2 read key part 1 - constant crdk2 : std_logic_vector(3 downto 0) := "0011"; --3 read key part 2 - constant crdk3 : std_logic_vector(3 downto 0) := "0100"; --4 read key part 3 - constant cmkd : std_logic_vector(3 downto 0) := "0101"; --5 make decrypt key - constant ccod : std_logic_vector(3 downto 0) := "0110"; --6 code text - constant crdt1 : std_logic_vector(3 downto 0) := "0111"; --7 read text part 1 - constant crdt2 : std_logic_vector(3 downto 0) := "1000"; --8 read text part 2 - constant ccto1 : std_logic_vector(3 downto 0) := "1001"; --9 ciphertext output part 1 (LSW) - constant ccto2 : std_logic_vector(3 downto 0) := "1010"; --A ciphertext output part 2 (MSW) - -- For input registers (early version, now for mux's) -- - constant in_ld_reg_L : std_logic_vector(1 downto 0) := "00"; -- Load low part of the register (64 & 80 bit) - constant in_ld_reg_H : std_logic_vector(1 downto 0) := "01"; -- Load high part of the register (64 & 80 bit) - constant in_ld_reg_HH : std_logic_vector(1 downto 0) := "10"; -- Load highest part of the register (80 bit only) - constant in_reg_Z : std_logic_vector(1 downto 0) := "11"; -- High impedance on the line (unused - in this design only for block input) - -- For output register -- - constant out_ld_reg : std_logic_vector(1 downto 0) := "00"; -- Load the output register - constant out_reg_L : std_logic_vector(1 downto 0) := "01"; -- send low part of the register to the output - constant out_reg_H : std_logic_vector(1 downto 0) := "10"; -- senf high part of the register to the output - constant out_reg_Z : std_logic_vector(1 downto 0) := "11"; -- High impedance on the line (unused - in this design only for block input) -end kody; \ No newline at end of file Index: Pure/bench/vhdl/sLayerTB.vhd =================================================================== --- Pure/bench/vhdl/sLayerTB.vhd (nonexistent) +++ Pure/bench/vhdl/sLayerTB.vhd (revision 4) @@ -0,0 +1,111 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Substitution layer test bench of Present encoder. ---- +---- Nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + +ENTITY sLayerTB IS +END sLayerTB; + +ARCHITECTURE behavior OF sLayerTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT slayer + PORT( + input : IN std_logic_vector(3 downto 0); + output : OUT std_logic_vector(3 downto 0) + ); + END COMPONENT; + + + --Inputs + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --BiDirs + signal input : std_logic_vector(3 downto 0); + signal output : std_logic_vector(3 downto 0); + + -- Clock period definitions + constant clk_period : time := 1ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: slayer PORT MAP ( + input => input, + output => output + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + reset <= '1'; + wait for 100ns; + reset <= '0'; + wait for clk_period; + input <= x"0"; + wait for clk_period; + input <= x"A"; + wait for clk_period; + input <= x"F"; + wait for clk_period; + -- insert stimulus here + assert false severity failure; + end process; + +END; \ No newline at end of file Index: Pure/bench/vhdl/PresentTB.vhd =================================================================== --- Pure/bench/vhdl/PresentTB.vhd (nonexistent) +++ Pure/bench/vhdl/PresentTB.vhd (revision 4) @@ -0,0 +1,150 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Test bench of Present encoder. Nothing special. Data taken---- +---- from http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY PresentTB IS +END PresentTB; + +ARCHITECTURE behavior OF PresentTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT PresentEnc + PORT( + plaintext : IN std_logic_vector(63 downto 0); + key : IN std_logic_vector(79 downto 0); + ciphertext : OUT std_logic_vector(63 downto 0); + start : IN std_logic; + clk : IN std_logic; + reset : IN std_logic; + ready : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal plaintext : std_logic_vector(63 downto 0) := (others => '0'); + signal key : std_logic_vector(79 downto 0) := (others => '0'); + signal start : std_logic := '0'; + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --Outputs + signal ciphertext : std_logic_vector(63 downto 0); + signal ready : std_logic; + + -- Clock period definitions + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: PresentEnc PORT MAP ( + plaintext => plaintext, + key => key, + ciphertext => ciphertext, + start => start, + clk => clk, + reset => reset, + ready => ready + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + + reset <= '1'; + start <= '0'; + wait for 100 ns; + reset <= '0'; + + plaintext <= (others => '0'); + key <= (others => '0'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + plaintext <= (others => '0'); + key <= (others => '1'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + plaintext <= (others => '1'); + key <= (others => '0'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + plaintext <= (others => '1'); + key <= (others => '1'); + start <= '1'; + wait for clk_period*40; + start <= '0'; + wait for clk_period; + + assert false severity failure; + + end process; + +END; Index: Pure/bench/vhdl/keyupdTB.vhd =================================================================== --- Pure/bench/vhdl/keyupdTB.vhd (nonexistent) +++ Pure/bench/vhdl/keyupdTB.vhd (revision 4) @@ -0,0 +1,122 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Key update test bench. It was much more used during ---- +---- inverse so data below are the same. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + +ENTITY keyupdTB IS +END keyupdTB; + +ARCHITECTURE behavior OF keyupdTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT keyupd + PORT( + key : IN std_logic_vector(79 downto 0); + num : IN std_logic_vector(4 downto 0); + keyout : OUT std_logic_vector(79 downto 0)--; + --clk, reset : std_logic + ); + END COMPONENT; + + + --Inputs + signal key : std_logic_vector(79 downto 0) := (others => '0'); + signal num : std_logic_vector(4 downto 0) := (others => '0'); + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + + --Outputs + signal keyout : std_logic_vector(79 downto 0); + + constant clk_period : time := 1ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: keyupd PORT MAP ( + key => key, + num => num, + keyout => keyout--, + --clk => clk, + --reset => reset + ); + + -- No clocks detected in port list. Replace clk below with + -- appropriate port name + + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + reset <= '1'; + wait for 100ns; + reset <='0'; + wait for clk_period; + key <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + num <= "00001"; + wait for clk_period; + key <= x"c0000000000000008000"; + num <= "00010"; + wait for clk_period; + key <= x"50001800000000010000"; + num <= "00011"; + wait for clk_period; + key <= x"8ba27a0eb8783ac96d59"; + num <= "11111"; + wait for clk_period; + assert false severity failure; + end process; +END; \ No newline at end of file Index: Pure/bench/vhdl/txt_util.vhd =================================================================== --- Pure/bench/vhdl/txt_util.vhd (nonexistent) +++ Pure/bench/vhdl/txt_util.vhd (revision 4) @@ -0,0 +1,586 @@ +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; + + +package txt_util is + + -- prints a message to the screen + procedure print(text: string); + + -- prints the message when active + -- useful for debug switches + procedure print(active: boolean; text: string); + + -- converts std_logic into a character + function chr(sl: std_logic) return character; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string; + + -- converts std_logic_vector into a string (binary base) + function str(slv: std_logic_vector) return string; + + -- converts boolean into a string + function str(b: boolean) return string; + + -- converts an integer into a single character + -- (can also be used for hex conversion and other bases) + function chr(int: integer) return character; + + -- converts integer into string using specified base + function str(int: integer; base: integer) return string; + + -- converts integer to string, using base 10 + function str(int: integer) return string; + + -- convert std_logic_vector into a string in hex format + function hstr(slv: std_logic_vector) return string; + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c: character) return character; + + -- convert a character to lower case + function to_lower(c: character) return character; + + -- convert a string to upper case + function to_upper(s: string) return string; + + -- convert a string to lower case + function to_lower(s: string) return string; + + + + -- functions to convert strings into other formats + -------------------------------------------------- + + -- converts a character into std_logic + function to_std_logic(c: character) return std_logic; + + -- converts a string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector; + + + + -- file I/O + ----------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string); + + -- print string to a file and start new line + procedure print(file out_file: TEXT; + new_string: in string); + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character); + +end txt_util; + + + + +package body txt_util is + + + + + -- prints text to the screen + + procedure print(text: string) is + variable msg_line: line; + begin + write(msg_line, text); + writeline(output, msg_line); + end print; + + + + + -- prints text to the screen when active + + procedure print(active: boolean; text: string) is + begin + if active then + print(text); + end if; + end print; + + + -- converts std_logic into a character + + function chr(sl: std_logic) return character is + variable c: character; + begin + case sl is + when 'U' => c:= 'U'; + when 'X' => c:= 'X'; + when '0' => c:= '0'; + when '1' => c:= '1'; + when 'Z' => c:= 'Z'; + when 'W' => c:= 'W'; + when 'L' => c:= 'L'; + when 'H' => c:= 'H'; + when '-' => c:= '-'; + end case; + return c; + end chr; + + + + -- converts std_logic into a string (1 to 1) + + function str(sl: std_logic) return string is + variable s: string(1 to 1); + begin + s(1) := chr(sl); + return s; + end str; + + + + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + + function str(slv: std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r := 1; + for i in slv'range loop + result(r) := chr(slv(i)); + r := r + 1; + end loop; + return result; + end str; + + + function str(b: boolean) return string is + + begin + if b then + return "true"; + else + return "false"; + end if; + end str; + + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function chr(int: integer) return character is + variable c: character; + begin + case int is + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; + end case; + return c; + end chr; + + + + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function str(int: integer; base: integer) return string is + + variable temp: string(1 to 10); + variable num: integer; + variable abs_int: integer; + variable len: integer := 1; + variable power: integer := 1; + + begin + + -- bug fix for negative numbers + abs_int := abs(int); + + num := abs_int; + + while num >= base loop -- Determine how many + len := len + 1; -- characters required + num := num / base; -- to represent the + end loop ; -- number. + + for i in len downto 1 loop -- Convert the number to + temp(i) := chr(abs_int/power mod base); -- a string starting + power := power * base; -- with the right hand + end loop ; -- side. + + -- return result and add sign if required + if int < 0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; + + end str; + + + -- convert integer to string, using base 10 + function str(int: integer) return string is + + begin + + return str(int, 10) ; + + end str; + + + + -- converts a std_logic_vector into a hex string. + function hstr(slv: std_logic_vector) return string is + variable hexlen: integer; + variable longslv : std_logic_vector(67 downto 0) := (others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen := (slv'left+1)/4; + if (slv'left+1) mod 4 /= 0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen -1) downto 0 loop + fourbit := longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen -I) := '0'; + when "0001" => hex(hexlen -I) := '1'; + when "0010" => hex(hexlen -I) := '2'; + when "0011" => hex(hexlen -I) := '3'; + when "0100" => hex(hexlen -I) := '4'; + when "0101" => hex(hexlen -I) := '5'; + when "0110" => hex(hexlen -I) := '6'; + when "0111" => hex(hexlen -I) := '7'; + when "1000" => hex(hexlen -I) := '8'; + when "1001" => hex(hexlen -I) := '9'; + when "1010" => hex(hexlen -I) := 'A'; + when "1011" => hex(hexlen -I) := 'B'; + when "1100" => hex(hexlen -I) := 'C'; + when "1101" => hex(hexlen -I) := 'D'; + when "1110" => hex(hexlen -I) := 'E'; + when "1111" => hex(hexlen -I) := 'F'; + when "ZZZZ" => hex(hexlen -I) := 'z'; + when "UUUU" => hex(hexlen -I) := 'u'; + when "XXXX" => hex(hexlen -I) := 'x'; + when others => hex(hexlen -I) := '?'; + end case; + end loop; + return hex(1 to hexlen); + end hstr; + + + + -- functions to manipulate strings + ----------------------------------- + + + -- convert a character to upper case + + function to_upper(c: character) return character is + + variable u: character; + + begin + + case c is + when 'a' => u := 'A'; + when 'b' => u := 'B'; + when 'c' => u := 'C'; + when 'd' => u := 'D'; + when 'e' => u := 'E'; + when 'f' => u := 'F'; + when 'g' => u := 'G'; + when 'h' => u := 'H'; + when 'i' => u := 'I'; + when 'j' => u := 'J'; + when 'k' => u := 'K'; + when 'l' => u := 'L'; + when 'm' => u := 'M'; + when 'n' => u := 'N'; + when 'o' => u := 'O'; + when 'p' => u := 'P'; + when 'q' => u := 'Q'; + when 'r' => u := 'R'; + when 's' => u := 'S'; + when 't' => u := 'T'; + when 'u' => u := 'U'; + when 'v' => u := 'V'; + when 'w' => u := 'W'; + when 'x' => u := 'X'; + when 'y' => u := 'Y'; + when 'z' => u := 'Z'; + when others => u := c; + end case; + + return u; + + end to_upper; + + + -- convert a character to lower case + + function to_lower(c: character) return character is + + variable l: character; + + begin + + case c is + when 'A' => l := 'a'; + when 'B' => l := 'b'; + when 'C' => l := 'c'; + when 'D' => l := 'd'; + when 'E' => l := 'e'; + when 'F' => l := 'f'; + when 'G' => l := 'g'; + when 'H' => l := 'h'; + when 'I' => l := 'i'; + when 'J' => l := 'j'; + when 'K' => l := 'k'; + when 'L' => l := 'l'; + when 'M' => l := 'm'; + when 'N' => l := 'n'; + when 'O' => l := 'o'; + when 'P' => l := 'p'; + when 'Q' => l := 'q'; + when 'R' => l := 'r'; + when 'S' => l := 's'; + when 'T' => l := 't'; + when 'U' => l := 'u'; + when 'V' => l := 'v'; + when 'W' => l := 'w'; + when 'X' => l := 'x'; + when 'Y' => l := 'y'; + when 'Z' => l := 'z'; + when others => l := c; + end case; + + return l; + + end to_lower; + + + + -- convert a string to upper case + + function to_upper(s: string) return string is + + variable uppercase: string (s'range); + + begin + + for i in s'range loop + uppercase(i):= to_upper(s(i)); + end loop; + return uppercase; + + end to_upper; + + + + -- convert a string to lower case + + function to_lower(s: string) return string is + + variable lowercase: string (s'range); + + begin + + for i in s'range loop + lowercase(i):= to_lower(s(i)); + end loop; + return lowercase; + + end to_lower; + + + +-- functions to convert strings into other types + + +-- converts a character into a std_logic + +function to_std_logic(c: character) return std_logic is + variable sl: std_logic; + begin + case c is + when 'U' => + sl := 'U'; + when 'X' => + sl := 'X'; + when '0' => + sl := '0'; + when '1' => + sl := '1'; + when 'Z' => + sl := 'Z'; + when 'W' => + sl := 'W'; + when 'L' => + sl := 'L'; + when 'H' => + sl := 'H'; + when '-' => + sl := '-'; + when others => + sl := 'X'; + end case; + return sl; + end to_std_logic; + + +-- converts a string into std_logic_vector + +function to_std_logic_vector(s: string) return std_logic_vector is + variable slv: std_logic_vector(s'high-s'low downto 0); + variable k: integer; +begin + k := s'high-s'low; + for i in s'range loop + slv(k) := to_std_logic(s(i)); + k := k - 1; + end loop; + return slv; +end to_std_logic_vector; + + + + + + +---------------- +-- file I/O -- +---------------- + + + +-- read variable length string from input file + +procedure str_read(file in_file: TEXT; + res_string: out string) is + + variable l: line; + variable c: character; + variable is_string: boolean; + + begin + + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i) := ' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + read(l, c, is_string); + res_string(i) := c; + if not is_string then -- found end of line + exit; + end if; + end loop; + +end str_read; + + +-- print string to a file +procedure print(file out_file: TEXT; + new_string: in string) is + + variable l: line; + + begin + + write(l, new_string); + writeline(out_file, l); + +end print; + + +-- print character to a file and start new line +procedure print(file out_file: TEXT; + char: in character) is + + variable l: line; + + begin + + write(l, char); + writeline(out_file, l); + +end print; + + + +-- appends contents of a string to a file until line feed occurs +-- (LF is considered to be the end of the string) + +procedure str_write(file out_file: TEXT; + new_string: in string) is + begin + + for i in new_string'range loop + print(out_file, new_string(i)); + if new_string(i) = LF then -- end of string + exit; + end if; + end loop; + +end str_write; + + + + +end txt_util; + + + + Index: Pure/bench/vhdl =================================================================== --- Pure/bench/vhdl (nonexistent) +++ Pure/bench/vhdl (revision 4)

Pure/bench/vhdl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Pure/bench =================================================================== --- Pure/bench (nonexistent) +++ Pure/bench (revision 4)

Pure/bench Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Pure/rtl/vhdl/counter.vhd =================================================================== --- Pure/rtl/vhdl/counter.vhd (nonexistent) +++ Pure/rtl/vhdl/counter.vhd (revision 4) @@ -0,0 +1,73 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Typical construction of 5bit counter. It is counting up. ---- +---- Nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity counter is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); +end counter; + +architecture Behavioral of counter is + signal cnt : std_logic_vector(w_5-1 downto 0) := (others => '0'); + begin + licznik : process (clk, reset, cnt) + begin + if (reset = '1') then + cnt <= (others => '0'); + elsif (clk'Event and clk = '1') then + if (cnt_res = '1') then + cnt <= cnt + 1; + end if; + end if; + end process licznik; + num <= cnt; + end Behavioral; + Index: Pure/rtl/vhdl/slayer.vhd =================================================================== --- Pure/rtl/vhdl/slayer.vhd (nonexistent) +++ Pure/rtl/vhdl/slayer.vhd (revision 4) @@ -0,0 +1,81 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Substitution layer of Present cipher. Simple logic. ---- +---- For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity slayer is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); +end slayer; + +architecture Behavioral of slayer is + + begin + output <= x"C" when input = x"0" else + x"5" when input = x"1" else + x"6" when input = x"2" else + x"B" when input = x"3" else + x"9" when input = x"4" else + x"0" when input = x"5" else + x"A" when input = x"6" else + x"D" when input = x"7" else + x"3" when input = x"8" else + x"E" when input = x"9" else + x"F" when input = x"A" else + x"8" when input = x"B" else + x"4" when input = x"C" else + x"7" when input = x"D" else + x"1" when input = x"E" else + x"2" when input = x"F" else + "ZZZZ"; + end Behavioral; \ No newline at end of file Index: Pure/rtl/vhdl/keyupd.vhd =================================================================== --- Pure/rtl/vhdl/keyupd.vhd (nonexistent) +++ Pure/rtl/vhdl/keyupd.vhd (revision 4) @@ -0,0 +1,86 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Key update module for present cipher it is 'signal ---- +---- mixing' made by rotation left by 61 bits, using one s-box, ---- +---- and output of the counter. For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity keyupd is + generic( + w_80: integer := 80; + w_5 : integer := 5; + w_4 : integer := 4); + port( + key : in std_logic_vector(w_80-1 downto 0); + num : in std_logic_vector(w_5-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); +end keyupd; + +architecture Behavioral of keyupd is + + component slayer is + generic(w_4: integer := 4); + port( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + signal changed : std_logic_vector(w_4-1 downto 0); + signal changin : std_logic_vector(w_4-1 downto 0); + signal keytemp : std_logic_vector(w_80-1 downto 0); + + begin + s1: slayer port map(input => changin, output => changed); + changin <= keytemp(79 downto 76); + keytemp <= key(18 downto 0) & key(79 downto 19); + keyout(79 downto 76)<= changed; + keyout(75 downto 20) <= keytemp(75 downto 20); + keyout(19 downto 15)<= keytemp(19 downto 15) xor num; + keyout(14 downto 0) <= keytemp(14 downto 0); + end Behavioral; \ No newline at end of file Index: Pure/rtl/vhdl/PresentEnc.vhd =================================================================== --- Pure/rtl/vhdl/PresentEnc.vhd (nonexistent) +++ Pure/rtl/vhdl/PresentEnc.vhd (revision 4) @@ -0,0 +1,220 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Top level of present encoder. For more information see ---- +---- below and http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity PresentEnc is + generic ( + w_2: integer := 2; + w_4: integer := 4; + w_5: integer := 5; + w_32: integer := 32; + w_64: integer := 64; + w_80: integer := 80 + ); + port( + plaintext : in std_logic_vector(w_64 - 1 downto 0); + key : in std_logic_vector(w_80 - 1 downto 0); + ciphertext : out std_logic_vector(w_64 - 1 downto 0); + start, clk, reset : in std_logic; + ready : out std_logic + ); +end PresentEnc; + +architecture Behavioral of PresentEnc is + + component Reg is + generic(width : integer := w_64); + port( + input : in STD_LOGIC_VECTOR(width - 1 downto 0); + output : out STD_LOGIC_VECTOR(width - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); + end component Reg; + + component AsyncMux is + generic ( + width : integer := 64 + ); + port ( + input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); + input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(width - 1 downto 0) + ); + end component AsyncMux; + + component PresentStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); + end component; + + -- substitution layer for decoding + component slayer is + generic ( + w_4 : integer := 4 + ); + port ( + input : in std_logic_vector(w_4-1 downto 0); + output : out std_logic_vector(w_4-1 downto 0) + ); + end component; + + -- permutation layer for decoding + component pLayer is + generic(w_64 : integer := 64); + port( + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_64-1 downto 0) + ); + end component; + + -- key update for decoding + component keyupd is + generic( + w_5 : integer := 5; + w_80: integer := 80 + ); + port( + num : in std_logic_vector(w_5-1 downto 0); + key : in std_logic_vector(w_80-1 downto 0); + keyout : out std_logic_vector(w_80-1 downto 0) + ); + end component; + + -- counter for decoding. It is counting up!!! + component counter is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, cnt_res : in std_logic; + num : out std_logic_vector (w_5-1 downto 0) + ); + end component; + + -- signals + + signal keynum : std_logic_vector (w_5-1 downto 0); + signal toXor, ciph, P, Pout, textToReg : std_logic_vector (w_64-1 downto 0); + signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0); + signal ready_sig, mux_ctrl, cnt_res, RegEn : std_logic; + + begin + + -- connections + + mux_64: AsyncMux generic map(width => w_64) port map( + input0 => plaintext, + input1 => Pout, + ctrl => mux_ctrl, + output => textToReg + ); + regText : Reg generic map(width => w_64) port map( + input => textToReg, + output => toXor, + enable => RegEn, + clk => clk, + reset => reset + ); + mux_80: AsyncMux generic map(width => w_80) port map( + input0 => key, + input1 => kupd, + ctrl => mux_ctrl, + output => keyToReg + ); + regKey : Reg generic map(width => w_80) port map( + input => keyToReg, + output => keyfout, + enable => RegEn, + clk => clk, + reset => reset + ); + slayers : for N in 15 downto 0 generate + s_x: slayer port map( + input => ciph(4*N+3 downto 4*N), + output => P(4*N+3 downto 4*N) + ); + end generate slayers; + p1: pLayer port map( + input => P, + output => Pout + ); + mixer: keyupd port map( + key => keyfout, + num => keynum, + keyout => kupd + ); + SM: PresentStateMachine port map( + start => start, + reset => reset, + ready => ready_sig, + cnt_res => cnt_res, + ctrl_mux => mux_ctrl, + clk => clk, + num => keynum, + RegEn => RegEn + ); + count: counter port map( + clk => clk, + reset => reset, + cnt_res => cnt_res, + num => keynum + ); + ciph <= toXor xor keyfout(79 downto 16); + ciphertext <= ciph; + ready <= ready_sig; +end Behavioral; Index: Pure/rtl/vhdl/PresentStateMachine.vhd =================================================================== --- Pure/rtl/vhdl/PresentStateMachine.vhd (nonexistent) +++ Pure/rtl/vhdl/PresentStateMachine.vhd (revision 4) @@ -0,0 +1,130 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- State machine for Present encoder. For more informations ---- +---- see below. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.kody.ALL; + +entity PresentStateMachine is + generic ( + w_5 : integer := 5 + ); + port ( + clk, reset, start : in std_logic; + ready, cnt_res, ctrl_mux, RegEn: out std_logic; + num : in std_logic_vector (w_5-1 downto 0) + ); +end PresentStateMachine; + +architecture Behavioral of PresentStateMachine is + + signal state : stany; + signal next_state : stany; + + begin + States : process(state, start, num) + begin + case state is + ---- Waiting for start + when NOP => + ready <= '0'; + cnt_res <= '0'; + ctrl_mux <= '0'; + RegEn <= '0'; + if (start = '1') then + next_state <= SM_START; + else + next_state <= NOP; + end if; + -- Decoding + when SM_START => + ready <= '0'; + RegEn <= '1'; + cnt_res <= '1'; + if (start = '1') then + -- control during first start + if (num = "00000") then + ctrl_mux <= '0'; + next_state <= SM_START; + -- last iteration + elsif (num = "11111") then + ctrl_mux <= '1'; + next_state <= SM_READY; + -- rest iterations + else + ctrl_mux <= '1'; + next_state <= SM_START; + end if; + else + ctrl_mux <= '0'; + next_state <= NOP; + end if; + -- Decoding end + when SM_READY => + cnt_res <= '0'; + RegEn <= '0'; + ready <= '1'; + if (start = '1') then + ctrl_mux <= '1'; + next_state <= SM_READY; + else + ctrl_mux <= '0'; + next_state <= NOP; + end if; + end case; + end process States; + + SM : process (clk, reset) + begin + if (reset = '1') then + state <= NOP; + elsif (clk'Event and clk = '1') then + state <= next_state; + end if; + end process SM; + + end Behavioral; + Index: Pure/rtl/vhdl/kody.vhd =================================================================== --- Pure/rtl/vhdl/kody.vhd (nonexistent) +++ Pure/rtl/vhdl/kody.vhd (revision 4) @@ -0,0 +1,55 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- This file contains types and constant used by this ---- +---- implementation of Present project ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +package kody is + -- type for PresentStateMachine to control the datapath & circuit -- + type stany is (NOP, SM_START, SM_READY); +end kody; \ No newline at end of file Index: Pure/rtl/vhdl/AsyncMux.vhd =================================================================== --- Pure/rtl/vhdl/AsyncMux.vhd (nonexistent) +++ Pure/rtl/vhdl/AsyncMux.vhd (revision 4) @@ -0,0 +1,73 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Simple construction of multiplexer. Nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity AsyncMux is + generic ( + width : integer := 64 + ); + port ( + input0 : in STD_LOGIC_VECTOR(width - 1 downto 0); + input1 : in STD_LOGIC_VECTOR(width - 1 downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(width - 1 downto 0) + ); +end AsyncMux; + +architecture Behavioral of AsyncMux is + +begin + output <= input0 when (ctrl = '0') else + input1; +end Behavioral; + Index: Pure/rtl/vhdl/pLayer.vhd =================================================================== --- Pure/rtl/vhdl/pLayer.vhd (nonexistent) +++ Pure/rtl/vhdl/pLayer.vhd (revision 4) @@ -0,0 +1,125 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Permutation layer of Present cipher. Simple signal mixing.---- +---- For more information see ---- +---- http://homes.esat.kuleuven.be/~abogdano/papers/ ---- +---- present_ches07.pdf ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity pLayer is + generic(w_64 : integer := 64); + port ( + input : in std_logic_vector(w_64-1 downto 0); + output : out std_logic_vector(w_64-1 downto 0) + ); +end pLayer; + +architecture Behavioral of pLayer is +begin + output(0) <= input(0); + output(16) <= input(1); + output(32) <= input(2); + output(48) <= input(3); + output(1) <= input(4); + output(17) <= input(5); + output(33) <= input(6); + output(49) <= input(7); + output(2) <= input(8); + output(18) <= input(9); + output(34) <= input(10); + output(50) <= input(11); + output(3) <= input(12); + output(19) <= input(13); + output(35) <= input(14); + output(51) <= input(15); + output(4) <= input(16); + output(20) <= input(17); + output(36) <= input(18); + output(52) <= input(19); + output(5) <= input(20); + output(21) <= input(21); + output(37) <= input(22); + output(53) <= input(23); + output(6) <= input(24); + output(22) <= input(25); + output(38) <= input(26); + output(54) <= input(27); + output(7) <= input(28); + output(23) <= input(29); + output(39) <= input(30); + output(55) <= input(31); + output(8) <= input(32); + output(24) <= input(33); + output(40) <= input(34); + output(56) <= input(35); + output(9) <= input(36); + output(25) <= input(37); + output(41) <= input(38); + output(57) <= input(39); + output(10) <= input(40); + output(26) <= input(41); + output(42) <= input(42); + output(58) <= input(43); + output(11) <= input(44); + output(27) <= input(45); + output(43) <= input(46); + output(59) <= input(47); + output(12) <= input(48); + output(28) <= input(49); + output(44) <= input(50); + output(60) <= input(51); + output(13) <= input(52); + output(29) <= input(53); + output(45) <= input(54); + output(61) <= input(55); + output(14) <= input(56); + output(30) <= input(57); + output(46) <= input(58); + output(62) <= input(59); + output(15) <= input(60); + output(31) <= input(61); + output(47) <= input(62); + output(63) <= input(63); +end Behavioral; \ No newline at end of file Index: Pure/rtl/vhdl/Reg.vhd =================================================================== --- Pure/rtl/vhdl/Reg.vhd (nonexistent) +++ Pure/rtl/vhdl/Reg.vhd (revision 4) @@ -0,0 +1,83 @@ +----------------------------------------------------------------------- +---- ---- +---- Present - a lightweight block cipher project ---- +---- ---- +---- This file is part of the Present - a lightweight block ---- +---- cipher project ---- +---- http://www.http://opencores.org/project,present ---- +---- ---- +---- Description: ---- +---- Register - nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Reg is + generic(width : integer := 64); + port( + input : in STD_LOGIC_VECTOR(width - 1 downto 0); + output : out STD_LOGIC_VECTOR(width - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); +end Reg; + +architecture Behavioral of Reg is + +signal reg : STD_LOGIC_VECTOR(width - 1 downto 0); + +begin + clock : process(clk, reset) + begin + if (reset = '1') then + reg <= (others => '0'); + elsif (clk = '1' and clk'Event) then + if (enable = '1') then + reg <= input; + end if; + end if; + end process clock; + output <= reg; +end Behavioral; + Index: Pure/rtl/vhdl =================================================================== --- Pure/rtl/vhdl (nonexistent) +++ Pure/rtl/vhdl (revision 4)

Pure/rtl/vhdl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Pure/rtl =================================================================== --- Pure/rtl (nonexistent) +++ Pure/rtl (revision 4)

Pure/rtl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Pure/doc/src =================================================================== --- Pure/doc/src (nonexistent) +++ Pure/doc/src (revision 4)

Pure/doc/src Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Pure/doc =================================================================== --- Pure/doc (nonexistent) +++ Pure/doc (revision 4)

Pure/doc Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Pure/sim =================================================================== --- Pure/sim (nonexistent) +++ Pure/sim (revision 4)

Pure/sim Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Pure/sw =================================================================== --- Pure/sw (nonexistent) +++ Pure/sw (revision 4)

Pure/sw Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Pure/syn/XC3ES500 =================================================================== --- Pure/syn/XC3ES500 (nonexistent) +++ Pure/syn/XC3ES500 (revision 4)

Pure/syn/XC3ES500 Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Pure/syn =================================================================== --- Pure/syn (nonexistent) +++ Pure/syn (revision 4)

Pure/syn Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property

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