URL
https://opencores.org/ocsvn/present/present/trunk
Subversion Repositories present
Compare Revisions
- This comparison shows the changes necessary to convert path
/present/trunk
- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/PureTesting/bench/vhdl/ShiftRegTB.vhd
1,134 → 1,134
----------------------------------------------------------------------- |
---- ---- |
---- Present - a lightweight block cipher project ---- |
---- ---- |
---- This file is part of the Present - a lightweight block ---- |
---- cipher project ---- |
---- http://www.http://opencores.org/project,present ---- |
---- ---- |
---- Description: ---- |
---- Test bench of shift register - nothing special. ---- |
---- To Do: ---- |
---- ---- |
---- Author(s): ---- |
---- - Krzysztof Gajewski, gajos@opencores.org ---- |
---- k.gajewski@gmail.com ---- |
---- ---- |
----------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and-or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
----------------------------------------------------------------------- |
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
use work.RSAFinalizerProperties.ALL; |
|
-- Uncomment the following library declaration if using |
-- arithmetic functions with Signed or Unsigned values |
--USE ieee.numeric_std.ALL; |
|
ENTITY ShiftRegTB IS |
END ShiftRegTB; |
|
ARCHITECTURE behavior OF ShiftRegTB IS |
|
-- Component Declaration for the Unit Under Test (UUT) |
|
COMPONENT ShiftReg |
-- generic (length_1 : integer := WORD_LENGTH; |
-- length_2 : integer := BYTE |
GENERIC ( |
length_1 : integer := BYTE; |
length_2 : integer := WORD_LENGTH |
); |
PORT( |
input : in STD_LOGIC_VECTOR(7 downto 0); |
--input : IN std_logic_vector(63 downto 0); |
output : out STD_LOGIC_VECTOR(63 downto 0); |
--output : OUT std_logic_vector(7 downto 0); |
en : in STD_LOGIC; |
shift : in STD_LOGIC; |
clk : in STD_LOGIC; |
reset : in STD_LOGIC |
); |
END COMPONENT; |
|
|
--Inputs |
signal input : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); |
--signal input : std_logic_vector(63 downto 0) := (others => '0'); |
signal en : STD_LOGIC := '0'; |
signal shift : STD_LOGIC := '0'; |
signal clk : STD_LOGIC := '0'; |
signal reset : STD_LOGIC := '0'; |
|
--Outputs |
signal output : STD_LOGIC_VECTOR(63 downto 0); |
--signal output : std_logic_vector(7 downto 0); |
|
-- Clock period definitions |
constant clk_period : time := 10 ns; |
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: ShiftReg PORT MAP ( |
input => input, |
output => output, |
en => en, |
shift => shift, |
clk => clk, |
reset => reset |
); |
|
-- Clock process definitions |
clk_process :process |
begin |
clk <= '0'; |
wait for clk_period/2; |
clk <= '1'; |
wait for clk_period/2; |
end process; |
|
|
-- Stimulus process |
stim_proc: process |
begin |
reset <= '0'; |
shift <= '0'; |
input <= "10101010"; |
--input <= "1111000011110000111100001111000011110000111100001111000011110000"; |
wait for 100 ns; |
reset <= '1'; |
wait for clk_period*10; |
en <= '1'; |
wait for clk_period*1; |
en <= '0'; |
wait for clk_period*1; |
shift <= '1'; |
wait for clk_period*10; |
assert false severity failure; |
end process; |
|
END; |
----------------------------------------------------------------------- |
---- ---- |
---- Present - a lightweight block cipher project ---- |
---- ---- |
---- This file is part of the Present - a lightweight block ---- |
---- cipher project ---- |
---- http://www.http://opencores.org/project,present ---- |
---- ---- |
---- Description: ---- |
---- Test bench of shift register - nothing special. ---- |
---- To Do: ---- |
---- ---- |
---- Author(s): ---- |
---- - Krzysztof Gajewski, gajos@opencores.org ---- |
---- k.gajewski@gmail.com ---- |
---- ---- |
----------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2013 Authors and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and-or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
----------------------------------------------------------------------- |
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
|
-- Uncomment the following library declaration if using |
-- arithmetic functions with Signed or Unsigned values |
--USE ieee.numeric_std.ALL; |
|
ENTITY ShiftRegTB IS |
END ShiftRegTB; |
|
ARCHITECTURE behavior OF ShiftRegTB IS |
|
-- Component Declaration for the Unit Under Test (UUT) |
|
COMPONENT ShiftReg |
-- generic (length_1 : integer := WORD_LENGTH; |
-- length_2 : integer := BYTE |
GENERIC ( |
length_1 : integer := 8; |
length_2 : integer := 64 |
); |
PORT( |
input : in STD_LOGIC_VECTOR(7 downto 0); |
--input : IN std_logic_vector(63 downto 0); |
output : out STD_LOGIC_VECTOR(63 downto 0); |
--output : OUT std_logic_vector(7 downto 0); |
en : in STD_LOGIC; |
shift : in STD_LOGIC; |
clk : in STD_LOGIC; |
reset : in STD_LOGIC |
); |
END COMPONENT; |
|
|
--Inputs |
signal input : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); |
--signal input : std_logic_vector(63 downto 0) := (others => '0'); |
signal en : STD_LOGIC := '0'; |
signal shift : STD_LOGIC := '0'; |
signal clk : STD_LOGIC := '0'; |
signal reset : STD_LOGIC := '0'; |
|
--Outputs |
signal output : STD_LOGIC_VECTOR(63 downto 0); |
--signal output : std_logic_vector(7 downto 0); |
|
-- Clock period definitions |
constant clk_period : time := 10 ns; |
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: ShiftReg PORT MAP ( |
input => input, |
output => output, |
en => en, |
shift => shift, |
clk => clk, |
reset => reset |
); |
|
-- Clock process definitions |
clk_process :process |
begin |
clk <= '0'; |
wait for clk_period/2; |
clk <= '1'; |
wait for clk_period/2; |
end process; |
|
|
-- Stimulus process |
stim_proc: process |
begin |
reset <= '0'; |
shift <= '0'; |
input <= "10101010"; |
--input <= "1111000011110000111100001111000011110000111100001111000011110000"; |
wait for 100 ns; |
reset <= '1'; |
wait for clk_period*10; |
reset <= '0'; |
en <= '1'; |
wait for clk_period*1; |
en <= '0'; |
wait for clk_period*1; |
shift <= '1'; |
wait for clk_period*10; |
assert false severity failure; |
end process; |
|
END; |
/PureTesting/bench/vhdl/PresentCommTB.vhd
106,10 → 106,10
stim_proc: process |
|
-- Variables |
file txt :text is in "test/data.txt"; |
file key :text is in "test/key.txt"; |
file txt2 :text is in "test/data2.txt"; |
file key2 :text is in "test/key2.txt"; |
file txt :text is in "../src/test/data.txt"; |
file key :text is in "../src/test/key.txt"; |
file txt2 :text is in "../src/test/data2.txt"; |
file key2 :text is in "../src/test/key2.txt"; |
|
variable line_in : line; |
variable line_content : string(1 to 8); |
301,7 → 301,7
DATA_RXD <= data; -- parity bit |
wait for 8.75 us; |
|
report "Koniec bajtu"; |
report "End of byte"; |
DATA_RXD <= '1'; -- stop bit |
wait for 100 us; |
end loop; |
360,7 → 360,7
DATA_RXD <= data; -- parity bit |
wait for 8.75 us; |
|
report "Koniec bajtu"; |
report "End of byte"; |
DATA_RXD <= '1'; -- stop bit |
wait for 100 us; |
end loop; |
/PureTesting/sim/rtl_sim/bin/test/key.txt
0,0 → 1,100
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
/PureTesting/sim/rtl_sim/bin/test/data.txt
0,0 → 1,80
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
11111111 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
/PureTesting/sim/rtl_sim/bin/test/key2.txt
0,0 → 1,100
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
/PureTesting/sim/rtl_sim/bin/test/data2.txt
0,0 → 1,80
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
00000000 |
|
|
|
|
|
|
|
|
1 |
PureTesting/sim/rtl_sim/bin/test
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: PureTesting/sim/rtl_sim/bin/PresentTB_isim_beh.wdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: PureTesting/sim/rtl_sim/bin/PresentTB_isim_beh.wdb
===================================================================
--- PureTesting/sim/rtl_sim/bin/PresentTB_isim_beh.wdb (nonexistent)
+++ PureTesting/sim/rtl_sim/bin/PresentTB_isim_beh.wdb (revision 8)
PureTesting/sim/rtl_sim/bin/PresentTB_isim_beh.wdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: PureTesting/sim/rtl_sim/bin/PresentCommTB_stx_beh.prj
===================================================================
--- PureTesting/sim/rtl_sim/bin/PresentCommTB_stx_beh.prj (nonexistent)
+++ PureTesting/sim/rtl_sim/bin/PresentCommTB_stx_beh.prj (revision 8)
@@ -0,0 +1,15 @@
+vhdl isim_temp "../../../rtl/vhdl/slayer.vhd"
+vhdl isim_temp "../../../rtl/vhdl/kody.vhd"
+vhdl isim_temp "../../../rtl/vhdl/Reg.vhd"
+vhdl isim_temp "../../../rtl/vhdl/PresentStateMachine.vhd"
+vhdl isim_temp "../../../rtl/vhdl/pLayer.vhd"
+vhdl isim_temp "../../../rtl/vhdl/keyupd.vhd"
+vhdl isim_temp "../../../rtl/vhdl/counter.vhd"
+vhdl isim_temp "../../../rtl/vhdl/AsyncMux.vhd"
+vhdl isim_temp "../../../rtl/vhdl/ShiftReg.vhd"
+vhdl isim_temp "../../../rtl/vhdl/RS232RefComp.vhd"
+vhdl isim_temp "../../../rtl/vhdl/PresentEnc.vhd"
+vhdl isim_temp "../../../rtl/vhdl/PresentCommSM.vhd"
+vhdl isim_temp "../../../rtl/vhdl/PresentComm.vhd"
+vhdl isim_temp "../../../bench/vhdl/txt_util.vhd"
+vhdl isim_temp "../../../bench/vhdl/PresentCommTB.vhd"
Index: PureTesting/sim/rtl_sim/bin/PresentCommTB_beh.prj
===================================================================
--- PureTesting/sim/rtl_sim/bin/PresentCommTB_beh.prj (nonexistent)
+++ PureTesting/sim/rtl_sim/bin/PresentCommTB_beh.prj (revision 8)
@@ -0,0 +1,15 @@
+vhdl work "../../../rtl/vhdl/slayer.vhd"
+vhdl work "../../../rtl/vhdl/kody.vhd"
+vhdl work "../../../rtl/vhdl/Reg.vhd"
+vhdl work "../../../rtl/vhdl/PresentStateMachine.vhd"
+vhdl work "../../../rtl/vhdl/pLayer.vhd"
+vhdl work "../../../rtl/vhdl/keyupd.vhd"
+vhdl work "../../../rtl/vhdl/counter.vhd"
+vhdl work "../../../rtl/vhdl/AsyncMux.vhd"
+vhdl work "../../../rtl/vhdl/ShiftReg.vhd"
+vhdl work "../../../rtl/vhdl/RS232RefComp.vhd"
+vhdl work "../../../rtl/vhdl/PresentEnc.vhd"
+vhdl work "../../../rtl/vhdl/PresentCommSM.vhd"
+vhdl work "../../../rtl/vhdl/PresentComm.vhd"
+vhdl work "../../../bench/vhdl/txt_util.vhd"
+vhdl work "../../../bench/vhdl/PresentCommTB.vhd"
Index: PureTesting/sim/rtl_sim/bin/sLayerTB_stx_beh.prj
===================================================================
--- PureTesting/sim/rtl_sim/bin/sLayerTB_stx_beh.prj (nonexistent)
+++ PureTesting/sim/rtl_sim/bin/sLayerTB_stx_beh.prj (revision 8)
@@ -0,0 +1,2 @@
+vhdl isim_temp "../../../rtl/vhdl/slayer.vhd"
+vhdl isim_temp "../../../bench/vhdl/sLayerTB.vhd"
Index: PureTesting/sim/rtl_sim/bin/PresentCommTB_isim_beh.wdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: PureTesting/sim/rtl_sim/bin/PresentCommTB_isim_beh.wdb
===================================================================
--- PureTesting/sim/rtl_sim/bin/PresentCommTB_isim_beh.wdb (nonexistent)
+++ PureTesting/sim/rtl_sim/bin/PresentCommTB_isim_beh.wdb (revision 8)
PureTesting/sim/rtl_sim/bin/PresentCommTB_isim_beh.wdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: PureTesting/sim/rtl_sim/bin/sLayerTB_beh.prj
===================================================================
--- PureTesting/sim/rtl_sim/bin/sLayerTB_beh.prj (nonexistent)
+++ PureTesting/sim/rtl_sim/bin/sLayerTB_beh.prj (revision 8)
@@ -0,0 +1,2 @@
+vhdl work "../../../rtl/vhdl/slayer.vhd"
+vhdl work "../../../bench/vhdl/sLayerTB.vhd"
Index: PureTesting/sim/rtl_sim/bin/keyupdTB_stx_beh.prj
===================================================================
--- PureTesting/sim/rtl_sim/bin/keyupdTB_stx_beh.prj (nonexistent)
+++ PureTesting/sim/rtl_sim/bin/keyupdTB_stx_beh.prj (revision 8)
@@ -0,0 +1,3 @@
+vhdl isim_temp "../../../rtl/vhdl/slayer.vhd"
+vhdl isim_temp "../../../rtl/vhdl/keyupd.vhd"
+vhdl isim_temp "../../../bench/vhdl/keyupdTB.vhd"
Index: PureTesting/sim/rtl_sim/bin/keyupdTB_beh.prj
===================================================================
--- PureTesting/sim/rtl_sim/bin/keyupdTB_beh.prj (nonexistent)
+++ PureTesting/sim/rtl_sim/bin/keyupdTB_beh.prj (revision 8)
@@ -0,0 +1,3 @@
+vhdl work "../../../rtl/vhdl/slayer.vhd"
+vhdl work "../../../rtl/vhdl/keyupd.vhd"
+vhdl work "../../../bench/vhdl/keyupdTB.vhd"
Index: PureTesting/sim/rtl_sim/bin/sLayerTB_isim_beh.wdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: PureTesting/sim/rtl_sim/bin/sLayerTB_isim_beh.wdb
===================================================================
--- PureTesting/sim/rtl_sim/bin/sLayerTB_isim_beh.wdb (nonexistent)
+++ PureTesting/sim/rtl_sim/bin/sLayerTB_isim_beh.wdb (revision 8)
PureTesting/sim/rtl_sim/bin/sLayerTB_isim_beh.wdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: PureTesting/sim/rtl_sim/bin/keyupdTB_isim_beh.wdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: PureTesting/sim/rtl_sim/bin/keyupdTB_isim_beh.wdb
===================================================================
--- PureTesting/sim/rtl_sim/bin/keyupdTB_isim_beh.wdb (nonexistent)
+++ PureTesting/sim/rtl_sim/bin/keyupdTB_isim_beh.wdb (revision 8)
PureTesting/sim/rtl_sim/bin/keyupdTB_isim_beh.wdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: PureTesting/sim/rtl_sim/bin/isim.cmd
===================================================================
--- PureTesting/sim/rtl_sim/bin/isim.cmd (nonexistent)
+++ PureTesting/sim/rtl_sim/bin/isim.cmd (revision 8)
@@ -0,0 +1,3 @@
+onerror {resume}
+wave add /
+run 1000 ns;
Index: PureTesting/sim/rtl_sim/bin/ShiftRegTB_stx_beh.prj
===================================================================
--- PureTesting/sim/rtl_sim/bin/ShiftRegTB_stx_beh.prj (nonexistent)
+++ PureTesting/sim/rtl_sim/bin/ShiftRegTB_stx_beh.prj (revision 8)
@@ -0,0 +1,2 @@
+vhdl isim_temp "../../../rtl/vhdl/ShiftReg.vhd"
+vhdl isim_temp "../../../bench/vhdl/ShiftRegTB.vhd"
Index: PureTesting/sim/rtl_sim/bin/ShiftRegTB_beh.prj
===================================================================
--- PureTesting/sim/rtl_sim/bin/ShiftRegTB_beh.prj (nonexistent)
+++ PureTesting/sim/rtl_sim/bin/ShiftRegTB_beh.prj (revision 8)
@@ -0,0 +1,2 @@
+vhdl work "../../../rtl/vhdl/ShiftReg.vhd"
+vhdl work "../../../bench/vhdl/ShiftRegTB.vhd"
Index: PureTesting/sim/rtl_sim/bin/ShiftRegTB_isim_beh.wdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: PureTesting/sim/rtl_sim/bin/ShiftRegTB_isim_beh.wdb
===================================================================
--- PureTesting/sim/rtl_sim/bin/ShiftRegTB_isim_beh.wdb (nonexistent)
+++ PureTesting/sim/rtl_sim/bin/ShiftRegTB_isim_beh.wdb (revision 8)
PureTesting/sim/rtl_sim/bin/ShiftRegTB_isim_beh.wdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: PureTesting/sim/rtl_sim/bin/PresentTB_stx_beh.prj
===================================================================
--- PureTesting/sim/rtl_sim/bin/PresentTB_stx_beh.prj (nonexistent)
+++ PureTesting/sim/rtl_sim/bin/PresentTB_stx_beh.prj (revision 8)
@@ -0,0 +1,10 @@
+vhdl isim_temp "../../../rtl/vhdl/slayer.vhd"
+vhdl isim_temp "../../../rtl/vhdl/kody.vhd"
+vhdl isim_temp "../../../rtl/vhdl/Reg.vhd"
+vhdl isim_temp "../../../rtl/vhdl/PresentStateMachine.vhd"
+vhdl isim_temp "../../../rtl/vhdl/pLayer.vhd"
+vhdl isim_temp "../../../rtl/vhdl/keyupd.vhd"
+vhdl isim_temp "../../../rtl/vhdl/counter.vhd"
+vhdl isim_temp "../../../rtl/vhdl/AsyncMux.vhd"
+vhdl isim_temp "../../../rtl/vhdl/PresentEnc.vhd"
+vhdl isim_temp "../../../bench/vhdl/PresentTB.vhd"
Index: PureTesting/sim/rtl_sim/bin/Makefile
===================================================================
--- PureTesting/sim/rtl_sim/bin/Makefile (nonexistent)
+++ PureTesting/sim/rtl_sim/bin/Makefile (revision 8)
@@ -0,0 +1,59 @@
+PROJECT=present-pure-testing
+
+RM=rm -rf
+
+PLATFORM=xc3s500e-fg320-5
+
+XILINX_DIR="D:/Programy/Xilinx/14.2/ISE_DS/ISE/bin/nt64/"
+FUSE=$(XILINX_DIR)"fuse.exe"
+VHPCOMP=$(XILINX_DIR)"vhpcomp.exe"
+
+clean:
+ $(RM) ./isim
+ $(RM) ./isim.wdb
+ $(RM) *.log
+ $(RM) *.xmsgs
+ $(RM) ./fuseRelaunch.cmd
+ $(RM) *.exe
+
+exports:
+ export DISPLAY=:0
+ export XILINX=D:/Programy/Xilinx/14.2/ISE_DS/ISE
+ export SYSOP=nt64
+ export PATH=${XILINX}/bin/${SYSOP}
+ export LD_LIBRARY_PATH=${XILINX}/lib/${SYSOP}
+
+PresentCommTB:
+ $(VHPCOMP) -work isim_temp -intstyle ise -prj ./PresentCommTB_stx_beh.prj
+ $(FUSE) -intstyle ise -incremental -o PresentCommTB_isim_beh.exe -prj ./PresentCommTB_beh.prj work.PresentCommTB
+
+run_PresentCommTB: exports PresentCommTB
+ "./PresentCommTB_isim_beh.exe" -intstyle ise -gui -tclbatch isim.cmd -wdb "PresentCommTB_isim_beh.wdb"
+
+PresentTB:
+ $(VHPCOMP) -work isim_temp -intstyle ise -prj ./PresentTB_stx_beh.prj
+ $(FUSE) -intstyle ise -incremental -o PresentTB_isim_beh.exe -prj ./PresentTB_beh.prj work.PresentTB
+
+run_PresentTB: exports PresentTB
+ "./PresentTB_isim_beh.exe" -intstyle ise -gui -tclbatch isim.cmd -wdb "PresentTB_isim_beh.wdb"
+
+keyupdTB:
+ $(VHPCOMP) -work isim_temp -intstyle ise -prj ./keyupdTB_stx_beh.prj
+ $(FUSE) -intstyle ise -incremental -o keyupdTB_isim_beh.exe -prj ./keyupdTB_beh.prj work.keyupdTB
+
+run_keyupdTB: exports keyupdTB
+ "./keyupdTB_isim_beh.exe" -intstyle ise -gui -tclbatch isim.cmd -wdb "keyupdTB_isim_beh.wdb"
+
+ShiftRegTB:
+ $(VHPCOMP) -work isim_temp -intstyle ise -prj ./ShiftRegTB_stx_beh.prj
+ $(FUSE) -intstyle ise -incremental -o ShiftRegTB_isim_beh.exe -prj ./ShiftRegTB_beh.prj work.ShiftRegTB
+
+run_ShiftRegTB: exports ShiftRegTB
+ "./ShiftRegTB_isim_beh.exe" -intstyle ise -gui -tclbatch isim.cmd -wdb "ShiftRegTB_isim_beh.wdb"
+
+sLayerTB:
+ $(VHPCOMP) -work isim_temp -intstyle ise -prj ./sLayerTB_stx_beh.prj
+ $(FUSE) -intstyle ise -incremental -o sLayerTB_isim_beh.exe -prj ./sLayerTB_beh.prj work.sLayerTB
+
+run_sLayerTB: exports sLayerTB
+ "./sLayerTB_isim_beh.exe" -intstyle ise -gui -tclbatch isim.cmd -wdb "sLayerTB_isim_beh.wdb"
\ No newline at end of file
Index: PureTesting/sim/rtl_sim/bin/PresentTB_beh.prj
===================================================================
--- PureTesting/sim/rtl_sim/bin/PresentTB_beh.prj (nonexistent)
+++ PureTesting/sim/rtl_sim/bin/PresentTB_beh.prj (revision 8)
@@ -0,0 +1,10 @@
+vhdl work "../../../rtl/vhdl/slayer.vhd"
+vhdl work "../../../rtl/vhdl/kody.vhd"
+vhdl work "../../../rtl/vhdl/Reg.vhd"
+vhdl work "../../../rtl/vhdl/PresentStateMachine.vhd"
+vhdl work "../../../rtl/vhdl/pLayer.vhd"
+vhdl work "../../../rtl/vhdl/keyupd.vhd"
+vhdl work "../../../rtl/vhdl/counter.vhd"
+vhdl work "../../../rtl/vhdl/AsyncMux.vhd"
+vhdl work "../../../rtl/vhdl/PresentEnc.vhd"
+vhdl work "../../../bench/vhdl/PresentTB.vhd"
Index: PureTesting/sim/rtl_sim/bin
===================================================================
--- PureTesting/sim/rtl_sim/bin (nonexistent)
+++ PureTesting/sim/rtl_sim/bin (revision 8)
PureTesting/sim/rtl_sim/bin
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: PureTesting/sim/rtl_sim
===================================================================
--- PureTesting/sim/rtl_sim (nonexistent)
+++ PureTesting/sim/rtl_sim (revision 8)
PureTesting/sim/rtl_sim
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: PureTesting/syn/XC3ES500/log
===================================================================
--- PureTesting/syn/XC3ES500/log (nonexistent)
+++ PureTesting/syn/XC3ES500/log (revision 8)
PureTesting/syn/XC3ES500/log
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: PureTesting/syn/XC3ES500/PresentComm.ut
===================================================================
--- PureTesting/syn/XC3ES500/PresentComm.ut (nonexistent)
+++ PureTesting/syn/XC3ES500/PresentComm.ut (revision 8)
@@ -0,0 +1,22 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:1
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g DCMShutdown:Disable
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:Yes
+-g DriveDone:No
Index: PureTesting/syn/XC3ES500/PresentComm.prj
===================================================================
--- PureTesting/syn/XC3ES500/PresentComm.prj (nonexistent)
+++ PureTesting/syn/XC3ES500/PresentComm.prj (revision 8)
@@ -0,0 +1,13 @@
+vhdl work "../../rtl/vhdl/slayer.vhd"
+vhdl work "../../rtl/vhdl/kody.vhd"
+vhdl work "../../rtl/vhdl/Reg.vhd"
+vhdl work "../../rtl/vhdl/PresentStateMachine.vhd"
+vhdl work "../../rtl/vhdl/pLayer.vhd"
+vhdl work "../../rtl/vhdl/keyupd.vhd"
+vhdl work "../../rtl/vhdl/counter.vhd"
+vhdl work "../../rtl/vhdl/AsyncMux.vhd"
+vhdl work "../../rtl/vhdl/ShiftReg.vhd"
+vhdl work "../../rtl/vhdl/RS232RefComp.vhd"
+vhdl work "../../rtl/vhdl/PresentEnc.vhd"
+vhdl work "../../rtl/vhdl/PresentCommSM.vhd"
+vhdl work "../../rtl/vhdl/PresentComm.vhd"
Index: PureTesting/syn/XC3ES500/out
===================================================================
--- PureTesting/syn/XC3ES500/out (nonexistent)
+++ PureTesting/syn/XC3ES500/out (revision 8)
PureTesting/syn/XC3ES500/out
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: PureTesting/syn/XC3ES500/PresentComm.xst
===================================================================
--- PureTesting/syn/XC3ES500/PresentComm.xst (nonexistent)
+++ PureTesting/syn/XC3ES500/PresentComm.xst (revision 8)
@@ -0,0 +1,56 @@
+set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn PresentComm.prj
+-ifmt mixed
+-ofn PresentComm
+-ofmt NGC
+-p xc3s500e-5-fg320
+-top PresentComm
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-keep_hierarchy Soft
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing YES
+-async_to_sync NO
+-mult_style Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
Index: PureTesting/syn/XC3ES500/Makefile
===================================================================
--- PureTesting/syn/XC3ES500/Makefile (nonexistent)
+++ PureTesting/syn/XC3ES500/Makefile (revision 8)
@@ -0,0 +1,52 @@
+PROJECT=present-pure-testing
+
+RM=rm -rf
+
+PLATFORM=xc3s500e-fg320-5
+UCF="../../rtl/vhdl/PresentCommImpl.ucf"
+
+XILINX_DIR="D:/Programy/Xilinx/14.2/ISE_DS/ISE/bin/nt64/"
+XST_DIR=$(XILINX_DIR)"xst.exe"
+NGDBUILD_DIR=$(XILINX_DIR)"ngdbuild.exe"
+MAP=$(XILINX_DIR)"map.exe"
+PAR=$(XILINX_DIR)"par.exe"
+TRCE=$(XILINX_DIR)"trce.exe"
+BITGEN=$(XILINX_DIR)"bitgen.exe"
+
+clean: clean_postgen
+ $(RM) "./out/"*.*
+ $(RM) "./log/"*.*
+
+clean_postgen:
+ $(RM) "./_xmsgs"
+ $(RM) "./_ngo"
+ $(RM) "./xlnx_auto_0_xdb"
+ $(RM) "./xst"
+ $(RM) *_vhdl.prj *.bgn *.bld *.csv *.drc *.lso *.map *.mrp *.ncd *.ngc *.ngd *.ngm *.ngr *.pad *.par *.pcf *.ptwx *.syr *.twr *.twx *.unroutes *.xpi *.xwbt
+
+synthesize: clean
+ mkdir "./xst"
+ mkdir "./xst/projnav.tmp"
+ $(XST_DIR) -intstyle ise -ifn "./PresentComm.xst" -ofn "./PresentComm.syr"
+
+translate: synthesize
+ $(NGDBUILD_DIR) -intstyle ise -dd _ngo -nt timestamp -uc $(UCF) -p $(PLATFORM) "PresentComm.ngc" PresentComm.ngd
+
+map: translate
+ $(MAP) -intstyle ise -p $(PLATFORM) -cm area -ir off -pr off -c 100 -o PresentComm_map.ncd PresentComm.ngd PresentComm.pcf
+
+par: map
+ $(PAR) -w -intstyle ise -pl std -rl std -t 1 PresentComm_map.ncd PresentComm.ncd PresentComm.pcf
+
+trce: par
+ $(TRCE) -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml PresentComm.twx PresentComm.ncd -o PresentComm.twr PresentComm.pcf -ucf $(UCF)
+
+bitgen: par
+ $(BITGEN) -intstyle ise -f PresentComm.ut PresentComm.ncd
+
+postgen:
+ mv *.bit ./out
+ mv *.xrpt ./log
+ mv *.txt ./log
+ mv *.xml ./log
+ mv *.html ./log
\ No newline at end of file
Index: PureTesting/uwagi.txt
===================================================================
--- PureTesting/uwagi.txt (nonexistent)
+++ PureTesting/uwagi.txt (revision 8)
@@ -0,0 +1,5 @@
+Problem z EXPORT zmiennych (SET),
+Instalacja cygwin/make.
+zamiana bibliotek w katalogu xilinx.
+
+Skrypty sima w cygwin, a otwieranie symulacji w CMD
\ No newline at end of file
Index: Pure/sim/rtl_sim/bin/keyupdTB_beh.prj
===================================================================
--- Pure/sim/rtl_sim/bin/keyupdTB_beh.prj (nonexistent)
+++ Pure/sim/rtl_sim/bin/keyupdTB_beh.prj (revision 8)
@@ -0,0 +1,3 @@
+vhdl work "../../../rtl/vhdl/slayer.vhd"
+vhdl work "../../../rtl/vhdl/keyupd.vhd"
+vhdl work "../../../bench/vhdl/keyupdTB.vhd"
Index: Pure/sim/rtl_sim/bin/sLayerTB_isim_beh.wdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: Pure/sim/rtl_sim/bin/sLayerTB_isim_beh.wdb
===================================================================
--- Pure/sim/rtl_sim/bin/sLayerTB_isim_beh.wdb (nonexistent)
+++ Pure/sim/rtl_sim/bin/sLayerTB_isim_beh.wdb (revision 8)
Pure/sim/rtl_sim/bin/sLayerTB_isim_beh.wdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: Pure/sim/rtl_sim/bin/PresentTB_isim_beh.wdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: Pure/sim/rtl_sim/bin/PresentTB_isim_beh.wdb
===================================================================
--- Pure/sim/rtl_sim/bin/PresentTB_isim_beh.wdb (nonexistent)
+++ Pure/sim/rtl_sim/bin/PresentTB_isim_beh.wdb (revision 8)
Pure/sim/rtl_sim/bin/PresentTB_isim_beh.wdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: Pure/sim/rtl_sim/bin/keyupdTB_isim_beh.wdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: Pure/sim/rtl_sim/bin/keyupdTB_isim_beh.wdb
===================================================================
--- Pure/sim/rtl_sim/bin/keyupdTB_isim_beh.wdb (nonexistent)
+++ Pure/sim/rtl_sim/bin/keyupdTB_isim_beh.wdb (revision 8)
Pure/sim/rtl_sim/bin/keyupdTB_isim_beh.wdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: Pure/sim/rtl_sim/bin/isim.cmd
===================================================================
--- Pure/sim/rtl_sim/bin/isim.cmd (nonexistent)
+++ Pure/sim/rtl_sim/bin/isim.cmd (revision 8)
@@ -0,0 +1,3 @@
+onerror {resume}
+wave add /
+run 1000 ns;
Index: Pure/sim/rtl_sim/bin/sLayerTB_stx_beh.prj
===================================================================
--- Pure/sim/rtl_sim/bin/sLayerTB_stx_beh.prj (nonexistent)
+++ Pure/sim/rtl_sim/bin/sLayerTB_stx_beh.prj (revision 8)
@@ -0,0 +1,2 @@
+vhdl isim_temp "../../../rtl/vhdl/slayer.vhd"
+vhdl isim_temp "../../../bench/vhdl/sLayerTB.vhd"
Index: Pure/sim/rtl_sim/bin/PresentTB_stx_beh.prj
===================================================================
--- Pure/sim/rtl_sim/bin/PresentTB_stx_beh.prj (nonexistent)
+++ Pure/sim/rtl_sim/bin/PresentTB_stx_beh.prj (revision 8)
@@ -0,0 +1,10 @@
+vhdl isim_temp "../../../rtl/vhdl/slayer.vhd"
+vhdl isim_temp "../../../rtl/vhdl/kody.vhd"
+vhdl isim_temp "../../../rtl/vhdl/Reg.vhd"
+vhdl isim_temp "../../../rtl/vhdl/PresentStateMachine.vhd"
+vhdl isim_temp "../../../rtl/vhdl/pLayer.vhd"
+vhdl isim_temp "../../../rtl/vhdl/keyupd.vhd"
+vhdl isim_temp "../../../rtl/vhdl/counter.vhd"
+vhdl isim_temp "../../../rtl/vhdl/AsyncMux.vhd"
+vhdl isim_temp "../../../rtl/vhdl/PresentEnc.vhd"
+vhdl isim_temp "../../../bench/vhdl/PresentTB.vhd"
Index: Pure/sim/rtl_sim/bin/sLayerTB_beh.prj
===================================================================
--- Pure/sim/rtl_sim/bin/sLayerTB_beh.prj (nonexistent)
+++ Pure/sim/rtl_sim/bin/sLayerTB_beh.prj (revision 8)
@@ -0,0 +1,2 @@
+vhdl work "../../../rtl/vhdl/slayer.vhd"
+vhdl work "../../../bench/vhdl/sLayerTB.vhd"
Index: Pure/sim/rtl_sim/bin/keyupdTB_stx_beh.prj
===================================================================
--- Pure/sim/rtl_sim/bin/keyupdTB_stx_beh.prj (nonexistent)
+++ Pure/sim/rtl_sim/bin/keyupdTB_stx_beh.prj (revision 8)
@@ -0,0 +1,3 @@
+vhdl isim_temp "../../../rtl/vhdl/slayer.vhd"
+vhdl isim_temp "../../../rtl/vhdl/keyupd.vhd"
+vhdl isim_temp "../../../bench/vhdl/keyupdTB.vhd"
Index: Pure/sim/rtl_sim/bin/Makefile
===================================================================
--- Pure/sim/rtl_sim/bin/Makefile (nonexistent)
+++ Pure/sim/rtl_sim/bin/Makefile (revision 8)
@@ -0,0 +1,45 @@
+PROJECT=present-pure
+
+RM=rm -rf
+
+PLATFORM=xc3s500e-fg320-5
+
+XILINX_DIR="D:/Programy/Xilinx/14.2/ISE_DS/ISE/bin/nt64/"
+FUSE=$(XILINX_DIR)"fuse.exe"
+VHPCOMP=$(XILINX_DIR)"vhpcomp.exe"
+
+clean:
+ $(RM) ./isim
+ $(RM) ./isim.wdb
+ $(RM) *.log
+ $(RM) *.xmsgs
+ $(RM) ./fuseRelaunch.cmd
+ $(RM) *.exe
+
+exports:
+ export DISPLAY=:0
+ export XILINX=D:/Programy/Xilinx/14.2/ISE_DS/ISE
+ export SYSOP=nt64
+ export PATH=${XILINX}/bin/${SYSOP}
+ export LD_LIBRARY_PATH=${XILINX}/lib/${SYSOP}
+
+PresentTB:
+ $(VHPCOMP) -work isim_temp -intstyle ise -prj ./PresentTB_stx_beh.prj
+ $(FUSE) -intstyle ise -incremental -o PresentTB_isim_beh.exe -prj ./PresentTB_beh.prj work.PresentTB
+
+run_PresentTB: exports PresentTB
+ "./PresentTB_isim_beh.exe" -intstyle ise -gui -tclbatch isim.cmd -wdb "PresentTB_isim_beh.wdb"
+
+keyupdTB:
+ $(VHPCOMP) -work isim_temp -intstyle ise -prj ./keyupdTB_stx_beh.prj
+ $(FUSE) -intstyle ise -incremental -o keyupdTB_isim_beh.exe -prj ./keyupdTB_beh.prj work.keyupdTB
+
+run_keyupdTB: exports keyupdTB
+ "./keyupdTB_isim_beh.exe" -intstyle ise -gui -tclbatch isim.cmd -wdb "keyupdTB_isim_beh.wdb"
+
+sLayerTB:
+ $(VHPCOMP) -work isim_temp -intstyle ise -prj ./sLayerTB_stx_beh.prj
+ $(FUSE) -intstyle ise -incremental -o sLayerTB_isim_beh.exe -prj ./sLayerTB_beh.prj work.sLayerTB
+
+run_sLayerTB: exports sLayerTB
+ "./sLayerTB_isim_beh.exe" -intstyle ise -gui -tclbatch isim.cmd -wdb "sLayerTB_isim_beh.wdb"
\ No newline at end of file
Index: Pure/sim/rtl_sim/bin/PresentTB_beh.prj
===================================================================
--- Pure/sim/rtl_sim/bin/PresentTB_beh.prj (nonexistent)
+++ Pure/sim/rtl_sim/bin/PresentTB_beh.prj (revision 8)
@@ -0,0 +1,10 @@
+vhdl work "../../../rtl/vhdl/slayer.vhd"
+vhdl work "../../../rtl/vhdl/kody.vhd"
+vhdl work "../../../rtl/vhdl/Reg.vhd"
+vhdl work "../../../rtl/vhdl/PresentStateMachine.vhd"
+vhdl work "../../../rtl/vhdl/pLayer.vhd"
+vhdl work "../../../rtl/vhdl/keyupd.vhd"
+vhdl work "../../../rtl/vhdl/counter.vhd"
+vhdl work "../../../rtl/vhdl/AsyncMux.vhd"
+vhdl work "../../../rtl/vhdl/PresentEnc.vhd"
+vhdl work "../../../bench/vhdl/PresentTB.vhd"
Index: Pure/sim/rtl_sim/bin
===================================================================
--- Pure/sim/rtl_sim/bin (nonexistent)
+++ Pure/sim/rtl_sim/bin (revision 8)
Pure/sim/rtl_sim/bin
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: Pure/sim/rtl_sim
===================================================================
--- Pure/sim/rtl_sim (nonexistent)
+++ Pure/sim/rtl_sim (revision 8)
Pure/sim/rtl_sim
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: Pure/syn/XC3ES500/PresentEnc.prj
===================================================================
--- Pure/syn/XC3ES500/PresentEnc.prj (nonexistent)
+++ Pure/syn/XC3ES500/PresentEnc.prj (revision 8)
@@ -0,0 +1,9 @@
+vhdl work "../../rtl/vhdl/slayer.vhd"
+vhdl work "../../rtl/vhdl/kody.vhd"
+vhdl work "../../rtl/vhdl/Reg.vhd"
+vhdl work "../../rtl/vhdl/PresentStateMachine.vhd"
+vhdl work "../../rtl/vhdl/pLayer.vhd"
+vhdl work "../../rtl/vhdl/keyupd.vhd"
+vhdl work "../../rtl/vhdl/counter.vhd"
+vhdl work "../../rtl/vhdl/AsyncMux.vhd"
+vhdl work "../../rtl/vhdl/PresentEnc.vhd"
Index: Pure/syn/XC3ES500/log
===================================================================
--- Pure/syn/XC3ES500/log (nonexistent)
+++ Pure/syn/XC3ES500/log (revision 8)
Pure/syn/XC3ES500/log
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: Pure/syn/XC3ES500/PresentEnc.xst
===================================================================
--- Pure/syn/XC3ES500/PresentEnc.xst (nonexistent)
+++ Pure/syn/XC3ES500/PresentEnc.xst (revision 8)
@@ -0,0 +1,56 @@
+set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn PresentEnc.prj
+-ifmt mixed
+-ofn PresentEnc
+-ofmt NGC
+-p xc3s500e-5-fg320
+-top PresentEnc
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-keep_hierarchy Soft
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing YES
+-async_to_sync NO
+-mult_style Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
Index: Pure/syn/XC3ES500/out
===================================================================
--- Pure/syn/XC3ES500/out (nonexistent)
+++ Pure/syn/XC3ES500/out (revision 8)
Pure/syn/XC3ES500/out
Property changes :
Added: bugtraq:number
## -0,0 +1 ##
+true
\ No newline at end of property
Index: Pure/syn/XC3ES500/PresentEnc.ut
===================================================================
--- Pure/syn/XC3ES500/PresentEnc.ut (nonexistent)
+++ Pure/syn/XC3ES500/PresentEnc.ut (revision 8)
@@ -0,0 +1,22 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:1
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g DCMShutdown:Disable
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:Yes
+-g DriveDone:No
Index: Pure/syn/XC3ES500/Makefile
===================================================================
--- Pure/syn/XC3ES500/Makefile (nonexistent)
+++ Pure/syn/XC3ES500/Makefile (revision 8)
@@ -0,0 +1,51 @@
+PROJECT=present-pure
+
+RM=rm -rf
+
+PLATFORM=xc3s500e-fg320-5
+
+XILINX_DIR="D:/Programy/Xilinx/14.2/ISE_DS/ISE/bin/nt64/"
+XST_DIR=$(XILINX_DIR)"xst.exe"
+NGDBUILD_DIR=$(XILINX_DIR)"ngdbuild.exe"
+MAP=$(XILINX_DIR)"map.exe"
+PAR=$(XILINX_DIR)"par.exe"
+TRCE=$(XILINX_DIR)"trce.exe"
+BITGEN=$(XILINX_DIR)"bitgen.exe"
+
+clean: clean_postgen
+ $(RM) "./out/"*.*
+ $(RM) "./log/"*.*
+
+clean_postgen:
+ $(RM) "./_xmsgs"
+ $(RM) "./_ngo"
+ $(RM) "./xlnx_auto_0_xdb"
+ $(RM) "./xst"
+ $(RM) *_vhdl.prj *.bgn *.bld *.csv *.drc *.lso *.map *.mrp *.ncd *.ngc *.ngd *.ngm *.ngr *.pad *.par *.pcf *.ptwx *.syr *.twr *.twx *.unroutes *.xpi *.xwbt
+
+synthesize: clean
+ mkdir "./xst"
+ mkdir "./xst/projnav.tmp"
+ $(XST_DIR) -intstyle ise -ifn "./PresentEnc.xst" -ofn "./PresentEnc.syr"
+
+translate: synthesize
+ $(NGDBUILD_DIR) -intstyle ise -dd _ngo -nt timestamp -i -p $(PLATFORM) "PresentEnc.ngc" PresentEnc.ngd
+
+map: translate
+ $(MAP) -intstyle ise -p $(PLATFORM) -cm area -ir off -pr off -c 100 -o PresentEnc_map.ncd PresentEnc.ngd PresentEnc.pcf
+
+par: map
+ $(PAR) -w -intstyle ise -ol high -t 1 PresentEnc_map.ncd PresentEnc.ncd PresentEnc.pcf
+
+trce: par
+ $(TRCE) -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml PresentEnc.twx PresentEnc.ncd -o PresentEnc.twr PresentEnc.pcf
+
+bitgen: par
+ $(BITGEN) -intstyle ise -f PresentEnc.ut PresentEnc.ncd
+
+postgen:
+ mv *.bit ./out
+ mv *.xrpt ./log
+ mv *.txt ./log
+ mv *.xml ./log
+ mv *.html ./log
\ No newline at end of file