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/rtl/hexmap.v
0,0 → 1,82
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: hexmap.v |
// |
// Project: A Real--time Clock Core |
// |
// Purpose: Converts a 4'bit hexadecimal value to the seven bits needed |
// by a seven segment display, specifying which bits are on and |
// which are off. |
// |
// The display I am working with, however, requires a separate |
// controller. This file only provides part of the input for that |
// controller. That controller deals with turning on each part |
// of the display in a rotating fashion, since the hardware I have |
// cannot display more than one character at a time. So, |
// buyer beware--this is not a complete seven segment display |
// solution. |
// |
// |
// The outputs of this routine are numbered as follows: |
// o_map[7] turns on the bar at the top of the display |
// o_map[6] turns on the top of the '1' |
// o_map[5] turns on the bottom of a '1' |
// o_map[4] turns on the bar at the bottom of the display |
// o_map[3] turns on the vertical bar at the bottom left |
// o_map[2] turns on the vertical bar at the top left, and |
// o_map[1] turns on the bar in the middle of the display. |
// The dash if you will. |
// Bit zero, from elsewhere, would be the decimal point. |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Tecnology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
module hexmap(i_clk, i_hex, o_map); |
input i_clk; |
input [3:0] i_hex; |
output reg [7:1] o_map; |
|
always @(posedge i_clk) |
case(i_hex) |
4'h0: o_map <= { 7'b1111110 }; |
4'h1: o_map <= { 7'b0110000 }; |
4'h2: o_map <= { 7'b1101101 }; |
4'h3: o_map <= { 7'b1111001 }; |
4'h4: o_map <= { 7'b0110011 }; |
4'h5: o_map <= { 7'b1011011 }; |
4'h6: o_map <= { 7'b1011111 }; |
4'h7: o_map <= { 7'b1110000 }; |
4'h8: o_map <= { 7'b1111111 }; |
4'h9: o_map <= { 7'b1111011 }; |
4'ha: o_map <= { 7'b1110111 }; |
4'hb: o_map <= { 7'b0011111 }; // b |
4'hc: o_map <= { 7'b1001110 }; |
4'hd: o_map <= { 7'b0111101 }; // d |
4'he: o_map <= { 7'b1001111 }; |
4'hf: o_map <= { 7'b1000111 }; |
endcase |
endmodule |
/rtl/rtcclock.v
0,0 → 1,468
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: rtcclock.v |
// |
// Project: A Wishbone Controlled Real--time Clock Core |
// |
// Purpose: Implement a real time clock, including alarm, count--down |
// timer, stopwatch, variable time frequency, and more. |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Tecnology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
module rtcclock(i_clk, |
// Wishbone interface |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, |
// o_wb_ack, o_wb_stb, o_wb_data, // no reads here |
// // Button inputs |
// i_btn, |
// Output registers |
o_data, // multiplexed based upon i_wb_addr |
// Output controls |
o_sseg, o_led, o_interrupt, |
// Time setting hack(s) |
i_hack); |
input i_clk; |
input i_wb_cyc, i_wb_stb, i_wb_we; |
input [2:0] i_wb_addr; |
input [31:0] i_wb_data; |
// input i_btn; |
output reg [31:0] o_data; |
output reg [31:0] o_sseg; |
output wire [15:0] o_led; |
output wire o_interrupt; |
input i_hack; |
|
reg [31:0] clock, stopwatch, ckspeed; |
reg [17:0] timer; |
|
wire ck_sel, tm_sel, sw_sel, sp_sel, al_sel; |
assign ck_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b000)); |
assign tm_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b001)); |
assign sw_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b010)); |
assign al_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b011)); |
assign sp_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b100)); |
|
reg [39:0] ck_counter; |
reg ck_carry; |
always @(posedge i_clk) |
{ ck_carry, ck_counter } <= ck_counter + { 8'h00, ckspeed }; |
|
wire ck_pps; |
reg ck_prepps, ck_ppm, ck_pph, ck_ppd; |
reg [7:0] ck_sub; |
initial clock = 32'h00000000; |
assign ck_pps = (ck_carry)&&(ck_prepps); |
always @(posedge i_clk) |
begin |
if (ck_carry) |
ck_sub <= ck_sub + 1; |
ck_prepps <= (ck_sub == 8'hff); |
|
if (ck_pps) |
begin // advance the seconds |
if (clock[3:0] >= 4'h9) |
clock[3:0] <= 4'h0; |
else |
clock[3:0] <= clock[3:0] + 4'h1; |
if (clock[7:0] >= 8'h59) |
clock[7:4] <= 4'h0; |
else if (clock[3:0] >= 4'h9) |
clock[7:4] <= clock[7:4] + 4'h1; |
end |
ck_ppm <= (clock[7:0] == 8'h59); |
|
if ((ck_pps)&&(ck_ppm)) |
begin // advance the minutes |
if (clock[11:8] >= 4'h9) |
clock[11:8] <= 4'h0; |
else |
clock[11:8] <= clock[11:8] + 4'h1; |
if (clock[15:8] >= 8'h59) |
clock[15:12] <= 4'h0; |
else if (clock[11:8] >= 4'h9) |
clock[15:12] <= clock[15:12] + 4'h1; |
end |
ck_pph <= (clock[15:0] == 16'h5959); |
|
if ((ck_pps)&&(ck_pph)) |
begin // advance the hours |
if (clock[21:16] >= 6'h23) |
begin |
clock[19:16] <= 4'h0; |
clock[21:20] <= 2'h0; |
end else if (clock[19:16] >= 4'h9) |
begin |
clock[19:16] <= 4'h0; |
clock[21:20] <= clock[21:20] + 2'h1; |
end else begin |
clock[19:16] <= clock[19:16] + 4'h1; |
end |
end |
// ppd <= (clock{15:8] == 8'h59); |
|
if ((ck_sel)&&(i_wb_we)) |
begin |
if (8'hff != i_wb_data[7:0]) |
begin |
clock[7:0] <= i_wb_data[7:0]; |
ck_ppm <= (i_wb_data[7:0] == 8'h59); |
end |
if (8'hff != i_wb_data[15:8]) |
begin |
clock[15:8] <= i_wb_data[15:8]; |
ck_pph <= (i_wb_data[15:8] == 8'h59); |
end |
if (6'h3f != i_wb_data[21:16]) |
clock[21:16] <= i_wb_data[21:16]; |
clock[31:22] <= i_wb_data[31:22]; |
if (8'h00 == i_wb_data[7:0]) |
ck_sub <= 8'h00; |
end |
end |
|
// Clock updates take several clocks, so let's make sure we |
// are only looking at a valid clock value before testing it. |
reg [21:0] ck_last_clock; |
always @(posedge i_clk) |
ck_last_clock <= clock[21:0]; |
|
|
reg tm_pps, tm_ppm, tm_int; |
wire tm_stopped, tm_running, tm_alarm; |
assign tm_stopped = ~timer[24]; |
assign tm_running = timer[24]; |
assign tm_alarm = timer[25]; |
reg [23:0] tm_start; |
reg [7:0] tm_sub; |
initial tm_start = 16'h00; |
initial timer = 18'h00; |
initial tm_int = 1'b0; |
initial tm_pps = 1'b0; |
always @(posedge i_clk) |
begin |
if (ck_carry) |
begin |
tm_sub <= tm_sub + 1; |
tm_pps <= (tm_sub == 8'hff); |
end else |
tm_pps <= 1'b0; |
|
if ((~tm_alarm)&&(tm_running)&&(tm_pps)) |
begin // If we are running ... |
timer[25] <= 1'b0; |
if (timer[23:0] == 24'h00) |
timer[25] <= 1'b1; |
else if (timer[3:0] != 4'h0) |
timer[3:0] <= timer[3:0]-4'h1; |
else begin // last digit is a zero |
timer[3:0] <= 4'h9; |
if (timer[7:4] != 4'h0) |
timer[7:4] <= timer[7:4]-4'h1; |
else begin // last two digits are zero |
timer[7:4] <= 4'h5; |
if (timer[11:8] != 4'h0) |
timer[11:8] <= timer[11:8]-4'h1; |
else begin // last three digits are zero |
timer[11:8] <= 4'h9; |
if (timer[15:12] != 4'h0) |
timer[15:12] <= timer[15:12]-4'h1; |
else begin |
timer[15:12] <= 4'h5; |
if (timer[19:16] != 4'h0) |
timer[19:16] <= timer[19:16]-4'h1; |
else begin |
// |
timer[19:16] <= 4'h9; |
timer[23:20] <= timer[23:20]-4'h1; |
end |
end |
end |
end |
end |
end |
|
if((~tm_alarm)&&(tm_running)) |
begin |
timer[25] <= (timer[23:0] == 24'h00); |
tm_int <= (timer[23:0] == 24'h00); |
end else tm_int <= 1'b0; |
if (tm_alarm) |
timer[24] <= 1'b0; |
|
if ((tm_sel)&&(i_wb_we)&&(tm_running)) // Writes while running |
// Only allowed to stop the timer, nothing more |
timer[24] <= i_wb_data[24]; |
else if ((tm_sel)&&(i_wb_we)&&(tm_stopped)) // Writes while off |
begin |
timer[24] <= i_wb_data[24]; |
if ((timer[24])||(i_wb_data[24])) |
timer[25] <= 1'b0; |
if (i_wb_data[23:0] != 24'h0000) |
begin |
timer[23:0] <= i_wb_data[23:0]; |
tm_start <= i_wb_data[23:0]; |
tm_sub <= 8'h00; |
end else if (timer[23:0] == 24'h00) |
begin // Resetting timer to last valid timer start val |
timer[23:0] <= tm_start; |
tm_sub <= 8'h00; |
end |
// Any write clears the alarm |
timer[25] <= 1'b0; |
end |
end |
|
// |
// Stopwatch functionality |
// |
// Setting bit '0' starts the stop watch, clearing it stops it. |
// Writing to the register with bit '1' high will clear the stopwatch, |
// and return it to zero provided that the stopwatch is stopped either |
// before or after the write. Hence, writing a '2' to the device |
// will always stop and clear it, whereas writing a '3' to the device |
// will only clear it if it was already stopped. |
reg sw_pps, sw_ppm, sw_pph; |
reg [7:0] sw_sub; |
wire sw_running; |
assign sw_running = stopwatch[0]; |
initial stopwatch = 32'h00001; |
always @(posedge i_clk) |
begin |
sw_pps <= 1'b0; |
if (sw_running) |
begin |
if (ck_carry) |
begin |
sw_sub <= sw_sub + 1; |
sw_pps <= (sw_sub == 8'hff); |
end |
end |
|
stopwatch[7:1] <= sw_sub[7:1]; |
|
if (sw_pps) |
begin // Second hand |
if (stopwatch[11:8] >= 4'h9) |
stopwatch[11:8] <= 4'h0; |
else |
stopwatch[11:8] <= stopwatch[11:8] + 4'h1; |
|
if (stopwatch[15:8] >= 8'h59) |
stopwatch[15:12] <= 4'h0; |
else if (stopwatch[11:8] >= 4'h9) |
stopwatch[15:12] <= stopwatch[15:12] + 4'h1; |
sw_ppm <= (stopwatch[15:8] == 8'h59); |
end else sw_ppm <= 1'b0; |
|
if (sw_ppm) |
begin // Minutes |
if (stopwatch[19:16] >= 4'h9) |
stopwatch[19:16] <= 4'h0; |
else |
stopwatch[19:16] <= stopwatch[19:16]+4'h1; |
|
if (stopwatch[23:16] >= 8'h59) |
stopwatch[23:20] <= 4'h0; |
else if (stopwatch[19:16] >= 4'h9) |
stopwatch[23:20] <= stopwatch[23:20]+4'h1; |
sw_pph <= (stopwatch[23:16] == 8'h59); |
end else sw_pph <= 1'b0; |
|
if (sw_pph) |
begin // And hours |
if (stopwatch[27:24] >= 4'h9) |
stopwatch[27:24] <= 4'h0; |
else |
stopwatch[27:24] <= stopwatch[27:24]+4'h1; |
|
if((stopwatch[27:24] >= 4'h9)&&(stopwatch[31:28] < 4'hf)) |
stopwatch[31:28] <= stopwatch[27:24]+4'h1; |
end |
|
if ((sw_sel)&&(i_wb_we)) |
begin |
stopwatch[0] <= i_wb_data[0]; |
if((i_wb_data[1])&&((~stopwatch[0])||(~i_wb_data[0]))) |
begin |
stopwatch[31:1] <= 31'h00; |
sw_sub <= 8'h00; |
sw_pps <= 1'b0; |
sw_ppm <= 1'b0; |
sw_pph <= 1'b0; |
end |
end |
end |
|
// |
// The alarm code |
// |
// Set the alarm register to the time you wish the board to "alarm". |
// The "alarm" will take place once per day at that time. At that |
// time, the RTC code will generate a clock interrupt, and the CPU/host |
// can come and see that the alarm tripped. |
// |
// |
reg [21:0] alarm_time; |
reg al_int, // The alarm interrupt line |
al_enabled, // Whether the alarm is enabled |
al_tripped; // Whether the alarm has tripped |
initial al_enabled= 1'b0; |
initial al_tripped= 1'b0; |
always @(posedge i_clk) |
begin |
if ((al_sel)&&(i_wb_we)) |
begin |
// Only adjust the alarm hours if the requested hours |
// are valid. This allows writes to the register, |
// without a prior read, to leave these configuration |
// bits alone. |
if (i_wb_data[21:16] != 6'h3f) |
alarm_time[21:16] <= i_wb_data[21:16]; |
// Here's the same thing for the minutes: only adjust |
// the alarm minutes if the new bits are not all 1's. |
if (i_wb_data[15:8] != 8'hff) |
alarm_time[15:8] <= i_wb_data[15:8]; |
// Here's the same thing for the seconds: only adjust |
// the alarm minutes if the new bits are not all 1's. |
if (i_wb_data[7:0] != 8'hff) |
alarm_time[7:0] <= i_wb_data[7:0]; |
al_enabled <= i_wb_data[24]; |
// Reset the alarm if a '1' is written to the tripped |
// register, or if the alarm is disabled. |
if ((i_wb_data[25])||(~i_wb_data[24])) |
al_tripped <= 1'b0; |
end |
|
al_int <= 1'b0; |
if ((ck_last_clock != alarm_time)&&(clock[21:0] == alarm_time) |
&&(al_enabled)) |
begin |
al_tripped <= 1'b1; |
al_int <= 1'b1; |
end |
end |
|
// |
// The ckspeed register is equal to 2^48 divded by the number of |
// clock ticks you expect per second. Adjust high for a slower |
// clock, lower for a faster clock. In this fashion, a single |
// real time clock RTL file can handle tracking the clock in any |
// device. Further, because this is only the lower 32 bits of a |
// 48 bit counter per seconds, the clock jitter is kept below |
// 1 part in 65 thousand. |
// |
initial ckspeed = 32'd2814750; // 2af31e = 2^48 / 100e6 MHz |
// In the case of verilator, comment the above and uncomment the line |
// below. The clock constant below is "close" to simulation time, |
// meaning that my verilator simulation is running about 300x slower |
// than board time. |
// initial ckspeed = 32'd786432000; |
always @(posedge i_clk) |
if ((sp_sel)&&(i_wb_we)) |
ckspeed <= i_wb_data; |
|
// |
// If you want very fine precision control over your clock, you need |
// to be able to transfer time from one location to another. This |
// is the beginning of that means: by setting a wire, i_hack, high |
// on a particular input, you can then read (later) what the clock |
// time was on that input. |
// |
// What's missing from this high precision adjustment mechanism is a |
// means of actually adjusting this time based upon the time |
// difference you measure here between the hack time and some time |
// on another clock, but we'll get there. |
// |
reg r_hack_carry; |
reg [29:0] hack_time; |
reg [39:0] hack_counter; |
always @(posedge i_clk) |
if (i_hack) |
begin |
hack_time <= { clock[21:0], ck_sub }; |
hack_counter <= ck_counter; |
r_hack_carry <= ck_carry; |
// if ck_carry is set, the clock register is in the |
// middle of a two clock update. In that case .... |
end else if (r_hack_carry) |
begin // update again on the next clock to get the correct |
// hack time. |
hack_time <= { clock[21:0], ck_sub }; |
r_hack_carry <= 1'b0; |
end |
|
reg [15:0] h_sseg; |
always @(posedge i_clk) |
case(clock[27:24]) |
4'h0: h_sseg <= { 2'b00, ck_last_clock[21:8] }; |
4'h1: h_sseg <= timer[15:0]; |
4'h2: h_sseg <= stopwatch[19:4]; |
4'h3: h_sseg <= ck_last_clock[15:0]; |
default: h_sseg <= { 2'b00, ck_last_clock[21:8] }; |
endcase |
|
wire [31:0] w_sseg; |
assign w_sseg[ 0] = (~ck_sub[7]); |
assign w_sseg[ 8] = 1'b0; |
assign w_sseg[16] = 1'b0; |
assign w_sseg[24] = 1'b0; |
hexmap ha(i_clk, h_sseg[ 3: 0], w_sseg[ 7: 1]); |
hexmap hb(i_clk, h_sseg[ 7: 4], w_sseg[15: 9]); |
hexmap hc(i_clk, h_sseg[11: 8], w_sseg[23:17]); |
hexmap hd(i_clk, h_sseg[15:12], w_sseg[31:25]); |
|
always @(posedge i_clk) |
if ((tm_alarm || al_tripped)&&(ck_sub[7])) |
o_sseg <= 32'h0000; |
else |
o_sseg <= w_sseg; |
|
reg [17:0] ledreg; |
always @(posedge i_clk) |
if ((ck_pps)&&(ck_ppm)) |
ledreg <= 18'h00; |
else if (ck_carry) |
ledreg <= ledreg + 18'h11; |
assign o_led = (tm_alarm||al_tripped)?{ (16){ck_sub[7]}}:ledreg[17:2]; |
|
assign o_interrupt = tm_int || al_int; |
|
always @(posedge i_clk) |
case(i_wb_addr[2:0]) |
3'b000: o_data <= { clock[31:22], ck_last_clock }; |
3'b001: o_data <= { 14'h00, timer }; |
3'b010: o_data <= stopwatch; |
3'b011: o_data <= { 6'h00, al_tripped, al_enabled, 2'b00, alarm_time }; |
3'b100: o_data <= ckspeed; |
3'b101: o_data <= { 2'b00, hack_time }; |
3'b110: o_data <= hack_counter[39:8]; |
3'b111: o_data <= { hack_counter[7:0], 24'h00 }; |
endcase |
|
endmodule |
/doc/spec.pdf
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doc/spec.pdf
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+application/octet-stream
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Index: doc/src/gpl-3.0.tex
===================================================================
--- doc/src/gpl-3.0.tex (nonexistent)
+++ doc/src/gpl-3.0.tex (revision 2)
@@ -0,0 +1,719 @@
+\documentclass[11pt]{article}
+
+\title{GNU GENERAL PUBLIC LICENSE}
+\date{Version 3, 29 June 2007}
+
+\begin{document}
+\maketitle
+
+\begin{center}
+{\parindent 0in
+
+Copyright \copyright\ 2007 Free Software Foundation, Inc. \texttt{http://fsf.org/}
+
+\bigskip
+Everyone is permitted to copy and distribute verbatim copies of this
+
+license document, but changing it is not allowed.}
+
+\end{center}
+
+\renewcommand{\abstractname}{Preamble}
+\begin{abstract}
+The GNU General Public License is a free, copyleft license for
+software and other kinds of works.
+
+The licenses for most software and other practical works are designed
+to take away your freedom to share and change the works. By contrast,
+the GNU General Public License is intended to guarantee your freedom to
+share and change all versions of a program--to make sure it remains free
+software for all its users. We, the Free Software Foundation, use the
+GNU General Public License for most of our software; it applies also to
+any other work released this way by its authors. You can apply it to
+your programs, too.
+
+When we speak of free software, we are referring to freedom, not
+price. Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+them if you wish), that you receive source code or can get it if you
+want it, that you can change the software or use pieces of it in new
+free programs, and that you know you can do these things.
+
+To protect your rights, we need to prevent others from denying you
+these rights or asking you to surrender the rights. Therefore, you have
+certain responsibilities if you distribute copies of the software, or if
+you modify it: responsibilities to respect the freedom of others.
+
+For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must pass on to the recipients the same
+freedoms that you received. You must make sure that they, too, receive
+or can get the source code. And you must show them these terms so they
+know their rights.
+
+Developers that use the GNU GPL protect your rights with two steps:
+(1) assert copyright on the software, and (2) offer you this License
+giving you legal permission to copy, distribute and/or modify it.
+
+For the developers' and authors' protection, the GPL clearly explains
+that there is no warranty for this free software. For both users' and
+authors' sake, the GPL requires that modified versions be marked as
+changed, so that their problems will not be attributed erroneously to
+authors of previous versions.
+
+Some devices are designed to deny users access to install or run
+modified versions of the software inside them, although the manufacturer
+can do so. This is fundamentally incompatible with the aim of
+protecting users' freedom to change the software. The systematic
+pattern of such abuse occurs in the area of products for individuals to
+use, which is precisely where it is most unacceptable. Therefore, we
+have designed this version of the GPL to prohibit the practice for those
+products. If such problems arise substantially in other domains, we
+stand ready to extend this provision to those domains in future versions
+of the GPL, as needed to protect the freedom of users.
+
+Finally, every program is threatened constantly by software patents.
+States should not allow patents to restrict development and use of
+software on general-purpose computers, but in those that do, we wish to
+avoid the special danger that patents applied to a free program could
+make it effectively proprietary. To prevent this, the GPL assures that
+patents cannot be used to render the program non-free.
+
+The precise terms and conditions for copying, distribution and
+modification follow.
+\end{abstract}
+
+\begin{center}
+{\Large \sc Terms and Conditions}
+\end{center}
+
+
+\begin{enumerate}
+
+\addtocounter{enumi}{-1}
+
+\item Definitions.
+
+``This License'' refers to version 3 of the GNU General Public License.
+
+``Copyright'' also means copyright-like laws that apply to other kinds of
+works, such as semiconductor masks.
+
+``The Program'' refers to any copyrightable work licensed under this
+License. Each licensee is addressed as ``you''. ``Licensees'' and
+``recipients'' may be individuals or organizations.
+
+To ``modify'' a work means to copy from or adapt all or part of the work
+in a fashion requiring copyright permission, other than the making of an
+exact copy. The resulting work is called a ``modified version'' of the
+earlier work or a work ``based on'' the earlier work.
+
+A ``covered work'' means either the unmodified Program or a work based
+on the Program.
+
+To ``propagate'' a work means to do anything with it that, without
+permission, would make you directly or secondarily liable for
+infringement under applicable copyright law, except executing it on a
+computer or modifying a private copy. Propagation includes copying,
+distribution (with or without modification), making available to the
+public, and in some countries other activities as well.
+
+To ``convey'' a work means any kind of propagation that enables other
+parties to make or receive copies. Mere interaction with a user through
+a computer network, with no transfer of a copy, is not conveying.
+
+An interactive user interface displays ``Appropriate Legal Notices''
+to the extent that it includes a convenient and prominently visible
+feature that (1) displays an appropriate copyright notice, and (2)
+tells the user that there is no warranty for the work (except to the
+extent that warranties are provided), that licensees may convey the
+work under this License, and how to view a copy of this License. If
+the interface presents a list of user commands or options, such as a
+menu, a prominent item in the list meets this criterion.
+
+\item Source Code.
+
+The ``source code'' for a work means the preferred form of the work
+for making modifications to it. ``Object code'' means any non-source
+form of a work.
+
+A ``Standard Interface'' means an interface that either is an official
+standard defined by a recognized standards body, or, in the case of
+interfaces specified for a particular programming language, one that
+is widely used among developers working in that language.
+
+The ``System Libraries'' of an executable work include anything, other
+than the work as a whole, that (a) is included in the normal form of
+packaging a Major Component, but which is not part of that Major
+Component, and (b) serves only to enable use of the work with that
+Major Component, or to implement a Standard Interface for which an
+implementation is available to the public in source code form. A
+``Major Component'', in this context, means a major essential component
+(kernel, window system, and so on) of the specific operating system
+(if any) on which the executable work runs, or a compiler used to
+produce the work, or an object code interpreter used to run it.
+
+The ``Corresponding Source'' for a work in object code form means all
+the source code needed to generate, install, and (for an executable
+work) run the object code and to modify the work, including scripts to
+control those activities. However, it does not include the work's
+System Libraries, or general-purpose tools or generally available free
+programs which are used unmodified in performing those activities but
+which are not part of the work. For example, Corresponding Source
+includes interface definition files associated with source files for
+the work, and the source code for shared libraries and dynamically
+linked subprograms that the work is specifically designed to require,
+such as by intimate data communication or control flow between those
+subprograms and other parts of the work.
+
+The Corresponding Source need not include anything that users
+can regenerate automatically from other parts of the Corresponding
+Source.
+
+The Corresponding Source for a work in source code form is that
+same work.
+
+\item Basic Permissions.
+
+All rights granted under this License are granted for the term of
+copyright on the Program, and are irrevocable provided the stated
+conditions are met. This License explicitly affirms your unlimited
+permission to run the unmodified Program. The output from running a
+covered work is covered by this License only if the output, given its
+content, constitutes a covered work. This License acknowledges your
+rights of fair use or other equivalent, as provided by copyright law.
+
+You may make, run and propagate covered works that you do not
+convey, without conditions so long as your license otherwise remains
+in force. You may convey covered works to others for the sole purpose
+of having them make modifications exclusively for you, or provide you
+with facilities for running those works, provided that you comply with
+the terms of this License in conveying all material for which you do
+not control copyright. Those thus making or running the covered works
+for you must do so exclusively on your behalf, under your direction
+and control, on terms that prohibit them from making any copies of
+your copyrighted material outside their relationship with you.
+
+Conveying under any other circumstances is permitted solely under
+the conditions stated below. Sublicensing is not allowed; section 10
+makes it unnecessary.
+
+\item Protecting Users' Legal Rights From Anti-Circumvention Law.
+
+No covered work shall be deemed part of an effective technological
+measure under any applicable law fulfilling obligations under article
+11 of the WIPO copyright treaty adopted on 20 December 1996, or
+similar laws prohibiting or restricting circumvention of such
+measures.
+
+When you convey a covered work, you waive any legal power to forbid
+circumvention of technological measures to the extent such circumvention
+is effected by exercising rights under this License with respect to
+the covered work, and you disclaim any intention to limit operation or
+modification of the work as a means of enforcing, against the work's
+users, your or third parties' legal rights to forbid circumvention of
+technological measures.
+
+\item Conveying Verbatim Copies.
+
+You may convey verbatim copies of the Program's source code as you
+receive it, in any medium, provided that you conspicuously and
+appropriately publish on each copy an appropriate copyright notice;
+keep intact all notices stating that this License and any
+non-permissive terms added in accord with section 7 apply to the code;
+keep intact all notices of the absence of any warranty; and give all
+recipients a copy of this License along with the Program.
+
+You may charge any price or no price for each copy that you convey,
+and you may offer support or warranty protection for a fee.
+
+\item Conveying Modified Source Versions.
+
+You may convey a work based on the Program, or the modifications to
+produce it from the Program, in the form of source code under the
+terms of section 4, provided that you also meet all of these conditions:
+ \begin{enumerate}
+ \item The work must carry prominent notices stating that you modified
+ it, and giving a relevant date.
+
+ \item The work must carry prominent notices stating that it is
+ released under this License and any conditions added under section
+ 7. This requirement modifies the requirement in section 4 to
+ ``keep intact all notices''.
+
+ \item You must license the entire work, as a whole, under this
+ License to anyone who comes into possession of a copy. This
+ License will therefore apply, along with any applicable section 7
+ additional terms, to the whole of the work, and all its parts,
+ regardless of how they are packaged. This License gives no
+ permission to license the work in any other way, but it does not
+ invalidate such permission if you have separately received it.
+
+ \item If the work has interactive user interfaces, each must display
+ Appropriate Legal Notices; however, if the Program has interactive
+ interfaces that do not display Appropriate Legal Notices, your
+ work need not make them do so.
+\end{enumerate}
+A compilation of a covered work with other separate and independent
+works, which are not by their nature extensions of the covered work,
+and which are not combined with it such as to form a larger program,
+in or on a volume of a storage or distribution medium, is called an
+``aggregate'' if the compilation and its resulting copyright are not
+used to limit the access or legal rights of the compilation's users
+beyond what the individual works permit. Inclusion of a covered work
+in an aggregate does not cause this License to apply to the other
+parts of the aggregate.
+
+\item Conveying Non-Source Forms.
+
+You may convey a covered work in object code form under the terms
+of sections 4 and 5, provided that you also convey the
+machine-readable Corresponding Source under the terms of this License,
+in one of these ways:
+ \begin{enumerate}
+ \item Convey the object code in, or embodied in, a physical product
+ (including a physical distribution medium), accompanied by the
+ Corresponding Source fixed on a durable physical medium
+ customarily used for software interchange.
+
+ \item Convey the object code in, or embodied in, a physical product
+ (including a physical distribution medium), accompanied by a
+ written offer, valid for at least three years and valid for as
+ long as you offer spare parts or customer support for that product
+ model, to give anyone who possesses the object code either (1) a
+ copy of the Corresponding Source for all the software in the
+ product that is covered by this License, on a durable physical
+ medium customarily used for software interchange, for a price no
+ more than your reasonable cost of physically performing this
+ conveying of source, or (2) access to copy the
+ Corresponding Source from a network server at no charge.
+
+ \item Convey individual copies of the object code with a copy of the
+ written offer to provide the Corresponding Source. This
+ alternative is allowed only occasionally and noncommercially, and
+ only if you received the object code with such an offer, in accord
+ with subsection 6b.
+
+ \item Convey the object code by offering access from a designated
+ place (gratis or for a charge), and offer equivalent access to the
+ Corresponding Source in the same way through the same place at no
+ further charge. You need not require recipients to copy the
+ Corresponding Source along with the object code. If the place to
+ copy the object code is a network server, the Corresponding Source
+ may be on a different server (operated by you or a third party)
+ that supports equivalent copying facilities, provided you maintain
+ clear directions next to the object code saying where to find the
+ Corresponding Source. Regardless of what server hosts the
+ Corresponding Source, you remain obligated to ensure that it is
+ available for as long as needed to satisfy these requirements.
+
+ \item Convey the object code using peer-to-peer transmission, provided
+ you inform other peers where the object code and Corresponding
+ Source of the work are being offered to the general public at no
+ charge under subsection 6d.
+ \end{enumerate}
+
+A separable portion of the object code, whose source code is excluded
+from the Corresponding Source as a System Library, need not be
+included in conveying the object code work.
+
+A ``User Product'' is either (1) a ``consumer product'', which means any
+tangible personal property which is normally used for personal, family,
+or household purposes, or (2) anything designed or sold for incorporation
+into a dwelling. In determining whether a product is a consumer product,
+doubtful cases shall be resolved in favor of coverage. For a particular
+product received by a particular user, ``normally used'' refers to a
+typical or common use of that class of product, regardless of the status
+of the particular user or of the way in which the particular user
+actually uses, or expects or is expected to use, the product. A product
+is a consumer product regardless of whether the product has substantial
+commercial, industrial or non-consumer uses, unless such uses represent
+the only significant mode of use of the product.
+
+``Installation Information'' for a User Product means any methods,
+procedures, authorization keys, or other information required to install
+and execute modified versions of a covered work in that User Product from
+a modified version of its Corresponding Source. The information must
+suffice to ensure that the continued functioning of the modified object
+code is in no case prevented or interfered with solely because
+modification has been made.
+
+If you convey an object code work under this section in, or with, or
+specifically for use in, a User Product, and the conveying occurs as
+part of a transaction in which the right of possession and use of the
+User Product is transferred to the recipient in perpetuity or for a
+fixed term (regardless of how the transaction is characterized), the
+Corresponding Source conveyed under this section must be accompanied
+by the Installation Information. But this requirement does not apply
+if neither you nor any third party retains the ability to install
+modified object code on the User Product (for example, the work has
+been installed in ROM).
+
+The requirement to provide Installation Information does not include a
+requirement to continue to provide support service, warranty, or updates
+for a work that has been modified or installed by the recipient, or for
+the User Product in which it has been modified or installed. Access to a
+network may be denied when the modification itself materially and
+adversely affects the operation of the network or violates the rules and
+protocols for communication across the network.
+
+Corresponding Source conveyed, and Installation Information provided,
+in accord with this section must be in a format that is publicly
+documented (and with an implementation available to the public in
+source code form), and must require no special password or key for
+unpacking, reading or copying.
+
+\item Additional Terms.
+
+``Additional permissions'' are terms that supplement the terms of this
+License by making exceptions from one or more of its conditions.
+Additional permissions that are applicable to the entire Program shall
+be treated as though they were included in this License, to the extent
+that they are valid under applicable law. If additional permissions
+apply only to part of the Program, that part may be used separately
+under those permissions, but the entire Program remains governed by
+this License without regard to the additional permissions.
+
+When you convey a copy of a covered work, you may at your option
+remove any additional permissions from that copy, or from any part of
+it. (Additional permissions may be written to require their own
+removal in certain cases when you modify the work.) You may place
+additional permissions on material, added by you to a covered work,
+for which you have or can give appropriate copyright permission.
+
+Notwithstanding any other provision of this License, for material you
+add to a covered work, you may (if authorized by the copyright holders of
+that material) supplement the terms of this License with terms:
+ \begin{enumerate}
+ \item Disclaiming warranty or limiting liability differently from the
+ terms of sections 15 and 16 of this License; or
+
+ \item Requiring preservation of specified reasonable legal notices or
+ author attributions in that material or in the Appropriate Legal
+ Notices displayed by works containing it; or
+
+ \item Prohibiting misrepresentation of the origin of that material, or
+ requiring that modified versions of such material be marked in
+ reasonable ways as different from the original version; or
+
+ \item Limiting the use for publicity purposes of names of licensors or
+ authors of the material; or
+
+ \item Declining to grant rights under trademark law for use of some
+ trade names, trademarks, or service marks; or
+
+ \item Requiring indemnification of licensors and authors of that
+ material by anyone who conveys the material (or modified versions of
+ it) with contractual assumptions of liability to the recipient, for
+ any liability that these contractual assumptions directly impose on
+ those licensors and authors.
+ \end{enumerate}
+
+All other non-permissive additional terms are considered ``further
+restrictions'' within the meaning of section 10. If the Program as you
+received it, or any part of it, contains a notice stating that it is
+governed by this License along with a term that is a further
+restriction, you may remove that term. If a license document contains
+a further restriction but permits relicensing or conveying under this
+License, you may add to a covered work material governed by the terms
+of that license document, provided that the further restriction does
+not survive such relicensing or conveying.
+
+If you add terms to a covered work in accord with this section, you
+must place, in the relevant source files, a statement of the
+additional terms that apply to those files, or a notice indicating
+where to find the applicable terms.
+
+Additional terms, permissive or non-permissive, may be stated in the
+form of a separately written license, or stated as exceptions;
+the above requirements apply either way.
+
+\item Termination.
+
+You may not propagate or modify a covered work except as expressly
+provided under this License. Any attempt otherwise to propagate or
+modify it is void, and will automatically terminate your rights under
+this License (including any patent licenses granted under the third
+paragraph of section 11).
+
+However, if you cease all violation of this License, then your
+license from a particular copyright holder is reinstated (a)
+provisionally, unless and until the copyright holder explicitly and
+finally terminates your license, and (b) permanently, if the copyright
+holder fails to notify you of the violation by some reasonable means
+prior to 60 days after the cessation.
+
+Moreover, your license from a particular copyright holder is
+reinstated permanently if the copyright holder notifies you of the
+violation by some reasonable means, this is the first time you have
+received notice of violation of this License (for any work) from that
+copyright holder, and you cure the violation prior to 30 days after
+your receipt of the notice.
+
+Termination of your rights under this section does not terminate the
+licenses of parties who have received copies or rights from you under
+this License. If your rights have been terminated and not permanently
+reinstated, you do not qualify to receive new licenses for the same
+material under section 10.
+
+\item Acceptance Not Required for Having Copies.
+
+You are not required to accept this License in order to receive or
+run a copy of the Program. Ancillary propagation of a covered work
+occurring solely as a consequence of using peer-to-peer transmission
+to receive a copy likewise does not require acceptance. However,
+nothing other than this License grants you permission to propagate or
+modify any covered work. These actions infringe copyright if you do
+not accept this License. Therefore, by modifying or propagating a
+covered work, you indicate your acceptance of this License to do so.
+
+\item Automatic Licensing of Downstream Recipients.
+
+Each time you convey a covered work, the recipient automatically
+receives a license from the original licensors, to run, modify and
+propagate that work, subject to this License. You are not responsible
+for enforcing compliance by third parties with this License.
+
+An ``entity transaction'' is a transaction transferring control of an
+organization, or substantially all assets of one, or subdividing an
+organization, or merging organizations. If propagation of a covered
+work results from an entity transaction, each party to that
+transaction who receives a copy of the work also receives whatever
+licenses to the work the party's predecessor in interest had or could
+give under the previous paragraph, plus a right to possession of the
+Corresponding Source of the work from the predecessor in interest, if
+the predecessor has it or can get it with reasonable efforts.
+
+You may not impose any further restrictions on the exercise of the
+rights granted or affirmed under this License. For example, you may
+not impose a license fee, royalty, or other charge for exercise of
+rights granted under this License, and you may not initiate litigation
+(including a cross-claim or counterclaim in a lawsuit) alleging that
+any patent claim is infringed by making, using, selling, offering for
+sale, or importing the Program or any portion of it.
+
+\item Patents.
+
+A ``contributor'' is a copyright holder who authorizes use under this
+License of the Program or a work on which the Program is based. The
+work thus licensed is called the contributor's ``contributor version''.
+
+A contributor's ``essential patent claims'' are all patent claims
+owned or controlled by the contributor, whether already acquired or
+hereafter acquired, that would be infringed by some manner, permitted
+by this License, of making, using, or selling its contributor version,
+but do not include claims that would be infringed only as a
+consequence of further modification of the contributor version. For
+purposes of this definition, ``control'' includes the right to grant
+patent sublicenses in a manner consistent with the requirements of
+this License.
+
+Each contributor grants you a non-exclusive, worldwide, royalty-free
+patent license under the contributor's essential patent claims, to
+make, use, sell, offer for sale, import and otherwise run, modify and
+propagate the contents of its contributor version.
+
+In the following three paragraphs, a ``patent license'' is any express
+agreement or commitment, however denominated, not to enforce a patent
+(such as an express permission to practice a patent or covenant not to
+sue for patent infringement). To ``grant'' such a patent license to a
+party means to make such an agreement or commitment not to enforce a
+patent against the party.
+
+If you convey a covered work, knowingly relying on a patent license,
+and the Corresponding Source of the work is not available for anyone
+to copy, free of charge and under the terms of this License, through a
+publicly available network server or other readily accessible means,
+then you must either (1) cause the Corresponding Source to be so
+available, or (2) arrange to deprive yourself of the benefit of the
+patent license for this particular work, or (3) arrange, in a manner
+consistent with the requirements of this License, to extend the patent
+license to downstream recipients. ``Knowingly relying'' means you have
+actual knowledge that, but for the patent license, your conveying the
+covered work in a country, or your recipient's use of the covered work
+in a country, would infringe one or more identifiable patents in that
+country that you have reason to believe are valid.
+
+If, pursuant to or in connection with a single transaction or
+arrangement, you convey, or propagate by procuring conveyance of, a
+covered work, and grant a patent license to some of the parties
+receiving the covered work authorizing them to use, propagate, modify
+or convey a specific copy of the covered work, then the patent license
+you grant is automatically extended to all recipients of the covered
+work and works based on it.
+
+A patent license is ``discriminatory'' if it does not include within
+the scope of its coverage, prohibits the exercise of, or is
+conditioned on the non-exercise of one or more of the rights that are
+specifically granted under this License. You may not convey a covered
+work if you are a party to an arrangement with a third party that is
+in the business of distributing software, under which you make payment
+to the third party based on the extent of your activity of conveying
+the work, and under which the third party grants, to any of the
+parties who would receive the covered work from you, a discriminatory
+patent license (a) in connection with copies of the covered work
+conveyed by you (or copies made from those copies), or (b) primarily
+for and in connection with specific products or compilations that
+contain the covered work, unless you entered into that arrangement,
+or that patent license was granted, prior to 28 March 2007.
+
+Nothing in this License shall be construed as excluding or limiting
+any implied license or other defenses to infringement that may
+otherwise be available to you under applicable patent law.
+
+\item No Surrender of Others' Freedom.
+
+If conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License. If you cannot convey a
+covered work so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you may
+not convey it at all. For example, if you agree to terms that obligate you
+to collect a royalty for further conveying from those to whom you convey
+the Program, the only way you could satisfy both those terms and this
+License would be to refrain entirely from conveying the Program.
+
+\item Use with the GNU Affero General Public License.
+
+Notwithstanding any other provision of this License, you have
+permission to link or combine any covered work with a work licensed
+under version 3 of the GNU Affero General Public License into a single
+combined work, and to convey the resulting work. The terms of this
+License will continue to apply to the part which is the covered work,
+but the special requirements of the GNU Affero General Public License,
+section 13, concerning interaction through a network will apply to the
+combination as such.
+
+\item Revised Versions of this License.
+
+The Free Software Foundation may publish revised and/or new versions of
+the GNU General Public License from time to time. Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+Each version is given a distinguishing version number. If the
+Program specifies that a certain numbered version of the GNU General
+Public License ``or any later version'' applies to it, you have the
+option of following the terms and conditions either of that numbered
+version or of any later version published by the Free Software
+Foundation. If the Program does not specify a version number of the
+GNU General Public License, you may choose any version ever published
+by the Free Software Foundation.
+
+If the Program specifies that a proxy can decide which future
+versions of the GNU General Public License can be used, that proxy's
+public statement of acceptance of a version permanently authorizes you
+to choose that version for the Program.
+
+Later license versions may give you additional or different
+permissions. However, no additional obligations are imposed on any
+author or copyright holder as a result of your choosing to follow a
+later version.
+
+\item Disclaimer of Warranty.
+
+\begin{sloppypar}
+ THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
+ APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE
+ COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM ``AS IS''
+ WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED,
+ INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE
+ RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.
+ SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL
+ NECESSARY SERVICING, REPAIR OR CORRECTION.
+\end{sloppypar}
+
+\item Limitation of Liability.
+
+ IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN
+ WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES
+ AND/OR CONVEYS THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR
+ DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL
+ DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM
+ (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED
+ INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE
+ OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH
+ HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
+ DAMAGES.
+
+\item Interpretation of Sections 15 and 16.
+
+If the disclaimer of warranty and limitation of liability provided
+above cannot be given local legal effect according to their terms,
+reviewing courts shall apply local law that most closely approximates
+an absolute waiver of all civil liability in connection with the
+Program, unless a warranty or assumption of liability accompanies a
+copy of the Program in return for a fee.
+
+\begin{center}
+{\Large\sc End of Terms and Conditions}
+
+\bigskip
+How to Apply These Terms to Your New Programs
+\end{center}
+
+If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+To do so, attach the following notices to the program. It is safest
+to attach them to the start of each source file to most effectively
+state the exclusion of warranty; and each file should have at least
+the ``copyright'' line and a pointer to where the full notice is found.
+
+{\footnotesize
+\begin{verbatim}
+
+
+Copyright (C)
+
+This program is free software: you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation, either version 3 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program. If not, see .
+\end{verbatim}
+}
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program does terminal interaction, make it output a short
+notice like this when it starts in an interactive mode:
+
+{\footnotesize
+\begin{verbatim}
+ Copyright (C)
+
+This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+\end{verbatim}
+}
+
+The hypothetical commands {\tt show w} and {\tt show c} should show
+the appropriate
+parts of the General Public License. Of course, your program's commands
+might be different; for a GUI interface, you would use an ``about box''.
+
+You should also get your employer (if you work as a programmer) or
+school, if any, to sign a ``copyright disclaimer'' for the program, if
+necessary. For more information on this, and how to apply and follow
+the GNU GPL, see \texttt{http://www.gnu.org/licenses/}.
+
+The GNU General Public License does not permit incorporating your
+program into proprietary programs. If your program is a subroutine
+library, you may consider it more useful to permit linking proprietary
+applications with the library. If this is what you want to do, use
+the GNU Lesser General Public License instead of this License. But
+first, please read \texttt{http://www.gnu.org/philosophy/why-not-lgpl.html}.
+
+\end{enumerate}
+
+\end{document}
Index: doc/src/GT.eps
===================================================================
--- doc/src/GT.eps (nonexistent)
+++ doc/src/GT.eps (revision 2)
@@ -0,0 +1,94 @@
+%!PS-Adobe-3.0 EPSF-3.0
+%%BoundingBox: 0 0 504 288
+%%Creator: Gisselquist Technology LLC
+%%Title: Gisselquist Technology Logo
+%%CreationDate: 11 Mar 2014
+%%EndComments
+%%BeginProlog
+/black { 0 setgray } def
+/white { 1 setgray } def
+/height { 288 } def
+/lw { height 8 div } def
+%%EndProlog
+% %%Page: 1
+
+false { % A bounding box
+ 0 setlinewidth
+ newpath
+ 0 0 moveto
+ 0 height lineto
+ 1.625 height mul lw add 0 rlineto
+ 0 height neg rlineto
+ closepath stroke
+} if
+
+true { % The "G"
+ newpath
+ height 2 div 1.25 mul height moveto
+ height 2 div height 4 div sub height lineto
+ 0 height 3 4 div mul lineto
+ 0 height 4 div lineto
+ height 4 div 0 lineto
+ height 3 4 div mul 0 lineto
+ height height 4 div lineto
+ height height 2 div lineto
+ %
+ height lw sub height 2 div lineto
+ height lw sub height 4 div lw 2 div add lineto
+ height 3 4 div mul lw 2 div sub lw lineto
+ height 4 div lw 2 div add lw lineto
+ lw height 4 div lw 2 div add lineto
+ lw height 3 4 div mul lw 2 div sub lineto
+ height 4 div lw 2 div add height lw sub lineto
+ height 2 div 1.25 mul height lw sub lineto
+ closepath fill
+ newpath
+ height 2 div height 2 div moveto
+ height 2 div 0 rlineto
+ 0 height 2 div neg rlineto
+ lw neg 0 rlineto
+ 0 height 2 div lw sub rlineto
+ height 2 div height 2 div lw sub lineto
+ closepath fill
+} if
+
+height 2 div 1.25 mul lw add 0 translate
+false {
+ newpath
+ 0 height moveto
+ height 0 rlineto
+ 0 lw neg rlineto
+ height lw sub 2 div neg 0 rlineto
+ 0 height lw sub neg rlineto
+ lw neg 0 rlineto
+ 0 height lw sub rlineto
+ height lw sub 2 div neg 0 rlineto
+ 0 lw rlineto
+ closepath fill
+} if
+
+true { % The "T" of "GT".
+ newpath
+ 0 height moveto
+ height lw add 2 div 0 rlineto
+ 0 height neg rlineto
+ lw neg 0 rlineto
+ 0 height lw sub rlineto
+ height lw sub 2 div neg 0 rlineto
+ closepath fill
+
+ % The right half of the top of the "T"
+ newpath
+ % (height + lw)/2 + lw
+ height lw add 2 div lw add height moveto
+ % height - (above) = height - height/2 - 3/2 lw = height/2-3/2lw
+ height 3 lw mul sub 2 div 0 rlineto
+ 0 lw neg rlineto
+ height 3 lw mul sub 2 div neg 0 rlineto
+ closepath fill
+} if
+
+
+grestore
+showpage
+%%EOF
Index: doc/src/gqtekspec.cls
===================================================================
--- doc/src/gqtekspec.cls (nonexistent)
+++ doc/src/gqtekspec.cls (revision 2)
@@ -0,0 +1,296 @@
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%/
+%
+% Copyright (C) 2015, Gisselquist Technology, LLC
+%
+% This template is free software: you can redistribute it and/or modify it
+% under the terms of the GNU General Public License as published by the
+% Free Software Foundation, either version 3 of the License, or (at your
+% option) any later version.
+%
+% This template is distributed in the hope that it will be useful, but WITHOUT
+% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
+% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+% for more details.
+%
+% You should have received a copy of the GNU General Public License along
+% with this program. If not, see for a copy.
+%
+% License: GPL, v3, as defined and found on www.gnu.org,
+% http://www.gnu.org/licenses/gpl.html
+%
+%
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+% \NeedsTeXFormat{LaTeX2e}[1995/12/01]
+\ProvidesClass{gqtekspec}[2015/03/03 v0.1 -- Gisselquist Technology Specification]
+\typeout{by Dan Gisselquist}
+\LoadClassWithOptions{report}
+\usepackage{datetime}
+\usepackage{graphicx}
+\usepackage[dvips]{pstricks}
+\usepackage{hhline}
+\usepackage{colortbl}
+\newdateformat{headerdate}{\THEYEAR/\twodigit{\THEMONTH}/\twodigit{\THEDAY}}
+\setlength{\hoffset}{0.25in}
+\setlength{\voffset}{-0.5in}
+\setlength{\marginparwidth}{0in}
+\setlength{\marginparsep}{0in}
+\setlength{\textwidth}{6in}
+\setlength{\oddsidemargin}{0in}
+
+% **************************************
+% * APPENDIX *
+% **************************************
+%
+\newcommand\appfl@g{\appendixname} %used to test \@chapapp
+%
+% \renewcommand\appendix{\par\clearpage
+ % \setcounter{chapter}{0}%
+ % \setcounter{section}{0}%
+ % \renewcommand\@chapapp{\appendixname}%
+ % \renewcommand\thechapter{\Alph{chapter}}
+ % \if@nosectnum\else
+ % \renewcommand\thesection{\Alph{chapter}.\arabic{section}}
+ % \fi
+% }
+
+
+% FIGURE
+% redefine the @caption command to put a period after the figure or
+% table number in the lof and lot tables
+\long\def\@caption#1[#2]#3{\par\addcontentsline{\csname
+ ext@#1\endcsname}{#1}{\protect\numberline{\csname
+ the#1\endcsname.}{\ignorespaces #2}}\begingroup
+ \@parboxrestore
+ \normalsize
+ \@makecaption{\csname fnum@#1\endcsname}{\ignorespaces #3}\par
+ \endgroup}
+
+% ****************************************
+% * TABLE OF CONTENTS, ETC. *
+% ****************************************
+
+\renewcommand\contentsname{Contents}
+\renewcommand\listfigurename{Figures}
+\renewcommand\listtablename{Tables}
+
+\newif\if@toc \@tocfalse
+\renewcommand\tableofcontents{%
+ \begingroup% temporarily set if@toc so that \@schapter will not
+ % put Table of Contents in the table of contents.
+ \@toctrue
+ \chapter*{\contentsname}
+ \endgroup
+ \thispagestyle{gqtekspecplain}
+
+ \baselineskip=10pt plus .5pt minus .5pt
+
+ {\raggedleft Page \par\vskip-\parskip}
+ \@starttoc{toc}%
+ \baselineskip=\normalbaselineskip
+ }
+
+\def\l@appendix{\pagebreak[3]
+ \vskip 1.0em plus 1pt % space above appendix line
+ \@dottedtocline{0}{0em}{8em}}
+
+\def\l@chapter{\pagebreak[3]
+ \vskip 1.0em plus 1pt % space above appendix line
+ \@dottedtocline{0}{0em}{4em}}
+
+% \if@nosectnum\else
+ % \renewcommand\l@section{\@dottedtocline{1}{5.5em}{2.4em}}
+ % \renewcommand\l@subsection{\@dottedtocline{2}{8.5em}{3.2em}}
+ % \renewcommand\l@subsubsection{\@dottedtocline{3}{11em}{4.1em}}
+ % \renewcommand\l@paragraph{\@dottedtocline{4}{13.5em}{5em}}
+ % \renewcommand\l@subparagraph{\@dottedtocline{5}{16em}{6em}}
+% \fi
+
+% LIST OF FIGURES
+%
+\def\listoffigures{%
+ \begingroup
+ \chapter*{\listfigurename}%
+ \endgroup
+ \thispagestyle{gqtekspecplain}%
+
+ \baselineskip=10pt plus .5pt minus .5pt%
+
+ {\hbox to \hsize{Figure\hfil Page} \par\vskip-\parskip}%
+
+ \rule[2mm]{\textwidth}{0.5mm}\par
+
+ \@starttoc{lof}%
+ \baselineskip=\normalbaselineskip}%
+
+\def\l@figure{\@dottedtocline{1}{1em}{4.0em}}
+
+% LIST OF TABLES
+%
+\def\listoftables{%
+ \begingroup
+ \chapter*{\listtablename}%
+ \endgroup
+ \thispagestyle{gqtekspecplain}%
+ \baselineskip=10pt plus .5pt minus .5pt%
+ {\hbox to \hsize{Table\hfil Page} \par\vskip-\parskip}%
+
+ % Added line underneath headings, 20 Jun 01, Capt Todd Hale.
+ \rule[2mm]{\textwidth}{0.5mm}\par
+
+ \@starttoc{lot}%
+ \baselineskip=\normalbaselineskip}%
+
+\let\l@table\l@figure
+
+% ****************************************
+% * PAGE STYLES *
+% ****************************************
+%
+\def\ps@gqtekspectoc{%
+ \let\@mkboth\@gobbletwo
+ \def \@oddhead{}
+ \def \@oddfoot{\rm
+ \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspectocn}}
+ \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot}
+\def\ps@gqtekspectocn{\let\@mkboth\@gobbletwo
+ \def \@oddhead{\rm \hfil\raisebox{10pt}{Page}}
+ \def \@oddfoot{\rm
+ \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspectocn}}
+ \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot}
+
+\def\ps@gqtekspeclof{\let\@mkboth\@gobbletwo
+ \def \@oddhead{}
+ \def \@oddfoot{\rm
+ \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclofn}}
+ \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot}
+\def\ps@gqtekspeclofn{\let\@mkboth\@gobbletwo
+ \def \@oddhead{\rm
+ \parbox{\textwidth}{\raisebox{0pt}{Figure}\hfil\raisebox{0pt}{Page} %
+ \raisebox{20pt}{\rule[10pt]{\textwidth}{0.5mm}} }}
+
+ \def \@oddfoot{\rm
+ \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclofn}}
+ \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot}
+
+\def\ps@gqtekspeclot{\let\@mkboth\@gobbletwo
+ \def \@oddhead{}
+ \def \@oddfoot{\rm
+ \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclotn}}
+ \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot}
+\def\ps@gqtekspeclotn{\let\@mkboth\@gobbletwo
+ \def \@oddhead{\rm
+ \parbox{\textwidth}{\raisebox{0pt}{Table}\hfil\raisebox{0pt}{Page} %
+ \raisebox{20pt}{\rule[10pt]{\textwidth}{0.5mm}} }}
+
+ \def \@oddfoot{\rm
+ \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclotn}}
+ \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot}
+
+\def\ps@gqtekspecplain{\let\@mkboth\@gobbletwo
+ \def \@oddhead{\rput(0,-2pt){\psline(0,0)(\textwidth,0)}\rm \hbox to 1in{\includegraphics[height=0.8\headheight]{GT.eps} Gisselquist Technology, LLC}\hfil\hbox{\@title}\hfil\hbox to 1in{\hfil\headerdate\@date}}
+ \def \@oddfoot{\rput(0,9pt){\psline(0,0)(\textwidth,0)}\rm \hbox to 1in{www.opencores.com\hfil}\hfil\hbox{\r@vision}\hfil\hbox to 1in{\hfil{\thepage}}}
+ \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot}
+
+% \def\author#1{\def\auth@r{#1}}
+% \def\title#1{\def\ti@tle{#1}}
+
+\def\logo{\begin{pspicture}(0,0)(5.67in,0.75in)
+ \rput[lb](0.05in,0.10in){\includegraphics[height=0.75in]{GT.eps}}
+ \rput[lb](1.15in,0.05in){\scalebox{1.8}{\parbox{2.0in}{Gisselquist\\Technology, LLC}}}
+ \end{pspicture}}
+% TITLEPAGE
+%
+\def\titlepage{\setcounter{page}{1}
+ \typeout{^^JTitle Page.}
+ \thispagestyle{empty}
+ \leftline{\rput(0,0){\psline(0,0)(\textwidth,0)}\hfill}
+ \vskip 2\baselineskip
+ \logo\hfil % Original is 3.91 in x 1.26 in, let's match V thus
+ \vskip 2\baselineskip
+ \vspace*{10pt}\vfil
+ \begin{minipage}{\textwidth}\raggedleft
+ \ifproject{\Huge\bfseries\MakeUppercase\@project} \\\fi
+ \vspace*{15pt}
+ {\Huge\bfseries\MakeUppercase\@title} \\
+ \vskip 10\baselineskip
+ \Large \@author \\
+ \ifemail{\Large \@email}\\\fi
+ \vskip 6\baselineskip
+ \Large \usdate\@date \\
+ \end{minipage}
+ % \baselineskip 22.5pt\large\rm\MakeUppercase\ti@tle
+ \vspace*{30pt}
+ \vfil
+ \newpage\baselineskip=\normalbaselineskip}
+
+\newenvironment{license}{\clearpage\typeout{^^JLicense Page.}\ \vfill\noindent}%
+ {\vfill\newpage}
+% ****************************************
+% * CHAPTER DEFINITIONS *
+% ****************************************
+%
+\renewcommand\chapter{\if@openright\cleardoublepage\else\clearpage\fi
+ \thispagestyle{gqtekspecplain}%
+ \global\@topnum\z@
+ \@afterindentfalse
+ \secdef\@chapter\@schapter}
+\renewcommand\@makechapterhead[1]{%
+ \hbox to \textwidth{\hfil\scalebox{1.8}{\Huge\bfseries \thechapter.}}\vskip 10\p@
+ \hbox to \textwidth{\rput(0,0){\psline[linewidth=0.04in](0,0)(\textwidth,0)}}\vskip \p@
+ \hbox to \textwidth{\rput(0,0){\psline[linewidth=0.04in](0,0)(\textwidth,0)}}\vskip 10\p@
+ \hbox to \textwidth{\hfill\scalebox{1.8}{\huge\bfseries #1}}%
+ \par\nobreak\vskip 40\p@}
+\renewcommand\@makeschapterhead[1]{%
+ \hbox to \textwidth{\hfill\scalebox{1.8}{\huge\bfseries #1}}%
+ \par\nobreak\vskip 40\p@}
+% ****************************************
+% * INITIALIZATION *
+% ****************************************
+%
+% Default initializations
+
+\ps@gqtekspecplain % 'gqtekspecplain' page style with lowered page nos.
+\onecolumn % Single-column.
+\pagenumbering{roman} % the first chapter will change pagenumbering
+ % to arabic
+\setcounter{page}{1} % in case a titlepage is not requested
+ % otherwise titlepage sets page to 1 since the
+ % flyleaf is not counted as a page
+\widowpenalty 10000 % completely discourage widow lines
+\clubpenalty 10000 % completely discourage club (orphan) lines
+\raggedbottom % don't force alignment of bottom of pages
+
+\date{\today}
+\newif\ifproject\projectfalse
+\def\project#1{\projecttrue\gdef\@project{#1}}
+\def\@project{}
+\newif\ifemail\emailfalse
+\def\email#1{\emailtrue\gdef\@email{#1}}
+\def\@email{}
+\def\revision#1{\gdef\r@vision{#1}}
+\def\r@vision{}
+\def\at{\makeatletter @\makeatother}
+\newdateformat{theyear}{\THEYEAR}
+\newenvironment{revisionhistory}{\clearpage\typeout{^^JRevision History.}%
+ \hbox to \textwidth{\hfil\scalebox{1.8}{\large\bfseries Revision History}}\vskip 10\p@\noindent%
+ \begin{tabular}{|p{0.5in}|p{1in}|p{1in}|p{2.875in}|}\hline
+ \rowcolor[gray]{0.8} Rev. & Date & Author & Description\\\hline\hline}
+ {\end{tabular}\clearpage}
+\newenvironment{clocklist}{\begin{tabular}{|p{0.75in}|p{0.5in}|l|l|p{2.875in}|}\hline
+ \rowcolor[gray]{0.85} Name & Source & \multicolumn{2}{l|}{Rates (MHz)} & Description \\\hhline{~|~|-|-|~}%
+ \rowcolor[gray]{0.85} & & Max & Min & \\\hline\hline}%
+ {\end{tabular}}
+\newenvironment{reglist}{\begin{tabular}{|p{0.75in}|p{0.5in}|p{0.5in}|p{0.5in}|p{2.875in}|}\hline
+ \rowcolor[gray]{0.85} Name & Address & Width & Access & Description \\\hline\hline}%
+ {\end{tabular}}
+\newenvironment{bitlist}{\begin{tabular}{|p{0.5in}|p{0.5in}|p{3.875in}|}\hline
+ \rowcolor[gray]{0.85} Bit \# & Access & Description \\\hline\hline}%
+ {\end{tabular}}
+\newenvironment{portlist}{\begin{tabular}{|p{0.75in}|p{0.5in}|p{0.75in}|p{3.375in}|}\hline
+ \rowcolor[gray]{0.85} Port & Width & Direction & Description \\\hline\hline}%
+ {\end{tabular}}
+\newenvironment{wishboneds}{\begin{tabular}{|p{2.5in}|p{2.5in}|}\hline
+ \rowcolor[gray]{0.85} Description & Specification \\\hline\hline}%
+ {\end{tabular}}
+\newenvironment{preface}{\chapter*{Preface}}{\par\bigskip\bigskip\leftline{\hfill\@author}}
+\endinput
Index: doc/src/spec.tex
===================================================================
--- doc/src/spec.tex (nonexistent)
+++ doc/src/spec.tex (revision 2)
@@ -0,0 +1,562 @@
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+%%
+%% Filename: spec.tex
+%%
+%% Project: A Wishbone Controlled Real-Time clock Core
+%%
+%% Purpose: This LaTeX file contains all of the documentation/description
+%% currently provided with this FPGA Real-time Clock Core.
+%% It's not nearly as interesting as the PDF file it creates,
+%% so I'd recommend reading that before diving into this file.
+%% You should be able to find the PDF file in the SVN distribution
+%% together with this PDF file and a copy of the GPL-3.0 license
+%% this file is distributed under. If not, just type 'make'
+%% in the doc directory and it (should) build without a problem.
+%%
+%%
+%% Creator: Dan Gisselquist
+%% Gisselquist Technology, LLC
+%%
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+%%
+%% Copyright (C) 2015, Gisselquist Technology, LLC
+%%
+%% This program is free software (firmware): you can redistribute it and/or
+%% modify it under the terms of the GNU General Public License as published
+%% by the Free Software Foundation, either version 3 of the License, or (at
+%% your option) any later version.
+%%
+%% This program is distributed in the hope that it will be useful, but WITHOUT
+%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
+%% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+%% for more details.
+%%
+%% You should have received a copy of the GNU General Public License along
+%% with this program. (It's in the $(ROOT)/doc directory, run make with no
+%% target there if the PDF file isn't present.) If not, see
+%% for a copy.
+%%
+%% License: GPL, v3, as defined and found on www.gnu.org,
+%% http://www.gnu.org/licenses/gpl.html
+%%
+%%
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\documentclass{gqtekspec}
+\project{Real-Time Clock}
+\title{Specification}
+\author{Dan Gisselquist, Ph.D.}
+\email{dgisselq\at opencores.org}
+\revision{Rev.~0.1}
+\begin{document}
+\pagestyle{gqtekspecplain}
+\titlepage
+\begin{license}
+Copyright (C) \theyear\today, Gisselquist Technology, LLC
+
+This project is free software (firmware): you can redistribute it and/or
+modify it under the terms of the GNU General Public License as published
+by the Free Software Foundation, either version 3 of the License, or (at
+your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program. If not, see \hbox{ } for a
+copy.
+\end{license}
+\begin{revisionhistory}
+0.1 & 5/25/2015 & Gisselquist & First Draft \\\hline
+\end{revisionhistory}
+% Revision History
+% Table of Contents, named Contents
+\tableofcontents
+% \listoffigures
+\listoftables
+\begin{preface}
+Every FPGA project needs to start with a very simple core. Then, working
+from simplicity, more and more complex cores can be built until an eventual
+application comes from all the tiny details.
+
+This real time clock is one such simple core. All of the pieces to this
+clock are simple. Nothing is inherently complex. However, placing this
+clock into a larger FPGA structure requires a Wishbone bus, and being able
+to command and control an FPGA over a wishbone bus is an achievement in
+itself. Further, the clock produces seven segment display output values
+and LED output values. These are also simple outputs, but still take a lot
+of work to complete. Finally, this clock will strobe an interrupt line.
+Reading and processing that interrupt line requires a whole 'nuther bit of
+logic and the ability to capture, recognize, and respond to interrupts.
+Hence, once you get a simple clock working, you have a lot working.
+\end{preface}
+
+\chapter{Introduction}
+\pagenumbering{arabic}
+\setcounter{page}{1}
+
+This Real--Time Clock implements a twenty four hour clock, count-down timer,
+stopwatch
+and alarm. It is designed to be configurable to adjust to whatever clock
+speed the underlying architecture is running on, so with only minor changes
+should run on any fundamental clock rate from about 66~kHz on up to
+250~TeraHertz with varying levels of accuracy along the way.
+
+This clock offers a fairly full feature set of capability: time, alarms,
+a countdown timer and a stopwatch, all features which are available from the
+wishbone bus.
+
+Other interfaces exist as well.
+
+Should you wish to investigate your clock's
+stability or try to guarantee it's fine precision accuracy, it is possible to
+provide a time hack pulse to the clock and subsequently read what all of the
+internal registers were set to at that time.
+
+When either the count--down timer reaches zero or the clock reaches the alarm
+time (if set), the clock module will produce an impulse which can be used
+as an interrupt trigger.
+
+This clock will also provide outputs sufficient to drive an external seven
+segment display driver and 16 LED's.
+
+Future enhancements may allow for button control and fine precision clock
+adjustment.
+
+The layout of this specification follows the format set by OpenCores.
+This introduction is the first chapter. Following this introduction is
+a short chapter describing how this clock is implemented,
+Chapt.~\ref{chap:arch}. Following this description, the Chapt.~\ref{chap:ops}
+gives a brief overview of how to operate the clock. Most of the details,
+however, are in the registers and their definitions. These you can find in
+Chapt.~\ref{chap:regs}. As for the wishbone, the wishbone spec requires a
+wishbone datasheet which you can find in Chapt.~\ref{chap:wishbone}.
+That leaves the final pertinent information necessary for implementing this
+core in Chapt.~\ref{chap:ioports}, the definitions and meanings of the
+various I/O ports.
+
+As always, write me if you have any questions or problems.
+
+\chapter{Architecture}\label{chap:arch}
+
+Central to this real time clock architecture is a 48~bit sub--second register.
+This register is incremented every clock by a user defined 32~bit value,
+{\tt CKSPEED}.
+When the register turns over at the end of each second, a second has taken
+place and all of the various clock registers are adjusted.
+
+Well, not quite but almost. The 48~bit register is actually split into a
+lower 40~bit register that is common to all clock components, as well as
+separate eight bit upper registers for the clock, timer, and stopwatch. In
+this fashion, these separate components can have different definitions for
+when seconds begin and end, and with sufficient precision to satisfy most
+applications.
+
+The next thing to note about this architecture is the format of the various
+clock registers: Binary Coded Decimal, or BCD. Hence an {\tt 8'h59} refers
+to a value of 59, rather than 89. In this fashion, setting the time to
+{\tt 24'h231520} will set it to 23~hours, 15~minutes, and 20~seconds. The
+only exception to this BCD format are the subseconds fields found in the
+stopwatch and time hack registers. Seconds and above are all encoded as BCD.
+
+\chapter{Operation}\label{chap:ops}
+
+\section{Time}
+To set the time, simply write to the clock register the current value of the
+time. If the seconds hand is written as zero, subsecond time will be cleared
+as well. The new clock value takes place one clock period after the value
+is written to the bus.
+
+To set only some parts of the time and not others, such as the minutes but
+not seconds or hours, write all '1's to the seconds and hours. In this way,
+writing a {\tt 24'h3f17ff} will set the minutes to 17, but not affect the
+rest of the clock.
+
+This is also the way to adjust the display without adjusting time. Suppose
+you wish to switch to display option '1', just write a {\tt 32'h013fffff} to
+the register and the display will switch without adjusting time.
+
+\section{Count-down Timer}
+To use the count down timer, set it to the amount of time you wish to count
+down for. When ready, or even in the same cycle, enable the count--down
+timer by setting the RUN bit high. At this point in time, the count--down
+timer is running. When it gets to zero, it will stop and trigger an interrupt.
+You can tell if the alarm has been triggered by the TRIGGER bit being set.
+Any write to the timer register will clear the alarm condition.
+
+While the timer is running, writing a '0' to the timer register will stop it
+without clearing the time remaining. In this state, writing to the register
+the RUN bit by itself will restart the timer, while anything else will set the
+timer to a new value. Further, if the timer is stopped at zero, then writing
+zero to the timer will reset the timer to the last start time it had.
+
+\section{Stopwatch}
+The stop watch supports three operations: start, stop, and clear. Writing a
+'1' to the stop watch register will start the stopwatch, while writing a '0'
+will stop it. When it starts next, it will start where it left off unless the
+register is cleared. To clear the register and set it back to zero, write a
+'2' to the register. This will effectively stop the register and clear it in
+one step. If the register is already stopped, writing a '3' will clear and
+start it in one step. However, the register can only be cleared while stopped.
+If the register is running, writing a '3' will have no effect.
+
+\section{Alarm}
+To set the alarm, just write the alarm time to the alarm register together
+with alarm enable bit. As with the time register, setting any field,
+whether hours, minutes, or seconds, to {\tt 8'hff} has no effect on that
+field. Hence, the alarm may be activated by writing {\tt 25'h13fffff} to
+the register and deactivated by writing {\tt 25'h03fffff}.
+
+Once the alarm is tripped, the RTC core will generate an interrupt. Further,
+the tripped bit in the alarm register will be set. To clear this bit and the
+alarm tripped condition, either disable the alarm or write a '1' to this bit.
+
+\section{Time Hacks}
+
+For finer precision timing, the RTC module allows for setting a time
+hack and reading the value from the device. On the clock following the
+time hack being high, the internal state, to include the time and the 48~bit
+counter, will be recorded and may then be read out. In this fashion,
+it is possible to capture, with as much precision as the device offers,
+the current time within the device.
+
+It is the users responsibility to read the time hack registers before a
+subsequent time hack pulse sets them to new values.
+
+\chapter{Registers}\label{chap:regs}
+This RTC clock module supports eight registers, as listed in
+Tbl.~\ref{tbl:reglist}. Of these eight, the first four have been so placed
+as to be the more routine or user used registers, while the latter four are
+more lower level.
+\begin{table}[htbp]
+\begin{center}
+\begin{reglist}
+CLOCK & 0 & 32 & R/W & Wall clock time register\\\hline
+TIMER & 1 & 32 & R/W & Count--down timer\\\hline
+STPWTCH & 2 & 32 & R/W & Stopwatch control and value\\\hline
+ALARM & 3 & 32 & R/W & Alarm time, and setting\\\hline\hline
+CKSPEED & 4 & 32 & R/W & Clock speed control.\\\hline
+HACKTIME &5 & 32 & R & Wall clock time at last hack.\\\hline
+HACKCNTHI&6 & 32 & R & Wall clock time.\\\hline
+HACKCNTLO&7 & 32 & R & Wall clock time.\\\hline
+\end{reglist}\caption{List of Registers}\label{tbl:reglist}
+\end{center}\end{table}
+Each register will be discussed in detail in this chapter.
+
+\section{Clock Time Register}
+The various bit fields associated with the current time may be found in
+the {\tt CLOCK} register, shown in Tbl.~\ref{tbl:clockreg}.
+\begin{table}[htbp]\begin{center}
+\begin{bitlist}
+28--31 & R & Always return zero.\\\hline
+24--27 & R/W & Seven Segment Display Mode.\\\hline
+22--23 & R & Always return zero.\\\hline
+16--21 & R/W & Current time, BCD hours\\\hline
+8--15 & R/W & Current time, BCD minutes\\\hline
+0--7 & R/W & Current time, BCD seconds\\\hline
+\end{bitlist}
+\caption{Clock Time Register Bit Definitions}\label{tbl:clockreg}
+\end{center}\end{table}
+This register contains six clock digits: two each for hours, minutes, and
+seconds. Each of these digits is encoded in Binary Coded Decimal (BCD).
+Therefore, 23~hours would be encoded as 6'h23 and not 6'h17. Writes to each
+of the various subcomponent registers will set that register, unless the
+write value is a 8'hff. The behaviour of the clock when non--decimal
+values are written, other than all F's, is undefined.
+
+Separate from the time, however, is the seven segment display mode. Four
+values are currently supported: 4'h0 to display the hours and minutes,
+4'h1 to display the timer in minutes and seconds, 4'h2 to display the
+stopwatch in lower order minutes, seconds, and sixteenths of a second, and
+4'h3 to display the minutes and seconds of the current time. In all cases,
+the decimal point will appear to the right of the lowest order digit
+and will blink with the second hand. That is, the decimal will be high for
+the second half of any second, and low at the top of the second.
+
+\section{Countdown Timer Register}
+The countdown timer register, whose bit--wise values are shown in
+Tbl.~\ref{tbl:timer},
+\begin{table}[htbp]
+\begin{center}
+\begin{bitlist}
+26--31 & R & Unused, always read as '0'.\\\hline
+25 & R/W & Alarm condition. Write a '1' to clear.\\\hline
+24 & R/W & Running, stopped on '0'\\\hline
+16--23 & R/W & BCD Hours\\\hline
+8--15 & R/W & BCD Minutes\\\hline
+0--7 & R/W & BCD Seconds\\\hline
+\end{bitlist}
+\caption{Count--down Timer register}\label{tbl:timer}
+\end{center}\end{table}
+controls the operation of the count--down timer. To use this timer, write
+some amount of time to the register, then write zeros with bit 24 set. The
+register will then reach an alarm condition after counting down that amount
+of time. (Alternatively, you could set bit 24 while writing the register,
+to set and start it in one operation.) To stop the register while it is
+running, just write all zeros. To restart the register, provided more than a
+second remains, write a {\tt 26'h1000000} to set it running again. Once
+the timer alarms, the timer will stop and the alarm condition will be set.
+Any write to the timer register after the alarm condition has been set will
+clear the alarm condition.
+
+\section{Stopwatch Register}
+The various bits of the stopwatch register are shown in
+Tbl.~\ref{tbl:stopwatch}.
+\begin{table}[htbp]
+\begin{center}
+\begin{bitlist}
+24--31 & R & Hours\\\hline
+16--23 & R & Minutes\\\hline
+8--15 & R & Sub Seconds\\\hline
+1--7 & R & Sub Seconds\\\hline
+1 & W & Clear\\\hline
+0 & R/W & Running\\\hline
+\end{bitlist}
+\caption{Stopwatch Register}\label{tbl:stopwatch}
+\end{center}\end{table}
+Of note is the bottom bit that, when set, means the stop watch is running.
+Set this bit to '1' to start the stopwatch, or to '0' to stop the stopwatch.
+Further, while the stopwatch is stopped, a '1' can be written to the clear
+bit. This will zero out the stopwatch and set it back to zero.
+
+\section{Alarm Register}
+The various bits of the alarm register are shown in Tbl.~\ref{tbl:alarm}.
+\begin{table}[htbp]
+\begin{center}
+\begin{bitlist}
+26--31 & R & Always reads zeros. \\\hline
+25 & R/W & Alarm tripped. Write a '1' to this register to clear any alarm
+ condition. (A tripped alarm will not trip again.)\\\hline
+24 & R/W & Alarm enabled\\\hline
+16--23 & R & Alarm time, BCD hours\\\hline
+8--15 & R & Alarm time, BCD minutes\\\hline
+0--7 & R/W & Alarm time, BCD Seconds\\\hline
+\end{bitlist}
+\caption{Alarm Register}\label{tbl:alarm}
+\end{center}\end{table}
+Basically, the alarm register consists a time and two more bits. The extra
+two bits encode whether or not the alarm is enabled, and whether or not it has
+been tripped. The alarm will be {\em tripped} whenever it is enabled, and the
+time changes to equal the alarm time. Once tripped, the alarm will stay
+in the alarmed or tripped condition until either a '1' is written to the
+tripped bit, or the alarm is disabled.
+
+As with the clock and timer registers, writing eight ones to any of the
+BCD fields when writing to this register will leave those fields untouched.
+
+\section{Clock Speed Register}
+The actual speed of the clock is controlled by the {\tt CKSPEED} register,
+shown in Tbl.~\ref{tbl:ckspeed}.
+\begin{table}[htbp]
+\begin{center}
+\begin{bitlist}
+0--31 & R/W & 48~bit counter time increment\\\hline
+\end{bitlist}
+\caption{Clock Speed Register}\label{tbl:ckspeed}
+\end{center}\end{table}
+This register contains a simple 32~bit unsigned value. To step the clock,
+this value is extended to 48~bits and added to the fractional seconds value.
+
+This value should be set to $2^{48}$ divided by the clock frequency of the
+controlling clock. Hence, for a 100~MHz clock, this value would be set to
+{\tt 32'd2814750}. For clocks near 100~MHz, this allows adjusting speed
+within about 40~clocks per second. For clocks near 500~MHz, this allows
+time adjustment to an accuracy of about about 800~clocks per second. In
+both cases, this is good enough to maintain a clock with less than a
+microsecond loss over the course of a year. Hence, this RTC module provides
+more logical stability than most hardware clocks on the market today.
+
+\section{Time--hack time}
+To support finer precision clock control, the time--hack capability exists.
+This capability consists of three registers, the time--hack time register
+shown in Tbl.~\ref{tbl:hacktime},
+\begin{table}[htbp]
+\begin{center}
+\begin{bitlist}
+24--31 & R & BCD Hours.\\\hline
+16--23 & R & BCD Minutes.\\\hline
+8--15 & R & BCD seconds.\\\hline
+0--7 & R & Subseconds, encoded in 256ths of a second\\\hline
+\end{bitlist}
+\caption{Time Hack Time Register}\label{tbl:hacktime}
+\end{center}\end{table}
+and two registers (Tbls.~\ref{tbl:hackcnthi}
+\begin{table}[htbp]
+\begin{center}
+\begin{bitlist}
+0--31 & R & Upper 32 bits of the internal 40~bit counter.\\\hline
+\end{bitlist}
+\caption{Time Hack Counter, High}\label{tbl:hackcnthi}
+\end{center}\end{table}
+and~\ref{tbl:hackcntlo})
+\begin{table}[htbp]
+\begin{center}
+\begin{bitlist}
+24--31 & R & Bottom 8~bits of the internal 40~bit counter.\\\hline
+0--23 & R & Always read as '0'.\\\hline
+\end{bitlist}
+\caption{Time Hack Counter, Low}\label{tbl:hackcntlo}
+\end{center}\end{table}
+capturing the contents of the 40~bit internal counter at the time of the hack.
+
+The time--hack time register is perhaps the simplest to understand. This
+captures the time of the time--hack in hours, minutes, seconds, and 8~fractional
+subsecond bits. The top 24~bits of this register will match the bottom 24~bits
+of the clock~time register at the time of the time hack. The bottom eight
+bits are the top eight bits of the 48~bit subsecond time counter. The
+rest of those 48~bits may then be returned in the other two time hack counter
+registers.
+
+At present, this functionality isn't yet truly fully featured. Once fully
+featured, there will (should) be a mechanism for adjusting this counter based
+upon information gleaned from the hack time. Implementation details have
+to date prevented this portion of the design from being implemented.
+
+\chapter{Wishbone Datasheet}\label{chap:wishbone}
+Tbl.~\ref{tbl:wishbone}
+\begin{table}[htbp]
+\begin{center}
+\begin{wishboneds}
+Revision level of wishbone & WB B4 spec \\\hline
+Type of interface & Slave, Read/Write \\\hline
+Port size & 32--bit \\\hline
+Port granularity & 32--bit \\\hline
+Maximum Operand Size & 32--bit \\\hline
+Data transfer ordering & (Irrelevant) \\\hline
+Clock constraints & Faster than 66~kHz \\\hline
+Signal Names & \begin{tabular}{ll}
+ Signal Name & Wishbone Equivalent \\\hline
+ {\tt i\_clk} & {\tt CLK\_I} \\
+ {\tt i\_wb\_cyc} & {\tt CYC\_I} \\
+ {\tt i\_wb\_stb} & {\tt STB\_I} \\
+ {\tt i\_wb\_we} & {\tt WE\_I} \\
+ {\tt i\_wb\_addr} & {\tt ADR\_I} \\
+ {\tt i\_wb\_data} & {\tt DAT\_I} \\
+ {\tt o\_wb\_ack} & {\tt ACK\_O} \\
+ {\tt o\_wb\_stall} & {\tt STALL\_O} \\
+ {\tt o\_wb\_data} & {\tt DAT\_O}
+ \end{tabular}\\\hline
+\end{wishboneds}
+\caption{Wishbone Datasheet}\label{tbl:wishbone}
+\end{center}\end{table}
+is required by the wishbone specification, and so
+it is included here. The big thing to notice is that this real time clock
+acts as a wishbone slave, and that all accesses to the
+clock registers are 32--bit reads and writes. The address bus does not offer
+byte level, but rather 32--bit word level resolution. Select lines are not
+implemented. Bit ordering is the normal ordering where bit~31 is the most
+significant bit and so forth. Although the stall line is implemented, it is
+always zero. Access delays are a single clock, so the clock after a read or
+write is placed on the bus the {\tt i\_wb\_ack} line will be high.
+
+\iffalse
+\chapter{Clocks}\label{chap:clocks}
+
+This core is based upon the Basys--3 design. The Basys--3 development board
+contains one external 100~MHz clock, which is sufficient to run this
+core. The logic within the core can also be run faster, or slower, as is
+necessary to meet the timing constraints associated with the internal
+operations of the core and it's surrounding environment. See
+Table.~\ref{tbl:clocks}.
+\begin{table}[htbp]
+\begin{center}
+\begin{clocklist}
+i\_clk & External & 250~THz & 66~kHz & System clock.\\\hline
+\end{clocklist}
+\caption{List of Clocks}\label{tbl:clocks}
+\end{center}\end{table}
+
+\fi
+
+\chapter{I/O Ports}\label{chap:ioports}
+The I/O ports for this core are shown in Tbls.~\ref{tbl:iowishbone}
+\begin{table}[htbp]
+\begin{center}
+\begin{portlist}
+i\_wb\_cyc & 1 & Input & Wishbone bus cycle wire.\\\hline
+i\_wb\_stb & 1 & Input & Wishbone strobe.\\\hline
+i\_wb\_we & 1 & Input & Wishbone write enable.\\\hline
+i\_wb\_addr & 5 & Input & Wishbone address.\\\hline
+i\_wb\_data & 32 & Input & Wishbone bus data register for use when writing
+ (configuring) the core from the bus.\\\hline
+o\_wb\_ack & 1 & Output & Return value acknowledging a wishbone write, or
+ signifying valid data in the case of a wishbone read request.
+ \\\hline
+o\_wb\_stall & 1 & Output & Indicates the device is not yet ready for another
+ wishbone access, effectively stalling the bus.\\\hline
+o\_wb\_data & 32 & Output & Wishbone data bus, returning data values read
+ from the interface.\\\hline
+\end{portlist}
+\caption{Wishbone I/O Ports}\label{tbl:iowishbone}
+\end{center}\end{table}
+and~Tbl.~\ref{tbl:ioother}.
+\begin{table}[htbp]
+\begin{center}
+\begin{portlist}
+o\_sseg & 32 & Output & Lines to control a seven segment display, to be
+ sent to that display's driver. Each eight bit byte controls
+ one digit in the display, with the bottom bit in the byte
+ controlling the decimal point.\\\hline
+o\_led & 16 & Output & Output LED's, consisting of a 16--bit counter counting
+ from zero to all ones each minute, and synchronized with each
+ minute so as to create an indicator of when the next minute
+ will take place when only the hours and minutes can be
+ displayed.\\\hline
+o\_interrupt & 1 & Output & A pulsed/strobed interrupt line. When the
+ clock needs to generate an interrupt, it will set this line
+ high for one clock cycle. \\\hline
+i\_hack & 1 & Input & When this line is raised, copies are made of the
+ internal state registers on the next clock. These registers can then
+ be used for an accurate time hack regarding the state of the clock
+ at the time this line was strobed.\\\hline
+\end{portlist}
+\caption{Other I/O Ports}\label{tbl:ioother}
+\end{center}\end{table}
+Tbl.~\ref{tbl:iowishbone} reiterates the wishbone I/O values just discussed in
+Chapt.~\ref{chap:wishbone}, and so need no further discussion here.
+
+This clock is designed for command and control via the wishbone. No other
+registers, beyond the wishbone bus, are required. However, several other
+may be valuable. These other registers are listed in Tbl.~\ref{tbl:ioother}.
+We'll discuss each of these in turn.
+
+First of the other I/O registers is the {\tt o\_sseg} register. This register
+encodes which outputs of a seven segment display need to be turned on to
+represent the value of the clock requested. This register consists of four
+eight bit bytes, with the highest order byte referencing the highest order
+display segment value. In each byte, the low order bit references a decimal
+point. The other bits are ordered around the zero, with the top bit being
+the top bar of a '0', the next highest order bit and so on following the
+zero clockwise. The final bit of each byte, the bit in the two's place,
+encodes whether or not the middle line is to be displayed. When either timer
+or alarm is triggered, this display will blink until the triggering conditions
+are cleared.
+
+This output is expected to be the input to a seven segment display driver,
+rather than being the output to the display itself.
+
+The next output lines are the 16~lines of the {\tt o\_led} bus. When connected
+with 16~LED's, these lines will create a counting display that will count up
+to each minute, synchronized to the minute. When either timer or alarm has
+triggered, all of the LED's will flash together until the triggered condition
+is reset.
+
+The third other line is the {\tt o\_interrupt} line. This line will be
+strobed by the RTC module any time the alarm is triggered or the timer runs
+out. The line will not remain high, but neither will it trigger a second
+time until the underlying interrupt is cleared. That is, the timer will only
+trigger once until cleared as will the alarm, but the alarm may trigger after
+the timer has triggered and before the timer clears.
+
+The final other I/O line is a simple input line. This line is expected to be
+strobed for one clock cycle any time a time hack is required. For example,
+should you wish to read and synchronize to a GPS PPS signal, strobe the device
+with the PPS (after dealing with any metastability issues), and read the time
+hacks that are produced.
+
+% Appendices
+% Index
+\end{document}
+
+
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+ dvips -q -z -t letter -P pdf -o gpl-3.0.ps gpl-3.0.dvi
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+ cd $(DSRC)/; latex spec.tex
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