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URL https://opencores.org/ocsvn/rtcclock/rtcclock/trunk

Subversion Repositories rtcclock

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  • This comparison shows the changes necessary to convert path 
    /rtcclock/trunk
    from Rev 3 to Rev 4
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  •

Rev 3 → Rev 4

/rtl/rtcclock.v
160,8 → 160,8
assign tm_alarm = timer[25];
reg [23:0] tm_start;
reg [7:0] tm_sub;
initial tm_start = 16'h00;
initial timer = 18'h00;
initial tm_start = 24'h00;
initial timer = 26'h00;
initial tm_int = 1'b0;
initial tm_pps = 1'b0;
always @(posedge i_clk)
251,7 → 251,7
reg [7:0] sw_sub;
wire sw_running;
assign sw_running = stopwatch[0];
initial stopwatch = 32'h00001;
initial stopwatch = 32'h00000;
always @(posedge i_clk)
begin
sw_pps <= 1'b0;
402,6 → 402,8
reg r_hack_carry;
reg [29:0] hack_time;
reg [39:0] hack_counter;
initial hack_time = 30'h0000;
initial hack_counter = 40'h0000;
always @(posedge i_clk)
if (i_hack)
begin
418,19 → 420,37
end
 
reg [15:0] h_sseg;
reg [3:0] dmask;
always @(posedge i_clk)
case(clock[27:24])
4'h0: h_sseg <= { 2'b00, ck_last_clock[21:8] };
4'h1: h_sseg <= timer[15:0];
4'h2: h_sseg <= stopwatch[19:4];
4'h3: h_sseg <= ck_last_clock[15:0];
default: h_sseg <= { 2'b00, ck_last_clock[21:8] };
4'h1: begin h_sseg <= timer[15:0];
if (tm_alarm) dmask <= 4'hf;
else begin
dmask[3] <= (12'h000 != timer[23:12]); // timer[15:12]
dmask[2] <= (16'h000 != timer[23: 8]); // timer[11: 8]
dmask[1] <= (20'h000 != timer[23: 4]); // timer[ 7: 4]
dmask[0] <= 1'b1; // Always on
end end
4'h2: begin h_sseg <= stopwatch[19:4];
dmask[3] <= (12'h00 != stopwatch[27:16]);
dmask[2] <= (16'h000 != stopwatch[27:12]);
dmask[1] <= 1'b1; // Always on, stopwatch[11:8]
dmask[0] <= 1'b1; // Always on, stopwatch[7:4]
end
4'h3: begin h_sseg <= ck_last_clock[15:0];
dmask[3:0] <= 4'hf;
end
default: begin // 4'h0
h_sseg <= { 2'b00, ck_last_clock[21:8] };
dmask[2:0] <= 3'hf;
dmask[3] <= (2'b00 != ck_last_clock[21:20]);
end
endcase
 
wire [31:0] w_sseg;
assign w_sseg[ 0] = (~ck_sub[7]);
assign w_sseg[ 8] = 1'b0;
assign w_sseg[16] = 1'b0;
assign w_sseg[ 0] = (~ck_sub[7]);
assign w_sseg[ 8] = (clock[27:24] == 4'h2);
assign w_sseg[16] = ((clock[27:24] == 4'h0)&&(~ck_sub[7]))||(clock[27:24] == 4'h3);
assign w_sseg[24] = 1'b0;
hexmap ha(i_clk, h_sseg[ 3: 0], w_sseg[ 7: 1]);
hexmap hb(i_clk, h_sseg[ 7: 4], w_sseg[15: 9]);
441,7 → 461,11
if ((tm_alarm || al_tripped)&&(ck_sub[7]))
o_sseg <= 32'h0000;
else
o_sseg <= w_sseg;
o_sseg <= {
(dmask[3])?w_sseg[31:24]:8'h00,
(dmask[2])?w_sseg[23:16]:8'h00,
(dmask[1])?w_sseg[15: 8]:8'h00,
(dmask[0])?w_sseg[ 7: 0]:8'h00 };
 
reg [17:0] ledreg;
always @(posedge i_clk)
449,7 → 473,10
ledreg <= 18'h00;
else if (ck_carry)
ledreg <= ledreg + 18'h11;
assign o_led = (tm_alarm||al_tripped)?{ (16){ck_sub[7]}}:ledreg[17:2];
assign o_led = (tm_alarm||al_tripped)?{ (16){ck_sub[7]}}:
{ ledreg[17:10],
ledreg[10], ledreg[11], ledreg[12], ledreg[13],
ledreg[14], ledreg[15], ledreg[16], ledreg[17] };
 
assign o_interrupt = tm_int || al_int;
 
456,7 → 483,7
always @(posedge i_clk)
case(i_wb_addr[2:0])
3'b000: o_data <= { clock[31:22], ck_last_clock };
3'b001: o_data <= { 14'h00, timer };
3'b001: o_data <= { 6'h00, timer };
3'b010: o_data <= stopwatch;
3'b011: o_data <= { 6'h00, al_tripped, al_enabled, 2'b00, alarm_time };
3'b100: o_data <= ckspeed;
/doc/spec.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/doc/src/gqtekspec.cls
235,13 → 235,13
\@afterindentfalse
\secdef\@chapter\@schapter}
\renewcommand\@makechapterhead[1]{%
\hbox to \textwidth{\hfil\scalebox{1.8}{\Huge\bfseries \thechapter.}}\vskip 10\p@
\hbox to \textwidth{\hfil{\Huge\bfseries \thechapter.}}\vskip 10\p@
\hbox to \textwidth{\rput(0,0){\psline[linewidth=0.04in](0,0)(\textwidth,0)}}\vskip \p@
\hbox to \textwidth{\rput(0,0){\psline[linewidth=0.04in](0,0)(\textwidth,0)}}\vskip 10\p@
\hbox to \textwidth{\hfill\scalebox{1.8}{\huge\bfseries #1}}%
\hbox to \textwidth{\hfill{\Huge\bfseries #1}}%
\par\nobreak\vskip 40\p@}
\renewcommand\@makeschapterhead[1]{%
\hbox to \textwidth{\hfill\scalebox{1.8}{\huge\bfseries #1}}%
\hbox to \textwidth{\hfill{\Huge\bfseries #1}}%
\par\nobreak\vskip 40\p@}
% ****************************************
% * INITIALIZATION *
/doc/src/spec.tex
45,7 → 45,7
\project{Real-Time Clock}
\title{Specification}
\author{Dan Gisselquist, Ph.D.}
\email{dgisselq\at opencores.org}
\email{dgisselq (at) opencores.org}
\revision{Rev.~0.1}
\begin{document}
\pagestyle{gqtekspecplain}

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