OpenCores
URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /rtf65002/trunk
    from Rev 22 to Rev 23
    ↔ Reverse comparison
  •

Rev 22 → Rev 23

/rtl/verilog/byte_jsl.v
43,7 → 43,6
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
91,7 → 90,6
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
139,7 → 137,6
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
188,7 → 185,6
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
/rtl/verilog/byte_jsr.v
43,7 → 43,6
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
92,7 → 91,6
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
163,7 → 161,6
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
/rtl/verilog/decode.v
43,7 → 43,7
`INY: begin res <= y + 32'd1; pc <= pc + 32'd1; end
`DEA: begin res <= acc - 32'd1; pc <= pc + 32'd1; end
`INA: begin res <= acc + 32'd1; pc <= pc + 32'd1; end
`TSX: begin res <= isp; pc <= pc + 32'd1; end
`TSX,`TSA: begin res <= isp; pc <= pc + 32'd1; end
`TXS,`TXA,`TXY: begin res <= x; pc <= pc + 32'd1; end
`TAX,`TAY,`TAS: begin res <= acc; pc <= pc + 32'd1; end
`TYA,`TYX: begin res <= y; pc <= pc + 32'd1; end
61,6 → 61,7
4'h6: res <= dp8;
4'h7: res <= abs8;
4'h8: res <= {vbr[31:1],nmoi};
4'h9: res <= derr_address;
4'hE: res <= {spage[31:8],sp};
4'hF: res <= isp;
endcase
125,6 → 126,8
`LDX_IMM16,`LDA_IMM16: begin res <= {{16{ir[23]}},ir[23:8]}; pc <= pc + 32'd3; end
`LDX_IMM8,`LDA_IMM8: begin res <= {{24{ir[15]}},ir[15:8]}; pc <= pc + 32'd2; end
 
`SUB_SP: begin res <= isp - {{24{ir[15]}},ir[15:8]}; pc <= pc + 32'd2; end
 
`LDX_ZPX,`LDY_ZPX:
begin
radr <= zpx32xy_address;
190,6 → 193,13
pc <= pc + 32'd4;
state <= STORE1;
end
`ST_DSP:
begin
wadr <= {{24{ir[23]}},ir[23:16]} + isp;
wdat <= rfoa;
pc <= pc + 32'd3;
state <= STORE1;
end
`ST_ABS:
begin
wadr <= ir[47:16];
264,6 → 274,15
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`ADD_DSP,`SUB_DSP,`OR_DSP,`AND_DSP,`EOR_DSP:
begin
a <= rfoa;
Rt <= ir[15:12];
radr <= {{24{ir[23]}},ir[23:16]} + isp;
pc <= pc + 32'd3;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX:
begin
a <= rfoa;
704,6 → 723,8
state <= LOAD_MAC1;
pc <= pc + 32'd2;
end
`MVN: state <= MVN1;
`MVP: state <= MVP1;
default: // unimplemented opcode
begin
radr <= isp_dec;
/rtl/verilog/php.v
47,7 → 47,6
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
/rtl/verilog/rtf65002d.v
100,6 → 100,7
`define ADD_ABS 8'h6D
`define ADD_ABSX 8'h7D
`define ADD_RIND 8'h72
`define ADD_DSP 8'h63
 
`define SUB_IMM8 8'hE5
`define SUB_IMM16 8'hF9
110,6 → 111,7
`define SUB_ABS 8'hED
`define SUB_ABSX 8'hFD
`define SUB_RIND 8'hF2
`define SUB_DSP 8'hE3
 
// CMP = SUB r0,....
 
163,6 → 165,7
`define AND_ABSY 8'h39
`define AND_RIND 8'h32
`define AND_I 8'h32
`define AND_DSP 8'h23
 
`define OR_IMM8 8'h05
`define OR_IMM16 8'h19
173,6 → 176,7
`define OR_ABS 8'h0D
`define OR_ABSX 8'h1D
`define OR_RIND 8'h12
`define OR_DSP 8'h03
 
`define ORA_IMM 8'h09
`define ORA_ZP 8'h05
197,6 → 201,7
`define EOR_ABSY 8'h59
`define EOR_RIND 8'h52
`define EOR_I 8'h52
`define EOR_DSP 8'h43
 
// LD is OR rt,r0,....
 
206,6 → 211,7
`define ST_ABS 8'h8D
`define ST_ABSX 8'h9D
`define ST_RIND 8'h92
`define ST_DSP 8'h83
 
`define ORB_ZPX 8'hB5
`define ORB_IX 8'hA1
376,6 → 382,9
`define BEQ_RR 8'hE2
`define INT0 8'hDC
`define INT1 8'hDD
`define SUB_SP 8'h4B
`define MVP 8'h44
`define MVN 8'h54
 
`define NOTHING 4'd0
`define SR_70 4'd1
392,6 → 401,7
`define IA_70 4'd12
`define IA_158 4'd13
`define BYTE_71 4'd14
`define WORD_312 4'd15
 
module icachemem(wclk, wr, adr, dat, rclk, pc, insn);
input wclk;
746,6 → 756,11
parameter INSN_BUS_ERROR = 7'd106;
parameter LOAD_MAC1 = 7'd107;
parameter LOAD_MAC2 = 7'd108;
parameter MVN1 = 7'd109;
parameter MVN2 = 7'd110;
parameter MVN3 = 7'd111;
parameter MVP1 = 7'd112;
parameter MVP2 = 7'd113;
 
input rst_md; // reset mode, 1=emulation mode, 0=native mode
input rst_i;
799,6 → 814,7
wire [31:0] isp_dec = isp - 32'd1;
wire [31:0] isp_inc = isp + 32'd1;
reg [31:0] pc;
reg [31:0] opc;
wire [31:0] pcp1 = pc + 32'd1;
wire [31:0] pcp2 = pc + 32'd2;
wire [31:0] pcp3 = pc + 32'd3;
876,6 → 892,7
wire [31:0] rdat;
reg [3:0] load_what;
reg [3:0] store_what;
reg [31:0] derr_address;
reg imiss;
reg dmiss;
reg icacheOn,dcacheOn;
907,6 → 924,7
wire isRTI = ir[7:0]==`RTI;
wire isRTL = ir[7:0]==`RTL;
wire isRTS = ir[7:0]==`RTS;
wire isMove = ir[7:0]==`MVP || ir[7:0]==`MVN;
wire ld_muldiv = state==DECODE && ir[7:0]==`RR;
wire md_done;
wire clk;
1293,13 → 1311,17
begin
radr <= isp_dec;
wadr <= isp_dec;
wdat <= pc;
wdat <= opc;
if (em | isOrb | isStb)
derr_address <= adr_o[31:0];
else
derr_address <= adr_o[33:2];
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {isp_dec,2'b00};
dat_o <= pc;
dat_o <= opc;
vect <= {vbr[31:9],9'd508,2'b00};
state <= IRQ1;
end
1307,17 → 1329,56
begin
radr <= isp_dec;
wadr <= isp_dec;
wdat <= pc;
wdat <= opc;
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {isp_dec,2'b00};
dat_o <= pc;
dat_o <= opc;
vect <= {vbr[31:9],9'd509,2'b00};
state <= IRQ1;
end
 
MVN1:
begin
radr <= x;
x <= x + 32'd1;
retstate <= MVN2;
load_what <= `WORD_312;
state <= LOAD_MAC1;
end
MVN2:
begin
wadr <= y;
wdat <= b;
y <= y + 32'd1;
acc <= acc - 32'd1;
state <= STORE1;
end
MVN3:
begin
state <= IFETCH;
if (acc==32'hFFFFFFFF)
pc <= pc + 32'd1;
end
MVP1:
begin
radr <= x;
x <= x - 32'd1;
retstate <= MVP2;
load_what <= `WORD_312;
state <= LOAD_MAC1;
end
MVP2:
begin
wadr <= y;
wdat <= b;
y <= y - 32'd1;
acc <= acc - 32'd1;
state <= STORE1;
end
 
endcase
 
`include "cache_controller.v"
/rtl/verilog/store.v
48,7 → 48,10
// Clear any previously set lock status
STORE2:
if (ack_i) begin
state <= IFETCH;
if (isMove)
state <= MVN3;
else
state <= IFETCH;
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
63,7 → 66,10
else if (write_allocate) begin
dmiss <= `TRUE;
state <= WAIT_DHIT;
retstate <= IFETCH;
if (isMove)
retstate <= MVN3;
else
retstate <= IFETCH;
end
end
else if (err_i) begin
72,7 → 78,6
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
/rtl/verilog/load_mac.v
43,6 → 43,11
res <= rdat;
state <= IFETCH;
end
`WORD_312:
begin
b <= rdat;
state <= retstate;
end
`BYTE_70:
begin
b8 <= rdat8;
191,6 → 196,11
res <= dat_i;
state <= IFETCH;
end
`WORD_312:
begin
b <= dat_i;
state <= retstate;
end
`BYTE_70:
begin
b8 <= dati;
326,7 → 336,6
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
state <= BUS_ERROR;
end
/rtl/verilog/ifetch.v
22,6 → 22,7
//
IFETCH:
begin
opc <= pc;
if (nmi_edge & !imiss & gie) begin // imiss indicates cache controller is active and this state is in a waiting loop
nmi_edge <= 1'b0;
wai <= 1'b0;
220,7 → 221,7
case(ir[7:0])
`TAY,`TXY,`DEY,`INY: begin y <= res; nf <= resn32; zf <= resz32; end
`TAX,`TYX,`TSX,`DEX,`INX: begin x <= res; nf <= resn32; zf <= resz32; end
`TAS,`TXS: begin isp <= res; gie <= 1'b1; end
`TAS,`TXS,`SUB_SP: begin isp <= res; gie <= 1'b1; end
`TSA,`TYA,`TXA,`INA,`DEA: begin acc <= res; nf <= resn32; zf <= resz32; end
`TRS:
begin

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.