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Rev 29 → Rev 30

/trunk/rtl/verilog/RTF65002PIC.v
2,7 → 2,7
//=============================================================================
// (C) 2013 Robert Finch
// All rights reserved.
// robfinch@Opencores.org
// robfinch<remove>@Opencores.org
//
// RTF65002PIC.v
//
50,6 → 50,14
// this register enables the interrupt indicated
// by the low order four bits of the input data
//
// 4 - write only
// this register indicates which interrupt inputs are
// edge sensitive
//
// 5 - write only
// This register resets the edge sense circuitry
// indicated by the low order four bits of the input data.
//
// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// |WISHBONE Datasheet
// |WISHBONE SoC Architecture Specification, Revision B.3
113,6 → 121,11
reg [15:0] ie; // interrupt enable register
reg ack1;
reg [3:0] irqenc;
wire [15:0] i = {i15,i14,i13,i12,i11,i10,i9,i8,i7,i6,i5,i4,i3,i2,i1,nmii};
reg [15:0] ib;
reg [15:0] iedge;
reg [15:0] rste;
reg [15:0] es;
 
wire cs = cyc_i && stb_i && adr_i[33:6]==pIOAddress[31:4];
assign vol_o = cs;
123,17 → 136,25
 
// write registers
always @(posedge clk_i)
if (rst_i)
if (rst_i) begin
ie <= 16'h0;
else if (cs & we_i)
case (adr_i[3:2])
2'd0,2'd1:
begin
ie[15:0] <= dat_i[15:0];
end
2'd2,2'd3:
ie[dat_i[3:0]] <= adr_i[2];
endcase
rste <= 16'h0;
end
else begin
rste <= 16'h0;
if (cs & we_i) begin
case (adr_i[4:2])
3'd0,3'd1:
begin
ie[15:0] <= dat_i[15:0];
end
3'd2,3'd3:
ie[dat_i[3:0]] <= adr_i[2];
3'd4: es <= dat_i[15:0];
3'd5: rste[dat_i[3:0]] <= 1'b1;
endcase
end
end
 
// read registers
always @(posedge clk_i)
152,28 → 173,27
assign irqo = irqenc != 4'h0;
assign nmio = nmii & ie[0];
 
// irq requests are latched on every clock edge to prevent
// Edge detect circuit
integer n;
always @(posedge clk_i)
begin
for (n = 1; n < 16; n = n + 1)
begin
ib[n] <= i[n];
if (i[n] & !ib[n]) iedge[n] <= 1'b1;
if (rste[n]) iedge[n] <= 1'b0;
end
end
 
// irq requests are latched on every rising clock edge to prevent
// misreads
// nmi is not encoded
always @(posedge clk_i)
case (1'b1)
i1&ie[1]: irqenc <= 4'd1;
i2&ie[2]: irqenc <= 4'd2;
i3&ie[3]: irqenc <= 4'd3;
i4&ie[4]: irqenc <= 4'd4;
i5&ie[5]: irqenc <= 4'd5;
i6&ie[6]: irqenc <= 4'd6;
i7&ie[7]: irqenc <= 4'd7;
i8&ie[8]: irqenc <= 4'd8;
i9&ie[9]: irqenc <= 4'd9;
i10&ie[10]: irqenc <= 4'd10;
i11&ie[11]: irqenc <= 4'd11;
i12&ie[12]: irqenc <= 4'd12;
i13&ie[13]: irqenc <= 4'd13;
i14&ie[14]: irqenc <= 4'd14;
i15&ie[15]: irqenc <= 4'd15;
default: irqenc <= 4'd0;
endcase
begin
irqenc <= 4'd0;
for (n = 15; n > 0; n = n - 1)
if (ie[n] & (es[n] ? iedge[n] : i[n])) irqenc <= n;
end
 
assign vecno = pVECNO|irqenc;
 
/trunk/rtl/verilog/rtf65002_defines.v
0,0 → 1,454
`timescale 1ns / 1ps
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// rtf65002.v
// - 32 bit CPU
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
`define TRUE 1'b1
`define FALSE 1'b0
 
//`define SUPPORT_ICACHE 1'b1
`define SUPPORT_DCACHE 1'b1
`define SUPPORT_BCD 1'b1
`define SUPPORT_DIVMOD 1'b1
//`define SUPPORT_EM8 1'b1
//`define SUPPORT_BYTE_IRQ 1'b1
`define SUPPORT_EXEC 1'b1
`define SUPPORT_BERR 1'b1
`define SUPPORT_STRING 1'b1
`define SUPPORT_SHIFT 1'b1
 
`define RST_VECT 34'h3FFFFFFF8
`define NMI_VECT 34'h3FFFFFFF4
`define IRQ_VECT 34'h3FFFFFFF0
`define BRK_VECTNO 9'd0
`define SLP_VECTNO 9'd1
`define BYTE_RST_VECT 34'h00000FFFC
`define BYTE_NMI_VECT 34'h00000FFFA
`define BYTE_IRQ_VECT 34'h00000FFFE
 
`define BRK 8'h00
`define RTI 8'h40
`define RTS 8'h60
`define PHP 8'h08
`define CLC 8'h18
`define PLP 8'h28
`define SEC 8'h38
`define PHA 8'h48
`define CLI 8'h58
`define PLA 8'h68
`define SEI 8'h78
`define DEY 8'h88
`define TYA 8'h98
`define TAY 8'hA8
`define CLV 8'hB8
`define INY 8'hC8
`define CLD 8'hD8
`define INX 8'hE8
`define SED 8'hF8
`define ROR_ACC 8'h6A
`define TXA 8'h8A
`define TXS 8'h9A
`define TAX 8'hAA
`define TSX 8'hBA
`define DEX 8'hCA
`define NOP 8'hEA
`define TXY 8'h9B
`define TYX 8'hBB
`define TAS 8'h1B
`define TSA 8'h3B
`define TRS 8'h8B
`define TSR 8'hAB
`define STP 8'hDB
`define NAT 8'hFB
`define EMM 8'hFB
`define INA 8'h1A
`define DEA 8'h3A
 
`define RR 8'h02
`define ADD_RR 4'd0
`define SUB_RR 4'd1
`define CMP_RR 4'd2
`define AND_RR 4'd3
`define EOR_RR 4'd4
`define OR_RR 4'd5
`define MUL_RR 4'd8
`define MULS_RR 4'd9
`define DIV_RR 4'd10
`define DIVS_RR 4'd11
`define MOD_RR 4'd12
`define MODS_RR 4'd13
`define ASL_RRR 4'd14
`define LSR_RRR 4'd15
`define LD_RR 8'h7B
 
`define ADD_IMM8 8'h65 // 8 bit operand
`define ADD_IMM16 8'h79 // 16 bit operand
`define ADD_IMM32 8'h69 // 32 bit operand
`define ADD_ZPX 8'h75 // there is no ZP mode, use R0 to syntheisze
`define ADD_IX 8'h61
`define ADD_IY 8'h71
`define ADD_ABS 8'h6D
`define ADD_ABSX 8'h7D
`define ADD_RIND 8'h72
`define ADD_DSP 8'h63
 
`define SUB_IMM8 8'hE5
`define SUB_IMM16 8'hF9
`define SUB_IMM32 8'hE9
`define SUB_ZPX 8'hF5
`define SUB_IX 8'hE1
`define SUB_IY 8'hF1
`define SUB_ABS 8'hED
`define SUB_ABSX 8'hFD
`define SUB_RIND 8'hF2
`define SUB_DSP 8'hE3
 
// CMP = SUB r0,....
 
`define ADC_IMM 8'h69
`define ADC_ZP 8'h65
`define ADC_ZPX 8'h75
`define ADC_IX 8'h61
`define ADC_IY 8'h71
`define ADC_ABS 8'h6D
`define ADC_ABSX 8'h7D
`define ADC_ABSY 8'h79
`define ADC_I 8'h72
 
`define SBC_IMM 8'hE9
`define SBC_ZP 8'hE5
`define SBC_ZPX 8'hF5
`define SBC_IX 8'hE1
`define SBC_IY 8'hF1
`define SBC_ABS 8'hED
`define SBC_ABSX 8'hFD
`define SBC_ABSY 8'hF9
`define SBC_I 8'hF2
 
`define CMP_IMM8 8'hC5
`define CMP_IMM32 8'hC9
`define CMP_IMM 8'hC9
`define CMP_ZP 8'hC5
`define CMP_ZPX 8'hD5
`define CMP_IX 8'hC1
`define CMP_IY 8'hD1
`define CMP_ABS 8'hCD
`define CMP_ABSX 8'hDD
`define CMP_ABSY 8'hD9
`define CMP_I 8'hD2
 
 
`define LDA_IMM8 8'hA5
`define LDA_IMM16 8'hB9
`define LDA_IMM32 8'hA9
 
`define AND_IMM8 8'h25
`define AND_IMM16 8'h39
`define AND_IMM32 8'h29
`define AND_IMM 8'h29
`define AND_ZP 8'h25
`define AND_ZPX 8'h35
`define AND_IX 8'h21
`define AND_IY 8'h31
`define AND_ABS 8'h2D
`define AND_ABSX 8'h3D
`define AND_ABSY 8'h39
`define AND_RIND 8'h32
`define AND_I 8'h32
`define AND_DSP 8'h23
 
`define OR_IMM8 8'h05
`define OR_IMM16 8'h19
`define OR_IMM32 8'h09
`define OR_ZPX 8'h15
`define OR_IX 8'h01
`define OR_IY 8'h11
`define OR_ABS 8'h0D
`define OR_ABSX 8'h1D
`define OR_RIND 8'h12
`define OR_DSP 8'h03
 
`define ORA_IMM 8'h09
`define ORA_ZP 8'h05
`define ORA_ZPX 8'h15
`define ORA_IX 8'h01
`define ORA_IY 8'h11
`define ORA_ABS 8'h0D
`define ORA_ABSX 8'h1D
`define ORA_ABSY 8'h19
`define ORA_I 8'h12
 
`define EOR_IMM 8'h49
`define EOR_IMM8 8'h45
`define EOR_IMM16 8'h59
`define EOR_IMM32 8'h49
`define EOR_ZP 8'h45
`define EOR_ZPX 8'h55
`define EOR_IX 8'h41
`define EOR_IY 8'h51
`define EOR_ABS 8'h4D
`define EOR_ABSX 8'h5D
`define EOR_ABSY 8'h59
`define EOR_RIND 8'h52
`define EOR_I 8'h52
`define EOR_DSP 8'h43
 
// LD is OR rt,r0,....
 
`define ST_ZPX 8'h95
`define ST_IX 8'h81
`define ST_IY 8'h91
`define ST_ABS 8'h8D
`define ST_ABSX 8'h9D
`define ST_RIND 8'h92
`define ST_DSP 8'h83
 
`define ORB_ZPX 8'hB5
`define ORB_IX 8'hA1
`define ORB_IY 8'hB1
`define ORB_ABS 8'hAD
`define ORB_ABSX 8'hBD
 
`define STB_ZPX 8'h74
`define STB_ABS 8'h9C
`define STB_ABSX 8'h9E
 
 
//`define LDB_RIND 8'hB2 // Conflict with LDX #imm16
 
`define LDA_IMM 8'hA9
`define LDA_ZP 8'hA5
`define LDA_ZPX 8'hB5
`define LDA_IX 8'hA1
`define LDA_IY 8'hB1
`define LDA_ABS 8'hAD
`define LDA_ABSX 8'hBD
`define LDA_ABSY 8'hB9
`define LDA_I 8'hB2
 
`define STA_ZP 8'h85
`define STA_ZPX 8'h95
`define STA_IX 8'h81
`define STA_IY 8'h91
`define STA_ABS 8'h8D
`define STA_ABSX 8'h9D
`define STA_ABSY 8'h99
`define STA_I 8'h92
 
`define ASL_IMM8 8'h24
`define ASL_ACC 8'h0A
`define ASL_ZP 8'h06
`define ASL_RR 8'h06
`define ASL_ZPX 8'h16
`define ASL_ABS 8'h0E
`define ASL_ABSX 8'h1E
 
`define ROL_ACC 8'h2A
`define ROL_ZP 8'h26
`define ROL_RR 8'h26
`define ROL_ZPX 8'h36
`define ROL_ABS 8'h2E
`define ROL_ABSX 8'h3E
 
`define LSR_IMM8 8'h34
`define LSR_ACC 8'h4A
`define LSR_ZP 8'h46
`define LSR_RR 8'h46
`define LSR_ZPX 8'h56
`define LSR_ABS 8'h4E
`define LSR_ABSX 8'h5E
 
`define ROR_RR 8'h66
`define ROR_ZP 8'h66
`define ROR_ZPX 8'h76
`define ROR_ABS 8'h6E
`define ROR_ABSX 8'h7E
 
`define DEC_RR 8'hC6
`define DEC_ZP 8'hC6
`define DEC_ZPX 8'hD6
`define DEC_ABS 8'hCE
`define DEC_ABSX 8'hDE
`define INC_RR 8'hE6
`define INC_ZP 8'hE6
`define INC_ZPX 8'hF6
`define INC_ABS 8'hEE
`define INC_ABSX 8'hFE
 
`define BIT_IMM 8'h89
`define BIT_ZP 8'h24
`define BIT_ZPX 8'h34
`define BIT_ABS 8'h2C
`define BIT_ABSX 8'h3C
 
// CMP = SUB r0,...
// BIT = AND r0,...
`define BPL 8'h10
`define BVC 8'h50
`define BCC 8'h90
`define BNE 8'hD0
`define BMI 8'h30
`define BVS 8'h70
`define BCS 8'hB0
`define BEQ 8'hF0
`define BRL 8'h82
`define BRA 8'h80
`define BHI 8'h13
`define BLS 8'h33
`define BGE 8'h93
`define BLT 8'hB3
`define BGT 8'hD3
`define BLE 8'hF3
 
`define JML 8'h5C
`define JMP 8'h4C
`define JMP_IND 8'h6C
`define JMP_INDX 8'h7C
`define JMP_RIND 8'hD2
`define JSR 8'h20
`define JSL 8'h22
`define JSR_INDX 8'hFC
`define JSR_RIND 8'hC2
`define RTS 8'h60
`define RTL 8'h6B
`define BSR 8'h62
`define NOP 8'hEA
 
`define BRK 8'h00
`define PLX 8'hFA
`define PLY 8'h7A
`define PHX 8'hDA
`define PHY 8'h5A
`define WAI 8'hCB
`define PUSH 8'h0B
`define POP 8'h2B
 
`define LDX_IMM 8'hA2
`define LDX_ZP 8'hA6
`define LDX_ZPX 8'hB6
`define LDX_ZPY 8'hB6
`define LDX_ABS 8'hAE
`define LDX_ABSY 8'hBE
 
`define LDX_IMM32 8'hA2
`define LDX_IMM16 8'hB2
`define LDX_IMM8 8'hA6
 
`define LDY_IMM 8'hA0
`define LDY_ZP 8'hA4
`define LDY_ZPX 8'hB4
`define LDY_IMM32 8'hA0
`define LDY_ABS 8'hAC
`define LDY_ABSX 8'hBC
 
`define STX_ZP 8'h86
`define STX_ZPX 8'h96
`define STX_ZPY 8'h96
`define STX_ABS 8'h8E
 
`define STY_ZP 8'h84
`define STY_ZPX 8'h94
`define STY_ABS 8'h8C
 
`define STZ_ZP 8'h64
`define STZ_ZPX 8'h74
`define STZ_ABS 8'h9C
`define STZ_ABSX 8'h9E
 
`define CPX_IMM 8'hE0
`define CPX_IMM32 8'hE0
`define CPX_ZP 8'hE4
`define CPX_ZPX 8'hE4
`define CPX_ABS 8'hEC
`define CPY_IMM 8'hC0
`define CPY_IMM32 8'hC0
`define CPY_ZP 8'hC4
`define CPY_ZPX 8'hC4
`define CPY_ABS 8'hCC
 
`define TRB_ZP 8'h14
`define TRB_ZPX 8'h14
`define TRB_ABS 8'h1C
`define TSB_ZP 8'h04
`define TSB_ZPX 8'h04
`define TSB_ABS 8'h0C
 
`define BAZ 8'hC1
`define BXZ 8'hD1
`define BEQ_RR 8'hE2
`define INT0 8'hDC
`define INT1 8'hDD
`define SUB_SP8 8'h85
`define SUB_SP16 8'h99
`define SUB_SP32 8'h89
`define MVP 8'h44
`define MVN 8'h54
`define STS 8'h64
`define EXEC 8'hEB
`define ATNI 8'h4B
 
`define PG2 8'h42
 
`define NOTHING 4'd0
`define SR_70 4'd1
`define SR_310 4'd2
`define BYTE_70 4'd3
`define WORD_310 4'd4
`define PC_70 4'd5
`define PC_158 4'd6
`define PC_2316 4'd7
`define PC_3124 4'd8
`define PC_310 4'd9
`define WORD_311 4'd10
`define IA_310 4'd11
`define IA_70 4'd12
`define IA_158 4'd13
`define BYTE_71 4'd14
`define WORD_312 4'd15
 
`define STW_DEF 6'h0
`define STW_ACC 6'd1
`define STW_X 6'd2
`define STW_Y 6'd3
`define STW_PC 6'd4
`define STW_PC2 6'd5
`define STW_PCHWI 6'd6
`define STW_SR 6'd7
`define STW_RFA 6'd8
`define STW_RFA8 6'd9
`define STW_RFA 6'd10
`define STW_RFA8 6'd11
`define STW_A 6'd12
`define STW_B 6'd13
`define STW_CALC 6'd14
 
`define STW_ACC8 6'd16
`define STW_X8 6'd17
`define STW_Y8 6'd18
`define STW_PC3124 6'd19
`define STW_PC2316 6'd20
`define STW_PC158 6'd21
`define STW_PC70 6'd22
`define STW_SR70 6'd23
 
/trunk/rtl/verilog/store.v
40,8 → 40,34
else
sel_o <= 4'hf;
adr_o <= {wadr,2'b00};
dat_o <= wdat;
case(store_what)
`STW_ACC: dat_o <= acc;
`STW_X: dat_o <= x;
`STW_Y: dat_o <= y;
`STW_PC: dat_o <= pc;
`STW_PC2: dat_o <= pc + 32'd2;
`STW_PCHWI: dat_o <= pc+{30'b0,~hwi,1'b0};
`STW_SR: dat_o <= sr;
`STW_RFA: dat_o <= rfoa;
`STW_RFA8: dat_o <= {4{rfoa[7:0]}};
`STW_A: dat_o <= a;
`STW_B: dat_o <= b;
`STW_CALC: dat_o <= calc_res;
`ifdef SUPPORT_EM8
`STW_ACC8: dat_o <= {4{acc8}};
`STW_X8: dat_o <= {4{x8}};
`STW_Y8: dat_o <= {4{y8}};
`STW_PC3124: dat_o <= {4{pc[31:24]}};
`STW_PC2316: dat_o <= {4{pc[23:16]}};
`STW_PC158: dat_o <= {4{pc[15:8]}};
`STW_PC70: dat_o <= {4{pc[7:0]}};
`STW_SR70: dat_o <= {4{sr8}};
`endif
default: dat_o <= wdat;
endcase
`ifdef SUPPORT_DCACHE
radr <= wadr; // Do a cache read to test the hit
`endif
state <= STORE2;
end
49,10 → 75,15
// Clear any previously set lock status
STORE2:
if (ack_i) begin
if (isMove)
wdat <= dat_o;
if (isMove|isSts) begin
state <= MVN3;
else
retstate <= MVN3;
end
else begin
state <= IFETCH;
retstate <= IFETCH;
end
lock_o <= 1'b0;
cyc_o <= 1'b0;
stb_o <= 1'b0;
60,6 → 91,52
sel_o <= 4'h0;
adr_o <= 34'h0;
dat_o <= 32'h0;
case(store_what)
`STW_PC,`STW_PC2,`STW_PCHWI:
if (isBrk) begin
radr <= isp_dec;
wadr <= isp_dec;
isp <= isp_dec;
store_what <= `STW_SR;
state <= STORE1;
retstate <= STORE1;
end
`STW_SR:
if (isBrk) begin
load_what <= `PC_310;
state <= LOAD_MAC1;
retstate <= LOAD_MAC1;
radr <= vect[31:2];
if (hwi)
im <= 1'b1;
em <= 1'b0; // make sure we process in native mode; we might have been called up during emulation mode
end
`ifdef SUPPORT_EM8
`STW_PC3124:
begin
store_what <= `STW_PC2316;
state <= STORE1;
end
`STW_PC2316:
begin
store_what <= `STW_PC158;
state <= STORE1;
end
`STW_PC158:
begin
store_what <= `STW_PC70;
state <= STORE1;
end
`STW_PC70:
begin
if (ir[7:0]==`BRK) begin
store_what <= `STW_SR70;
state <= STORE1;
end
end
`endif
endcase
`ifdef SUPPORT_DCACHE
if (dhit) begin
wrsel <= sel_o;
wr <= 1'b1;
67,12 → 144,10
else if (write_allocate) begin
dmiss <= `TRUE;
state <= WAIT_DHIT;
if (isMove)
retstate <= MVN3;
else
retstate <= IFETCH;
end
`endif
end
`ifdef SUPPORT_BERR
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
82,5 → 157,6
dat_o <= 32'h0;
state <= BUS_ERROR;
end
`endif
 
/trunk/rtl/verilog/rtf65002d.v
24,671 → 24,8
//
// ============================================================================
//
`define TRUE 1'b1
`define FALSE 1'b0
`include "rtf65002_defines.v"
 
`define RST_VECT 34'h3FFFFFFF8
`define NMI_VECT 34'h3FFFFFFF4
`define IRQ_VECT 34'h3FFFFFFF0
`define BRK_VECTNO 9'd0
`define SLP_VECTNO 9'd1
`define BYTE_RST_VECT 34'h00000FFFC
`define BYTE_NMI_VECT 34'h00000FFFA
`define BYTE_IRQ_VECT 34'h00000FFFE
 
`define BRK 8'h00
`define RTI 8'h40
`define RTS 8'h60
`define PHP 8'h08
`define CLC 8'h18
`define PLP 8'h28
`define SEC 8'h38
`define PHA 8'h48
`define CLI 8'h58
`define PLA 8'h68
`define SEI 8'h78
`define DEY 8'h88
`define TYA 8'h98
`define TAY 8'hA8
`define CLV 8'hB8
`define INY 8'hC8
`define CLD 8'hD8
`define INX 8'hE8
`define SED 8'hF8
`define ROR_ACC 8'h6A
`define TXA 8'h8A
`define TXS 8'h9A
`define TAX 8'hAA
`define TSX 8'hBA
`define DEX 8'hCA
`define NOP 8'hEA
`define TXY 8'h9B
`define TYX 8'hBB
`define TAS 8'h1B
`define TSA 8'h3B
`define TRS 8'h8B
`define TSR 8'hAB
`define STP 8'hDB
`define NAT 8'hFB
`define EMM 8'hFB
`define INA 8'h1A
`define DEA 8'h3A
 
`define RR 8'h02
`define ADD_RR 4'd0
`define SUB_RR 4'd1
`define CMP_RR 4'd2
`define AND_RR 4'd3
`define EOR_RR 4'd4
`define OR_RR 4'd5
`define MUL_RR 4'd8
`define MULS_RR 4'd9
`define DIV_RR 4'd10
`define DIVS_RR 4'd11
`define MOD_RR 4'd12
`define MODS_RR 4'd13
`define ASL_RRR 4'd14
`define LSR_RRR 4'd15
`define LD_RR 8'h7B
 
`define ADD_IMM8 8'h65 // 8 bit operand
`define ADD_IMM16 8'h79 // 16 bit operand
`define ADD_IMM32 8'h69 // 32 bit operand
`define ADD_ZPX 8'h75 // there is no ZP mode, use R0 to syntheisze
`define ADD_IX 8'h61
`define ADD_IY 8'h71
`define ADD_ABS 8'h6D
`define ADD_ABSX 8'h7D
`define ADD_RIND 8'h72
`define ADD_DSP 8'h63
 
`define SUB_IMM8 8'hE5
`define SUB_IMM16 8'hF9
`define SUB_IMM32 8'hE9
`define SUB_ZPX 8'hF5
`define SUB_IX 8'hE1
`define SUB_IY 8'hF1
`define SUB_ABS 8'hED
`define SUB_ABSX 8'hFD
`define SUB_RIND 8'hF2
`define SUB_DSP 8'hE3
 
// CMP = SUB r0,....
 
`define ADC_IMM 8'h69
`define ADC_ZP 8'h65
`define ADC_ZPX 8'h75
`define ADC_IX 8'h61
`define ADC_IY 8'h71
`define ADC_ABS 8'h6D
`define ADC_ABSX 8'h7D
`define ADC_ABSY 8'h79
`define ADC_I 8'h72
 
`define SBC_IMM 8'hE9
`define SBC_ZP 8'hE5
`define SBC_ZPX 8'hF5
`define SBC_IX 8'hE1
`define SBC_IY 8'hF1
`define SBC_ABS 8'hED
`define SBC_ABSX 8'hFD
`define SBC_ABSY 8'hF9
`define SBC_I 8'hF2
 
`define CMP_IMM8 8'hC5
`define CMP_IMM32 8'hC9
`define CMP_IMM 8'hC9
`define CMP_ZP 8'hC5
`define CMP_ZPX 8'hD5
`define CMP_IX 8'hC1
`define CMP_IY 8'hD1
`define CMP_ABS 8'hCD
`define CMP_ABSX 8'hDD
`define CMP_ABSY 8'hD9
`define CMP_I 8'hD2
 
 
`define LDA_IMM8 8'hA5
`define LDA_IMM16 8'hB9
`define LDA_IMM32 8'hA9
 
`define AND_IMM8 8'h25
`define AND_IMM16 8'h39
`define AND_IMM32 8'h29
`define AND_IMM 8'h29
`define AND_ZP 8'h25
`define AND_ZPX 8'h35
`define AND_IX 8'h21
`define AND_IY 8'h31
`define AND_ABS 8'h2D
`define AND_ABSX 8'h3D
`define AND_ABSY 8'h39
`define AND_RIND 8'h32
`define AND_I 8'h32
`define AND_DSP 8'h23
 
`define OR_IMM8 8'h05
`define OR_IMM16 8'h19
`define OR_IMM32 8'h09
`define OR_ZPX 8'h15
`define OR_IX 8'h01
`define OR_IY 8'h11
`define OR_ABS 8'h0D
`define OR_ABSX 8'h1D
`define OR_RIND 8'h12
`define OR_DSP 8'h03
 
`define ORA_IMM 8'h09
`define ORA_ZP 8'h05
`define ORA_ZPX 8'h15
`define ORA_IX 8'h01
`define ORA_IY 8'h11
`define ORA_ABS 8'h0D
`define ORA_ABSX 8'h1D
`define ORA_ABSY 8'h19
`define ORA_I 8'h12
 
`define EOR_IMM 8'h49
`define EOR_IMM8 8'h45
`define EOR_IMM16 8'h59
`define EOR_IMM32 8'h49
`define EOR_ZP 8'h45
`define EOR_ZPX 8'h55
`define EOR_IX 8'h41
`define EOR_IY 8'h51
`define EOR_ABS 8'h4D
`define EOR_ABSX 8'h5D
`define EOR_ABSY 8'h59
`define EOR_RIND 8'h52
`define EOR_I 8'h52
`define EOR_DSP 8'h43
 
// LD is OR rt,r0,....
 
`define ST_ZPX 8'h95
`define ST_IX 8'h81
`define ST_IY 8'h91
`define ST_ABS 8'h8D
`define ST_ABSX 8'h9D
`define ST_RIND 8'h92
`define ST_DSP 8'h83
 
`define ORB_ZPX 8'hB5
`define ORB_IX 8'hA1
`define ORB_IY 8'hB1
`define ORB_ABS 8'hAD
`define ORB_ABSX 8'hBD
 
`define STB_ZPX 8'h74
`define STB_ABS 8'h9C
`define STB_ABSX 8'h9E
 
 
//`define LDB_RIND 8'hB2 // Conflict with LDX #imm16
 
`define LDA_IMM 8'hA9
`define LDA_ZP 8'hA5
`define LDA_ZPX 8'hB5
`define LDA_IX 8'hA1
`define LDA_IY 8'hB1
`define LDA_ABS 8'hAD
`define LDA_ABSX 8'hBD
`define LDA_ABSY 8'hB9
`define LDA_I 8'hB2
 
`define STA_ZP 8'h85
`define STA_ZPX 8'h95
`define STA_IX 8'h81
`define STA_IY 8'h91
`define STA_ABS 8'h8D
`define STA_ABSX 8'h9D
`define STA_ABSY 8'h99
`define STA_I 8'h92
 
`define ASL_IMM8 8'h24
`define ASL_ACC 8'h0A
`define ASL_ZP 8'h06
`define ASL_RR 8'h06
`define ASL_ZPX 8'h16
`define ASL_ABS 8'h0E
`define ASL_ABSX 8'h1E
 
`define ROL_ACC 8'h2A
`define ROL_ZP 8'h26
`define ROL_RR 8'h26
`define ROL_ZPX 8'h36
`define ROL_ABS 8'h2E
`define ROL_ABSX 8'h3E
 
`define LSR_IMM8 8'h34
`define LSR_ACC 8'h4A
`define LSR_ZP 8'h46
`define LSR_RR 8'h46
`define LSR_ZPX 8'h56
`define LSR_ABS 8'h4E
`define LSR_ABSX 8'h5E
 
`define ROR_RR 8'h66
`define ROR_ZP 8'h66
`define ROR_ZPX 8'h76
`define ROR_ABS 8'h6E
`define ROR_ABSX 8'h7E
 
`define DEC_RR 8'hC6
`define DEC_ZP 8'hC6
`define DEC_ZPX 8'hD6
`define DEC_ABS 8'hCE
`define DEC_ABSX 8'hDE
`define INC_RR 8'hE6
`define INC_ZP 8'hE6
`define INC_ZPX 8'hF6
`define INC_ABS 8'hEE
`define INC_ABSX 8'hFE
 
`define BIT_IMM 8'h89
`define BIT_ZP 8'h24
`define BIT_ZPX 8'h34
`define BIT_ABS 8'h2C
`define BIT_ABSX 8'h3C
 
// CMP = SUB r0,...
// BIT = AND r0,...
`define BPL 8'h10
`define BVC 8'h50
`define BCC 8'h90
`define BNE 8'hD0
`define BMI 8'h30
`define BVS 8'h70
`define BCS 8'hB0
`define BEQ 8'hF0
`define BRL 8'h82
`define BRA 8'h80
 
`define JML 8'h5C
`define JMP 8'h4C
`define JMP_IND 8'h6C
`define JMP_INDX 8'h7C
`define JMP_RIND 8'hD2
`define JSR 8'h20
`define JSL 8'h22
`define JSR_INDX 8'hFC
`define JSR_RIND 8'hC2
`define RTS 8'h60
`define RTL 8'h6B
`define BSR 8'h62
`define NOP 8'hEA
 
`define BRK 8'h00
`define PLX 8'hFA
`define PLY 8'h7A
`define PHX 8'hDA
`define PHY 8'h5A
`define WAI 8'hCB
`define PUSH 8'h0B
`define POP 8'h2B
 
`define LDX_IMM 8'hA2
`define LDX_ZP 8'hA6
`define LDX_ZPX 8'hB6
`define LDX_ZPY 8'hB6
`define LDX_ABS 8'hAE
`define LDX_ABSY 8'hBE
 
`define LDX_IMM32 8'hA2
`define LDX_IMM16 8'hB2
`define LDX_IMM8 8'hA6
 
`define LDY_IMM 8'hA0
`define LDY_ZP 8'hA4
`define LDY_ZPX 8'hB4
`define LDY_IMM32 8'hA0
`define LDY_ABS 8'hAC
`define LDY_ABSX 8'hBC
 
`define STX_ZP 8'h86
`define STX_ZPX 8'h96
`define STX_ZPY 8'h96
`define STX_ABS 8'h8E
 
`define STY_ZP 8'h84
`define STY_ZPX 8'h94
`define STY_ABS 8'h8C
 
`define STZ_ZP 8'h64
`define STZ_ZPX 8'h74
`define STZ_ABS 8'h9C
`define STZ_ABSX 8'h9E
 
`define CPX_IMM 8'hE0
`define CPX_IMM32 8'hE0
`define CPX_ZP 8'hE4
`define CPX_ZPX 8'hE4
`define CPX_ABS 8'hEC
`define CPY_IMM 8'hC0
`define CPY_IMM32 8'hC0
`define CPY_ZP 8'hC4
`define CPY_ZPX 8'hC4
`define CPY_ABS 8'hCC
 
`define TRB_ZP 8'h14
`define TRB_ZPX 8'h14
`define TRB_ABS 8'h1C
`define TSB_ZP 8'h04
`define TSB_ZPX 8'h04
`define TSB_ABS 8'h0C
 
`define BAZ 8'hC1
`define BXZ 8'hD1
`define BEQ_RR 8'hE2
`define INT0 8'hDC
`define INT1 8'hDD
`define SUB_SP8 8'h85
`define SUB_SP16 8'h99
`define SUB_SP32 8'h89
`define MVP 8'h44
`define MVN 8'h54
`define EXEC 8'hEB
`define ATNI 8'h4B
 
`define NOTHING 4'd0
`define SR_70 4'd1
`define SR_310 4'd2
`define BYTE_70 4'd3
`define WORD_310 4'd4
`define PC_70 4'd5
`define PC_158 4'd6
`define PC_2316 4'd7
`define PC_3124 4'd8
`define PC_310 4'd9
`define WORD_311 4'd10
`define IA_310 4'd11
`define IA_70 4'd12
`define IA_158 4'd13
`define BYTE_71 4'd14
`define WORD_312 4'd15
 
module icachemem(wclk, wr, adr, dat, rclk, pc, insn);
input wclk;
input wr;
input [33:0] adr;
input [31:0] dat;
input rclk;
input [31:0] pc;
output reg [63:0] insn;
 
wire [63:0] insn0;
wire [63:0] insn1;
wire [31:0] pcp8 = pc + 32'd8;
reg [31:0] rpc;
 
always @(posedge rclk)
rpc <= pc;
 
// memL and memH combined allow a 64 bit read
syncRam2kx32_1rw1r ramL0
(
.wrst(1'b0),
.wclk(wclk),
.wce(~adr[2]),
.we(wr),
.wsel(4'hF),
.wadr(adr[13:3]),
.i(dat),
.wo(),
.rrst(1'b0),
.rclk(rclk),
.rce(1'b1),
.radr(pc[13:3]),
.o(insn0[31:0])
);
 
syncRam2kx32_1rw1r ramH0
(
.wrst(1'b0),
.wclk(wclk),
.wce(adr[2]),
.we(wr),
.wsel(4'hF),
.wadr(adr[13:3]),
.i(dat),
.wo(),
.rrst(1'b0),
.rclk(rclk),
.rce(1'b1),
.radr(pc[13:3]),
.o(insn0[63:32])
);
 
syncRam2kx32_1rw1r ramL1
(
.wrst(1'b0),
.wclk(wclk),
.wce(~adr[2]),
.we(wr),
.wsel(4'hF),
.wadr(adr[13:3]),
.i(dat),
.wo(),
.rrst(1'b0),
.rclk(rclk),
.rce(1'b1),
.radr(pcp8[13:3]),
.o(insn1[31:0])
);
 
syncRam2kx32_1rw1r ramH1
(
.wrst(1'b0),
.wclk(wclk),
.wce(adr[2]),
.we(wr),
.wsel(4'hF),
.wadr(adr[13:3]),
.i(dat),
.wo(),
.rrst(1'b0),
.rclk(rclk),
.rce(1'b1),
.radr(pcp8[13:3]),
.o(insn1[63:32])
);
 
always @(rpc or insn0 or insn1)
case(rpc[2:0])
3'd0: insn <= insn0[63:0];
3'd1: insn <= {insn1[7:0],insn0[63:8]};
3'd2: insn <= {insn1[15:0],insn0[63:16]};
3'd3: insn <= {insn1[23:0],insn0[63:24]};
3'd4: insn <= {insn1[31:0],insn0[63:32]};
3'd5: insn <= {insn1[39:0],insn0[63:40]};
3'd6: insn <= {insn1[47:0],insn0[63:48]};
3'd7: insn <= {insn1[55:0],insn0[63:56]};
endcase
endmodule
 
module tagmem(wclk, wr, adr, rclk, pc, hit0, hit1);
input wclk;
input wr;
input [33:0] adr;
input rclk;
input [31:0] pc;
output hit0;
output hit1;
 
wire [31:0] pcp8 = pc + 32'd8;
wire [31:0] tag0;
wire [31:0] tag1;
reg [31:0] rpc;
reg [31:0] rpcp8;
 
always @(posedge rclk)
rpc <= pc;
always @(posedge rclk)
rpcp8 <= pcp8;
 
syncRam1kx32_1rw1r ram0 (
.wrst(1'b0),
.wclk(wclk),
.wce(adr[3:2]==2'b11),
.we(wr),
.wsel(4'hF),
.wadr(adr[13:4]),
.i(adr[31:0]),
.wo(),
 
.rrst(1'b0),
.rclk(rclk),
.rce(1'b1),
.radr(pc[13:4]),
.o(tag0)
);
 
syncRam1kx32_1rw1r ram1 (
.wrst(1'b0),
.wclk(wclk),
.wce(adr[3:2]==2'b11),
.we(wr),
.wsel(4'hF),
.wadr(adr[13:4]),
.i(adr[31:0]),
.wo(),
 
.rrst(1'b0),
.rclk(rclk),
.rce(1'b1),
.radr(pcp8[13:4]),
.o(tag1)
);
 
assign hit0 = tag0[31:14]==rpc[31:14] && tag0[0];
assign hit1 = tag1[31:14]==rpcp8[31:14] && tag1[0];
 
endmodule
 
module dcachemem(wclk, wr, sel, wadr, wdat, rclk, radr, rdat);
input wclk;
input wr;
input [3:0] sel;
input [31:0] wadr;
input [31:0] wdat;
input rclk;
input [31:0] radr;
output [31:0] rdat;
 
syncRam2kx32_1rw1r ram0 (
.wrst(1'b0),
.wclk(wclk),
.wce(1'b1),
.we(wr),
.wsel(sel),
.wadr(wadr[10:0]),
.i(wdat),
.wo(),
.rrst(1'b0),
.rclk(rclk),
.rce(1'b1),
.radr(radr[10:0]),
.o(rdat)
);
 
endmodule
 
module dtagmem(wclk, wr, wadr, rclk, radr, hit);
input wclk;
input wr;
input [31:0] wadr;
input rclk;
input [31:0] radr;
output hit;
 
reg [31:0] rradr;
wire [31:0] tag;
 
syncRam512x32_1rw1r u1
(
.wrst(1'b0),
.wclk(wclk),
.wce(wadr[1:0]==2'b11),
.we(wr),
.wadr(wadr[10:2]),
.i(wadr),
.wo(),
.rrst(1'b0),
.rclk(rclk),
.rce(1'b1),
.radr(radr[10:2]),
.o(tag)
);
 
 
always @(rclk)
rradr <= radr;
assign hit = tag[31:11]==rradr[31:11];
 
endmodule
 
module overflow(op, a, b, s, v);
 
input op; // 0=add,1=sub
input a;
input b;
input s; // sum
output v;
 
// Overflow:
// Add: the signs of the inputs are the same, and the sign of the
// sum is different
// Sub: the signs of the inputs are different, and the sign of
// the sum is the same as B
assign v = (op ^ s ^ b) & (~op ^ a ^ b);
 
endmodule
/*
// This table being setup to set the pc increment. It should synthesize to a ROM.
module m_pcinc(opcode,inc);
input [7:0] opcode;
output [3:0] inc;
 
always @(opcode)
if (em)
else
case(opcode)
`BRK: inc <= 4'd1;
`BPL,`BMI,`BCS,`BCC,`BVS,`BVC,`BEQ,`BNE,`BRA: inc <= 4'd2;
`BRL: inc <= 4'd3;
`CLC,`SEC,`CLD,`SED,`CLV,`CLI,`SEI: inc <= 4'd1;
`TAS,`TSA,`TAY,`TYA,`TAX,`TXA,`TSX,`TXS,`TYX,`TXY: inc <= 4'd1;
`TRS,`TSR: inc <= 4'd2;
`INY,`DEY,`INX,`DEX,`INA,`DEA: inc <= 4'd1;
`EMM: inc <= 4'd1;
`PHA,`PHX,`PHY,`PHP: inc <= 4'd1;
`PLA,`PLX,`PLY,`PLP: inc <= 4'd1;
`PUSH,`POP: inc <= 4'd2;
`STP,`WAI: inc <= 4'd1;
`JMP,`JSR: inc <= 4'd3;
`JML,`JSL,`JMP_IND,`JMP_INDX,`JSR_INDX: inc <= 4'd5;
`JMP_RIND,`JSR_RIND: inc <= 4'd2;
`RTS,`RTI,`RTL: inc <= 4'd1;
`NOP: inc <= 4'd1;
`BSR: inc <= 4'd3;
`RR: inc <= 4'd3;
`LD_RR: inc <= 4'd2;
`ADD_IMM8,`SUB_IMM8,`AND_IMM8,`OR_IMM8,`EOR_IMM8: inc <= 4'd2;
`ADD_IMM16,`SUB_IMM16,`AND_IMM16,`OR_IMM16,`EOR_IMM16: inc <= 4'd3;
`ADD_IMM32,`SUB_IMM32,`AND_IMM32,`OR_IMM32,`EOR_IMM32: inc <= 4'd5;
`ADD_ZPX,`SUB_ZPX,`AND_ZPX,`OR_ZPX,`EOR_ZPX: inc <= 4'd4;
`ADD_IX,`SUB_IX,`AND_IX,`OR_IX,`EOR_IX: inc <= 4'd4;
`ADD_IY,`SUB_IY,`AND_IY,`OR_IY,`EOR_IY: inc <= 4'd4;
`ADD_ABS,`SUB_ABS,`AND_ABS,`OR_ABS,`EOR_ABS: inc <= 4'd6;
`ADD_ABSX,`SUB_ABSX,`AND_ABSX,`OR_ABSX,`EOR_ABSX: inc <= 4'd7;
`ADD_RIND,`SUB_RIND,`AND_RIND,`OR_RIND,`EOR_RIND: inc <= 4'd2;
`ADD_DSP,`SUB_DSP,`AND_DSP,`OR_DSP,`EOR_DSP: inc <= 4'd3;
endcase
endmodule*/
 
 
 
module rtf65002d(rst_md, rst_i, clk_i, nmi_i, irq_i, irq_vect, bte_o, cti_o, bl_o, lock_o, cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_i, dat_o);
parameter IDLE = 3'd0;
parameter LOAD_DCACHE = 3'd1;
696,101 → 33,65
parameter LOAD_IBUF1 = 3'd3;
parameter LOAD_IBUF2 = 3'd4;
parameter LOAD_IBUF3 = 3'd5;
parameter RESET1 = 7'd0;
parameter IFETCH = 7'd1;
parameter JMP_IND1 = 7'd2;
parameter JMP_IND2 = 7'd3;
parameter DECODE = 7'd4;
parameter STORE1 = 7'd5;
parameter STORE2 = 7'd6;
parameter LOAD1 = 7'd7;
parameter LOAD2 = 7'd8;
parameter IRQ1 = 7'd9;
parameter IRQ2 = 7'd10;
parameter IRQ3 = 7'd11;
parameter CALC = 7'd12;
parameter JSR1 = 7'd13;
parameter JSR_INDX1 = 7'd14;
parameter JSR161 = 7'd15;
parameter RTS1 = 7'd16;
parameter IX1 = 7'd18;
parameter IX2 = 7'd19;
parameter IX3 = 7'd20;
parameter IX4 = 7'd21;
parameter IY1 = 7'd22;
parameter IY2 = 7'd23;
parameter IY3 = 7'd24;
parameter BSR1 = 7'd32;
parameter BYTE_IX5 = 7'd37;
parameter BYTE_IY5 = 7'd42;
parameter BYTE_JSR1 = 7'd46;
parameter BYTE_JSR2 = 7'd47;
parameter BYTE_JSR3 = 7'd48;
parameter BYTE_IRQ1 = 7'd49;
parameter BYTE_IRQ2 = 7'd50;
parameter BYTE_IRQ3 = 7'd51;
parameter BYTE_IRQ4 = 7'd52;
parameter BYTE_IRQ5 = 7'd53;
parameter BYTE_IRQ6 = 7'd54;
parameter BYTE_IRQ7 = 7'd55;
parameter BYTE_IRQ8 = 7'd56;
parameter BYTE_IRQ9 = 7'd57;
parameter BYTE_JMP_IND1 = 7'd58;
parameter BYTE_JMP_IND2 = 7'd59;
parameter BYTE_JMP_IND3 = 7'd60;
parameter BYTE_JMP_IND4 = 7'd61;
parameter BYTE_JSR_INDX1 = 7'd62;
parameter BYTE_JSR_INDX2 = 7'd63;
parameter BYTE_JSR_INDX3 = 7'd64;
parameter RTI1 = 7'd65;
parameter RTI2 = 7'd66;
parameter RTI3 = 7'd67;
parameter RTI4 = 7'd68;
parameter BYTE_RTS1 = 7'd69;
parameter BYTE_RTS2 = 7'd70;
parameter BYTE_RTS3 = 7'd71;
parameter BYTE_RTS4 = 7'd72;
parameter BYTE_RTS5 = 7'd73;
parameter BYTE_RTS6 = 7'd74;
parameter BYTE_RTS7 = 7'd75;
parameter BYTE_RTS8 = 7'd76;
parameter BYTE_RTS9 = 7'd77;
parameter BYTE_RTI1 = 7'd78;
parameter BYTE_RTI2 = 7'd79;
parameter BYTE_RTI3 = 7'd80;
parameter BYTE_RTI4 = 7'd81;
parameter BYTE_RTI5 = 7'd82;
parameter BYTE_RTI6 = 7'd83;
parameter BYTE_RTI7 = 7'd84;
parameter BYTE_RTI8 = 7'd85;
parameter BYTE_RTI9 = 7'd86;
parameter BYTE_RTI10 = 7'd87;
parameter BYTE_JSL1 = 7'd88;
parameter BYTE_JSL2 = 7'd89;
parameter BYTE_JSL3 = 7'd90;
parameter BYTE_JSL4 = 7'd91;
parameter BYTE_JSL5 = 7'd92;
parameter BYTE_JSL6 = 7'd93;
parameter BYTE_JSL7 = 7'd94;
parameter BYTE_PLP1 = 7'd95;
parameter BYTE_PLP2 = 7'd96;
parameter BYTE_PLA1 = 7'd97;
parameter BYTE_PLA2 = 7'd98;
parameter WAIT_DHIT = 7'd99;
parameter RESET2 = 7'd100;
parameter MULDIV1 = 7'd101;
parameter MULDIV2 = 7'd102;
parameter BYTE_DECODE = 7'd103;
parameter BYTE_CALC = 7'd104;
parameter BUS_ERROR = 7'd105;
parameter INSN_BUS_ERROR = 7'd106;
parameter LOAD_MAC1 = 7'd107;
parameter LOAD_MAC2 = 7'd108;
parameter MVN1 = 7'd109;
parameter MVN2 = 7'd110;
parameter MVN3 = 7'd111;
parameter MVP1 = 7'd112;
parameter MVP2 = 7'd113;
parameter RESET1 = 6'd0;
parameter IFETCH = 6'd1;
parameter DECODE = 6'd2;
parameter STORE1 = 6'd3;
parameter STORE2 = 6'd4;
parameter IRQ0 = 6'd5;
parameter IRQ1 = 6'd6;
parameter IRQ2 = 6'd7;
parameter IRQ3 = 6'd8;
parameter CALC = 6'd9;
parameter JSR_INDX1 = 6'd10;
parameter JSR161 = 6'd11;
parameter RTS1 = 6'd12;
parameter IY3 = 6'd13;
parameter BSR1 = 6'd14;
parameter BYTE_IX5 = 6'd15;
parameter BYTE_IY5 = 6'd16;
parameter BYTE_JSR1 = 6'd17;
parameter BYTE_JSR2 = 6'd18;
parameter BYTE_JSR3 = 6'd19;
parameter BYTE_IRQ1 = 6'd20;
parameter BYTE_IRQ2 = 6'd21;
parameter BYTE_IRQ3 = 6'd22;
parameter BYTE_IRQ4 = 6'd23;
parameter BYTE_IRQ5 = 6'd24;
parameter BYTE_IRQ6 = 6'd25;
parameter BYTE_IRQ7 = 6'd26;
parameter BYTE_IRQ8 = 6'd27;
parameter BYTE_IRQ9 = 6'd28;
parameter BYTE_JSR_INDX1 = 6'd29;
parameter BYTE_JSR_INDX2 = 6'd30;
parameter BYTE_JSR_INDX3 = 6'd31;
parameter BYTE_JSL1 = 6'd32;
parameter BYTE_JSL2 = 6'd33;
parameter BYTE_JSL3 = 6'd34;
parameter BYTE_JSL4 = 6'd35;
parameter BYTE_JSL5 = 6'd36;
parameter BYTE_JSL6 = 6'd37;
parameter BYTE_JSL7 = 6'd38;
parameter BYTE_PLP1 = 6'd39;
parameter BYTE_PLP2 = 6'd40;
parameter BYTE_PLA1 = 6'd41;
parameter BYTE_PLA2 = 6'd42;
parameter WAIT_DHIT = 6'd43;
parameter RESET2 = 6'd44;
parameter MULDIV1 = 6'd45;
parameter MULDIV2 = 6'd46;
parameter BYTE_DECODE = 6'd47;
parameter BYTE_CALC = 6'd48;
parameter BUS_ERROR = 6'd49;
parameter INSN_BUS_ERROR = 6'd50;
parameter LOAD_MAC1 = 6'd51;
parameter LOAD_MAC2 = 6'd52;
parameter MVN1 = 6'd53;
parameter MVN2 = 6'd54;
parameter MVN3 = 6'd55;
parameter MVP1 = 6'd56;
parameter MVP2 = 6'd57;
parameter STS1 = 6'd58;
 
input rst_md; // reset mode, 1=emulation mode, 0=native mode
input rst_i;
812,8 → 113,8
input [31:0] dat_i;
output reg [31:0] dat_o;
 
reg [6:0] state;
reg [6:0] retstate;
reg [5:0] state;
reg [5:0] retstate;
reg [2:0] cstate;
wire [63:0] insn;
reg [63:0] ibuf;
848,16 → 149,10
reg [3:0] suppress_pcinc;
reg [31:0] pc;
reg [31:0] opc;
wire [31:0] pcp1 = pc + (32'd1 & suppress_pcinc);
wire [31:0] pcp2 = pc + (32'd2 & suppress_pcinc);
wire [31:0] pcp3 = pc + (32'd3 & suppress_pcinc);
wire [31:0] pcp4 = pc + (32'd4 & suppress_pcinc);
wire [31:0] pcp5 = pc + (32'd5 & suppress_pcinc);
wire [31:0] pcp6 = pc + (32'd6 & suppress_pcinc);
wire [31:0] pcp7 = pc + (32'd7 & suppress_pcinc);
wire [31:0] pcp8 = pc + (32'd8 & suppress_pcinc);
reg [31:0] dp; // 32 bit mode direct page register
reg [31:0] dp8; // 8 bit mode direct page register
wire [3:0] pc_inc;
wire [31:0] pcp2 = pc + (32'd2 & suppress_pcinc); // for branches
wire [31:0] pcp4 = pc + (32'd4 & suppress_pcinc); // for branches
wire [31:0] pcp8 = pc + 32'd8; // cache controller needs this
reg [31:0] abs8; // 8 bit mode absolute address register
reg [31:0] vbr; // vector table base register
wire bhit=pc==bufadr;
890,8 → 185,13
wire lfsr_fb;
xnor(lfsr_fb,lfsr[0],lfsr[1],lfsr[21],lfsr[31]);
reg [31:0] a, b;
`ifdef SUPPORT_SHIFT
wire [31:0] shlo = a << b[4:0];
wire [31:0] shro = a >> b[4:0];
`else
wire [31:0] shlo = 32'd0;
wire [31:0] shro = 32'd0;
`endif
reg [7:0] b8;
reg [32:0] res;
reg [8:0] res8;
902,10 → 202,6
wire resz32 = res[31:0]==32'd0;
wire resn8 = res8[7];
wire resn32 = res[31];
wire resn = em ? res8[7] : res[31];
wire resz = em ? res8[7:0]==8'h00 : res[31:0]==32'd0;
wire resc = em ? res8[8] : res[32];
wire resv = em ? resv8 : resv32;
 
reg [31:0] vect;
reg [31:0] ia; // temporary reg to hold indirect address
914,7 → 210,11
reg isDataCacheLoad;
reg isCacheReset;
wire hit0,hit1;
`ifdef SUPPORT_DCACHE
wire dhit;
`else
wire dhit = 1'b0;
`endif
reg write_allocate;
reg wr;
reg [3:0] wrsel;
932,13 → 232,28
reg imiss;
reg dmiss;
reg icacheOn,dcacheOn;
`ifdef SUPPORT_DCACHE
wire unCachedData = radr[31:20]==12'hFFD || !dcacheOn; // I/O area is uncached
`else
wire unCachedData = 1'b1;
`endif
`ifdef SUPPORT_ICACHE
wire unCachedInsn = pc[31:13]==19'h0 || !icacheOn; // The lowest 8kB is uncached.
`else
wire unCachedInsn = 1'b1;
`endif
 
wire isSub = ir[7:0]==`SUB_ZPX || ir[7:0]==`SUB_IX || ir[7:0]==`SUB_IY ||
ir[7:0]==`SUB_ABS || ir[7:0]==`SUB_ABSX || ir[7:0]==`SUB_IMM8 || ir[7:0]==`SUB_IMM16 || ir[7:0]==`SUB_IMM32;
wire isSub8 = ir[7:0]==`SBC_ZP || ir[7:0]==`SBC_ZPX || ir[7:0]==`SBC_IX || ir[7:0]==`SBC_IY || ir[7:0]==`SBC_I ||
ir[7:0]==`SBC_ABS || ir[7:0]==`SBC_ABSX || ir[7:0]==`SBC_ABSY || ir[7:0]==`SBC_IMM;
reg [31:0] history_buf [63:0];
reg [5:0] history_ndx;
reg hist_capture;
 
reg isBrk,isMove,isSts;
reg isRTI,isRTL,isRTS;
reg isOrb,isStb;
reg isRMW;
reg isSub,isSub8;
 
 
wire isCmp = ir[7:0]==`CPX_ZPX || ir[7:0]==`CPX_ABS || ir[7:0]==`CPX_IMM32 ||
ir[7:0]==`CPY_ZPX || ir[7:0]==`CPY_ABS || ir[7:0]==`CPY_IMM32;
wire isRMW32 =
954,23 → 269,50
ir[7:0]==`ASL_ABSX || ir[7:0]==`ROL_ABSX || ir[7:0]==`LSR_ABSX || ir[7:0]==`ROR_ABSX || ir[7:0]==`INC_ABSX || ir[7:0]==`DEC_ABSX ||
ir[7:0]==`TRB_ZP || ir[7:0]==`TRB_ZPX || ir[7:0]==`TRB_ABS || ir[7:0]==`TSB_ZP || ir[7:0]==`TSB_ZPX || ir[7:0]==`TSB_ABS;
;
wire isRMW = em ? isRMW8 : isRMW32;
wire isOrb = ir[7:0]==`ORB_ZPX || ir[7:0]==`ORB_IX || ir[7:0]==`ORB_IY || ir[7:0]==`ORB_ABS || ir[7:0]==`ORB_ABSX;
wire isStb = ir[7:0]==`STB_ZPX || ir[7:0]==`STB_ABS || ir[7:0]==`STB_ABSX;
wire isRTI = ir[7:0]==`RTI;
wire isRTL = ir[7:0]==`RTL;
wire isRTS = ir[7:0]==`RTS;
wire isMove = ir[7:0]==`MVP || ir[7:0]==`MVN;
 
// Registerable decodes
// The following decodes can be registered because they aren't needed until at least the cycle after
// the DECODE stage.
 
always @(posedge clk)
if (state==DECODE) begin
isSub <= ir[7:0]==`SUB_ZPX || ir[7:0]==`SUB_IX || ir[7:0]==`SUB_IY ||
ir[7:0]==`SUB_ABS || ir[7:0]==`SUB_ABSX || ir[7:0]==`SUB_IMM8 || ir[7:0]==`SUB_IMM16 || ir[7:0]==`SUB_IMM32;
isSub8 <= ir[7:0]==`SBC_ZP || ir[7:0]==`SBC_ZPX || ir[7:0]==`SBC_IX || ir[7:0]==`SBC_IY || ir[7:0]==`SBC_I ||
ir[7:0]==`SBC_ABS || ir[7:0]==`SBC_ABSX || ir[7:0]==`SBC_ABSY || ir[7:0]==`SBC_IMM;
isRMW <= em ? isRMW8 : isRMW32;
isOrb <= ir[7:0]==`ORB_ZPX || ir[7:0]==`ORB_IX || ir[7:0]==`ORB_IY || ir[7:0]==`ORB_ABS || ir[7:0]==`ORB_ABSX;
isStb <= ir[7:0]==`STB_ZPX || ir[7:0]==`STB_ABS || ir[7:0]==`STB_ABSX;
isRTI <= ir[7:0]==`RTI;
isRTL <= ir[7:0]==`RTL;
isRTS <= ir[7:0]==`RTS;
isBrk <= ir[7:0]==`BRK;
isMove <= ir[7:0]==`MVP || ir[7:0]==`MVN;
isSts <= ir[7:0]==`STS;
end
 
`ifdef SUPPORT_EXEC
wire isExec = ir[7:0]==`EXEC;
wire isAtni = ir[7:0]==`ATNI;
`else
wire isExec = 1'b0;
wire isAtni = 1'b0;
`endif
wire ld_muldiv = state==DECODE && ir[7:0]==`RR;
wire md_done;
wire clk;
reg isIY;
 
rtf65002_pcinc upci1
(
.opcode(ir[7:0]),
.suppress_pcinc(suppress_pcinc),
.inc(pc_inc)
);
 
mult_div umd1
(
.rst(rst),
.rst(rst_i),
.clk(clk),
.ld(ld_muldiv),
.op(ir[23:20]),
981,22 → 323,23
.r(r),
.done(md_done)
);
 
icachemem icm0 (
 
`ifdef SUPPORT_ICACHE
rtf65002_icachemem icm0 (
.wclk(clk),
.wr(ack_i & isInsnCacheLoad),
.adr(adr_o),
.dat(dat_i),
.rclk(~clk_i),
.rclk(~clk),
.pc(pc),
.insn(insn)
);
 
tagmem tgm0 (
rtf65002_itagmem tgm0 (
.wclk(clk),
.wr((ack_i & isInsnCacheLoad)|isCacheReset),
.adr({adr_o[31:1],!isCacheReset}),
.rclk(~clk_i),
.rclk(~clk),
.pc(pc),
.hit0(hit0),
.hit1(hit1)
1003,26 → 346,31
);
 
wire ihit = (hit0 & hit1);//(pc[2:0] > 3'd1 ? hit1 : 1'b1));
`else
wire ihit = 1'b0;
`endif
 
dcachemem dcm0 (
`ifdef SUPPORT_DCACHE
rtf65002_dcachemem dcm0 (
.wclk(clk),
.wr(wr | (ack_i & isDataCacheLoad)),
.sel(wr ? wrsel : sel_o),
.wadr(wr ? wadr : adr_o[33:2]),
.wdat(wr ? wdat : dat_i),
.rclk(~clk_i),
.rclk(~clk),
.radr(radr),
.rdat(rdat)
);
 
dtagmem dtm0 (
rtf65002_dtagmem dtm0 (
.wclk(clk),
.wr(wr | (ack_i & isDataCacheLoad)),
.wadr(wr ? wadr : adr_o[33:2]),
.rclk(~clk_i),
.rclk(~clk),
.radr(radr),
.hit(dhit)
);
`endif
 
overflow uovr1 (
.op(isSub),
1046,10 → 394,12
wire [7:0] bcso;
wire bcaico,bcaco,bcsico,bcsco;
 
`ifdef SUPPORT_BCD
BCDAdd ubcdai1 (.ci(cf),.a(acc8),.b(ir[15:8]),.o(bcaio),.c(bcaico));
BCDAdd ubcda2 (.ci(cf),.a(acc8),.b(b8),.o(bcao),.c(bcaco));
BCDSub ubcdsi1 (.ci(cf),.a(acc8),.b(ir[15:8]),.o(bcsio),.c(bcsico));
BCDSub ubcds2 (.ci(cf),.a(acc8),.b(b8),.o(bcso),.c(bcsco));
`endif
 
reg [7:0] dati;
always @(radr2LSB or dat_i)
1081,22 → 431,61
`BVC: takb <= !vf;
`BRA: takb <= 1'b1;
`BRL: takb <= 1'b1;
`BHI: takb <= cf & !zf;
`BLS: takb <= !cf | zf;
`BGE: takb <= (nf & vf)|(!nf & !vf);
`BLT: takb <= (nf & !vf)|(!nf & vf);
`BGT: takb <= (nf & vf & !zf) + (!nf & !vf & !zf);
`BLE: takb <= zf | (nf & !vf)|(!nf & vf);
//`BAZ: takb <= acc8==8'h00;
//`BXZ: takb <= x8==8'h00;
default: takb <= 1'b0;
endcase
 
wire [31:0] zp_address = dp8 + ir[15:8];
wire [31:0] zpx_address = zp_address + x8;
wire [31:0] zpy_address = zp_address + y8;
wire [31:0] abs_address = abs8 + {16'h0,ir[23:8]};
wire [31:0] absx_address = abs8 + {16'h0,ir[23:8] + {8'h0,x8}}; // simulates 64k bank wrap-around
wire [31:0] absy_address = abs8 + {16'h0,ir[23:8] + {8'h0,y8}};
wire [31:0] zpx32xy_address = dp + ir[23:12] + rfoa;
wire [31:0] absx32xy_address = ir[47:16] + rfob;
wire [31:0] zpx32_address = dp + ir[31:20] + rfob;
wire [31:0] absx32_address = ir[55:24] + rfob;
wire [31:0] zp_address = {abs8[31:12],4'h0,ir[15:8]};
wire [31:0] zpx_address = {abs8[31:12],4'h0,ir[15:8]} + x8;
wire [31:0] zpy_address = {abs8[31:12],4'h0,ir[15:8]} + y8;
wire [31:0] abs_address = {abs8[31:12],12'h00} + {16'h0,ir[23:8]};
wire [31:0] absx_address = {abs8[31:12],12'h00} + {16'h0,ir[23:8] + {8'h0,x8}}; // simulates 64k bank wrap-around
wire [31:0] absy_address = {abs8[31:12],12'h00} + {16'h0,ir[23:8] + {8'h0,y8}};
wire [31:0] zpx32xy_address = ir[23:12] + rfoa;
wire [31:0] absx32xy_address = ir[47:16] + rfob;
wire [31:0] zpx32_address = ir[31:20] + rfob;
wire [31:0] absx32_address = ir[55:24] + rfob;
 
reg [32:0] calc_res;
always @(a or b or b8 or x or y or df or cf or Rt or shlo or shro)
begin
case(ir[7:0])
`RR:
case(ir[23:20])
`ASL_RRR: calc_res <= shlo;
`LSR_RRR: calc_res <= shro;
default: calc_res <= 33'd0;
endcase
`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND: calc_res <= a + b + {31'b0,df&cf};
`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND: calc_res <= a - b - {31'b0,df&~cf&|Rt}; // Also CMP
`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND: calc_res <= a & b; // Also BIT
`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND: calc_res <= a | b; // Also LD
`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND: calc_res <= a ^ b;
`LDX_ZPY,`LDX_ABS,`LDX_ABSY: calc_res <= b;
`LDY_ZPX,`LDY_ABS,`LDY_ABSX: calc_res <= b;
`CPX_ZPX,`CPX_ABS: calc_res <= x - b;
`CPY_ZPX,`CPY_ABS: calc_res <= y - b;
`ASL_IMM8: calc_res <= shlo;
`LSR_IMM8: calc_res <= shro;
`ASL_ZPX,`ASL_ABS,`ASL_ABSX: calc_res <= {b,1'b0};
`ROL_ZPX,`ROL_ABS,`ROL_ABSX: calc_res <= {b,cf};
`LSR_ZPX,`LSR_ABS,`LSR_ABSX: calc_res <= {b[0],1'b0,b[31:1]};
`ROR_ZPX,`ROR_ABS,`ROR_ABSX: calc_res <= {b[0],cf,b[31:1]};
`INC_ZPX,`INC_ABS,`INC_ABSX: calc_res <= b + 32'd1;
`DEC_ZPX,`DEC_ABS,`DEC_ABSX: calc_res <= b - 32'd1;
`ORB_ZPX,`ORB_ABS,`ORB_ABSX: calc_res <= a | {24'h0,b8};
default: calc_res <= 33'd0;
endcase
end
 
 
//-----------------------------------------------------------------------------
// Clock control
// - reset or NMI reenables the clock
1136,7 → 525,7
first_ifetch <= `TRUE;
wr <= 1'b0;
cf <= 1'b0;
ir <= 56'hEAEAEAEAEAEAEA;
ir <= 64'hEAEAEAEAEAEAEAEA;
imiss <= `FALSE;
dmiss <= `FALSE;
dcacheOn <= 1'b0;
1159,8 → 548,6
exbuf <= 64'd0;
spage <= 32'h00000100;
bufadr <= 32'd0;
dp <= 32'd0;
dp8 <= 32'd0;
abs8 <= 32'd0;
clk_en <= 1'b1;
isCacheReset <= `TRUE;
1167,6 → 554,9
gie <= 1'b0;
tick <= 32'd0;
isIY <= 1'b0;
load_what <= `NOTHING;
hist_capture <= `TRUE;
history_ndx <= 6'd0;
end
else begin
tick <= tick + 32'd1;
1194,7 → 584,15
 
`include "ifetch.v"
`include "decode.v"
`ifdef SUPPORT_EM8
`include "byte_decode.v"
`include "byte_calc.v"
`include "byte_jsr.v"
`include "byte_jsl.v"
`ifdef SUPPORT_BYTE_IRQ
`include "byte_irq.v"
`endif
`endif
 
`include "load_mac.v"
`include "store.v"
1203,33 → 601,8
if (dhit)
state <= retstate;
 
`include "byte_calc.v"
`include "calc.v"
`include "byte_jsr.v"
`include "byte_jsl.v"
 
JSR1:
if (ack_i) begin
state <= IFETCH;
retstate <= IFETCH;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
sel_o <= 4'h0;
adr_o <= 34'd0;
dat_o <= 32'd0;
pc <= vect;
isp <= isp_dec;
if (dhit) begin
wrsel <= sel_o;
wr <= 1'b1;
end
else if (write_allocate) begin
state <= WAIT_DHIT;
dmiss <= `TRUE;
end
end
 
JSR_INDX1:
if (ack_i) begin
load_what <= `PC_310;
1272,9 → 645,17
dmiss <= `TRUE;
end
end
 
`include "byte_irq.v"
 
/*
IRQ0:
begin
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {wadr,2'b00};
dat_o <= wdat;
state <= IRQ1;
end
IRQ1:
if (ack_i) begin
ir <= 64'd0; // Force instruction decoder to BRK
1285,6 → 666,7
we_o <= 1'b0;
sel_o <= 4'h0;
isp <= isp_dec;
`ifdef SUPPORT_DCACHE
if (dhit) begin
wrsel <= sel_o;
wr <= 1'b1;
1293,6 → 675,7
state <= WAIT_DHIT;
dmiss <= `TRUE;
end
`endif
end
IRQ2:
begin
1317,6 → 700,7
we_o <= 1'b0;
sel_o <= 4'h0;
isp <= isp_dec;
`ifdef SUPPORT_DCACHE
if (dhit) begin
wrsel <= sel_o;
wr <= 1'b1;
1325,15 → 709,14
dmiss <= `TRUE;
state <= WAIT_DHIT;
end
`endif
radr <= vect[31:2];
if (hwi)
im <= 1'b1;
em <= 1'b0; // make sure we process in native mode; we might have been called up during emulation mode
end
 
*/
MULDIV1:
state <= MULDIV2;
MULDIV2:
if (md_done) begin
state <= IFETCH;
case(ir[23:20])
1346,6 → 729,7
endcase
end
 
`ifdef SUPPORT_BERR
BUS_ERROR:
begin
radr <= isp_dec;
1355,15 → 739,9
derr_address <= adr_o[31:0];
else
derr_address <= adr_o[33:2];
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {isp_dec,2'b00};
dat_o <= opc;
vect <= {vbr[31:9],9'd508,2'b00};
hwi <= `TRUE;
state <= IRQ1;
state <= IRQ0;
end
INSN_BUS_ERROR:
begin
1370,21 → 748,17
radr <= isp_dec;
wadr <= isp_dec;
wdat <= opc;
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {isp_dec,2'b00};
dat_o <= opc;
vect <= {vbr[31:9],9'd509,2'b00};
hwi <= `TRUE;
state <= IRQ1;
state <= IRQ0;
end
/*
`endif
 
`ifdef SUPPORT_STRING
MVN1:
begin
radr <= x;
x <= x + 32'd1;
res <= x + 32'd1;
retstate <= MVN2;
load_what <= `WORD_312;
state <= LOAD_MAC1;
1393,8 → 767,9
begin
radr <= y;
wadr <= y;
wdat <= b;
y <= y + 32'd1;
store_what <= `STW_B;
x <= res;
res <= y + 32'd1;
acc <= acc - 32'd1;
state <= STORE1;
end
1401,6 → 776,7
MVN3:
begin
state <= IFETCH;
y <= res;
if (acc==32'hFFFFFFFF)
pc <= pc + 32'd1;
end
1407,7 → 783,7
MVP1:
begin
radr <= x;
x <= x - 32'd1;
res <= x - 32'd1;
retstate <= MVP2;
load_what <= `WORD_312;
state <= LOAD_MAC1;
1416,12 → 792,23
begin
radr <= y;
wadr <= y;
wdat <= b;
y <= y - 32'd1;
store_what <= `STW_B;
x <= res;
res <= y - 32'd1;
acc <= acc - 32'd1;
state <= STORE1;
end
*/
STS1:
begin
radr <= y;
wadr <= y;
store_what <= `STW_X;
res <= y + 32'd1;
acc <= acc - 32'd1;
state <= STORE1;
end
`endif
 
endcase
 
`include "cache_controller.v"
/trunk/rtl/verilog/calc.v
18,47 → 18,22
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Datapath calculations for 32 bit mode.
// Extra state required for some datapath operations.
// ============================================================================
//
CALC:
begin
state <= IFETCH;
res <= calc_res;
wadr <= radr; // These two lines for the shift/inc/dec ops
store_what <= `STW_CALC;
case(ir[7:0])
//The following handled in the DECODE stage which reduces the CPI at a cost of clock frequency.
`RR:
case(ir[23:20])
// `ADD_RR: res <= a + b;
// `SUB_RR: res <= a - b; // Also CMP
// `AND_RR: res <= a & b; // Also BIT
// `OR_RR: res <= a | b;
// `EOR_RR: res <= a ^ b;
// `MUL_RR: prod <= a * b; // slows the whole core down
`ASL_RRR: res <= shlo;
`LSR_RRR: res <= shro;
endcase
`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND: begin res <= a + b + {31'b0,df&cf}; end
`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND: begin res <= a - b - {31'b0,df&~cf&|Rt}; end // Also CMP
`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND: begin res <= a & b; end // Also BIT
`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND: begin res <= a | b; end // Also LD
`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND: begin res <= a ^ b; end
`LDX_ZPY,`LDX_ABS,`LDX_ABSY: begin res <= b; end
`LDY_ZPX,`LDY_ABS,`LDY_ABSX: begin res <= b; end
`CPX_ZPX,`CPX_ABS: begin res <= x - b; end
`CPY_ZPX,`CPY_ABS: begin res <= y - b; end
`ASL_IMM8: res <= shlo;
`LSR_IMM8: res <= shro;
//The following handled in the DECODE stage which reduces the CPI at a cost of clock frequency.
// `ASL_RR: begin res <= {a,1'b0}; end
// `ROL_RR: begin res <= {a,cf}; end
// `LSR_RR: begin res <= {a[0],1'b0,a[31:1]}; end
// `ROR_RR: begin res <= {a[0],cf,a[31:1]}; end
`ASL_ZPX,`ASL_ABS,`ASL_ABSX: begin res <= {b,1'b0}; wdat <= {b,1'b0}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
`ROL_ZPX,`ROL_ABS,`ROL_ABSX: begin res <= {b,cf}; wdat <= {b,cf}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
`LSR_ZPX,`LSR_ABS,`LSR_ABSX: begin res <= {b[0],1'b0,b[31:1]}; wdat <= {b[0],1'b0,b[31:1]}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
`ROR_ZPX,`ROR_ABS,`ROR_ABSX: begin res <= {b[0],cf,b[31:1]}; wdat <= {b[0],cf,b[31:1]}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
`INC_ZPX,`INC_ABS,`INC_ABSX: begin res <= b + 1; wdat <= b + 1; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
`DEC_ZPX,`DEC_ABS,`DEC_ABSX: begin res <= b - 1; wdat <= b - 1; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
`ORB_ZPX,`ORB_ABS,`ORB_ABSX: begin res <= a | {24'h0,b8}; end
`ASL_ZPX,`ASL_ABS,`ASL_ABSX,
`ROL_ZPX,`ROL_ABS,`ROL_ABSX,
`LSR_ZPX,`LSR_ABS,`LSR_ABSX,
`ROR_ZPX,`ROR_ABS,`ROR_ABSX,
`INC_ZPX,`INC_ABS,`INC_ABSX,
`DEC_ZPX,`DEC_ABS,`DEC_ABSX:
state <= STORE1;
endcase
end
/trunk/rtl/verilog/cache_controller.v
27,6 → 27,7
IDLE:
begin
if (!cyc_o) begin
`ifdef SUPPORT_DCACHE
// A write to a cacheable address does not cause a cache load
if (dmiss) begin
isDataCacheLoad <= `TRUE;
40,7 → 41,10
adr_o <= {radr[31:2],4'h0};
cstate <= LOAD_DCACHE;
end
else if (!unCachedInsn && imiss && !hit0) begin
else
`endif
`ifdef SUPPORT_ICACHE
if (!unCachedInsn && imiss && !hit0) begin
isInsnCacheLoad <= `TRUE;
bte_o <= 2'b00;
cti_o <= 3'd001;
62,7 → 66,9
adr_o <= {pcp8[31:4],4'h0};
cstate <= LOAD_ICACHE;
end
else if (unCachedInsn && imiss) begin
else
`endif
if (unCachedInsn && imiss) begin
bte_o <= 2'b00;
cti_o <= 3'b001;
bl_o <= 6'd2;
74,6 → 80,7
end
end
end
`ifdef SUPPORT_DCACHE
LOAD_DCACHE:
if (ack_i) begin
if (adr_o[3:2]==2'b11) begin
90,6 → 97,7
adr_o <= adr_o + 34'd4;
end
// What to do here
`ifdef SUPPORT_BERR
else if (err_i) begin
if (adr_o[3:2]==2'b11) begin
dmiss <= `FALSE;
107,6 → 115,9
end
adr_o <= adr_o + 34'd4;
end
`endif
`endif
`ifdef SUPPORT_ICACHE
LOAD_ICACHE:
if (ack_i) begin
if (adr_o[3:2]==2'b11) begin
122,6 → 133,7
end
adr_o <= adr_o + 34'd4;
end
`ifdef SUPPORT_BERR
else if (err_i) begin
if (adr_o[3:2]==2'b11) begin
imiss <= `FALSE;
137,6 → 149,8
end
adr_o <= adr_o + 34'd4;
end
`endif
`endif
LOAD_IBUF1:
if (ack_i|err_i) begin
case(pc[1:0])
177,6 → 191,7
imiss <= `FALSE;
bufadr <= pc; // clears the miss
end
`ifdef SUPPORT_BERR
else if (err_i) begin
case(pc[1:0])
2'd0: ;
195,5 → 210,6
imiss <= `FALSE;
bufadr <= pc; // clears the miss
end
`endif
 
endcase
/trunk/rtl/verilog/rtf65002_dcachemem.v
0,0 → 1,49
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
module rtf65002_dcachemem(wclk, wr, sel, wadr, wdat, rclk, radr, rdat);
input wclk;
input wr;
input [3:0] sel;
input [31:0] wadr;
input [31:0] wdat;
input rclk;
input [31:0] radr;
output [31:0] rdat;
 
syncRam2kx32_1rw1r ram0 (
.wrst(1'b0),
.wclk(wclk),
.wce(1'b1),
.we(wr),
.wsel(sel),
.wadr(wadr[10:0]),
.i(wdat),
.wo(),
.rrst(1'b0),
.rclk(rclk),
.rce(1'b1),
.radr(radr[10:0]),
.o(rdat)
);
 
endmodule
/trunk/rtl/verilog/byte_irq.v
25,7 → 25,6
//
BYTE_IRQ1:
if (ack_i) begin
ir <= 64'd0;
state <= BYTE_IRQ2;
retstate <= BYTE_IRQ2;
cyc_o <= 1'b0;
178,8 → 177,9
end
BYTE_IRQ9:
if (ack_i) begin
state <= BYTE_JMP_IND1;
retstate <= BYTE_JMP_IND1;
load_what <= `PC_70;
state <= LOAD_MAC1;
retstate <= LOAD_MAC1;
cyc_o <= 1'b0;
stb_o <= 1'b0;
we_o <= 1'b0;
/trunk/rtl/verilog/decode.v
25,28 → 25,32
first_ifetch <= `TRUE;
Rt <= 4'h0; // Default
state <= IFETCH;
pc <= pcp1;
pc <= pc + pc_inc;
a <= rfoa;
// This case statement should include all opcodes or the opcode
// will end up being treated as an undefined operation.
case(ir[7:0])
`STP: begin clk_en <= 1'b0; end
`NOP: casex(ir[63:0])
{`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp8;
{8'hxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp7;
{16'hxxxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp6;
{24'hxxxxxx,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp5;
{32'hxxxxxxxx,`NOP,`NOP,`NOP,`NOP}: pc <= pcp4;
{40'hxxxxxxxxxx,`NOP,`NOP,`NOP}: pc <= pcp3;
{48'hxxxxxxxxxxxx,`NOP,`NOP}: pc <= pcp2;
{56'hxxxxxxxxxxxxxx,`NOP}: pc <= pcp1;
endcase
`CLC: begin cf <= 1'b0; end
`SEC: begin cf <= 1'b1; end
`CLV: begin vf <= 1'b0; end
`CLI: begin im <= 1'b0; end
`CLD: begin df <= 1'b0; end
`SED: begin df <= 1'b1; end
`SEI: begin im <= 1'b1; end
`WAI: begin wai <= 1'b1; end
`EMM: begin em <= 1'b1; end
`STP: clk_en <= 1'b0;
`NOP: ;
// casex(ir[63:0])
// {`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp8;
// {8'hxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp7;
// {16'hxxxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp6;
// {24'hxxxxxx,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp5;
// {32'hxxxxxxxx,`NOP,`NOP,`NOP,`NOP}: pc <= pcp4;
// {40'hxxxxxxxxxx,`NOP,`NOP,`NOP}: pc <= pcp3;
// {48'hxxxxxxxxxxxx,`NOP,`NOP}: pc <= pcp2;
// {56'hxxxxxxxxxxxxxx,`NOP}: pc <= pcp1;
// endcase
`CLC: cf <= 1'b0;
`SEC: cf <= 1'b1;
`CLV: vf <= 1'b0;
`CLI: im <= 1'b0;
`CLD: df <= 1'b0;
`SED: df <= 1'b1;
`SEI: im <= 1'b1;
`WAI: wai <= 1'b1;
`EMM: em <= 1'b1;
`DEX: begin
res <= x - 32'd1;
// DEX/BNE accelerator
65,34 → 69,41
// end
// end
end
`INX: begin res <= x + 32'd1; end
`DEY: begin res <= y - 32'd1; end
`INY: begin res <= y + 32'd1; end
`DEA: begin res <= acc - 32'd1; end
`INA: begin res <= acc + 32'd1; end
`TSX,`TSA: begin res <= isp; end
`TXS,`TXA,`TXY: begin res <= x; end
`TAX,`TAY,`TAS: begin res <= acc; end
`TYA,`TYX: begin res <= y; end
`TRS: begin
res <= rfoa; pc <= pcp2; end
`INX: res <= x + 32'd1;
`DEY: res <= y - 32'd1;
`INY: res <= y + 32'd1;
`DEA: res <= acc - 32'd1;
`INA: res <= acc + 32'd1;
`TSX,`TSA: res <= isp;
`TXS,`TXA,`TXY: res <= x;
`TAX,`TAY,`TAS: res <= acc;
`TYA,`TYX: res <= y;
`TRS: res <= rfoa;
`TSR: begin
Rt <= ir[15:12];
case(ir[11:8])
4'h0: res <= {write_allocate,dcacheOn,icacheOn};
4'h1: res <= dp;
4'h0:
begin
`ifdef SUPPORT_ICACHE
res[0] <= icacheOn;
`endif
`ifdef SUPPORT_DCACHE
res[1] <= dcacheOn;
res[2] <= write_allocate;
`endif
res[31:3] <= 29'd0;
end
4'h2: res <= prod[31:0];
4'h3: res <= prod[63:32];
4'h4: res <= tick;
4'h5: begin res <= lfsr; lfsr <= {lfsr[30:0],lfsr_fb}; end
4'h6: res <= dp8;
4'h7: res <= abs8;
4'h7: begin res <= history_buf[history_ndx]; history_ndx <= history_ndx + 6'd1; end// was abs8
4'h8: res <= {vbr[31:1],nmoi};
4'h9: res <= derr_address;
4'hE: res <= {spage[31:8],sp};
4'hF: res <= isp;
default: res <= 32'd0;
endcase
pc <= pcp2;
end
`ASL_ACC: begin res <= {acc,1'b0}; end
`ROL_ACC: begin res <= {acc,cf};end
102,75 → 113,88
`RR:
begin
state <= IFETCH;
Rt <= ir[19:16];
case(ir[23:20])
`ADD_RR: begin res <= rfoa + rfob + {31'b0,df&cf}; a <= rfoa; b <= rfob; end
`SUB_RR: begin res <= rfoa - rfob - {31'b0,df&~cf&|ir[19:16]}; a <= rfoa; b <= rfob; end
`AND_RR: begin res <= rfoa & rfob; a <= rfoa; b <= rfob; end // for bit flags
`OR_RR: begin res <= rfoa | rfob; a <= rfoa; b <= rfob; end
`EOR_RR: begin res <= rfoa ^ rfob; a <= rfoa; b <= rfob; end
`ADD_RR: begin res <= rfoa + rfob + {31'b0,df&cf}; b <= rfob; end
`SUB_RR: begin res <= rfoa - rfob - {31'b0,df&~cf&|ir[19:16]}; b <= rfob; end
`AND_RR: begin res <= rfoa & rfob; b <= rfob; end // for bit flags
`OR_RR: begin res <= rfoa | rfob; b <= rfob; end
`EOR_RR: begin res <= rfoa ^ rfob; b <= rfob; end
`MUL_RR: begin state <= MULDIV1; end
`MULS_RR: begin state <= MULDIV1; end
`ifdef SUPPORT_DIVMOD
`DIV_RR: begin state <= MULDIV1; end
`DIVS_RR: begin state <= MULDIV1; end
`MOD_RR: begin state <= MULDIV1; end
`MODS_RR: begin state <= MULDIV1; end
`ASL_RRR: begin a <= rfoa; b <= rfob; state <= CALC; end
`LSR_RRR: begin a <= rfoa; b <= rfob; state <= CALC; end
`endif
`ifdef SUPPORT_SHIFT
`ASL_RRR: begin b <= rfob; state <= CALC; end
`LSR_RRR: begin b <= rfob; state <= CALC; end
`endif
default:
begin
Rt <= 4'h0;
ir <= {8{`BRK}};
hwi <= `TRUE;
vect <= {vbr[31:9],9'd495,2'b00};
pc <= pc; // override the pc increment
state <= DECODE;
end
endcase
Rt <= ir[19:16];
pc <= pcp3;
end
`LD_RR: begin res <= rfoa; Rt <= ir[15:12]; pc <= pcp2; end
`ASL_RR: begin res <= {rfoa,1'b0}; pc <= pcp2; Rt <= ir[15:12]; end
`ROL_RR: begin res <= {rfoa,cf}; pc <= pcp2; Rt <= ir[15:12]; end
`LSR_RR: begin res <= {rfoa[0],1'b0,rfoa[31:1]}; pc <= pcp2; Rt <= ir[15:12]; end
`ROR_RR: begin res <= {rfoa[0],cf,rfoa[31:1]}; pc <= pcp2; Rt <= ir[15:12]; end
`DEC_RR: begin res <= rfoa - 32'd1; pc <= pcp2; Rt <= ir[15:12]; end
`INC_RR: begin res <= rfoa + 32'd1; pc <= pcp2; Rt <= ir[15:12]; end
`LD_RR: begin res <= rfoa; Rt <= ir[15:12]; end
`ASL_RR: begin res <= {rfoa,1'b0}; Rt <= ir[15:12]; end
`ROL_RR: begin res <= {rfoa,cf}; Rt <= ir[15:12]; end
`LSR_RR: begin res <= {rfoa[0],1'b0,rfoa[31:1]}; Rt <= ir[15:12]; end
`ROR_RR: begin res <= {rfoa[0],cf,rfoa[31:1]}; Rt <= ir[15:12]; end
`DEC_RR: begin res <= rfoa - 32'd1; Rt <= ir[15:12]; end
`INC_RR: begin res <= rfoa + 32'd1; Rt <= ir[15:12]; end
 
`ADD_IMM8: begin res <= rfoa + {{24{ir[23]}},ir[23:16]} + {31'b0,df&cf}; Rt <= ir[15:12]; pc <= pcp3; a <= rfoa; b <= {{24{ir[23]}},ir[23:16]}; end
`SUB_IMM8: begin res <= rfoa - {{24{ir[23]}},ir[23:16]} - {31'b0,df&~cf&|ir[15:12]}; Rt <= ir[15:12]; pc <= pcp3; a <= rfoa; b <= {{24{ir[23]}},ir[23:16]}; end
`OR_IMM8: begin res <= rfoa | {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pcp3; b <= {{24{ir[23]}},ir[23:16]}; end
`AND_IMM8: begin res <= rfoa & {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pcp3; b <= {{24{ir[23]}},ir[23:16]}; end
`EOR_IMM8: begin res <= rfoa ^ {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pcp3; b <= {{24{ir[23]}},ir[23:16]}; end
`CMP_IMM8: begin res <= acc - {{24{ir[15]}},ir[15:8]}; Rt <= 4'h0; pc <= pcp2; b <= {{24{ir[15]}},ir[15:8]}; end
`ASL_IMM8: begin a <= rfoa; b <= ir[20:16]; Rt <= ir[15:12]; pc <= pcp3; state <= CALC; end
`LSR_IMM8: begin a <= rfoa; b <= ir[20:16]; Rt <= ir[15:12]; pc <= pcp3; state <= CALC; end
 
`ADD_IMM16: begin res <= rfoa + {{16{ir[31]}},ir[31:16]} + {31'b0,df&cf}; Rt <= ir[15:12]; pc <= pcp4; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
`SUB_IMM16: begin res <= rfoa - {{16{ir[31]}},ir[31:16]} - {31'b0,df&~cf&|ir[15:12]}; Rt <= ir[15:12]; pc <= pcp4; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
`OR_IMM16: begin res <= rfoa | {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pcp4; b <= {{16{ir[31]}},ir[31:16]}; end
`AND_IMM16: begin res <= rfoa & {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pcp4; b <= {{16{ir[31]}},ir[31:16]}; end
`EOR_IMM16: begin res <= rfoa ^ {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pcp4; b <= {{16{ir[31]}},ir[31:16]}; end
`ADD_IMM8: begin res <= rfoa + {{24{ir[23]}},ir[23:16]} + {31'b0,df&cf}; Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
`SUB_IMM8: begin res <= rfoa - {{24{ir[23]}},ir[23:16]} - {31'b0,df&~cf&|ir[15:12]}; Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
`OR_IMM8: begin res <= rfoa | {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; end
`AND_IMM8: begin res <= rfoa & {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
`EOR_IMM8: begin res <= rfoa ^ {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; end
`CMP_IMM8: begin res <= acc - {{24{ir[15]}},ir[15:8]}; end
`ifdef SUPPORT_SHIFT
`ASL_IMM8: begin b <= ir[20:16]; Rt <= ir[15:12]; state <= CALC; end
`LSR_IMM8: begin b <= ir[20:16]; Rt <= ir[15:12]; state <= CALC; end
`endif
`ADD_IMM16: begin res <= rfoa + {{16{ir[31]}},ir[31:16]} + {31'b0,df&cf}; Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; end
`SUB_IMM16: begin res <= rfoa - {{16{ir[31]}},ir[31:16]} - {31'b0,df&~cf&|ir[15:12]}; Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; end
`OR_IMM16: begin res <= rfoa | {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; end
`AND_IMM16: begin res <= rfoa & {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; end
`EOR_IMM16: begin res <= rfoa ^ {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; end
`ADD_IMM32: begin res <= rfoa + ir[47:16]; Rt <= ir[15:12] + {31'b0,df&cf}; pc <= pcp6; a <= rfoa; b <= ir[47:16]; end
`SUB_IMM32: begin res <= rfoa - ir[47:16]; Rt <= ir[15:12] - {31'b0,df&~cf&|ir[15:12]}; pc <= pcp6; a <= rfoa; b <= ir[47:16]; end
`OR_IMM32: begin res <= rfoa | ir[47:16]; Rt <= ir[15:12]; pc <= pcp6; b <= ir[47:16]; end
`AND_IMM32: begin res <= rfoa & ir[47:16]; Rt <= ir[15:12]; pc <= pcp6; b <= ir[47:16]; end
`EOR_IMM32: begin res <= rfoa ^ ir[47:16]; Rt <= ir[15:12]; pc <= pcp6; b <= ir[47:16]; end
`ADD_IMM32: begin res <= rfoa + ir[47:16] + {31'b0,df&cf}; Rt <= ir[15:12]; b <= ir[47:16]; end
`SUB_IMM32: begin res <= rfoa - ir[47:16] - {31'b0,df&~cf&|ir[15:12]}; Rt <= ir[15:12]; b <= ir[47:16]; end
`OR_IMM32: begin res <= rfoa | ir[47:16]; Rt <= ir[15:12]; end
`AND_IMM32: begin res <= rfoa & ir[47:16]; Rt <= ir[15:12]; b <= ir[47:16]; end
`EOR_IMM32: begin res <= rfoa ^ ir[47:16]; Rt <= ir[15:12]; end
 
`LDX_IMM32,`LDY_IMM32,`LDA_IMM32: begin res <= ir[39:8]; pc <= pcp5; end
`LDX_IMM16,`LDA_IMM16: begin res <= {{16{ir[23]}},ir[23:8]}; pc <= pcp3; end
`LDX_IMM8,`LDA_IMM8: begin res <= {{24{ir[15]}},ir[15:8]}; pc <= pcp2; end
`LDX_IMM32,`LDY_IMM32,`LDA_IMM32: res <= ir[39:8];
`LDX_IMM16,`LDA_IMM16: res <= {{16{ir[23]}},ir[23:8]};
`LDX_IMM8,`LDA_IMM8: res <= {{24{ir[15]}},ir[15:8]};
 
`SUB_SP8: begin res <= isp - {{24{ir[15]}},ir[15:8]}; pc <= pcp2; end
`SUB_SP16: begin res <= isp - {{16{ir[23]}},ir[23:8]}; pc <= pcp3; end
`SUB_SP32: begin res <= isp - ir[39:8]; pc <= pcp5; end
`SUB_SP8: res <= isp - {{24{ir[15]}},ir[15:8]};
`SUB_SP16: res <= isp - {{16{ir[23]}},ir[23:8]};
`SUB_SP32: res <= isp - ir[39:8];
 
`CPX_IMM32: res <= x - ir[39:8];
`CPY_IMM32: res <= y - ir[39:8];
 
`LDX_ZPX,`LDY_ZPX:
begin
radr <= zpx32xy_address;
pc <= pcp3;
load_what <= `WORD_311;
state <= LOAD_MAC1;
end
`ORB_ZPX:
begin
a <= rfoa;
Rt <= ir[19:16];
radr <= zpx32_address[31:2];
radr2LSB <= zpx32_address[1:0];
pc <= pcp4;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
177,17 → 201,14
`LDX_ABS,`LDY_ABS:
begin
radr <= ir[39:8];
pc <= pcp5;
load_what <= `WORD_311;
state <= LOAD_MAC1;
end
`ORB_ABS:
begin
a <= rfoa;
Rt <= ir[15:12];
radr <= ir[47:18];
radr2LSB <= ir[17:16];
pc <= pcp6;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
194,17 → 215,14
`LDX_ABSY,`LDY_ABSX:
begin
radr <= absx32xy_address;
pc <= pcp6;
load_what <= `WORD_311;
state <= LOAD_MAC1;
end
`ORB_ABSX:
begin
a <= rfoa;
Rt <= ir[19:16];
radr <= absx32_address[31:2];
radr2LSB <= absx32_address[1:0];
pc <= pcp7;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
211,8 → 229,7
`ST_ZPX:
begin
wadr <= zpx32_address;
wdat <= rfoa;
pc <= pcp4;
store_what <= `STW_RFA;
state <= STORE1;
end
`STB_ZPX:
219,22 → 236,19
begin
wadr <= zpx32_address[31:2];
wadr2LSB <= zpx32_address[1:0];
wdat <= {4{rfoa[7:0]}};
pc <= pcp4;
store_what <= `STW_RFA8;
state <= STORE1;
end
`ST_DSP:
begin
wadr <= {{24{ir[23]}},ir[23:16]} + isp;
wdat <= rfoa;
pc <= pcp3;
store_what <= `STW_RFA;
state <= STORE1;
end
`ST_ABS:
begin
wadr <= ir[47:16];
wdat <= rfoa;
pc <= pcp6;
store_what <= `STW_RFA;
state <= STORE1;
end
`STB_ABS:
241,15 → 255,13
begin
wadr <= ir[47:18];
wadr2LSB <= ir[17:16];
wdat <= {4{rfoa[7:0]}};
pc <= pcp6;
store_what <= `STW_RFA8;
state <= STORE1;
end
`ST_ABSX:
begin
wadr <= absx32_address;
wdat <= rfoa;
pc <= pcp7;
store_what <= `STW_RFA;
state <= STORE1;
end
`STB_ABSX:
256,79 → 268,66
begin
wadr <= absx32_address[31:2];
wadr2LSB <= absx32_address[1:0];
wdat <= {4{rfoa[7:0]}};
pc <= pcp7;
store_what <= `STW_RFA8;
state <= STORE1;
end
`STX_ZPX:
begin
wadr <= dp + ir[23:12] + rfoa;
wdat <= x;
pc <= pcp3;
wadr <= zpx32xy_address;
store_what <= `STW_X;
state <= STORE1;
end
`STX_ABS:
begin
wadr <= ir[39:8];
wdat <= x;
pc <= pcp5;
store_what <= `STW_X;
state <= STORE1;
end
`STY_ZPX:
begin
wadr <= dp + ir[23:12] + rfoa;
wdat <= y;
pc <= pcp3;
wadr <= zpx32xy_address;
store_what <= `STW_Y;
state <= STORE1;
end
`STY_ABS:
begin
wadr <= ir[39:8];
wdat <= y;
pc <= pcp5;
store_what <= `STW_Y;
state <= STORE1;
end
`ADD_ZPX,`SUB_ZPX,`OR_ZPX,`AND_ZPX,`EOR_ZPX:
begin
a <= rfoa;
Rt <= ir[19:16];
radr <= zpx32_address;
pc <= pcp4;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
begin
radr <= dp + rfoa + ir[23:12];
pc <= pcp3;
radr <= zpx32xy_address;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`ADD_DSP,`SUB_DSP,`OR_DSP,`AND_DSP,`EOR_DSP:
begin
a <= rfoa;
Rt <= ir[15:12];
radr <= {{24{ir[23]}},ir[23:16]} + isp;
pc <= pcp3;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX:
begin
a <= rfoa;
if (ir[7:0]!=`ST_IX) // for ST_IX, Rt=0
Rt <= ir[19:16];
pc <= pcp4;
radr <= dp + ir[31:20] + rfob;
radr <= zpx32_address;
load_what <= `IA_310;
store_what <= `STW_A;
state <= LOAD_MAC1;
end
`ADD_RIND,`SUB_RIND,`OR_RIND,`AND_RIND,`EOR_RIND:
begin
radr <= rfob;
a <= rfoa;
Rt <= ir[19:16];
pc <= pcp3;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
335,27 → 334,23
`ST_RIND:
begin
wadr <= rfob;
wdat <= rfoa;
pc <= pcp2;
store_what <= `STW_RFA;
state <= STORE1;
end
`ADD_IY,`SUB_IY,`OR_IY,`AND_IY,`EOR_IY,`ST_IY:
begin
a <= rfoa;
if (ir[7:0]!=`ST_IY) // for ST_IY, Rt=0
Rt <= ir[19:16];
pc <= pcp4;
isIY <= 1'b1;
radr <= dp + ir[31:20];
radr <= ir[31:20];
load_what <= `IA_310;
store_what <= `STW_A;
state <= LOAD_MAC1;
end
`ADD_ABS,`SUB_ABS,`OR_ABS,`AND_ABS,`EOR_ABS:
begin
a <= rfoa;
radr <= ir[47:16];
Rt <= ir[15:12];
pc <= pcp6;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
362,49 → 357,32
`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS:
begin
radr <= ir[39:8];
pc <= pcp5;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`ADD_ABSX,`SUB_ABSX,`OR_ABSX,`AND_ABSX,`EOR_ABSX:
begin
a <= rfoa;
radr <= ir[55:24] + rfob;
radr <= absx32_address;
Rt <= ir[19:16];
pc <= pcp7;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX:
begin
radr <= ir[47:16] + rfob;
pc <= pcp6;
radr <= absx32xy_address;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`CPX_IMM32:
begin
res <= x - ir[39:8];
pc <= pcp5;
state <= IFETCH;
end
`CPY_IMM32:
begin
res <= y - ir[39:8];
pc <= pcp5;
state <= IFETCH;
end
 
`CPX_ZPX:
begin
radr <= dp + ir[23:12] + rfoa;
pc <= pcp3;
radr <= zpx32xy_address;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`CPY_ZPX:
begin
radr <= dp + ir[23:12] + rfoa;
pc <= pcp3;
radr <= zpx32xy_address;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
411,7 → 389,6
`CPX_ABS:
begin
radr <= ir[39:8];
pc <= pcp5;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
418,38 → 395,24
`CPY_ABS:
begin
radr <= ir[39:8];
pc <= pcp5;
load_what <= `WORD_310;
state <= LOAD_MAC1;
end
`BRK:
begin
bf <= 1'b1;
bf <= !hwi;
hist_capture <= `FALSE;
radr <= isp_dec;
wadr <= isp_dec;
wdat <= pc+2;
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {isp_dec,2'b00};
dat_o <= pc+2;
vect <= {vbr[31:9],`BRK_VECTNO,2'b00};
state <= IRQ1;
isp <= isp_dec;
store_what <= `STW_PCHWI;
state <= STORE1;
end
`INT0,`INT1:
begin
radr <= isp_dec;
wadr <= isp_dec;
wdat <= pc + 32'd2;
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {isp_dec,2'b00};
dat_o <= pc + 32'd2;
ir <= {8{`BRK}};
vect <= {vbr[31:9],ir[15:7],2'b00};
state <= IRQ1;
state <= DECODE;
end
`JMP:
begin
484,15 → 447,11
begin
radr <= isp_dec;
wadr <= isp_dec;
wdat <= suppress_pcinc[0] ? pc + 32'd3 : pc + 32'd2;
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {isp_dec,2'b00};
dat_o <= suppress_pcinc[0] ? pc + 32'd3 : pc + 32'd2;
vect <= {pc[31:16],ir[23:8]};
state <= JSR1;
isp <= isp_dec;
store_what <= `STW_DEF;
wdat <= pc+{31'd1,suppress_pcinc[0]};
pc <= {pc[31:16],ir[23:8]};
state <= STORE1;
end
`JSR_RIND:
begin
499,48 → 458,35
radr <= isp_dec;
wadr <= isp_dec;
wdat <= pc + 32'd2;
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {isp_dec,2'b00};
dat_o <= pc + 32'd2;
vect <= rfoa;
state <= JSR1;
$stop;
isp <= isp_dec;
store_what <= `STW_DEF;
pc <= rfoa;
state <= STORE1;
end
`JSL:
begin
radr <= isp_dec;
wadr <= isp_dec;
isp <= isp_dec;
store_what <= `STW_DEF;
wdat <= suppress_pcinc[0] ? pc + 32'd5 : pc + 32'd2;
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {isp_dec,2'b00};
dat_o <= suppress_pcinc[0] ? pc + 32'd5 : pc + 32'd2;
vect <= ir[39:8];
state <= JSR1;
pc <= ir[39:8];
state <= STORE1;
end
`BSR:
begin
radr <= isp_dec;
wadr <= isp_dec;
wdat <= suppress_pcinc[0] ? pc + 32'd3 : pc + 32'd2;
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {isp_dec,2'b00};
dat_o <= suppress_pcinc[0] ? pc + 32'd3 : pc + 32'd2;
vect <= pc + {{16{ir[23]}},ir[23:8]};
state <= JSR1;
isp <= isp_dec;
store_what <= `STW_DEF;
wdat <= pc+{31'd1,suppress_pcinc[0]};
pc <= pc + {{16{ir[23]}},ir[23:8]};
state <= STORE1;
end
`JSR_INDX:
begin
radr <= isp - 32'd1;
wadr <= isp - 32'd1;
radr <= isp_dec;
wadr <= isp_dec;
wdat <= suppress_pcinc[0] ? pc + 32'd5 : pc + 32'd2;
cyc_o <= 1'b1;
stb_o <= 1'b1;
570,25 → 516,20
state <= LOAD_MAC1;
end
`RTI: begin
hist_capture <= `TRUE;
radr <= isp;
load_what <= `SR_310;
state <= LOAD_MAC1;
end
`BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA:
`BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA,
`BGT,`BGE,`BLT,`BLE,`BHI,`BLS:
begin
state <= IFETCH;
if (ir[15:8]==8'h00) begin
radr <= isp_dec;
wadr <= isp_dec;
wdat <= pc + 32'd2;
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {isp_dec,2'b00};
dat_o <= pc + 32'd2;
ir <= {8{`BRK}};
pc <= pc; // override the pc increment
vect <= {vbr[31:9],`SLP_VECTNO,2'b00};
state <= IRQ1;
state <= DECODE;
end
else if (ir[15:8]==8'h1) begin
if (takb)
603,49 → 544,13
pc <= pcp2;
end
end
/* `BEQ_RR:
begin
state <= IFETCH;
if (ir[23:16]==8'h00) begin
radr <= isp_dec;
wadr <= isp_dec;
wdat <= pc + 32'd2;
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {isp_dec,2'b00};
dat_o <= pc + 32'd2;
vect <= `SLP_VECT;
state <= IRQ1;
end
else if (ir[23:16]==8'h1) begin
if (rfoa==rfob)
pc <= pc + {{16{ir[39]}},ir[39:24]};
else
pc <= pc + 32'd5;
end
else begin
if (takb)
pc <= pc + {{24{ir[23]}},ir[23:16]};
else
pc <= pc + 32'd3;
end
end*/
`BRL:
begin
if (ir[23:8]==16'h0000) begin
radr <= isp_dec;
wadr <= isp_dec;
wdat <= suppress_pcinc[0] ? pc + 32'd3 : pc + 32'd2;
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {isp_dec,2'b00};
dat_o <= suppress_pcinc[0] ? pc + 32'd3 : pc + 32'd2;
ir <= {8{`BRK}};
vect <= {vbr[31:9],`SLP_VECTNO,2'b00};
state <= IRQ1;
pc <= pc; // override the pc increment
state <= DECODE;
end
else begin
pc <= pc + {{16{ir[23]}},ir[23:8]};
652,83 → 557,53
state <= IFETCH;
end
end
`ifdef SUPPORT_EXEC
`EXEC,`ATNI:
begin
exbuf[31:0] <= rfoa;
exbuf[63:32] <= rfob;
pc <= pc + 32'd2;
state <= IFETCH;
end
`endif
`PHP:
begin
cyc_o <= 1'b1;
stb_o <= 1'b1;
sel_o <= 4'hF;
we_o <= 1'b1;
radr <= isp_dec;
wadr <= isp_dec;
wdat <= sr;
adr_o <= {isp_dec,2'b00};
dat_o <= sr;
store_what <= `STW_SR;
isp <= isp_dec;
state <= STORE2;
state <= STORE1;
end
`PHA:
begin
cyc_o <= 1'b1;
stb_o <= 1'b1;
sel_o <= 4'hF;
we_o <= 1'b1;
radr <= isp_dec;
wadr <= isp_dec;
wdat <= acc;
adr_o <= {isp_dec,2'b00};
dat_o <= acc;
store_what <= `STW_ACC;
isp <= isp_dec;
state <= STORE2;
state <= STORE1;
end
`PHX:
begin
cyc_o <= 1'b1;
stb_o <= 1'b1;
sel_o <= 4'hF;
we_o <= 1'b1;
radr <= isp_dec;
wadr <= isp_dec;
wdat <= x;
adr_o <= {isp_dec,2'b00};
dat_o <= x;
store_what <= `STW_X;
isp <= isp_dec;
state <= STORE2;
state <= STORE1;
end
`PHY:
begin
cyc_o <= 1'b1;
stb_o <= 1'b1;
sel_o <= 4'hF;
we_o <= 1'b1;
radr <= isp_dec;
wadr <= isp_dec;
wdat <= y;
adr_o <= {isp_dec,2'b00};
dat_o <= y;
store_what <= `STW_Y;
isp <= isp_dec;
state <= STORE2;
state <= STORE1;
end
`PUSH:
begin
cyc_o <= 1'b1;
stb_o <= 1'b1;
sel_o <= 4'hF;
we_o <= 1'b1;
radr <= isp_dec;
wadr <= isp_dec;
wdat <= rfoa;
adr_o <= {isp_dec,2'b00};
dat_o <= rfoa;
state <= STORE2;
store_what <= `STW_RFA;
state <= STORE1;
isp <= isp_dec;
pc <= pcp2;
end
`PLP:
begin
750,23 → 625,20
isp <= isp_inc;
load_what <= `WORD_311;
state <= LOAD_MAC1;
pc <= pcp2;
end
// `MVN: state <= MVN1;
// `MVP: state <= MVP1;
`ifdef SUPPORT_STRING
`MVN: state <= MVN1;
`MVP: state <= MVP1;
`STS: state <= STS1;
`endif
default: // unimplemented opcode
begin
radr <= isp_dec;
wadr <= isp_dec;
wdat <= suppress_pcinc[0] ? pc + 32'd1 : pc + 32'd2;
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {isp_dec,2'b00};
dat_o <= suppress_pcinc[0] ? pc + 32'd1 : pc + 32'd2;
res <= 32'd0;
ir <= {8{`BRK}};
hwi <= `TRUE;
vect <= {vbr[31:9],9'd495,2'b00};
state <= IRQ1;
end
pc <= pc; // override the pc increment
state <= DECODE;
end
endcase
end
/trunk/rtl/verilog/mult_div.v
23,6 → 23,8
//
// ============================================================================
//
`define SUPPORT_DIVMOD 1'b1
 
`define MUL 4'd8
`define MULS 4'd9
`define DIV 4'd10
79,6 → 81,7
res_sgn <= a[31] ^ b[31];
state <= MULT;
end
`ifdef SUPPORT_DIVMOD
`DIV,`MOD:
begin
aa <= a;
97,6 → 100,7
res_sgn <= a[31] ^ b[31];
state <= DIV;
end
`endif
default:
state <= IDLE;
endcase
106,6 → 110,7
state <= res_sgn ? FIX_SIGN : IDLE;
p <= aa * bb;
end
`ifdef SUPPORT_DIVMOD
DIV:
begin
q <= {q[30:0],~diff[31]};
124,6 → 129,7
end
cnt <= cnt - 6'd1;
end
`endif
 
FIX_SIGN:
begin
/trunk/rtl/verilog/rtf65002_icachemem.v
0,0 → 1,120
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
module rtf65002_icachemem(wclk, wr, adr, dat, rclk, pc, insn);
input wclk;
input wr;
input [33:0] adr;
input [31:0] dat;
input rclk;
input [31:0] pc;
output reg [63:0] insn;
 
wire [63:0] insn0;
wire [63:0] insn1;
wire [31:0] pcp8 = pc + 32'd8;
reg [31:0] rpc;
 
always @(posedge rclk)
rpc <= pc;
 
// memL and memH combined allow a 64 bit read
syncRam2kx32_1rw1r ramL0
(
.wrst(1'b0),
.wclk(wclk),
.wce(~adr[2]),
.we(wr),
.wsel(4'hF),
.wadr(adr[13:3]),
.i(dat),
.wo(),
.rrst(1'b0),
.rclk(rclk),
.rce(1'b1),
.radr(pc[13:3]),
.o(insn0[31:0])
);
 
syncRam2kx32_1rw1r ramH0
(
.wrst(1'b0),
.wclk(wclk),
.wce(adr[2]),
.we(wr),
.wsel(4'hF),
.wadr(adr[13:3]),
.i(dat),
.wo(),
.rrst(1'b0),
.rclk(rclk),
.rce(1'b1),
.radr(pc[13:3]),
.o(insn0[63:32])
);
 
syncRam2kx32_1rw1r ramL1
(
.wrst(1'b0),
.wclk(wclk),
.wce(~adr[2]),
.we(wr),
.wsel(4'hF),
.wadr(adr[13:3]),
.i(dat),
.wo(),
.rrst(1'b0),
.rclk(rclk),
.rce(1'b1),
.radr(pcp8[13:3]),
.o(insn1[31:0])
);
 
syncRam2kx32_1rw1r ramH1
(
.wrst(1'b0),
.wclk(wclk),
.wce(adr[2]),
.we(wr),
.wsel(4'hF),
.wadr(adr[13:3]),
.i(dat),
.wo(),
.rrst(1'b0),
.rclk(rclk),
.rce(1'b1),
.radr(pcp8[13:3]),
.o(insn1[63:32])
);
 
always @(rpc or insn0 or insn1)
case(rpc[2:0])
3'd0: insn <= insn0[63:0];
3'd1: insn <= {insn1[7:0],insn0[63:8]};
3'd2: insn <= {insn1[15:0],insn0[63:16]};
3'd3: insn <= {insn1[23:0],insn0[63:24]};
3'd4: insn <= {insn1[31:0],insn0[63:32]};
3'd5: insn <= {insn1[39:0],insn0[63:40]};
3'd6: insn <= {insn1[47:0],insn0[63:48]};
3'd7: insn <= {insn1[55:0],insn0[63:56]};
endcase
endmodule
/trunk/rtl/verilog/rtf65002_dtagmem.v
0,0 → 1,56
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
module rtf65002_dtagmem(wclk, wr, wadr, rclk, radr, hit);
input wclk;
input wr;
input [31:0] wadr;
input rclk;
input [31:0] radr;
output hit;
 
reg [31:0] rradr;
wire [31:0] tag;
 
syncRam512x32_1rw1r u1
(
.wrst(1'b0),
.wclk(wclk),
.wce(wadr[1:0]==2'b11),
.we(wr),
.wadr(wadr[10:2]),
.i(wadr),
.wo(),
.rrst(1'b0),
.rclk(rclk),
.rce(1'b1),
.radr(radr[10:2]),
.o(tag)
);
 
 
always @(posedge rclk)
rradr <= radr;
assign hit = tag[31:11]==rradr[31:11];
 
endmodule
/trunk/rtl/verilog/rtf65002_itagmem.v
0,0 → 1,80
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
module rtf65002_itagmem(wclk, wr, adr, rclk, pc, hit0, hit1);
input wclk;
input wr;
input [33:0] adr;
input rclk;
input [31:0] pc;
output hit0;
output hit1;
 
wire [31:0] pcp8 = pc + 32'd8;
wire [31:0] tag0;
wire [31:0] tag1;
reg [31:0] rpc;
reg [31:0] rpcp8;
 
always @(posedge rclk)
rpc <= pc;
always @(posedge rclk)
rpcp8 <= pcp8;
 
syncRam1kx32_1rw1r ram0 (
.wrst(1'b0),
.wclk(wclk),
.wce(adr[3:2]==2'b11),
.we(wr),
.wsel(4'hF),
.wadr(adr[13:4]),
.i(adr[31:0]),
.wo(),
 
.rrst(1'b0),
.rclk(rclk),
.rce(1'b1),
.radr(pc[13:4]),
.o(tag0)
);
 
syncRam1kx32_1rw1r ram1 (
.wrst(1'b0),
.wclk(wclk),
.wce(adr[3:2]==2'b11),
.we(wr),
.wsel(4'hF),
.wadr(adr[13:4]),
.i(adr[31:0]),
.wo(),
 
.rrst(1'b0),
.rclk(rclk),
.rce(1'b1),
.radr(pcp8[13:4]),
.o(tag1)
);
 
assign hit0 = tag0[31:14]==rpc[31:14] && tag0[0];
assign hit1 = tag1[31:14]==rpcp8[31:14] && tag1[0];
 
endmodule
/trunk/rtl/verilog/load_mac.v
21,7 → 21,10
// ============================================================================
//
LOAD_MAC1:
if (unCachedData) begin
`ifdef SUPPORT_DCACHE
if (unCachedData)
`endif
begin
if (isRMW)
lock_o <= 1'b1;
cyc_o <= 1'b1;
30,6 → 33,7
adr_o <= {radr,2'b00};
state <= LOAD_MAC2;
end
`ifdef SUPPORT_DCACHE
else if (dhit) begin
case(load_what)
`WORD_310:
48,6 → 52,7
b <= rdat;
state <= retstate;
end
`ifdef SUPPORT_EM8
`BYTE_70:
begin
b8 <= rdat8;
58,6 → 63,7
res8 <= rdat8;
state <= IFETCH;
end
`endif
`SR_310:
begin
cf <= rdat[0];
75,6 → 81,7
else // PLP
state <= IFETCH;
end
`ifdef SUPPORT_EM8
`SR_70:
begin
cf <= rdat8[0];
140,6 → 147,7
else
state <= IFETCH;
end
`endif
`PC_310:
begin
pc <= rdat;
161,6 → 169,7
load_what <= `WORD_310;
end
end
`ifdef SUPPORT_EM8
`IA_70:
begin
radr <= radr34p1[33:2];
174,10 → 183,12
ia[31:16] <= 16'h0000;
state <= isIY ? BYTE_IY5 : BYTE_IX5;
end
`endif
endcase
end
else
dmiss <= `TRUE;
`endif
LOAD_MAC2:
if (ack_i) begin
cyc_o <= 1'b0;
201,6 → 212,7
b <= dat_i;
state <= retstate;
end
`ifdef SUPPORT_EM8
`BYTE_70:
begin
b8 <= dati;
211,6 → 223,7
res8 <= dati;
state <= IFETCH;
end
`endif
`SR_310: begin
cf <= dat_i[0];
zf <= dat_i[1];
229,6 → 242,7
else // PLP
state <= IFETCH;
end
`ifdef SUPPORT_EM8
`SR_70: begin
cf <= dati[0];
zf <= dati[1];
293,6 → 307,7
else
state <= IFETCH;
end
`endif
`PC_310: begin
pc <= dat_i;
load_what <= `NOTHING;
314,6 → 329,7
state <= LOAD_MAC1;
end
end
`ifdef SUPPORT_EM8
`IA_70:
begin
radr <= radr34p1[33:2];
328,8 → 344,10
ia[31:16] <= 16'h0000;
state <= isIY ? BYTE_IY5 : BYTE_IX5;
end
`endif
endcase
end
`ifdef SUPPORT_BERR
else if (err_i) begin
lock_o <= 1'b0;
cyc_o <= 1'b0;
339,6 → 357,7
dat_o <= 32'h0;
state <= BUS_ERROR;
end
`endif
RTS1:
begin
pc <= pc + 32'd1;
348,9 → 367,10
begin
radr <= radr + y;
wadr <= radr + y;
wdat <= a;
if (ir[7:0]==`ST_IY)
if (ir[7:0]==`ST_IY) begin
store_what <= `STW_A;
state <= STORE1;
end
else begin
load_what <= `WORD_310;
state <= LOAD_MAC1;
357,6 → 377,7
end
isIY <= 1'b0;
end
`ifdef SUPPORT_EM8
BYTE_IX5:
begin
radr <= ia[31:2];
366,7 → 387,7
if (ir[7:0]==`STA_IX || ir[7:0]==`STA_I) begin
wadr <= ia[31:2];
wadr2LSB <= ia[1:0];
wdat <= {4{acc8}};
store_what <= `STW_ACC8;
state <= STORE1;
end
end
379,7 → 400,7
if (ir[7:0]==`STA_IY) begin
wadr <= iapy8[31:2];
wadr2LSB <= iapy8[1:0];
wdat <= {4{acc8}};
store_what <= `STW_ACC8;
state <= STORE1;
end
else begin
387,3 → 408,4
state <= LOAD_MAC1;
end
end
`endif
/trunk/rtl/verilog/ifetch.v
22,52 → 22,31
//
IFETCH:
begin
if (em)
vect <= `BYTE_IRQ_VECT;
else
vect <= {vbr[31:9],`BRK_VECTNO,2'b00};
suppress_pcinc <= 4'hF; // default: no suppression of increment
opc <= pc;
hwi <= `FALSE;
store_what <= `STW_DEF;
if (nmi_edge & !imiss & gie & !isExec & !isAtni) begin // imiss indicates cache controller is active and this state is in a waiting loop
ir <= 64'd0;
nmi_edge <= 1'b0;
wai <= 1'b0;
bf <= 1'b0;
hwi <= `TRUE;
if (em & !nmoi) begin
radr <= {spage[31:8],sp[7:2]};
radr2LSB <= sp[1:0];
wadr <= {spage[31:8],sp[7:2]};
wadr2LSB <= sp[1:0];
wdat <= {4{pc[31:24]}};
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
case(sp[1:0])
2'd0: sel_o <= 4'b0001;
2'd1: sel_o <= 4'b0010;
2'd2: sel_o <= 4'b0100;
2'd3: sel_o <= 4'b1000;
endcase
adr_o <= {spage[31:8],sp[7:2],2'b00};
dat_o <= {4{pc[31:24]}};
sp <= sp_dec;
vect <= `BYTE_NMI_VECT;
state <= BYTE_IRQ1;
state <= BYTE_DECODE;
end
else begin
radr <= isp_dec;
wadr <= isp_dec;
wdat <= pc;
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {isp_dec,2'b00};
dat_o <= pc;
state <= DECODE;
vect <= `NMI_VECT;
state <= IRQ1;
end
end
else if (irq_i && !imiss & gie & !isExec & !isAtni) begin
wai <= 1'b0;
if (im) begin
wai <= 1'b0;
if (isExec) begin
ir <= exbuf;
exbuf <= 64'd0;
94,42 → 73,14
end
end
else begin
bf <= 1'b0;
wai <= 1'b0;
ir <= 64'd0;
hwi <= `TRUE;
if (em & !nmoi) begin
radr <= {spage[31:8],sp[7:2]};
radr2LSB <= sp[1:0];
wadr <= {spage[31:8],sp[7:2]};
wadr2LSB <= sp[1:0];
wdat <= {4{pc[31:24]}};
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
case(sp[1:0])
2'd0: sel_o <= 4'b0001;
2'd1: sel_o <= 4'b0010;
2'd2: sel_o <= 4'b0100;
2'd3: sel_o <= 4'b1000;
endcase
adr_o <= {spage[31:8],sp[7:2],2'b00};
dat_o <= {4{pc[31:24]}};
sp <= sp_dec;
vect <= `BYTE_IRQ_VECT;
state <= BYTE_IRQ1;
state <= BYTE_DECODE;
end
else begin
radr <= isp_dec;
wadr <= isp_dec;
wdat <= pc;
cyc_o <= 1'b1;
stb_o <= 1'b1;
we_o <= 1'b1;
sel_o <= 4'hF;
adr_o <= {isp_dec,2'b00};
dat_o <= pc;
vect <= {vbr[31:9],irq_vect,2'b00};
state <= IRQ1;
state <= DECODE;
end
end
end
161,6 → 112,11
end
if (first_ifetch) begin
first_ifetch <= `FALSE;
if (hist_capture) begin
history_buf[history_ndx] <= pc;
history_ndx <= history_ndx+6'd1;
end
`ifdef SUPPORT_EM8
if (em) begin
case(ir[7:0])
`TAY,`TXY,`DEY,`INY: begin y[7:0] <= res8; nf <= resn8; zf <= resz8; end
230,7 → 186,9
`LDY_IMM,`LDY_ZP,`LDY_ZPX,`LDY_ABS,`LDY_ABSX: begin y[7:0] <= res8; nf <= resn8; zf <= resz8; end
endcase
end
else begin
else
`endif
begin
regfile[Rt] <= res;
case(Rt)
4'h1: acc <= res;
239,23 → 197,22
default: ;
endcase
case(ir[7:0])
`TAY,`TXY,`DEY,`INY: begin y <= res; nf <= resn32; zf <= resz32; end
`TAX,`TYX,`TSX,`DEX,`INX: begin x <= res; nf <= resn32; zf <= resz32; end
`TAS,`TXS: begin isp <= res; gie <= 1'b1; end
`SUB_SP8,`SUB_SP16,`SUB_SP32: isp <= res;
`TSA,`TYA,`TXA,`INA,`DEA: begin acc <= res; nf <= resn32; zf <= resz32; end
`TRS:
begin
case(ir[15:12])
4'h0: begin
$display("res=%h",res);
`ifdef SUPPORT_ICACHE
icacheOn <= res[0];
`endif
`ifdef SUPPORT_DCACHE
dcacheOn <= res[1];
write_allocate <= res[2];
`endif
end
4'h1: dp <= res;
4'h5: lfsr <= res;
4'h6: dp8 <= res;
4'h7: abs8 <= res;
4'h8: begin vbr <= {res[31:9],9'h000}; nmoi <= res[0]; end
4'hE: begin sp <= res[7:0]; spage[31:8] <= res[31:8]; end
275,20 → 232,11
begin nf <= b[31]; vf <= b[30]; zf <= resz32; end
else
begin nf <= resn32; zf <= resz32; end
`OR_RR: begin nf <= resn32; zf <= resz32; end
`EOR_RR: begin nf <= resn32; zf <= resz32; end
`MUL_RR: begin nf <= resn32; zf <= resz32; end
`MULS_RR: begin nf <= resn32; zf <= resz32; end
`DIV_RR: begin nf <= resn32; zf <= resz32; end
`DIVS_RR: begin nf <= resn32; zf <= resz32; end
`MOD_RR: begin nf <= resn32; zf <= resz32; end
`MODS_RR: begin nf <= resn32; zf <= resz32; end
`ASL_RRR: begin nf <= resn32; zf <= resz32; end
`LSR_RRR: begin nf <= resn32; zf <= resz32; end
default:
begin nf <= resn32; zf <= resz32; end
endcase
`LD_RR: begin zf <= resz32; nf <= resn32; end
`DEC_RR,`INC_RR: begin zf <= resz32; nf <= resn32; end
`ASL_RR,`ROL_RR,`LSR_RR,`ROR_RR: begin cf <= resc32; nf <= resn32; zf <= resz32; end
`ADD_IMM8,`ADD_IMM16,`ADD_IMM32,`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND:
begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end
`SUB_IMM8,`SUB_IMM16,`SUB_IMM32,`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND:
305,27 → 253,30
`OR_IMM8,`OR_IMM16,`OR_IMM32,`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND,
`EOR_IMM8,`EOR_IMM16,`EOR_IMM32,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND:
begin nf <= resn32; zf <= resz32; end
`ASL_ACC: begin acc <= res; cf <= resc32; nf <= resn32; zf <= resz32; end
`ROL_ACC: begin acc <= res; cf <= resc32; nf <= resn32; zf <= resz32; end
`LSR_ACC: begin acc <= res; cf <= resc32; nf <= resn32; zf <= resz32; end
`ROR_ACC: begin acc <= res; cf <= resc32; nf <= resn32; zf <= resz32; end
`ASL_ZPX,`ASL_ABS,`ASL_ABSX: begin cf <= resc32; nf <= resn32; zf <= resz32; end
`ROL_ZPX,`ROL_ABS,`ROL_ABSX: begin cf <= resc32; nf <= resn32; zf <= resz32; end
`LSR_ZPX,`LSR_ABS,`LSR_ABSX: begin cf <= resc32; nf <= resn32; zf <= resz32; end
`ROR_ZPX,`ROR_ABS,`ROR_ABSX: begin cf <= resc32; nf <= resn32; zf <= resz32; end
`ASL_ACC,`ROL_ACC,`LSR_ACC,`ROR_ACC:
begin acc <= res; cf <= resc32; nf <= resn32; zf <= resz32; end
`ASL_RR,`ROL_RR,`LSR_RR,`ROR_RR,
`ASL_ZPX,`ASL_ABS,`ASL_ABSX,
`ROL_ZPX,`ROL_ABS,`ROL_ABSX,
`LSR_ZPX,`LSR_ABS,`LSR_ABSX,
`ROR_ZPX,`ROR_ABS,`ROR_ABSX:
begin cf <= resc32; nf <= resn32; zf <= resz32; end
`ASL_IMM8: begin nf <= resn32; zf <= resz32; end
`LSR_IMM8: begin nf <= resn32; zf <= resz32; end
`INC_ZPX,`INC_ABS,`INC_ABSX: begin nf <= resn32; zf <= resz32; end
`DEC_ZPX,`DEC_ABS,`DEC_ABSX: begin nf <= resn32; zf <= resz32; end
`PLA: begin acc <= res; zf <= resz32; nf <= resn32; end
`PLX: begin x <= res; zf <= resz32; nf <= resn32; end
`PLY: begin y <= res; zf <= resz32; nf <= resn32; end
`LDX_IMM32,`LDX_IMM16,`LDX_IMM8,`LDX_ZPY,`LDX_ABS,`LDX_ABSY: begin x <= res; nf <= resn32; zf <= resz32; end
`LDY_IMM32,`LDY_ZPX,`LDY_ABS,`LDY_ABSX: begin y <= res; nf <= resn32; zf <= resz32; end
`TAX,`TYX,`TSX,`DEX,`INX,
`LDX_IMM32,`LDX_IMM16,`LDX_IMM8,`LDX_ZPY,`LDX_ABS,`LDX_ABSY,`PLX:
begin x <= res; nf <= resn32; zf <= resz32; end
`TAY,`TXY,`DEY,`INY,
`LDY_IMM32,`LDY_ZPX,`LDY_ABS,`LDY_ABSX,`PLY:
begin y <= res; nf <= resn32; zf <= resz32; end
`CPX_IMM32,`CPX_ZPX,`CPX_ABS: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
`CPY_IMM32,`CPY_ZPX,`CPY_ABS: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
`CMP_IMM8: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
`LDA_IMM32,`LDA_IMM16,`LDA_IMM8: begin acc <= res; nf <= resn32; zf <= resz32; end
`TSA,`TYA,`TXA,`INA,`DEA,
`LDA_IMM32,`LDA_IMM16,`LDA_IMM8,`PLA: begin acc <= res; nf <= resn32; zf <= resz32; end
`POP: begin nf <= resn32; zf <= resz32; end
endcase
end
end
/trunk/rtl/verilog/overflow.v
0,0 → 1,39
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
module overflow(op, a, b, s, v);
 
input op; // 0=add,1=sub
input a;
input b;
input s; // sum
output v;
 
// Overflow:
// Add: the signs of the inputs are the same, and the sign of the
// sum is different
// Sub: the signs of the inputs are different, and the sign of
// the sum is the same as B
assign v = (op ^ s ^ b) & (~op ^ a ^ b);
 
endmodule
/trunk/rtl/verilog/rtf65002_pcinc.v
0,0 → 1,93
// ============================================================================
// __
// \\__/ o\ (C) 2013 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
`include "rtf65002_defines.v"
 
// This table being setup to set the pc increment. It should synthesize to a ROM.
module rtf65002_pcinc(opcode,suppress_pcinc,inc);
input [7:0] opcode;
input [3:0] suppress_pcinc;
output reg [3:0] inc;
 
always @(opcode)
if (suppress_pcinc==4'hF)
case(opcode)
`BRK: inc <= 4'd0;
`INT0,`INT1: inc <= 4'd0;
`BPL,`BMI,`BCS,`BCC,`BVS,`BVC,`BEQ,`BNE,`BRA,`BGT,`BLE,`BGE,`BLT,`BHI,`BLS: inc <= 4'd2;
`BRL: inc <= 4'd3;
`EXEC,`ATNI: inc <= 4'd2;
`CLC,`SEC,`CLD,`SED,`CLV,`CLI,`SEI: inc <= 4'd1;
`TAS,`TSA,`TAY,`TYA,`TAX,`TXA,`TSX,`TXS,`TYX,`TXY: inc <= 4'd1;
`TRS,`TSR: inc <= 4'd2;
`INY,`DEY,`INX,`DEX,`INA,`DEA: inc <= 4'd1;
`EMM: inc <= 4'd1;
`PHA,`PHX,`PHY,`PHP: inc <= 4'd1;
`PLA,`PLX,`PLY,`PLP: inc <= 4'd1;
`PUSH,`POP: inc <= 4'd2;
`STP,`WAI: inc <= 4'd1;
`JMP,`JML,`JMP_IND,`JMP_INDX,`JMP_RIND,
`JSR,`JSR_RIND,`JSL,`BSR,`JSR_INDX,`RTS,`RTL,`RTI: inc <= 4'd0;
`JML,`JSL,`JMP_IND,`JMP_INDX,`JSR_INDX: inc <= 4'd5;
`JMP_RIND,`JSR_RIND: inc <= 4'd2;
`NOP: inc <= 4'd1;
`BSR: inc <= 4'd3;
`RR: inc <= 4'd3;
`LD_RR: inc <= 4'd2;
`ADD_IMM8,`SUB_IMM8,`AND_IMM8,`OR_IMM8,`EOR_IMM8,`ASL_IMM8,`LSR_IMM8: inc <= 4'd3;
`LDX_IMM8,`LDA_IMM8,`CMP_IMM8,`SUB_SP8: inc <= 4'd2;
`ADD_IMM16,`SUB_IMM16,`AND_IMM16,`OR_IMM16,`EOR_IMM16: inc <= 4'd4;
`LDX_IMM16,`LDA_IMM16,`SUB_SP16: inc <= 4'd3;
`ADD_IMM32,`SUB_IMM32,`AND_IMM32,`OR_IMM32,`EOR_IMM32: inc <= 4'd6;
`LDX_IMM32,`LDY_IMM32,`LDA_IMM32,`SUB_SP32,`CPX_IMM32,`CPY_IMM32: inc <= 4'd5;
`ADD_ZPX,`SUB_ZPX,`AND_ZPX,`OR_ZPX,`EOR_ZPX: inc <= 4'd4;
`ADD_IX,`SUB_IX,`AND_IX,`OR_IX,`EOR_IX: inc <= 4'd4;
`ADD_IY,`SUB_IY,`AND_IY,`OR_IY,`EOR_IY: inc <= 4'd4;
`ADD_ABS,`SUB_ABS,`AND_ABS,`OR_ABS,`EOR_ABS: inc <= 4'd6;
`ADD_ABSX,`SUB_ABSX,`AND_ABSX,`OR_ABSX,`EOR_ABSX: inc <= 4'd7;
`ADD_RIND,`SUB_RIND,`AND_RIND,`OR_RIND,`EOR_RIND: inc <= 4'd3;
`ADD_DSP,`SUB_DSP,`AND_DSP,`OR_DSP,`EOR_DSP: inc <= 4'd3;
`ASL_ACC,`LSR_ACC,`ROR_ACC,`ROL_ACC: inc <= 4'd1;
`ASL_RR,`ROL_RR,`LSR_RR,`ROR_RR,`INC_RR,`DEC_RR: inc <= 4'd2;
`ST_RIND: inc <= 4'd2;
`LDX_ZPX,`LDY_ZPX,`ST_DSP,`STX_ZPX,`STY_ZPX,`CPX_ZPX,`CPY_ZPX,
`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX,
`ADD_DSP,`SUB_DSP,`OR_DSP,`AND_DSP,`EOR_DSP,
`ADD_RIND,`SUB_RIND,`OR_RIND,`AND_RIND,`EOR_RIND: inc <= 4'd3;
`ORB_ZPX,`ST_ZPX,`STB_ZPX,`ADD_ZPX,`SUB_ZPX,`OR_ZPX,`AND_ZPX,`EOR_ZPX,
`ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX,
`ADD_IY,`SUB_IY,`OR_IY,`AND_IY,`EOR_IY,`ST_IY: inc <= 4'd4;
`LDX_ABS,`LDY_ABS,`STX_ABS,`STY_ABS,
`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS,`CPX_ABS,`CPY_ABS: inc <= 4'd5;
`ORB_ABS,`LDX_ABSY,`LDY_ABSX,`ST_ABS,`STB_ABS,
`ADD_ABS,`SUB_ABS,`OR_ABS,`AND_ABS,`EOR_ABS,
`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX: inc <= 4'd6;
`ORB_ABSX,`ST_ABSX,`STB_ABSX,
`ADD_ABSX,`SUB_ABSX,`OR_ABSX,`AND_ABSX,`EOR_ABSX: inc <= 4'd7;
`PHP,`PHA,`PHX,`PHY,`PLP,`PLA,`PLX,`PLY: inc <= 4'd1;
`PUSH,`POP: inc <= 4'd2;
`MVN,`MVP,`STS: inc <= 4'd1;
default: inc <= 4'd0; // unimplemented instruction
endcase
else
inc <= 4'd0;
endmodule

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