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Rev 19 → Rev 20

/rtl/verilog/gfx_CalcAddress4.v
38,6 → 38,7
output [6:0] mb_o;
output [6:0] me_o;
 
parameter BPP6 = 3'd0;
parameter BPP8 = 3'd1;
parameter BPP12 = 3'd2;
parameter BPP16 = 3'd3;
44,9 → 45,13
parameter BPP24 = 3'd4;
parameter BPP32 = 3'd5;
 
// This coefficient is a fixed point fraction representing the inverse of the
// number of pixels per strip. The inverse (reciprocal) is used for a high
// speed divide operation.
reg [15:0] coeff;
always @(color_depth_i)
case(color_depth_i)
BPP6: coeff = 3121; // 1/21 * 65536
BPP8: coeff = 4096; // 1/16 * 65536
BPP12: coeff = 6554; // 1/10 * 65536
BPP16: coeff = 8192; // 1/8 * 65536
54,9 → 59,11
BPP32: coeff = 16384; // 1/4 * 65536
endcase
 
// Bits per pixel minus one.
reg [5:0] bpp;
always @(color_depth_i)
case(color_depth_i)
BPP6: bpp = 5;
BPP8: bpp = 7;
BPP12: bpp = 11;
BPP16: bpp = 15;
64,9 → 71,12
BPP32: bpp = 31;
endcase
 
// This coefficient is the number of bits used by all pixels in the strip.
// Used to determine pixel placement in the strip.
reg [7:0] coeff2;
always @(color_depth_i)
case(color_depth_i)
BPP6: coeff2 = 126;
BPP8: coeff2 = 128;
BPP12: coeff2 = 120;
BPP16: coeff2 = 128;
74,11 → 84,19
BPP32: coeff2 = 128;
endcase
 
// Compute the fixed point horizonal strip number value. This has 16 binary
// point places.
wire [27:0] strip_num65k = x_coord_i * coeff;
wire [15:0] strip_fract = strip_num65k[15:0]+16'h7F;
// Truncate off the binary fraction to get the strip number. The strip
// number will be used to form part of the address.
wire [13:0] strip_num = strip_num65k[27:16];
// Calculate pixel position within strip using the fractional part of the
// horizontal strip number.
wire [15:0] strip_fract = strip_num65k[15:0]+16'h7F; // +7F to round
// Pixel beginning bit is ratio of pixel # into all bits used by pixels
wire [15:0] ndx = strip_fract[15:7] * coeff2;
assign mb_o = ndx[15:9];
assign me_o = mb_o + bpp;
assign mb_o = ndx[15:9]; // Get whole pixel position (discard fraction)
assign me_o = mb_o + bpp; // Set high order position for mask
// num_strips is essentially a constant value unless the screen resolution changes.
// Gain performance here by regstering the multiply so that there aren't two
// cascaded multiplies when calculating the offset.
85,7 → 103,6
reg [27:0] num_strips65k;
always @(posedge clk)
num_strips65k <= hdisplayed_i * coeff;
wire [13:0] strip_num = strip_num65k[27:16];
wire [13:0] num_strips = num_strips65k[27:16];
 
wire [31:0] offset = {{4'b0,num_strips} * y_coord_i + strip_num,4'h0};
/rtl/verilog/rtfBitmapController4.v
55,6 → 55,7
parameter REG_COLOR = 10'd11;
parameter REG_PCMD = 10'd12;
 
parameter BPP6 = 3'd0;
parameter BPP8 = 3'd1;
parameter BPP12 = 3'd2;
parameter BPP16 = 3'd3;
185,7 → 186,7
bm_base_addr1 <= BM_BASE_ADDR1;
bm_base_addr2 <= BM_BASE_ADDR2;
hrefdelay <= 12'd54;//12'd218;
vrefdelay <= 12'd16;//12'd27;
vrefdelay <= 12'd18;//12'd27;
map <= 12'd0;
pcmd <= 2'b00;
rstcmd1 <= 1'b0;
263,7 → 264,7
// Horizontal and Vertical timing reference counters
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 
wire pe_hsync;
wire pe_hsync, pe_hsync2;
wire pe_vsync;
edge_det edh1
(
276,6 → 277,17
.ee()
);
 
edge_det edh2
(
.rst(rst_i),
.clk(m_clk_i),
.ce(1'b1),
.i(hsync),
.pe(pe_hsync2),
.ne(),
.ee()
);
 
edge_det edv1
(
.rst(rst_i),
325,6 → 337,7
reg [4:0] shifts;
always @(color_depth)
case(color_depth)
BPP6: shifts = 5'd21;
BPP8: shifts = 5'd16;
BPP12: shifts = 5'd10;
BPP16: shifts = 5'd8;
335,12 → 348,11
 
wire vFetch = pixelRow < vDisplayed;
wire fifo_rrst = pixelCol==12'hFFF;
wire fifo_wrst = pe_hsync;
wire fifo_wrst = pe_hsync2;
 
wire[31:0] grAddr,xyAddr;
reg [11:0] fetchCol;
wire [6:0] mb,me;
reg [31:4] strip_addr;
reg [127:0] mem_strip;
wire [127:0] mem_strip_o;
wire [31:0] mem_color;
347,8 → 359,9
 
gfx_CalcAddress u1
(
.clk(vclk),
.base_address_i(baseAddr),
.color_depth_i(color_depth),
.color_depth_i({1'b0,color_depth}),
.hdisplayed_i(hDisplayed),
.x_coord_i(0),
.y_coord_i(pixelRow),
359,8 → 372,9
 
gfx_CalcAddress u2
(
.clk(vclk),
.base_address_i(baseAddr),
.color_depth_i(color_depth),
.color_depth_i({1'b0,color_depth}),
.hdisplayed_i(hDisplayed),
.x_coord_i(px),
.y_coord_i(py),
387,7 → 401,7
);
 
always @(posedge m_clk_i)
if (pe_hsync)
if (pe_hsync2)
mapctr <= 12'hFFE;
else begin
if (mapctr == map)
408,11 → 422,14
reg load_fifo;
always @(posedge m_clk_i)
//load_fifo <= fifo_cnt < 10'd1000 && vFetch && onoff && xonoff && !m_cyc_o && do_loads;
load_fifo <= fifo_cnt < 8'd224 && vFetch && onoff && xonoff && fetchCol < hDisplayed && !m_cyc_o && do_loads && memreq;
load_fifo <= /*fifo_cnt < 8'd224 &&*/ vFetch && onoff && xonoff && fetchCol < hDisplayed && !m_cyc_o && do_loads && memreq;
// The following table indicates the number of pixel that will fit into the
// video fifo.
reg [11:0] hCmp;
always @(color_depth)
case(color_depth)
BPP8: hCmp = 12'd4096;
BPP6: hCmp = 12'd4095;
BPP8: hCmp = 12'd4095; // must be 12 bits
BPP12: hCmp = 12'd2559;
BPP16: hCmp = 12'd2048;
BPP24: hCmp = 12'd1279;
424,7 → 441,7
if (!(hDisplayed < hCmp))
do_loads <= 1'b1;
// otherwise load the fifo only when the row changes to conserve memory bandwidth
else if (pixelRow != opixelRow)
else if (vc==4'd1)//pixelRow != opixelRow)
do_loads <= 1'b1;
else if (blankEdge)
do_loads <= 1'b0;
446,20 → 463,28
 
reg [31:0] adr;
always @(posedge m_clk_i)
if (fifo_wrst)
adr <= grAddr;
else begin
if (state==WAITLOAD && m_ack_i)
adr <= adr + 32'd16;
end
 
always @(posedge m_clk_i)
if (fifo_wrst)
fetchCol <= 12'd0;
else begin
if (state==WAITLOAD && m_ack_i)
fetchCol <= fetchCol + shifts;
end
 
always @(posedge m_clk_i)
if (rst_i) begin
wb_nack();
fetchCol <= 12'd0;
opixelRow <= 12'hFFF;
strip_addr <= 28'hFFFFFFF;
rstcmd <= 1'b0;
state <= IDLE;
end
else begin
if (fifo_wrst) begin
fetchCol <= 12'd0;
adr <= grAddr;
opixelRow <= pixelRow;
end
case(state)
WAITRST:
if (pcmd==2'b00) begin
475,23 → 500,17
m_adr_o <= adr;
state <= WAITLOAD;
end
// The adr_o[6:5]==2'b11 causes the controller to wait until all four
// The adr_o[5:4]==2'b11 causes the controller to wait until all four
// 128 bit strips from the memory controller have been processed. Otherwise
// there would be cache thrashing in the memory controller and the memory
// bandwidth available would be greatly reduced. However fetches are also
// aloowed when loads are not active or all strips for the current scan-
// allowed when loads are not active or all strips for the current scan-
// line have been fetched.
else if (pcmd!=2'b00 && (m_adr_o[6:5]==2'b11 || !(vFetch && onoff && xonoff && fetchCol < hDisplayed) || !do_loads)) begin
if (xyAddr[31:4]!=strip_addr || 1) begin
m_cyc_o <= 1'b1;
m_we_o <= 1'b0;
m_adr_o <= xyAddr;
state <= LOADSTRIP;
end
else if (pcmd==2'b01)
state <= LOADCOLOR;
else if (pcmd==2'b10)
state <= STORESTRIP;
else if (pcmd!=2'b00 && (m_adr_o[5:4]==2'b11 || !(vFetch && onoff && xonoff && fetchCol < hDisplayed) || !do_loads)) begin
m_cyc_o <= 1'b1;
m_we_o <= 1'b0;
m_adr_o <= xyAddr;
state <= LOADSTRIP;
end
LOADCOLOR:
begin
528,9 → 547,7
end
WAITLOAD:
if (m_ack_i) begin
fetchCol <= fetchCol + shifts;
wb_nack();
adr <= adr + 32'd16;
state <= IDLE;
end
endcase
547,13 → 564,14
reg [23:0] rgbo2,rgbo4;
reg [127:0] rgbo3;
always @(posedge vclk)
case(color_depth)
BPP8: rgbo4 <= greyscale ? {3{rgbo3[7:0]}} : rgbo3[7:0];
BPP12: rgbo4 <= {rgbo3[11:8],4'h0,rgbo3[7:4],4'h0,rgbo3[3:0],4'h0};
BPP16: rgbo4 <= {rgbo3[15:11],3'b0,rgbo3[10:5],2'b0,rgbo3[4:0],3'b0};
BPP24: rgbo4 <= rgbo3[23:0];
BPP32: rgbo4 <= rgbo3[23:0];
endcase
case(color_depth)
BPP6: rgbo4 <= greyscale ? {3{rgbo3[5:0],2'b00}} : rgbo3[5:0];
BPP8: rgbo4 <= greyscale ? {3{rgbo3[7:0]}} : rgbo3[7:0];
BPP12: rgbo4 <= {rgbo3[11:8],4'h0,rgbo3[7:4],4'h0,rgbo3[3:0],4'h0};
BPP16: rgbo4 <= {rgbo3[15:11],3'b0,rgbo3[10:5],2'b0,rgbo3[4:0],3'b0};
BPP24: rgbo4 <= rgbo3[23:0];
BPP32: rgbo4 <= rgbo3[23:0];
endcase
 
reg rd_fifo,rd_fifo1,rd_fifo2;
reg de;
607,6 → 625,7
rgbo3 <= rgbo1;
else if (shift) begin
case(color_depth)
BPP6: rgbo3 <= {rgbo3[127:6]};
BPP8: rgbo3 <= {rgbo3[127:8]};
BPP12: rgbo3 <= {rgbo3[127:12]};
BPP16: rgbo3 <= {rgbo3[127:16]};
616,11 → 635,25
end
 
 
/* Debugging
wire [127:0] dat;
assign dat[11:0] = pixelRow[0] ? 12'hEA4 : 12'h000;
assign dat[23:12] = pixelRow[1] ? 12'hEA4 : 12'h000;
assign dat[35:24] = pixelRow[2] ? 12'hEA4 : 12'h000;
assign dat[47:36] = pixelRow[3] ? 12'hEA4 : 12'h000;
assign dat[59:48] = pixelRow[4] ? 12'hEA4 : 12'h000;
assign dat[71:60] = pixelRow[5] ? 12'hEA4 : 12'h000;
assign dat[83:72] = pixelRow[6] ? 12'hEA4 : 12'h000;
assign dat[95:84] = pixelRow[7] ? 12'hEA4 : 12'h000;
assign dat[107:96] = pixelRow[8] ? 12'hEA4 : 12'h000;
assign dat[119:108] = pixelRow[9] ? 12'hEA4 : 12'h000;
*/
 
rtfVideoFifo3 uf1
(
.wrst(fifo_wrst),
.wclk(m_clk_i),
.wr(m_cyc_o & m_ack_i),
.wr(m_ack_i && state==WAITLOAD),
.di(m_dat_i),
.rrst(fifo_rrst),
.rclk(vclk),
644,7 → 677,7
integer nn,n;
always @(mb_i or me_i or nn)
for (nn = 0; nn < 128; nn = nn + 1)
mask[nn] <= (nn >= mb_i) ^ (nn <= me_i) ^ (me_i >= mb_i);
mask[nn] <= (nn >= mb_i) & (nn <= me_i);
always @*
begin
for (n = 0; n < 128; n = n + 1)
666,7 → 699,7
integer nn,n;
always @(mb_i or me_i or nn)
for (nn = 0; nn < 128; nn = nn + 1)
mask[nn] <= (nn >= mb_i) ^ (nn <= me_i) ^ (me_i >= mb_i);
mask[nn] <= (nn >= mb_i) & (nn <= me_i);
 
always @*
begin

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